JP3882080B2 - Bias current simulation method in SFQ logic circuit, bias current simulation apparatus in SFQ logic circuit, bias current simulation program in SFQ logic circuit, recording medium recording bias current simulation program in SFQ logic circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an SFQ logic circuit using a single flux quantum (SFQ) as an information carrier, and more particularly to a method, apparatus, program and program for simulating a bias current in an SFQ logic circuit. The present invention relates to a recorded recording medium.
[0002]
[Prior art]
An SFQ logic circuit using a single magnetic flux quantum as an information carrier has a feature that it operates at ultra high speed and low power consumption. For this reason, various applications such as a petaflop scale computer, a backbone high-end router, and an A / D converter for software defined radio are expected. However, SFQ logic circuit technology is immature as compared with CMOS circuit technology, and is currently at the stage of aiming at full operation of a circuit including about 10,000 Josephson junctions.
[0003]
With regard to such an SFQ logic circuit, for example, there is a technique for reducing the chip area by reducing the occupied area of the passive transmission line described in Patent Document 1 below.
[0004]
Here, as one of the factors hindering the large-scale integration of the SFQ logic circuit, there is a problem of supplying a bias current for driving the SFQ logic circuit. Superconducting circuits such as SFQ logic circuits are generally sensitive to magnetic fields, and circuit operation experiments are usually performed under strict magnetic shielding. When the circuit is scaled up, the direct current bias current required to drive the circuit also increases, so that the influence of the magnetic field generated by the bias current itself may not be negligible. Therefore, in order to increase the scale of the SFQ logic circuit, it is necessary to examine how much the bias current affects the circuit operation and to appropriately deal with the problem if the problem is serious.
[0005]
Here, as a result of an experiment using a TFF (Toggle Flip-Flop) cell shown in FIG. 8, it is confirmed that the current flowing through the bias line reduces the operation margin of the circuit more than expected. In the figure, 10 is a TFF cell, 12 is an SFQ signal line that is a signal line through which an SFQ pulse is transmitted, and 13 is a bias line.
[0006]
Current injection ports (PORT1, PORT2, PORT3, PORT4) are provided at the four corners of the TFF cell 10 shown in FIG. _c was passed through the TFF cell 10. Then, the ground bias current I _B required by the TFF cell 10 is supplied from one of the remaining two current injection ports (PORT 1), and the operation bias margin of the circuit is examined. A reduction in operating margin appeared at current values above a certain level. Therefore, when the amount of bias current supplied by the circuit increases in scale, the magnetic field generated by the bias current increases the risk of causing a reduction in the operating margin.
[0007]
To solve this problem, conventionally, the bias line 13 is shielded to eliminate the influence of the current flowing through the bias line 13 on the circuit operation. For example, if the bias line 13 of the TFF cell 10 which is the designed SFQ cell has a superconducting stripline structure, the influence of the magnetic field generated by the bias current on the circuit operation is considered to be extremely small in view of common sense.
[0008]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-68995
[Problems to be solved by the invention]
However, in the above-described prior art in which the shield is applied to the bias line, since it is not possible to provide a shield at all points such as the area where the SFQ signal line 12 and the bias line 13 intersect (bias bridge) in FIG. At present, the influence on the operation cannot be completely eliminated.
[0010]
Next, the limit of effectiveness of the shield will be described. FIG. 9 shows a cross-sectional view of the shield structure. The shield structure is realized by wrapping the bias line 13 with an insulating layer 135 and further wrapping with a superconducting shield 131. In the current superconducting circuit manufacturing process, all three superconducting layers of the ground layer 134, the base layer 133, and the counter layer 132 shown in FIG. However, in an actual circuit, there is a region where the bias line 13 and the SFQ signal line 12 intersect.
[0011]
Although this region is called a bias bridge, it is impossible to shield the bias line 13 in this vicinity in the current superconducting three-layer circuit manufacturing process. As described above, all three superconducting layers are required to realize the shield structure. However, if the counter layer is used for the SFQ signal line 12, there is a portion that cannot be shielded.
[0012]
FIG. 10 shows a circuit layout of the Ex-OR cell. It can be seen that the SFQ signal line 12 and the bias line 13 intersect to form the bias bridge 11 near the input / output of the SFQ signal in the Ex-OR cell 20. Note that the bias line 13 in FIG. 10 is shielded.
[0013]
FIG. 11 is a diagram showing the influence on the circuit operation by supplying a bias current for driving the circuit to the circuit of the Ex-OR cell 20 shown in FIG. That is, while a bias current is supplied from a certain port to the Ex-OR cell 20, a closed-loop closed current is supplied between the ports, and the current range is shown in which the circuit operates normally. . In FIG. 11, for example, Port 1 (3 → 2) indicates that a bias current is supplied from Port 1 of the Ex-OR cell 20 shown in FIG. 10 while a closed current is supplied from Port 3 to Port 2. From FIG. 11, it can be seen that the bias current flowing in the vicinity of the bias bridge 11 that cannot be shielded has a considerable influence on the circuit operation.
[0014]
In other words, the shield structure itself is very effective in reducing the influence of the bias current, but in an actual circuit, all the bias lines 13 cannot be shielded. There is a limit to its effectiveness.
[0015]
It is an object of the present invention to provide a bias current simulation method that can solve the above-described problems and know the bias current distribution of the SFQ logic circuit.
[0016]
[Means for Solving the Problems]
As described above, it is difficult to completely avoid the influence of the bias current flowing through the bias line 13, but if the bias current value is a certain level, the influence is small and can be ignored. The problem is how much bias current can flow.
[0017]
If a critical value for allowing a certain bias current so far is set, the allowable amount of the bias current that can be passed through the bias bridge 11 is required even if it is necessary to investigate the influence of the bias current on all the cells. It will be decided for every cell.
[0018]
When supplying a bias current to a large-scale circuit, if the distribution of the current flowing through the bias line 13 for all cells can be obtained by calculation, it is determined in advance whether the bias current has a serious effect on the circuit operation. It is possible to know and is very effective in design.
[0019]
In the present invention, the idea that the influence of the bias current is suppressed by anything is changed, and a certain allowable value that the influence of the bias current on the circuit operation can be ignored so far is experimentally grasped for each cell. In addition, a bias current simulation technique is provided in which the bias current distribution of the entire circuit is simulated in advance so that a dangerous part can be detected in advance and the layout can be changed as necessary.
[0020]
That is, the bias current simulation method in the SFQ logic circuit according to the present invention is a method for simulating the bias current in the SFQ logic circuit using a single magnetic flux quantum (SFQ) as an information carrier, and inputs the SFQ logic circuit data. Replacing the bias line of the SFQ logic circuit with a circuit made of only a resistor based on the input SFQ logic circuit data, and the SFQ logic circuit based on an equivalent circuit made up of only the resistor And calculating a bias current distribution at.
[0021]
According to the present invention, in the bias current simulation method in the SFQ logic circuit, the step of replacing the bias line of the SFQ logic circuit with a circuit composed only of a resistor includes the bias line of the SFQ logic circuit including a resistor and an inductance. A step of replacing with an equivalent circuit, and a step of generating an equivalent circuit composed of only a resistor by replacing an inductance in the equivalent circuit composed of the resistor and the inductance with a resistor.
[0022]
The bias current simulation apparatus in the SFQ logic circuit of the present invention is an apparatus for simulating the bias current in the SFQ logic circuit using a single magnetic flux quantum (SFQ) as an information carrier, and inputs the SFQ logic circuit data. Means for replacing the bias line of the SFQ logic circuit with a circuit consisting only of a resistor based on the inputted SFQ logic circuit data, and the SFQ logic circuit based on an equivalent circuit consisting only of the resistor In the bias current simulation apparatus in the SFQ logic circuit, the means for replacing the bias line of the SFQ logic circuit with a circuit composed only of a resistor is provided. , Bias of the SFQ logic circuit Means for replacing IN with an equivalent circuit composed of resistance and inductance, and means for replacing the inductance in the equivalent circuit composed of resistance and inductance with a resistance to generate an equivalent circuit composed only of resistance. It is characterized by that.
[0023]
The program of the present invention is a bias current simulation program in an SFQ logic circuit for causing a computer to execute the bias current simulation method in the SFQ logic circuit.
[0024]
A recording medium on which the program of the present invention is recorded is a recording medium on which a bias current simulation program in an SFQ logic circuit for causing a computer to execute the bias current simulation method in the SFQ logic circuit is recorded.
[0025]
By using the present invention, it becomes possible to know the distribution of the bias current of the SFQ logic circuit.
[0026]
Further, according to the recording medium in which the bias current simulation program in the SFQ logic circuit of the present invention is recorded, the bias current simulation program in the SFQ logic circuit is stored in a recording medium such as a CD-ROM, CDR / W, or a flexible disk. Can be provided.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing an example of the configuration of a bias current simulation apparatus that implements the present invention. Reference numeral 1 denotes a bias current simulation apparatus, 100 denotes a circuit data input unit, 101 denotes an equivalent circuit generation unit, 102 denotes a bias current distribution calculation unit, and 103 denotes a converted value storage unit.
[0028]
The circuit data input unit 100 inputs data of the SFQ logic circuit. The equivalent circuit generation unit 101 replaces the bias line of the SFQ logic circuit with an equivalent circuit composed of a resistor and an inductance based on the input SFQ logic circuit data, and then replaces the inductance in the equivalent circuit with a resistor. An equivalent circuit composed only of resistors is generated.
[0029]
The bias current distribution calculation unit 102 calculates a bias current distribution in the SFQ logic circuit based on an equivalent circuit composed only of the generated resistance. The conversion value storage unit 103 stores a correspondence relationship between the inductance in the equivalent circuit composed of the resistance and the inductance and the value of the resistance that replaces the inductance.
[0030]
FIG. 2 is a diagram showing an example of a bias current simulation process flow according to the present invention. First, SFQ logic circuit data is input (step S1). For example, circuit data of a JTL (Josephson transmission line) cell 30 shown in FIG. Next, based on the input circuit data, the bias line of the SFQ logic circuit is replaced with an equivalent circuit composed of a resistor and an inductance (step S2).
[0031]
That is, in general, since a superconductor behaves as an inductance in terms of an electric circuit, a bias line network of an SFQ logic circuit formed by arranging cells is an inductance circuit network. More precisely, a feed resistor for supplying a certain current to the Josephson junction is also included in the network, so it can be said that the circuit is composed of a resistor and an inductance. The circuit is replaced with an equivalent circuit composed of resistance and inductance based on the circuit data.
[0032]
For example, the bias line 13 of the JTL cell 30 is replaced with an equivalent circuit as shown in FIG. 3B based on the circuit data of the JTL cell 30 of FIG. The portion of the bias feed resistor 14 surrounded by an ellipse in FIG. 3A corresponds to R ₁ in the equivalent circuit of FIG. 3B, and the portion other than the bias feed resistor 14 of the bias line 13 is, for example, FIG. ) Equivalent to inductances L _{1 to} L ₆ in the equivalent circuit. For the replacement, for example, a three-dimensional electromagnetic field analysis tool is used.
[0033]
Next, an inductance in the equivalent circuit composed of the replaced resistance and inductance is replaced with a resistance to generate an equivalent circuit composed only of the resistance (step S3). This step S3 will be described in detail below.
[0034]
For example, the inductance network itself in which equivalent circuits as shown in FIG. 3B are arranged is equipotential, and the current supplied to the Josephson junction of the JTL cell 30 does not depend on the shape of the inductance network at all. .
[0035]
On the other hand, the distribution of current flowing through the inductance network strongly depends on the position and size of the feed resistor as well as the size of the inductance of the bias line 13. Specifically, for each of the many inductance loops present in the inductance network, a current distribution that satisfies the condition for quantizing the magnetic flux in the loop is taken. That is, the current distribution in the bias line network is a distribution that satisfies the equipotential law with respect to the feed resistance, but otherwise satisfies the flux quantization condition of the inductance loop.
[0036]
A current distribution that satisfies the magnetic flux quantization condition in each inductance loop means that a larger amount of current flows in a path with a smaller inductance, which means that a larger amount of current flows in a path with a smaller resistance. Is equivalent to that. Therefore, the inductance network can be replaced with a resistance network.
[0037]
FIG. 4 shows an image diagram for explaining this. That is, in the inductance loop as shown in FIG. 4A, a magnetic flux quantization condition of L ₁₀ × I ₁₂ = L ₁₁ × I ₁₃ is satisfied, and a large current flows in a path with a small inductance. Therefore, the inductance loop as shown in FIG. 4A can be replaced with the resistance circuit of FIG. 4B showing that a larger amount of current flows in a path having a smaller resistance. In this case, in the present invention, the replacement is performed so that the ratio of L ₁₀ and L _{11 and} the ratio of R ₁₁ and R ₁₂ are equal. As a result, the equipotential law (R ₁₁ × I ₁₂ = R ₁₂ × I ₁₃ ) is established in the generated resistance circuit.
[0038]
In the present invention, the replacement from the inductance to the resistance is performed by referring to the converted value storage unit 103 in which the correspondence relationship between the inductance and the resistance value is stored, for example.
[0039]
However, if the potential generated by the replaced resistor is approximately the same as the potential generated by the bias feed resistor 14, the generated potential is biased because the equipotential law to be satisfied with respect to the bias feed resistor 14 is also affected. It is replaced with a resistance that is so small that it is completely negligible compared to the potential generated in the feed resistor 14.
[0040]
By the above replacement, in step S3, for example, from the equivalent circuit shown in FIG. 3B, the bias of each JTL cell 30 including the resistors R ₁ , R _A , R _C , and R _D as shown in FIG. An equivalent circuit for line 13 is generated. R ₁ corresponds to the bias feed resistor 14.
[0041]
Then, a bias current distribution in the SFQ logic circuit is calculated based on an equivalent circuit composed only of the generated resistors (step S4).
[0042]
6 and 7 are diagrams showing a bias current simulation experiment based on the equivalent circuit shown in FIG. As shown in FIG. 6, after four JTL cells 30 of J _{1 to} J ₄ are arranged, a bias current is applied by applying a voltage of 2.5 mV. 5, for example, R ₁ is 8.34Ω, R _A is 7.17 pΩ, R _C is 5.43 pΩ, and R _D is 7.17 pΩ.
[0043]
As a result of the experiment, as shown in FIG. 7, for example, the current value of the cell J ₂ at the position of the resistor R ₁ in FIG. 5 is 440.5 μA, and the current of the cell J ₁ at the position of the resistor R ₁ in FIG. The value is 299.2 μA, the current value of the cell J ₃ at the position of the resistor R ₁ in FIG. 5 is 246.2 μA, and the current value of the cell J ₂ at the position of the resistor R ₂ in FIG. 5 is 212.4 μA. became.
[0044]
【The invention's effect】
By using the present invention, it is possible to know the bias current distribution of the SFQ logic circuit, so that it is possible to predict in advance whether or not there is an influence of the bias current.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an example of a configuration of a bias current simulation apparatus.
FIG. 2 is a diagram illustrating an example of a bias current simulation process flow;
FIG. 3 is a diagram illustrating an example of a layout of a JTL cell.
FIG. 4 is a diagram illustrating a replacement from an inductance network to a resistance network.
FIG. 5 is a diagram illustrating an example of an equivalent circuit of a bias line of a JTL cell.
FIG. 6 is a diagram showing a simulation experiment of a bias current.
FIG. 7 is a diagram showing the results of a bias current simulation experiment.
FIG. 8 shows a TFF cell.
FIG. 9 is a cross-sectional view of a shield structure.
FIG. 10 is a diagram showing an Ex-OR cell.
FIG. 11 is a diagram showing the influence of bias current on circuit operation.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Bias current simulation apparatus 10 TFF cell 11 Bias bridge 12 SFQ signal line 13 Bias line 14 Bias feed resistance 20 Ex-OR cell 30 JTL cell 100 Circuit data input part 101 Equivalent circuit generation part 102 Bias current distribution calculation part 103 Conversion value memory | storage 131 Superconducting shield 132 Counter layer 133 Base layer 134 Ground layer 135 Insulating layer

Claims (6)

A method of simulating a bias current in an SFQ logic circuit using a single flux quantum (SFQ) as an information carrier,
Inputting the SFQ logic circuit data;
Replacing the bias line of the SFQ logic circuit with a circuit consisting only of resistors based on the input SFQ logic circuit data;
A bias current simulation method in the SFQ logic circuit, comprising: calculating a bias current distribution in the SFQ logic circuit based on an equivalent circuit including only the resistor. The bias current simulation method in the SFQ logic circuit according to claim 1,
The step of replacing the bias line of the SFQ logic circuit with a circuit consisting only of a resistor includes:
Replacing the bias line of the SFQ logic circuit with an equivalent circuit comprising a resistor and an inductance;
A method for simulating a bias current in an SFQ logic circuit, comprising: replacing an inductance in an equivalent circuit composed of the resistor and the inductance with a resistor and generating an equivalent circuit composed of only the resistor. An apparatus for simulating a bias current in an SFQ logic circuit using a single flux quantum (SFQ) as an information carrier,
Means for inputting the SFQ logic circuit data;
Means for replacing the bias line of the SFQ logic circuit with a circuit consisting only of a resistor based on the input SFQ logic circuit data;
A bias current simulation apparatus in an SFQ logic circuit, comprising: means for calculating a bias current distribution in the SFQ logic circuit based on an equivalent circuit composed only of the resistor. The bias current simulation apparatus in the SFQ logic circuit according to claim 3,
Means for replacing the bias line of the SFQ logic circuit with a circuit consisting only of a resistor,
Means for replacing the bias line of the SFQ logic circuit with an equivalent circuit composed of a resistor and an inductance;
A bias current simulation apparatus in an SFQ logic circuit, comprising means for replacing an inductance in an equivalent circuit composed of the resistor and the inductance with a resistor and generating an equivalent circuit composed of only the resistor. A bias current simulation program in an SFQ logic circuit for causing a computer to execute the bias current simulation method in the SFQ logic circuit according to claim 1. A recording medium recording a bias current simulation program in an SFQ logic circuit for causing a computer to execute the bias current simulation method in the SFQ logic circuit according to claim 1.

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