JP3881290B2 - Plasma processing equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma processing apparatus, and more particularly to a plasma processing apparatus for processing a sample such as a wafer uniformly within a wafer surface.
[0002]
[Prior art]
2. Description of the Related Art Plasma processing apparatuses such as a plasma CVD (chemical vapor deposition) apparatus and a plasma etching apparatus are widely used as a semiconductor manufacturing apparatus for manufacturing a semiconductor device by processing a processed plate material such as a silicon wafer (hereinafter referred to as a wafer). . In these plasma processing apparatuses, it is generally very important to perform uniform processing within the wafer surface. For example, in a plasma CVD apparatus, a film forming speed and film composition that are as uniform as possible within a wafer surface are required. In a plasma etching apparatus, an etching speed that is as uniform as possible within a wafer surface and the shape of a groove or hole is required. Desired. If a sufficiently uniform process cannot be realized, the performance of individual semiconductor devices formed on the same wafer will vary, and in some cases, defects will occur, and the price of semiconductor devices due to a decrease in production yield. There is a risk of rising.
[0003]
Among these non-uniformities, the semiconductor chip is located near the outer edge of the wafer due to non-uniformity in wafer processing caused by factors such as mechanical, electromagnetic or thermal singularities near the outer edge of the wafer. It may be difficult to manufacture. In this case, the chip is designed so that the chip is not formed in an area where it is difficult to manufacture the chip, but the unused area near the outer peripheral edge of the wafer according to such a design rule is referred to as edge exclusion (hereinafter referred to as EE). .) And this E.E. E. Is one factor that determines semiconductor prices.
[0004]
Therefore, various studies have been made on the in-plane uniformity of processing in a plasma processing apparatus. For example, Japanese Patent Application Laid-Open No. 7-66174 discloses an insulation or portion having a portion called a “wall” that is used with a pedestal that supports a wafer and the plasma sheath is selected to be uniform across the entire surface of the wafer. It is stated that the use of a “ring” made of a dielectric material eliminates or significantly reduces non-vertical field lines on the wafer.
[0005]
[Problems to be solved by the invention]
However, the plasma processing apparatus described in Japanese Patent Application Laid-Open No. 7-66174 is a batch type etching apparatus in which a wafer is mechanically fixed to a wafer stage called a pedestal in an oblique direction with a holding clip. This is a preferred invention, which is an apparatus that has become commonly used in recent years, that is, wafers are transferred one by one by an automatic transfer means, placed horizontally on a sample holding means, and electrostatically adsorbed. In addition, it has been found that there are various difficulties in applying to a device that applies a bias potential to the sample holding means.
[0006]
In addition to Japanese Laid-Open Patent Publication No. 7-66174, Japanese Patent Laid-Open Publication No. 11-74099 discloses that a conductor or dielectric ring is provided around the sample holding means and has some influence on the electric field on the wafer. JP-A-2001-185542 is known. However, each publication has a different purpose and problem, and even if the described configuration is used, the lines of electric force that are not perpendicular to the wafer surface due to the bias potential cannot be eliminated or greatly reduced. .
[0007]
Accordingly, an object of the present invention has been made in view of such problems, and the distribution of the electric field strength when a bias potential is applied to the wafer is uniform up to the outer peripheral edge of the wafer. A plasma processing apparatus capable of performing uniform processing within a wafer surface by preventing or mitigating concentration of an electric field on the outer periphery edge of the wafer by maintaining the surface substantially perpendicular to the wafer surface to the outer periphery edge. It is to provide.
[0008]
[Means for Solving the Problems]
The present invention employs the following means in order to solve the above problems.
A processing chamber for processing a sample, an evacuation unit for depressurizing the processing chamber, a processing gas supply unit for supplying a processing gas to the processing chamber, a sample holding unit for holding a sample to be processed in the processing chamber, A plasma processing apparatus comprising bias applying means for applying a bias potential to the sample holding means, electrostatic adsorption means for electrostatically adsorbing the sample to the sample holding means, and plasma generating means for generating plasma in the processing chamber The upper surface of the sample holding means has a step, the sample is placed on the uppermost stage, and the bias potential can be applied to a surface lower than the placement surface of the sample. ring-shaped member made of a conductor for a uniform electric field intensity distribution on the surface is provided, and the upper surface of the ring-shaped member is equal to or lower and the upper surface of the specimen, the ring The plasma processing apparatus, wherein a member made the upper surface of the member from the dielectric covering.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows an embodiment in which the present invention is applied to a plasma etching apparatus, and is a schematic sectional view of the plasma etching apparatus.
[0010]
In FIG. 1, a processing chamber 100 is a vacuum vessel capable of achieving a vacuum of about 10000 / Pa, an antenna 110 that radiates electromagnetic waves in the upper part, and a lower electrode on which a sample W such as a wafer is placed in the lower part. 130 is provided. The antenna 110 and the lower electrode 130 are installed so as to face each other in parallel. Around the processing chamber 100, a magnetic field forming unit 101 made of, for example, an electromagnetic coil and a yoke is installed. Then, due to the interaction between the electromagnetic wave radiated from the antenna 110 and the magnetic field formed by the magnetic field forming means 101, the processing gas introduced into the processing chamber is converted into plasma, generating plasma P, and processing the sample W. .
[0011]
On the other hand, the processing chamber 100 is evacuated by the evacuation means 106 and the pressure is controlled by the pressure control means 107. The processing pressure is adjusted to a range of 0.1 Pa to 10 Pa. The processing chamber 100 is at ground potential.
[0012]
The antenna 110 is held in a housing 114 as a part of the vacuum container. A shower plate 115 is provided on the surface of the antenna 110 that is in contact with the plasma. A processing gas for performing processing such as sample etching and film formation is supplied from a gas supply means (not shown) with a predetermined flow rate and a mixing ratio, and is controlled to a predetermined distribution through a number of holes provided in the shower plate 115. , And supplied to the processing chamber 100.
[0013]
An antenna power source 121 and an antenna bias power source 122 are connected to the antenna 110 via matching circuit / filter systems 123 and 124, respectively, and are connected to the ground through the filter 125. The antenna power supply 121 supplies power of a UHF band frequency from 300 MHz to 1 GHz. In this embodiment, the frequency of the antenna power supply 121 is 450 MHz. On the other hand, the antenna bias power source 122 applies bias power having a frequency in the range of several tens of kHz to several tens of MHz to the antenna 110. In this embodiment, the frequency is 13.56 MHz. The sample W is a wafer having a diameter of 300 mm.
[0014]
For example, a bias power supply 141 that supplies a bias power in a range of 200 kHz to 13.56 MHz is connected to the lower electrode 130 via a matching circuit / filter system 142 to control a bias applied to the sample W, and a filter 143 is provided. Connected to ground. In this embodiment, the frequency of the bias power supply 141 is 400 kHz.
[0015]
The lower electrode 130 has a wafer stage 131, and a sample W such as a wafer is placed and held on the upper surface thereof, that is, the sample placement surface. The wafer stage 131 is made of aluminum as a base material, and a dielectric layer for electrostatic adsorption (hereinafter abbreviated as an electrostatic adsorption film) is formed on the upper surface thereof. By applying a DC voltage of several hundreds to several kV to the wafer stage 131 from the DC power source 144 and the filter 145 for electrostatic chucking, an electrostatic chucking force is generated, and the sample W such as a wafer is chucked and held. As the electrostatic adsorption film, for example, a dielectric material in which alumina or titania is mixed with alumina is used. Further, the surface of the wafer stage 131 is controlled to a predetermined temperature by a temperature control means (not shown). Then, an inert gas, for example, He gas, is supplied to the surface of the wafer stage 131 with a predetermined flow rate and pressure, and heat transfer with the sample W is enhanced. Thereby, the surface temperature of the sample W can be accurately controlled within a range of, for example, about 20 ° C. to 110 ° C. The diameter of the upper surface of the wafer stage 131 is about 1-2 mm smaller than the diameter of the sample W. As a result, the electrostatic adsorption film on the upper surface of the wafer stage 131 is not directly exposed to plasma, that is, damage due to plasma can be prevented, so that it can be used for a long period of time.
[0016]
The upper surface of the wafer stage 131 has a step, the sample W is placed on the uppermost stage, and a lower surface than the sample placement surface is a ring-shaped member made of a conductor to which a bias potential can be applied. A conductor ring 132 is provided. The upper surface of the ring-shaped member is desirably the same as or lower than the upper surface of the sample.
[0017]
The conductor ring 132 is made of aluminum. This is because the surface of the conductor ring 132 is basically required to have the same potential as that of the wafer stage 131 when a bias is applied, so that the wafer stage 131 and the conductor ring 132 have equivalent electrical characteristics. This is because it is necessary. Further, when the temperature of the wafer stage 131 and the conductor ring 132 changes, the dimensions of these members thermally expand or contract. However, if they are made of individual materials and have different coefficients of thermal expansion, the wafer stage 131 and the conductor ring Thermal stresses can occur during 132 and can cause irregular deformation. If the conductor ring 132 is irregularly deformed, the distribution of the electric field on the outer periphery of the wafer may change. Therefore, the material of the conductor ring 132 is a material having a thermal expansion coefficient comparable to that of the wafer stage 131. Is preferred.
[0018]
If necessary, the surface of the conductor ring 132 is covered with a dielectric coating such as anodizing (so-called anodized) or surface treatment (spray coating) such as spraying to prevent abnormal discharge or short circuit. .
[0019]
In addition, the upper surface of the conductor ring 132 is covered with a cover ring 133 made of a dielectric material for the purpose of preventing the metal ring from being exposed to plasma and thinning. The cover ring 133 is preferably made of ceramic such as alumina or quartz. For the cover ring 133 in this example, alumina formed by sintering was used.
[0020]
Here, care should be taken regarding the height of the cover ring 133. It is desirable that the uppermost surface of the cover ring 133 is flush with the upper surface of the wafer W or higher than the upper surface of the wafer W. Moreover, the difference in height between them is preferably 2 mm or less. This is because when the uppermost surface of the cover ring 133 is lower than the upper surface of the wafer W, an electric field may be concentrated on the upper periphery of the wafer W. On the other hand, if the height is higher than 2 mm, foreign matter adhering to the cover ring 133 may fall onto the wafer W, which is not preferable.
[0021]
Next, the effect of uniforming the electric field distribution on the wafer when the apparatus of this embodiment is used will be specifically described.
[0022]
FIG. 2 is an enlarged view of the vicinity of the outer periphery of the wafer W in FIG. The difference Hw−Hf between the height Hw to the upper surface of the wafer W and the height Hf to the upper surface of the conductor ring 132 in FIG. 2 is 2.6 mm, and the conductor ring inner diameter Df and the outermost stage of the wafer stage 131 are outside. The difference Df−Ds from the diameter Ds is 0.3 mm. The surface of the conductor ring 132 is anodized. This is to prevent the inner peripheral portion of the conductor ring 132 from being in contact with the plasma and being etched. In FIG. 2, the ground E is installed inside the cover ring 133, but the position of the ground is not necessarily inside the cover ring, and may be installed outside the cover ring. In addition, the bias of the lower electrode 130 in the figure is applied to a conductor in which the wafer stage 131 and the conductor ring 132 are regarded as one body.
[0023]
FIG. 3 shows the result of analysis of the distribution of the electric field formed by the bias potential at this time. As is clear from FIG. 3, the equipotential surface formed by the bias potential is substantially parallel to the upper surface of the wafer W from the vicinity of the center to the outer peripheral edge of the wafer W.
[0024]
On the other hand, FIG. 4 is a conventional example, and shows an enlarged view of the vicinity of the outer peripheral portion of the wafer W when a conductor ring is not used. Further, FIG. 5 shows a result obtained by analyzing the distribution of the electric field formed by the bias potential in the configuration of FIG. As can be seen from FIG. 5, the interval between equipotential surfaces formed by the bias potential is narrow near the outer peripheral edge of the wafer W, and the electric field concentrates and becomes stronger.
[0025]
Such non-uniformity of the electric field distribution can be made clearer than the graphs of FIGS. FIG. 6 is a diagram showing a result of analysis obtained for the relationship between the distance r from the center of the wafer W and the electric field lines at the height of 1 mm above the wafer and the angle θ formed by the wafer surface. It can be seen that the angle of the lines of electric force when the conductor ring 132 is used is substantially perpendicular to the wafer surface. On the other hand, the angle of the lines of electric force when the conductor ring is not used decreases as it approaches the outer peripheral edge of the wafer (150 mm), and is approximately 66 ° near the outer peripheral edge of the wafer.
[0026]
FIG. 7 is a diagram showing a result obtained by analysis of the relationship between the distance r from the center of the wafer W and the electric field strength E at a position 1 mm above the wafer. It can be seen that the electric field intensity E when the conductor ring 132 is used is substantially constant up to the outermost periphery of the wafer. On the other hand, it can be seen that the electric field intensity E when the conductor ring is not used clearly rises and changes as it approaches the outer peripheral edge of the wafer (150 mm). As described above, by applying the present invention, the angle of the electric lines of force formed by the bias potential can be made substantially perpendicular to the wafer surface even at the outer peripheral portion of the wafer, so that the charged particles in the plasma are perpendicular to each other. You can pull in. Thereby, it can be seen that the sidewall shape after etching is uniform over the entire surface of the wafer. Further, the fact that the electric field strength formed by the bias potential is uniform even at the outer peripheral portion of the wafer means that the kinetic energy of the charged particles in the plasma is uniform, so that there is no deviation in the etching rate. Therefore, when the present invention is applied, E.I. E. It can be seen that the target area can be reduced.
[0027]
Actually, the silicon wafer was etched in the etching apparatus using the conductor ring 132 shown in FIG. As a result of verifying the side wall shape of the groove formed after etching and the depth of the groove, that is, the etching rate, it was possible to achieve highly uniform etching from the center of the wafer to the vicinity of the outer peripheral edge.
[0028]
Next, a second embodiment of the present invention will be described in detail with reference to the drawings.
8 differs from the first embodiment in the shapes of the conductor ring 132 and the cover ring 133 of the lower electrode 130. The difference of Hw−Hf in FIG. 8 is 0.6 mm, and the difference of Df−Ds is 3.5 mm. FIG. 9 shows a result obtained by analyzing the distribution of the electric field formed by the bias potential at this time. As is clear from FIG. 9, the equipotential surface formed by the bias potential is substantially parallel to the upper surface of the wafer W from the vicinity of the center to the outer peripheral edge of the wafer W. This result is almost the same as the equipotential surface shown in FIG. 3 when the conductor ring 132 shown in FIG. 2 is used.
[0029]
FIG. 10 is a diagram showing a result of analysis obtained for the relationship between the distance r from the center of the wafer W and the electric field lines at the height of 1 mm above the wafer and the angle θ formed by the wafer surface. The angle of the electric lines of force when the conductor ring 1321 is used is substantially perpendicular to the wafer surface up to the wafer end, and the angle of the electric lines of force when the conductor ring is not used is prominent at the wafer end. It is clearly different from the tendency to become smaller. FIG. 11 is a diagram showing a result obtained by analyzing the relationship between the distance r from the center of the wafer W and the electric field intensity E at a position 1 mm above the wafer. The electric field strength when the conductor ring 1321 is used is substantially constant until reaching the outermost periphery of the wafer, while the electric field strength E when the conductor ring is not used clearly increases at the outer periphery of the wafer.
[0030]
The silicon wafer was actually etched by the etching apparatus using the conductor ring 1321 shown in FIG. As a result of verifying the side wall shape of the groove formed after etching and the depth of the groove, that is, the etching rate, it was possible to achieve highly uniform etching from the center of the wafer to the vicinity of the outer peripheral edge.
[0031]
Next, another embodiment of the present invention will be briefly described with reference to the drawings.
12 and 13 are different from the first embodiment in the shapes of the conductor ring 132 and the cover ring 133 of the lower electrode 130. The difference of Hw−Hf in FIG. 12 is 6 mm, and the difference of Df−Ds is 0.6 mm. Moreover, the difference of Hw-Hf in FIG. 13 is 1.6 mm, and the difference of Df-Ds is 8 mm. In these examples, the silicon wafer was actually etched, and the side wall shape and depth of the groove formed after the etching, that is, the etching rate was verified. It was possible to achieve highly uniform etching.
[0032]
Next, further studies were made on the allowable values of the difference of Hw−Hf and the difference of Df−Ds.
FIG. 14 is a diagram illustrating the relationship between the difference of Hw−Hf, the difference of Df−Ds, and the angle θ formed between the lines of electric force and the wafer surface. In addition, from the measurement results in a detailed experiment conducted separately, in a wafer with a diameter of 300 mm, when the distance r from the wafer center is 149 mm and θ at a point of 1 mm on the wafer is 85 ° to 95 °, the etching result is good I know that Therefore, in FIG. 14, when the range of Hw−Hf and Df−Ds in which θ is in the range of 85 ° to 95 ° is examined, the range in which Hw−Hf ≦ 7 and Df−Ds ≦ 10 is a preferable range. It turns out that there is.
[0033]
As described above, when the present invention is applied, the wafers are transferred one by one by the automatic transfer means, placed horizontally on the sample holding means, held by electrostatic adsorption, and the sample holding means is biased. Thus, the plasma processing apparatus capable of performing uniform processing within the wafer surface can be provided, in which the electric field intensity distribution on the wafer is uniform up to the outer peripheral edge of the wafer. Further, according to the configuration of the present invention, since there is no “wall” at a position higher than the upper surface of the wafer, which has been used in the prior art, foreign matter attached to the “wall” falls on the wafer. Problems can also be reduced.
[0034]
The present invention is not limited to application to the plasma etching apparatus described in the first to third embodiments.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a plasma etching apparatus to which the present invention is applied.
FIG. 2 is an enlarged view of the vicinity of an outer peripheral portion of a wafer W in FIG.
FIG. 3 is a diagram showing a result obtained by analyzing a distribution of an electric field formed by a bias potential in the configuration of FIG. 2;
FIG. 4 is an enlarged view of the vicinity of an outer peripheral portion of a wafer W in a conventional example.
5 is a diagram showing a result obtained by analyzing a distribution of an electric field formed by a bias potential in the configuration of FIG. 4;
FIG. 6 is a diagram showing the relationship between the distance from the wafer center and the angle θ formed between the lines of electric force and the wafer surface.
FIG. 7 is a diagram showing the relationship between the distance from the wafer center and the electric field intensity E.
FIG. 8 is an enlarged view of the vicinity of the outer periphery of a wafer W of a plasma etching apparatus to which another embodiment of the present invention is applied.
9 is a diagram showing a result obtained by analyzing a distribution of an electric field formed by a bias potential in the configuration of FIG.
FIG. 10 is a diagram showing the relationship between the distance from the wafer center and the angle θ between the electric lines of force and the wafer surface.
FIG. 11 is a diagram showing the relationship between the distance from the wafer center and the electric field strength.
FIG. 12 is an enlarged view of the vicinity of the outer periphery of a wafer W of a plasma etching apparatus to which another embodiment of the present invention is applied.
FIG. 13 is an enlarged view of the vicinity of the outer periphery of a wafer W of a plasma etching apparatus to which another embodiment of the present invention is applied.
FIG. 14 is a diagram showing the relationship between Hw−Hf, Df−Dw, and the angle θ formed between the lines of electric force and the wafer surface.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Processing chamber 106 ... Vacuum exhaust means 110 ... Antenna 121 ... Antenna power source 122 ... Antenna bias power source 130 ... Lower electrode 131 ... Wafer stage 132 ... Conductor ring 133 ... Cover ring 141 ... Lower electrode Bias power supply, 144... DC power supply for electrostatic attraction.

Claims (6)

A processing chamber for processing a sample, an evacuation unit for depressurizing the processing chamber, a processing gas supply unit for supplying a processing gas to the processing chamber, a sample holding unit for holding a sample to be processed in the processing chamber, A plasma processing apparatus comprising bias applying means for applying a bias potential to the sample holding means, electrostatic adsorption means for electrostatically adsorbing the sample to the sample holding means, and plasma generating means for generating plasma in the processing chamber In
The top surface of the sample holding means has a step, is placed on the upper is placed the sample, the lower surface than the mounting surface of the sample on the sample surface a said bias potential can be applied A ring-shaped member made of a conductor for making the electric field intensity distribution in the substrate uniform , and the upper surface of the ring-shaped member is the same as or lower than the upper surface of the sample, and the upper surface of the ring-shaped member is a dielectric A plasma processing apparatus characterized in that a member made of is covered.   2. The plasma processing apparatus according to claim 1, wherein a difference between an upper surface of the ring-shaped member and an upper surface of the sample is 7 mm or less, and an inner diameter of the ring-shaped member and an outermost diameter of the uppermost stage of the sample holding means The plasma processing apparatus is characterized in that the difference between them is 10 mm or less. In the plasma processing apparatus according to claim 1 Symbol placement, the material of the annular member made of the conductor, the plasma processing apparatus, characterized in that the same as the base material of the sample holding means. The plasma processing apparatus according to claim 1 Symbol placement, the material of the member made of the dielectric material, a plasma processing apparatus which is a ceramic or quartz. 2. The plasma processing apparatus according to claim 1, wherein a surface of the ring-shaped member made of the conductor is covered with a dielectric film made of a member different from the member made of the dielectric. .   6. The plasma processing apparatus according to claim 5, wherein the dielectric coating is a sprayed coating or an anodic oxide film.

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