JP3877490B2 - Magnetic element and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to information recording / reproducing memory technology using a ferromagnetic material, and more particularly, to a magnetic element using a ferromagnetic tunnel junction and a manufacturing method thereof.
[0002]
[Prior art]
Magnetic random access memory (hereinafter abbreviated as MRAM), which is a magnetic element, is a general term for solid-state memory that uses the magnetization direction of a ferromagnetic material as a record carrier of information and can rewrite, hold, and read recorded information at any time. It is.
[0003]
In the MRAM, information is recorded by associating whether the magnetization direction of the ferromagnetic material constituting the memory cell is parallel or anti-parallel to a certain reference direction by corresponding to binary information “1” and “0”. . The recording information is written by reversing the magnetization direction of the ferromagnetic material of each cell by a current magnetic field generated by passing a current through a write line arranged in a cross stripe shape. In principle, the power consumption during recording and holding is zero, and this is a non-volatile memory that holds recording even when the power is turned off.
[0004]
Reading recorded information is a phenomenon in which the electrical resistance of a memory cell changes depending on the relative angle between the magnetization direction of the ferromagnetic material constituting the cell and the sense current, or the relative angle of magnetization between a plurality of ferromagnetic layers, so-called magnetoresistance. Use the effect. In the read operation, with the sense current flowing through the ferromagnetic material constituting each cell, the magnetization direction of the ferromagnetic material is changed by a current magnetic field in the same way as at the time of writing, and the change in electrical resistance at that time is regarded as a voltage change. Detect and do. By setting the magnitude of the magnetic field at this time to be smaller than the ferromagnetic coercive force, nondestructive reading can be realized.
[0005]
In an MRAM having a recording capacity of about 1 Mb that is currently being studied for practical use, a giant magneto-resistance effect (hereinafter referred to as GMR effect) is used to read recorded information from a memory element.
[0006]
Currently, the GMR effect value of a non-bonded NiFe / Cu / Co three-layer film that is often used as an element exhibiting the GMR effect (hereinafter abbreviated as GMR element) is approximately 6 to 8%, and the sheet resistance is several tens of Ω / □ It is about. Therefore, even if a sheet resistance of 100Ω / □ and a resistance change rate of 5% are assumed, the read signal with respect to the sense current of 10 mA is only 5 mV. Therefore, the speeding up of reading is insufficient, and further higher output of the reading signal is demanded.
[0007]
In order to solve these points, a proposal has been made to apply a ferromagnetic tunnel effect (hereinafter referred to as TMR effect) instead of the GMR effect.
[0008]
An element exhibiting the TMR effect (hereinafter abbreviated as a TMR element) is mainly composed of a three-layer film composed of ferromagnetic layer 1 / insulating layer / ferromagnetic layer 2, and current flows through the insulating layer. The resistance value of the TMR element is typically a junction area μm.²10 per hit⁴~ L0⁶Ω. Therefore, tentatively 1 μm²Assuming that the element has a resistance value of 10 kΩ and a resistance change rate of 25%, a read signal of 25 mV can be obtained with a sense current of 10 μA.
[0009]
A TMR element is basically a vertical structure element, and an MRAM using the TMR element generally has a structure in which a plurality of TMR elements are connected in parallel on a data line.
[0010]
The types of the detailed structure are as follows: (1) each TMR element is provided with a selection semiconductor element, (2) a selection transistor is provided for each data line, and (3) a plurality of TMR elements are arranged in a matrix. And a selection transistor for each row data line and column data line (see, for example, j. Appl. Phys. 81, 3758 (1997)).
[0011]
For microfabrication of the GMR and TMR element portions, a processing process using both photolithography and ion milling using Ar ions is generally used. However, the ion milling method is a physical sputtering method, and has a defect that a material to be processed becomes a residue as a residue and reattaches to the side surface of the resist mask or processing apparatus.
[0012]
Currently, in the semiconductor field, dry etching methods using chemical reactions such as chemical dry etching (hereinafter abbreviated as CDE) and reactive ion etching (hereinafter abbreviated as RIE) are actively used. ing.
[0013]
In the etching of Si, SiO2, etc. using a chemical reaction, the workpiece is removed as a halide having a high vapor pressure in the vapor phase. However, halides of 3d transition metals such as Fe, Ni, Co, and Cu used for GMR elements and TMR elements have low vapor pressure, and it is difficult to apply the process used for semiconductor processing as it is. In addition, a method of chemical etching by forming an organometallic compound using a mixed gas of carbon monoxide and ammonia has been devised (see, for example, Journal of Applied Magnetics Society of Japan, Vol. 22, p1383), but the chemical reaction rate. Is inadequate, and there is a problem that it is unavoidable to be a process in which physical sputtering by a reaction gas is mixed, and it has not been put into practical use.
[0014]
In recent years, in the manufacturing process of DRAM, MPU, etc., Cu wiring is often used instead of the conventional Al wiring for the purpose of reducing wiring delay, improving electromigration resistance and heat dissipation. As described above, Cu is difficult to chemically etch with a halogen-based reaction gas used for etching Al. Therefore, a buried wiring forming technique (damascene method) has been proposed as a completely different method from the conventional method of depositing and flattening an interlayer insulating film after processing the wiring. (See, for example, Prcc IEEE VMIC p20 (1991)). This is because, after a trench serving as a wiring portion is formed in advance in an interlayer insulating film, a wiring film such as Cu is formed on the entire surface, and a method such as chemical mechanical polishing (hereinafter abbreviated as CMP) is used. In this method, planarization is performed to realize wiring separation. Furthermore, a dual damascene method is also known in which a metal film is buried in not only the wiring but also the connection hole to the lower wiring. (See, for example, Proc. IEEE VMIC p. 144 (1991)).
[0015]
These damascene methods are mainly applied to passive elements such as wiring and connection holes.
[0016]
As an application example for an active element, for example, a damascene gate structure transistor in which a gate portion of a MOS transistor is formed by a damascene method is known. However, a manufacturing method using the damascene method of the memory element portion is not known at present.
[0017]
On the other hand, when the TMR element is applied to MRAM, it is necessary to connect the electrodes at both ends to an external circuit such as a data line or a selection transistor. In particular, since the TMR element has a vertical structure, element isolation by an insulating film is essential when the upper electrode is connected to an external wiring. A contact hole for wiring connection is formed in the insulating film. The contact hole can be formed by (1) etching an insulator by reactive chemical etching using a resist mask, (2) forming an insulating film while leaving the resist used for element processing, and then using a solvent or the like. The two main methods are stripping the resist (self-alignment process).
[0018]
However, in the method (1), the mask alignment margin in this process defines the minimum processing dimension of the element, and the miniaturization is difficult, and in the method (2), the miniaturization progresses and the photoresist is developed. When the thickness and the element size are approximately the same, there are drawbacks such as difficulty in removing the resist.
[0019]
[Problems to be solved by the invention]
As described above, photolithography and ion milling using Ar or the like are mainly used as conventional microfabrication methods for memory elements in MRAM. However, the ion milling method, which is a physical sputtering method, has the disadvantage that the material to be processed becomes a residue as a residue as it is processed and reattaches to the side of the resist mask or in the processing apparatus, causing deterioration in device characteristics and yield. Have.
[0020]
The present invention has been made to cope with such problems, and provides a magnetic element manufactured by suppressing the use of an etching method by physical sputtering such as an ion milling method as much as possible, and a method for manufacturing the same. It is aimed.
[0021]
[Means for Solving the Problems]
  According to the present invention,A first wiring pattern provided on a semiconductor substrate, a first insulating layer provided on the semiconductor substrate and the first wiring pattern, and a second insulating layer formed on the first insulating layer A first connection hole formed at a predetermined position on the wiring pattern of the first insulating layer, and a second connection formed in the second insulating layer formed in communication with an upper portion of the first connection hole A ferromagnetic tunnel junction in which a hole, a first ferromagnetic electrode formed in the first connection hole, and a second ferromagnetic electrode formed in the second connection hole constitute a tunnel junction through a tunnel barrier layer And a magnetic element comprising a connection plug connected to the ferromagnetic tunnel junction and a second wiring pattern connected to the connection plug, wherein the first ferromagnetic electrode and the second ferromagnetic electrode are respectively Shaped by first and second connection holes It is defined, and the lower bottom area of the second ferromagnetic electrode is larger than the upper area of the first ferromagnetic electrodeThis is a magnetic element.
[0022]
  Also according to the invention,Forming a first wiring pattern on the semiconductor substrate; forming a first insulating film on the semiconductor substrate and the first wiring pattern; and selectively removing the first insulating film. Forming a first connection hole reaching the wiring pattern; forming a first ferromagnetic electrode film in the first connection hole and on the first insulating film; and the first on the first insulating film. Removing the ferromagnetic electrode film to leave the first ferromagnetic electrode film in the first connection hole; and an upper surface of the first ferromagnetic electrode film left in the first connection hole; Forming a tunnel barrier layer on the first insulating film; depositing a passivation film on the tunnel barrier layer; and forming a second insulating film on the passivation film; and the second insulating film and the passivation Selectively remove the membrane Forming a second connection hole having a lower bottom area larger than an upper area of the first connection hole reaching the tunnel barrier layer; and a second ferromagnetic electrode film in the second connection hole and on the second insulating film Forming, removing the second ferromagnetic electrode film on the second insulating film, leaving the second ferromagnetic electrode film in the second connection hole, and the second ferromagnetic electrode Forming a second wiring pattern electrically connected to the film on the second insulating film. A method of manufacturing a magnetic element, comprising:
[0023]
  Also according to the invention,Forming a first wiring pattern on the semiconductor substrate; forming a first insulating film on the semiconductor substrate and the first wiring pattern; and selectively removing the first insulating film. Forming a first connection hole reaching the wiring pattern; forming a first ferromagnetic electrode film in the first connection hole and on the first insulating film; and the first on the first insulating film. Removing the ferromagnetic electrode film to leave the first ferromagnetic electrode film in the first connection hole; and an upper surface of the first ferromagnetic electrode film left in the first connection hole; Forming a tunnel barrier layer on the first insulating film; depositing a passivation film on the tunnel barrier layer; and forming a second insulating film on the passivation film; and the second insulating film and the passivation Selectively remove the membrane Forming a second connection hole having a lower bottom area larger than an upper area of the first connection hole reaching the tunnel barrier layer; a second ferromagnetic electrode film in the second connection hole and on the second insulating film; Forming a connection plug film; and removing the second ferromagnetic electrode film and the connection plug film on the second insulating film to form the second ferromagnetic electrode film and the connection in the second connection hole A method of manufacturing a magnetic element, comprising: a step of leaving a plug film; and a step of forming a second wiring pattern electrically connected to the connection plug film on the second insulating film. is there.
[0024]
  Also according to the invention,Forming a first wiring pattern on the semiconductor substrate; forming a first insulating film on the semiconductor substrate and the first wiring pattern; and selectively removing the first insulating film. Forming a first connection hole reaching the wiring pattern; forming a first ferromagnetic electrode film in the first connection hole and on the first insulating film; and the first on the first insulating film. Removing the ferromagnetic electrode film to leave the first ferromagnetic electrode film in the first connection hole; and an upper surface of the first ferromagnetic electrode film left in the first connection hole; Forming a tunnel barrier layer on the first insulating film; forming a second ferromagnetic electrode film on the tunnel barrier layer; and in the first connection hole on the second ferromagnetic electrode film. A hard mass having a cross-sectional area larger than the upper area of the first ferromagnetic electrode film Forming a second insulating film on the processed second ferromagnetic electrode film and the first insulating film, and a step of processing the second ferromagnetic electrode film using the hard mask. And a second wiring pattern electrically connected to the second ferromagnetic electrode film by selectively removing the second insulating film located on the processed second ferromagnetic electrode film Forming on the second insulating film. A method for manufacturing a magnetic element, comprising:
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an example of the magnetic element of the present invention will be described with reference to the drawings.
[0029]
FIG. 1 is a schematic layout diagram of a magnetic memory device in which a magnetic element of the present invention is formed.
[0030]
The magnetic memory device of this embodiment has a plurality of memory cells, and each memory cell includes a TMR element 14 having a ferromagnetic tunnel junction and a selection transistor 2.
[0031]
  The selection transistor 2 and the TMR element 14 are on the main surface of the semiconductor substrate 1.Are formed at predetermined locations on the insulating layer formed on the upper surface of the lower wiring pattern 11. In the TMR element 14, an upper electrode 23 is formed by a ferromagnetic tunnel junction via a tunnel barrier 22 on the lower electrode 21 connected to the lower wiring pattern 11, and the upper electrode 23 is a contact serving as a connection plug. It is connected to the upper wiring pattern 16 through the metal 15. Also,A word line 3 serving as a gate of the selection transistor 2 is formed on the semiconductor substrate 1. A drain region 4 a and a source region 4 b of the selection transistor 2 are formed in the region of the semiconductor substrate 1 on both sides of the word line 3. Note that the source region 4b also serves as the source region of the select transistor of the adjacent cell.
[0032]
  An interlayer insulating film 5 is formed on the selection transistor 2, and a lower wiring pattern 11 made of a metal layer is formed on the interlayer insulating film 5. The lower wiring pattern 11 is connected to the drain region 4 a of the selection transistor 2 through a tact 6 provided in the interlayer insulating film 5. In addition,7Is a writing line.
[0033]
  A TMR element 14 is provided inside the connection hole 12 a formed in the insulating layer 12 on the lower wiring pattern 11 so that one end is electrically connected to the lower wiring pattern 11. The other end of the TMR element 14 is connected to the data line 16 via the contact metal 15. Therefore, the TMR element 14 is provided on the passivation film 41 where the lower wiring pattern 11 and the data line 16 intersect. Also the data line16Is an insulating filmPassivation film 41Covered with
[0034]
  Write line7The description of the write / read circuit except for is omitted. For the configuration of the writing / reading circuit and the peripheral circuit associated therewith, a well-known semiconductor technology, for example, a well-known technology used in a DRAM, a ferroelectric memory or the like can be used.
[0035]
For manufacturing the semiconductor circuit portion and the peripheral circuit portion excluding the TMR element 14, a conventionally known semiconductor manufacturing technique can be used, and a detailed description thereof is omitted.
[0036]
Desirable forms in the manufacturing method of these configurations are as follows. In addition, the same code | symbol as FIG. 1 has shown the same function part.
[0037]
  (1) The insulating film 12 formed on the metal film that forms the lower wiring pattern 11 is made of SiO.₂, SiOF, HSQ (hydrogen silsesqueioxane), MSQ (Methyl Silsesquioxane), Phosphorus-added glass, Al₂O₃The material species is not limited as long as it has an insulating function. In view of reducing the capacitance between wirings, a low dielectric constant material is preferable. As the film forming method, a sputtering method, a CVD method, a coating method, and the like are suitable, but the method is not particularly limited.
[0038]
(2) As a method for selectively removing the insulating film 12 on the lower wiring pattern 11, CDE or RIE using a halogen-based gas or a fluorocarbon-based gas is suitable. The details and reactive gas species are not limited. However, in order to reduce the dimensional conversion difference with respect to the element region, an etching method having a characteristic capable of etching a connection hole with a high aspect ratio is preferable. As a mask at the time of etching, in addition to a mask using an organic molecular polymer, a hard mask made of metal or dielectric having a pattern transferred by a so-called lift-off method may be used. Pattern transfer onto the mask may be performed using a conventionally known lithography technique such as photolithography or electron beam drawing.
[0039]
(3) As a method for forming a material film on the insulating film 12 having the connection holes 12a, sputtering, vapor deposition, CVD, plating, or the like is appropriate. In order to realize flat filling in the connection hole 12a, the vapor deposition method and the plating method are particularly optimal. For example, a method obtained by improving the conventional technique such as a long throw spanter method or a collimator spanter method can be used. The details of the method are not limited as long as each method has a function of forming a film and flatly filling the connection hole 12a.
[0040]
In addition to the conductive ferromagnetic film that forms the upper ferromagnetic electrode, the material film includes a dielectric film that forms the tunnel barrier portion of the element. Use of a laminated film made of a plurality of metals and alloys in the conductive ferromagnetic film is a preferable form from the viewpoint of improving the function of the TMR element 14. For material films made of these different kinds of materials, it is desirable to select and use the optimum forming method as appropriate.
[0041]
(4) The CMP method is the most suitable method for element isolation by removing part of the material film and insulating film and leaving the material film in the connection hole 12a. The polishing agent, polishing conditions, end point detection method, and the like at that time are not limited in the present invention. In addition to the CMP method, a method such as an etch back method or a chemical removal method can be used as long as it has the above action.
[0042]
(5) An optional process may be added after the element isolation and before the upper wiring forming process. The gist of the present invention is to form and separate an element region by removing a part of the material film and the insulating film and leaving the material film in the connection hole. In the case of a TMR element, the active region of the element is limited to the lower electrode region. That is, after forming only the lower electrode in the steps described in (1) to (4), the tunnel barrier portion and the upper electrode may be formed by different methods.
[0043]
(6) In the step of connecting the element and the upper wiring pattern 16, it is preferable to re-use the steps described in (1) to (4) to bury the portion of the connection hole 12a. At that time, as shown in the figure, a contact metal is formed on the upper electrode 23 with a connecting metal, and then a removal process is performed, so that a connection hole is formed in a self-aligning manner, and a preferable form is obtained.
[0044]
Therefore, if these manufacturing methods are used, it is possible to minimize the use of etching by physical sputtering such as ion milling at the time of device processing, and the following excellent features are obtained.
[0045]
(1) In etching by physical sputtering, a material to be processed is reattached as a residue in the wafer or in the processing apparatus with processing. These cause undesirable deterioration of the wafer characteristics and a decrease in yield. In particular, in the case of a TMR element, redeposition to the bonding side surface causes a leakage of the bonding and causes fatal damage to the element characteristics. In the present invention, it is possible to eliminate such problems relating to reattachment as much as possible. For example, even when only the lower electrode is formed by embedding and the upper electrode is formed by ion milling, the etching of the upper electrode does not reach the lower electrode, so that junction leakage due to reattachment does not occur.
[0046]
(2) In order to reduce redeposition to the vicinity of an element in an etching process by physical sputtering, a method in which an ion beam used for sputtering is incident with being inclined with respect to the normal line of the substrate is often used. However, in such ion beam etching by oblique incidence, the side surface angle after processing has a taper angle of several tens of degrees. Further, since the side surface angle changes depending on the beam incident angle, the mask side surface inclination, and the mask thickness, the result of the dimensional conversion difference varies depending on the process. Since the resistance value and magnetic characteristic of the TMR element depend on the element area and its shape, the variation in the dimensional conversion difference directly leads to the variation in the element characteristic. In the present invention, since the element region can be accurately defined by CDE, RIE, etc., such characteristic variations can be eliminated.
[0047]
(3) When a TMR element is processed by an etching method involving charged particles such as an ion milling method, electrostatic breakdown of the insulating film portion causes deterioration of element characteristics. In the present invention, since the processing process involving charged particles can be eliminated as much as possible from the processing of the TMR element, such a problem can be reduced.
[0048]
In the present invention, the connecting hole portion can be formed by embedding in the connecting step between the element and the upper wiring. At this time, after forming the connection metal on the upper electrode and then performing the removal step, the connection hole is formed in a self-aligning manner, and the mask process at the time of forming the connection hole can be omitted.
[0049]
  Next, the magnetic element of the present inventionReference exampleWill be described.
[0050]
(Reference example1)
  2 (a) to (f) show the present invention.Reference example 1It is the schematic diagram which showed the cross section for every manufacturing process. FIG. 2F shows the final shape. That is, in this embodiment, the case where the TMR element is formed on the lower data line or the metal pad (lower wiring pattern) for connection to the selection transistor is shown.
[0051]
  As shown in FIG.Reference example 1In the magnetic element using the ferromagnetic tunnel junction, the TMR element 14 is formed at a predetermined position of the insulating layer formed on the upper surface of the lower wiring pattern 11 formed of a metal film, and the lower electrode 21 of the TMR element 14 is formed. Is connected to the lower wiring pattern 11. Further, an upper electrode 23 is formed by a ferromagnetic tunnel junction via a tunnel barrier 22 on the lower electrode 21 of the TMR element 14, and the upper electrode 23 is connected to an upper wiring pattern 16 via a contact metal 15 which is a connection plug. Connected to.
[0052]
Next, the manufacturing method about these structures is demonstrated. First, a 300 nm thick SiO 2 film is formed on the first metal film (W 200 nm / TiN 50 nm) forming the lower wiring pattern 11.₂A first insulating film 12 made of is deposited by plasma CVD. Thereafter, an opening 13a for defining an embedded portion is formed in the photoresist 13 by applying, exposing and developing the photoresist 13 as shown in FIG. Next, the first insulating film 12 is etched until it reaches the first metal film 11 by RIE using a fluorocarbon-based reaction gas to obtain the connection hole 12a. At this time, TiN on the surface of the first metal film which is the lower wiring pattern 11 functions as an etching stopper film. (FIG. 2 (b)). After removing the photoresist 13 with a solvent (FIG. 2 (c)), it is mounted on a vacuum apparatus for film formation, and cleaning with Ar ions and annealing at 250 ° C. are performed to clean the surface. Subsequently, the lower electrode 21, the tunnel barrier 22, and the upper electrode 23 of the TMR 14 are deposited in the same vacuum apparatus. (FIG. 2 (d)).
[0053]
  Reference example 1Then, an electron beam heating vapor deposition apparatus (not shown) and an ultrahigh vacuum MBE apparatus (not shown) equipped with a Knudsen cell were used for film formation. The distance between the evaporation source and the wafer is about 40 cm, and the molecular beam from the evaporation source is incident on the wafer almost in parallel. The lower electrode 21 was made of a NiFe 20 nm / Co 5 nm bilayer film, and the upper electrode 23 was made of a Co 20 nm single layer film, which were deposited by electron beam heating evaporation. The tunnel barrier 22 is an amorphous Al film with a thickness of 1 nm.₂O₃The Al was evaporated from the Knudsen cell in an oxygen atmosphere and deposited on the wafer. After the upper electrode 23 was deposited, 300 nm-thick Al was further deposited as a contact metal 15 by sputtering. (FIG. 2 (d)) Thereafter, the surface deposition layer and the first insulating film 12 are removed by CMP and planarized by the CMP method, so that the first insulating film 12 and the metal in the connection hole 12a are flush with each other. This metal becomes the contact metal 15. (FIG. 2 (e)) Thereafter, a work-affected layer generated on the processed surface of the contact metal 15 is removed by wet etching, and then a second metal film 16 for forming an upper wiring pattern is formed. The second metal film 16 was made of Al having a thickness of 300 nm, and was deposited on the entire surface by a sputtering method, and then a wiring pattern was formed by photolithography and RIE. (FIG. 2 (f)).
[0054]
  Reference example 1Then, the surface deposition layer and the first insulating film 12 are removed until reaching a part of the contact metal 15, and the surface is planarized to form the connection hole in a self-aligning manner. That is, the conventional interlayer insulation film formation and connection hole formation after the surface planarization by the CMP method can be omitted.
[0055]
The problem with the method described above is how the multilayer films 21 to 23 constituting the TMR element 14 can be deposited flatly in the opening 12a formed in the first insulating film 12. Furthermore, the multilayer films 21 to 23 deposited in the openings are required to be completely separated from the multilayer films deposited other than the grooves at the time of deposition.
[0056]
For this, as described above, it is preferable to use the MBE method capable of forming a highly directional molecular beam. The side wall shape of the first insulating film on the side surface of the opening may be an inversely tapered shape. In this case, a void is generated on the side surface of the opening after the film formation. This can be solved by depositing a new insulating film by the CVD method or the like before the surface removal by the CMP method.
[0057]
  Reference example 1Since the shape of the TMR film (element) 14 is defined by the shape of the connection hole 12a, the resistance value and magnetic characteristics of the TMR 14 can be controlled to desired values by changing the shape.
[0058]
(Reference example2)
  3 (a) to 3 (i) show the present invention.Reference example 2It is the schematic diagram which showed the cross section for every manufacturing process. FIG. 3 (i) shows the final shape. That is, thisReference example 2The figure shows a case where a TMR element is formed on a lower data line or a metal pad (lower wiring pattern) 11 for connection to a selection transistor.
[0059]
  As shown in FIG.Reference example 2In the TMR element 14 using the ferromagnetic tunnel junction, a barrier portion 22 is formed on the side wall and the bottom of the contact metal 15 that is a connection plug.Reference example 1Therefore, the same functional parts as those in FIG. 2 are denoted by the same reference numerals, and individual descriptions are omitted.
[0060]
Next, the manufacturing method about these structures is demonstrated.
[0061]
  Up to the process of FIG.Reference example 1The detailed description thereof will be omitted. After the opening 12a is formed in the first insulating film 12, it is mounted on a film forming vacuum device, cleaned with Ar ions for surface cleaning, and annealed at 250 ° C., and then the lower electrode 21 of the TMR element 14 NiFe5nm / IrMnl5nm / Co5nmthreeA layer film is formed by the MBE method. (FIG. 3 (d)). Subsequently, a 1 nm-thick Al film that becomes the tunnel barrier 22 in the same vacuum apparatus.₂O₃Membrane Al₂O₃It is formed by sputtering from a target. Thereafter, SiO film having a film thickness of 300 nm is formed by plasma CVD.₂A film 31 is deposited. At this time, A forming the tunnel barrier 22l ₂O₃SiO film with a thickness of about 10 nm before CVD deposition to protect the film₂A film may be formed on the entire surface in advance by sputtering. (FIG. 3 (e)).
[0062]
Next, the surface deposition layer is removed by CMP until a part of the first insulating film 12 is reached. Next, the SiO left in the opening by wet etching₂The film 31 is removed. (FIG. 3 (f). Thereafter, the film is mounted on a vacuum apparatus for film formation, annealed at 250 ° C. to clean the surface, and then a Co5 nm / NiFe20 nm bilayer film that becomes the upper electrode 23 of the TMR element 14 is formed. By the MBE method, 300 nm-thick Al was further deposited as a contact metal 15 by a sputtering method (FIG. 3G).
[0063]
Thereafter, the connection hole 12a is formed in a self-aligned manner by taking out from the vacuum apparatus, removing a part of the surface deposition layer and the first insulating film 12 by CMP, and flattening the surface. (FIG. 3 (h)).
[0064]
  Thereafter, after the work-affected layer of the contact metal 15 is removed by wet etching, a second metal film 16 for forming an upper wiring pattern is formed. The second metal film 16 was made of Al having a thickness of 300 nm, and was deposited on the entire surface by a sputtering method, and then a wiring pattern was formed by photolithography and RIE. (Fig. 3 (i))
  Reference example 2Since the shape of TMR14 is prescribed | regulated by the shape of the connection hole 12a, the resistance value and magnetic characteristic of TMR14 can be controlled to a desired value by changing the shape.
[0065]
  Next, examples of the present invention will be described.
(Example1)
  4 (a) to 4 (k) show the present invention.Example 1It is the schematic diagram which showed the cross section for every manufacturing process. FIG. 4K shows the final shape. That is, this example1In the figure, the TMR element is formed on the lower data line or the metal pad (wiring pattern) 11 for connection to the selection transistor.
[0066]
As shown in FIG. 4 (k), the magnetic element using the ferromagnetic tunnel junction of the present embodiment has a predetermined portion of the first insulating layer 12 formed on the upper surface of the lower wiring pattern 11 formed of a metal film. A TMR element 14 is formed, and a lower electrode 21 of the TMR element 14 is connected to the lower wiring pattern 11. An upper electrode 23 is formed on the lower electrode 21 of the TMR element 14 via a tunnel barrier 22, and the upper electrode 23 is connected to the upper wiring pattern 16 via a hard mask 32 in the second insulating layer 17. is doing.
[0067]
Next, the manufacturing method about these structures is demonstrated.
[0068]
  Up to the process of FIG.Reference example 1Since it is the same as, detailed description thereof is omitted. After the opening 12a is formed in the first insulating film, it is mounted on a vacuum apparatus for film formation, cleaned with Ar ions for surface cleaning, and annealed at 250 ° C. After that, the lower electrode 21 of the TMR element 14 and A five-layer film of W100 nm / Ta100 nm / NiFe5 nm / IrMn5 nm / Co5 nm is formed by sputtering. (FIG. 4 (d)). Next, the surface deposition layer is removed up to the surface of the lower electrode 21 by CMP. (FIG. 4 (e)).
[0069]
Subsequently, the film was mounted on a vacuum apparatus for film formation (not shown), cleaned with Ar ions for surface cleaning, annealed at 250 ° C., and then 1 nm thick Al serving as a tunnel barrier 22 in the same vacuum apparatus.₂O₃Membrane Al₂O₃It is formed by sputtering from a target. Further, a Co5 nm / NiFe 20 nm two-layer film that becomes the upper electrode 23 of the TMR element 14 was deposited by sputtering in the same vacuum apparatus. (FIG. 4 (f)).
[0070]
Thereafter, the resist pattern 13 shown in the figure is formed by a photolithography process. (FIG. 4 (g)). Subsequently, Ti having a film thickness of 200 nm is deposited by an evaporation method, and the resist is removed with a solvent to form a hard mask 32 shown in FIG. Using the Ti film as a mask, the upper electrode 23 is processed by an ion milling method. (FIG. 4 (i)).
[0071]
Here, as shown in the figure, the cross sectional area of the hard mask 32 is set to be larger than the cross sectional area of the lower electrode 21. As a result, even when etching occurs beyond the tunnel barrier 22, the conductive material does not reattach to the side surfaces of the junction, so that deterioration of element characteristics can be prevented. In the configuration of this embodiment, the Al of the tunnel barrier 22 is₂○₃The film and the first insulating film 12 can be used as an etching stop film.
[0072]
In this embodiment, the hard mask 32 made of a Ti film is formed by a so-called lift-off method. As a method for forming the hard mask 32, for example, etching may be performed by RIE or the like after the entire Al film is formed. In that case, it is preferable to form an etching stop film such as Au on the upper electrode 23.
[0073]
In that case, it is necessary to change the materials of the hard mask 32 and the etching stop film to increase the selection ratio at the time of etching such as RIE. In this application, for example, a combination of Al, Pt, and Cu is suitable.
[0074]
After the processing of the upper electrode 23, the SiO mask having a film thickness of 200 nm is formed on the entire surface while leaving the hard mask 32.₂A second insulating film 17 made of is deposited by plasma CVD. Thereafter, until the hard mask 32 is reached, the second insulating film 17 is removed by CMP until the connection hole 17a can be formed in a self-aligning manner (FIG. 4J). (FIG. 4 (k)).
[0075]
In this embodiment, since the hard mask 32 has conductivity, after the processing of the upper electrode 23 is completed, the connection between the upper electrode 23 and the second metal film 16 is obtained without passing through the removal process of the hard mask 32. be able to. The hard mask 32 is made of SiO.₂In the case of using an insulator such as the one described above, a removal step of the hard mask 32 may be inserted between FIG. 4 (j) and FIG. 4 (k).
[0076]
According to the present embodiment, since the shape of the TMR 14 is defined by the shapes of the connection holes 12a and 17a, the resistance value and magnetic characteristics of the TMR 14 can be controlled to desired values by changing the shape.
[0077]
  (Example 2)5 (a) to (j) show the present invention.Example 2It is the schematic diagram which showed the cross section for every manufacturing process. FIG. 5 (j) shows the final shape. That is, this example2In the figure, the TMR element is formed on the lower data line or the metal pad (wiring pattern) 11 for connection to the selection transistor.
[0078]
As shown in FIG. 4 (j), the magnetic element using the ferromagnetic tunnel junction of the present embodiment has a predetermined portion of the first insulating layer 12 formed on the upper surface of the lower wiring pattern 11 formed of a metal film. A lower electrode 21 of the TMR element 14 is formed, and the lower electrode 21 of the TMR element 14 is connected to the lower wiring pattern 11. Further, an upper electrode 23 is formed in the second insulating layer 17 via the tunnel barrier 22 on the lower electrode 21 of the TMR element 14, and the upper electrode 23 is connected to the upper wiring pattern 16.
[0079]
Next, the manufacturing method about these structures is demonstrated.
[0080]
  Up to the process of FIG.Example 1Therefore, the same functional parts as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0081]
That is, after removing the surface deposition layer, it is mounted on a vacuum device for film formation, cleaned with Ar ions for surface cleaning, annealed at 250 ° C., and then the film thickness that will become the tunnel barrier 22 in the same vacuum device 1nm Al₂O₃Membrane Al₂O₃It is formed by sputtering from a target. Further, a passivation film 33 of SiN10 nm is deposited on the tunnel barrier 22 to protect the interface of the tunnel barrier 22. (FIG. 5 (f)) After the passivation film 33 is deposited, the SiOnm film having a thickness of 200 nm is formed on the entire surface.₂A second insulating film 17 made of is deposited by plasma CVD.
[0082]
  Then photo resist(Not shown)Photoresist by coating process, exposure process and development process(Not shown)An opening for defining the embedded portion is formed in the substrate.
[0083]
  Next, the second insulating film 17 is etched until reaching the pan passivation film 33 by RIE using a fluorocarbon-based reaction gas. At this time, the passivation film 33 functions as an etching stopper film. Thereafter, the passivation film 33 is first removed by wet etching. Next, after mounting on a vacuum apparatus for film formation and performing annealing at 250 ° C. for surface cleaning, a two-layer film of Co5 nm / NiFe 20 nm to be the upper electrode 23 of the TMR element 14 is further added.Contact metal (not shown)As a film, 300 nm thick Al was deposited by sputtering. (FIG. 5 (h)).
[0084]
Thereafter, the connection hole 17a is formed in a self-aligning manner by removing the surface deposition layer and the second insulating film 17 by CMP from the vacuum apparatus. (FIG. 5I) Thereafter, the second metal film 16 for forming the upper wiring pattern is formed. The second metal film 16 was made of Al having a thickness of 300 nm, and was deposited on the entire surface by a sputtering method, and then a wiring pattern was formed by photolithography and RIE. (Fig. 5 (j))
According to the present embodiment, since the shape of the TMR 14 is defined by the shapes of the connection holes 12a and 17a, the resistance value and magnetic characteristics of the TMR 14 can be controlled to desired values by changing the shape.
[0085]
As described above in detail, by using the magnetic element of the present invention and the manufacturing method thereof, the use of an etching method by physical sputtering such as an ion milling method can be suppressed as much as possible.
[0086]
As a result, it becomes possible to reduce the influence of re-attachment of a workpiece, reduction of dimensional conversion difference, and electrostatic breakdown, which cause deterioration of wafer characteristics and yield reduction.
[0087]
【The invention's effect】
According to the present invention, a magnetic element having a ferromagnetic tunnel junction and a large storage capacity can be obtained with a high yield.
[Brief description of the drawings]
FIG. 1 is a schematic layout diagram of a magnetic memory device in which a magnetic element of the present invention is formed.
FIG. 2 of the present inventionReference examplesThe schematic diagram which showed the cross section of the element for every manufacturing process.
FIG. 3 of the present inventionThe manufacturing process of the reference exampleThe schematic diagram which showed the cross section of the element for every manufacturing process.
FIG. 4 is a schematic diagram showing a cross section of an element for each manufacturing process according to an embodiment of the present invention.
FIG. 5 is a schematic view showing a cross section of an element for each manufacturing process according to an embodiment of the present invention.

Claims (4)

A first wiring pattern provided on a semiconductor substrate, a first insulating layer provided on the semiconductor substrate and the first wiring pattern, and a second insulating layer formed on the first insulating layer A first connection hole formed at a predetermined position on the wiring pattern of the first insulating layer, and a second connection formed in the second insulating layer formed in communication with an upper portion of the first connection hole A ferromagnetic tunnel junction in which a hole, a first ferromagnetic electrode formed in the first connection hole, and a second ferromagnetic electrode formed in the second connection hole constitute a tunnel junction through a tunnel barrier layer And a magnetic element comprising a connection plug connected to the ferromagnetic tunnel junction and a second wiring pattern connected to the connection plug, wherein the first ferromagnetic electrode and the second ferromagnetic electrode are respectively Shaped by first and second connection holes It is defined, and the lower bottom area of the second ferromagnetic electrode, the magnetic element characterized by larger top area of the first ferromagnetic electrode. Forming a first wiring pattern on the semiconductor substrate; forming a first insulating film on the semiconductor substrate and the first wiring pattern; and selectively removing the first insulating film. Forming a first connection hole reaching the wiring pattern; forming a first ferromagnetic electrode film in the first connection hole and on the first insulating film; and the first on the first insulating film. Removing the ferromagnetic electrode film to leave the first ferromagnetic electrode film in the first connection hole; and an upper surface of the first ferromagnetic electrode film left in the first connection hole; Forming a tunnel barrier layer on the first insulating film; depositing a passivation film on the tunnel barrier layer; and forming a second insulating film on the passivation film; and the second insulating film and the passivation. Selectively remove the membrane Forming a second connection hole having a lower bottom area larger than an upper area of the first connection hole reaching the tunnel barrier layer; and a second ferromagnetic electrode film in the second connection hole and on the second insulating film Forming, removing the second ferromagnetic electrode film on the second insulating film, leaving the second ferromagnetic electrode film in the second connection hole, and the second ferromagnetic electrode And forming a second wiring pattern electrically connected to the film on the second insulating film. Forming a first wiring pattern on the semiconductor substrate; forming a first insulating film on the semiconductor substrate and the first wiring pattern; and selectively removing the first insulating film. Forming a first connection hole reaching the wiring pattern; forming a first ferromagnetic electrode film in the first connection hole and on the first insulating film; and the first on the first insulating film. Removing the ferromagnetic electrode film to leave the first ferromagnetic electrode film in the first connection hole; and an upper surface of the first ferromagnetic electrode film left in the first connection hole; Forming a tunnel barrier layer on the first insulating film; depositing a passivation film on the tunnel barrier layer; and forming a second insulating film on the passivation film; and the second insulating film and the passivation. Selectively remove the membrane Forming a second connection hole having a lower bottom area larger than an upper area of the first connection hole reaching the tunnel barrier layer; a second ferromagnetic electrode film in the second connection hole and on the second insulating film; Forming a connection plug film; and removing the second ferromagnetic electrode film and the connection plug film on the second insulating film to form the second ferromagnetic electrode film and the connection in the second connection hole A method of manufacturing a magnetic element, comprising: a step of leaving a plug film; and a step of forming a second wiring pattern electrically connected to the connection plug film on the second insulating film. Forming a first wiring pattern on the semiconductor substrate; forming a first insulating film on the semiconductor substrate and the first wiring pattern; and selectively removing the first insulating film. Forming a first connection hole reaching the wiring pattern; forming a first ferromagnetic electrode film in the first connection hole and on the first insulating film; and the first on the first insulating film. Removing the ferromagnetic electrode film to leave the first ferromagnetic electrode film in the first connection hole; and an upper surface of the first ferromagnetic electrode film left in the first connection hole; Tunnel burr on the first insulating film Forming a second layer, forming a second ferromagnetic electrode film on the tunnel barrier layer, and forming the first ferromagnetic electrode film in the first connection hole on the second ferromagnetic electrode film. Forming a hard mask having a cross-sectional area larger than the upper area of the substrate, processing the second ferromagnetic electrode film using the hard mask, processing the second ferromagnetic electrode film and the first Forming a second insulating film on the insulating film; and selectively removing the second insulating film located on the processed second ferromagnetic electrode film to form the second ferromagnetic electrode film. Forming a second wiring pattern to be electrically connected on the second insulating film. A method of manufacturing a magnetic element, comprising:

Images