JP3869025B2

JP3869025B2 - Manufacturing method of semiconductor memory device

Info

Publication number: JP3869025B2
Application number: JP33824994A
Authority: JP
Inventors: 茂樹天野; 康夫佐藤
Original assignee: 聯華電子股▲ふん▼有限公司
Priority date: 1993-12-28
Filing date: 1994-12-27
Publication date: 2007-01-17
Anticipated expiration: 2022-01-17
Also published as: JPH07235613A

Description

【０００１】
【産業上の利用分野】
本発明は、ＤＲＡＭ（Dynamic Random Access Memory）等の半導体記憶装置及びその製造方法に関する。
【０００２】
【従来の技術】
従来、ＤＲＡＭ等の半導体記憶装置においては、製造プロセスのランダムな欠陥による歩留り低下を防止するために、冗長回路方式が採用されている。即ち、ＤＲＡＭ等では、膨大な数のメモリセルを１チップ内に集積することにより記憶容量を増大させているが、チップ内に、欠陥のあるメモリセルが１個あるだけでそのチップは不良となり、歩留りが低下する。
【０００３】
冗長回路方式では、例えば、欠陥を生じたメモリセルに接続されたアドレス指定用のワードライン又はビットラインがアドレスデコーダから切り離されるとともに、予備メモリセルに接続されたアドレス指定用のワードライン又はビットラインがアドレスデコーダと接続される。これによって、欠陥を生じたメモリセルを予備メモリセルに置き換えることができ、歩留りが向上する。
【０００４】
予備メモリセルへの切り換えを行う具体的な方法としては、例えば、レーザービームスポットによりヒューズを切断して、欠陥を生じたメモリセルを予備のメモリセルに置き換えるという、レーザーヒューズ方式が広く用いられている。
【０００５】
また、電気的にヒューズを溶断する電気ヒューズ方式も広く用いられており、例えば、特開昭６０−６５５４５号公報、特開昭６２−１３９１９８号公報、特開平４−１４７００号公報等に開示されている。
【０００６】
【発明が解決しようとする課題】
しかしながら、上記レーザーヒューズ方式では、テスターからの情報によりレーザービーム位置を制御してレーザービームを照射する工程が比較的繁雑であり、また、高精度位置制御機能を持つレーザービームスポット照射装置が必要であるという問題があった。更に、ヒューズ切断の際に周辺回路に与えるダメージの問題もあった。
【０００７】
一方、電気ヒューズ方式でも、ヒューズを電気的に溶断する際の周辺回路への影響や基板へのダメージが問題となっていた。
【０００８】
そこで、本発明の目的は、周辺回路や基板にダメージを与えることなく冗長回路のメモリセルへの切り換えを行うことができる半導体記憶装置及びその製造方法を提供することである。
【０００９】
【課題を解決するための手段】
上述の課題を解決するために、本発明では、半導体基板の第１の素子形成領域に第１の絶縁膜と第１の導電性膜とが順次形成され、前記半導体基板の第２の素子形成領域に第２の絶縁膜と第２の導電性膜とが順次形成され、前記第１の素子形成領域にはＭＯＳトランジスタ及びこのＭＯＳトランジスタの一対の不純物拡散層の一方に接続された下部電極を有するキャパシタが形成され、前記第２の素子形成領域には電気的に書き換えが可能な不揮発性の浮遊ゲート型トランジスタが形成された半導体記憶装置の製造方法において、前記第２の素子形成領域において前記第２の導電性膜に接し、且つ、前記第１の素子形成領域において前記不純物拡散層の一方に接する第３の導電性膜を形成する工程と、前記第１の素子形成領域及び前記第２の素子形成領域において、前記第３の導電性膜の上に誘電体膜を形成する工程と、前記第１の素子形成領域及び前記第２の素子形成領域において、前記誘電体膜の上に第４の導電性膜を形成する工程と、前記第４の導電性膜、前記誘電体膜及び前記第３の導電性膜をパターニングして、前記第１の素子形成領域には、前記第４の導電性膜を上部電極とし、前記第３の導電性膜を前記下部電極とする前記キャパシタを形成するとともに、前記第２の素子形成領域には、前記第４の導電性膜を制御ゲートとし、前記第２の導電性膜及び前記第３の導電性膜を浮遊ゲートとする前記浮遊ゲート型トランジスタの複合ゲート部を形成する工程とを備えている。
【００１４】
本発明の一態様においては、前記誘電体膜の上に前記第４の導電性膜を形成した後、前記複合ゲート部を形成する工程において、前記誘電体膜と前記第４の導電性膜とを同時にパターニングする。
【００１５】
本発明の一態様においては、前記誘電体膜の上に前記第４の導電性膜を形成した後、前記複合ゲート部を形成する工程において、前記第３の導電性膜と前記誘電体膜と前記第４の導電性膜とを同時にパターニングする。
【００１６】
本発明の一態様においては、前記第３の導電性膜を形成した後、少なくとも前記第３の導電性膜をパターニングすることにより、前記第１の素子形成領域の前記不純物拡散層の一方に接する前記第３の導電性膜と、前記第２の素子形成領域の前記第２の導電性膜に接する前記第３の導電性膜とを分離する工程を有する。
【００１７】
本発明の一態様においては、前記第３の導電性膜の上に前記誘電体膜を形成した後、前記誘電体膜をパターニングすることにより、前記第１の素子形成領域の前記誘電体膜と、前記第２の素子形成領域の前記誘電体膜とを分離する工程を有する。
【００１８】
本発明の一態様においては、前記第３の導電性膜を形成する前に、前記第１の素子形成領域において前記ＭＯＳトランジスタの前記不純物拡散層の一方に達する前記第１のコンタクト孔と、前記第２の素子形成領域において前記第２の導電性膜に達する前記第２のコンタクト孔とを有する層間絶縁膜を形成し、前記第３の導電性膜が前記第１のコンタクト孔及び前記第２のコンタクト孔の内面から前記層間絶縁膜の上に延びるように形成する。
【００１９】
本発明の一態様においては、半導体基板の第１の素子形成領域に第１の絶縁膜と第１の導電性膜とが順次形成され、前記半導体基板の第２の素子形成領域に第２の絶縁膜と第２の導電性膜とが順次形成され、前記第１の素子形成領域にはＭＯＳトランジスタ及びこのＭＯＳトランジスタの一対の不純物拡散層の一方に接続された下部電極を有するキャパシタが形成され、前記第２の素子形成領域には電気的に書き換えが可能な不揮発性の浮遊ゲート型トランジスタが形成された半導体記憶装置の製造方法において、前記第１の素子形成領域及び前記第２の素子形成領域に層間絶縁膜を形成し、前記第１の素子形成領域において前記ＭＯＳトランジスタの前記不純物拡散層の一方に達する第１のコンタクト孔を前記層間絶縁膜に形成し、前記第２の素子形成領域において前記第２の導電性膜に達する第２のコンタクト孔を前記層間絶縁膜に形成する工程と、前記第１の素子形成領域及び前記第２の素子形成領域に第３の導電性膜を形成し、前記第３の導電性膜をパターニングすることにより、前記第１のコンタクト孔から前記層間絶縁膜の上に延びる前記第３の導電性膜のパターンを形成する工程と、前記第２の素子形成領域の前記第２のコンタクト孔における前記第２の導電性膜の上及び前記第１の素子形成領域の前記第３の導電性膜の上に誘電体膜を形成する工程と、前記誘電体膜の上に第４の導電性膜を形成する工程と、前記誘電体膜及び前記第４の導電性膜をパターニングすることにより、前記第１の素子形成領域には、前記第４の導電性膜を上部電極とし、前記第３の導電性膜を前記下部電極とする前記キャパシタを形成するとともに、前記第２の素子形成領域には、前記第４の導電性膜を制御ゲートとし、前記第２の導電性膜を浮遊ゲートとする前記浮遊ゲート型トランジスタの複合ゲート部を形成する工程とを備えている。
【００２０】
本発明の一態様においては、前記誘電体膜をパターニングしてから前記誘電体膜の上に前記第４の導電性膜を形成する。
【００２１】
本発明の一態様においては、前記誘電体膜の上に前記第４の導電性膜を形成した後、前記複合ゲート部を形成する工程において、前記誘電体膜と前記第４の導電性膜とを同時にパターニングする。
【００２２】
本発明の一態様においては、前記第３の導電性膜の上に前記誘電体膜を形成した後、前記誘電体膜をパターニングすることにより、前記第１の素子形成領域の前記誘電体膜と、前記第２の素子形成領域の前記誘電体膜とを分離する工程を有する。
【００２３】
本発明の一態様においては、前記第１の絶縁膜及び前記第２の絶縁膜を同じ材料で同時に形成し、前記第１の導電性膜及び前記第２の導電性膜を同じ材料で同時に形成する。
【００２４】
本発明の一態様においては、１個のＭＯＳトランジスタと１個のキャパシタとから構成された第１のメモリセルからなる第１のメモリセルアレイを半導体基板の第１の素子形成領域に備え、電気的に書き換えが可能で浮遊ゲートと制御ゲートとを有する不揮発性の第２のメモリセルからなる第２のメモリセルアレイを前記半導体基板の第２の素子形成領域に備えた半導体記憶装置の製造方法において、前記第１の素子形成領域の前記半導体基板の上及び前記第２の素子形成領域の前記半導体基板の上に、第１の絶縁膜をそれぞれ形成する工程と、前記第１の素子形成領域の前記第１の絶縁膜の上及び前記第２の素子形成領域の前記第１の絶縁膜の上に第１の導電性膜をそれぞれ形成した後、前記第１の素子形成領域の前記第１の導電性膜を前記ＭＯＳトランジスタのゲート電極の形状にパターニングするとともに、前記第２の素子形成領域の前記第１の導電性膜を前記浮遊ゲートの形状にパターニングする工程と、前記ＭＯＳトランジスタの前記ゲート電極の両側の前記第１の素子形成領域及び前記浮遊ゲートの両側の前記第２の素子形成領域にイオン注入を行って、前記第１の素子形成領域及び前記第２の素子形成領域に一対の不純物拡散層をそれぞれ形成する工程と、前記半導体基板の全面に第２の絶縁膜を形成した後、前記第１の素子形成領域において前記不純物拡散層の一方に達する第１の開孔を前記第２の絶縁膜に形成し、前記第２の素子形成領域において前記第１の導電性膜に達する第２の開孔を前記第２の絶縁膜に形成する工程と、前記第１の開孔及び前記第２の開孔をそれぞれ埋め込むように第２の導電性膜を形成した後、前記第１の素子形成領域の前記第２の導電性膜と前記第２の素子形成領域の前記第２の導電性膜とを分離するようにパターニングする工程と、前記第２の導電性膜の上に誘電体膜を形成してから前記誘電体膜の上に第３の導電性膜を形成し、前記第１の素子形成領域の前記第３の導電性膜と前記第２の素子形成領域の前記第３の導電性膜とを分離するようにパターニングする工程とを備えている。
【００２５】
本発明の一態様においては、前記第２の導電性膜の上に前記誘電体膜を形成した後、前記誘電体膜をパターニングすることにより、前記第１の素子形成領域の前記誘電体膜と、前記第２の素子形成領域の前記誘電体膜とを分離する。
【００２６】
本発明の一態様においては、１個のＭＯＳトランジスタと１個のキャパシタとから構成された第１のメモリセルからなる第１のメモリセルアレイを半導体基板の第１の素子形成領域に備え、電気的に書き換えが可能で浮遊ゲートと制御ゲートとを有する不揮発性の第２のメモリセルからなる第２のメモリセルアレイを前記半導体基板の第２の素子形成領域に備えた半導体記憶装置の製造方法において、前記第１の素子形成領域の前記半導体基板の上及び前記第２の素子形成領域の前記半導体基板の上に第１の絶縁膜を形成する工程と、前記第１の素子形成領域の前記第１の絶縁膜の上及び前記第２の素子形成領域の前記第１の絶縁膜の上に第１の導電性膜を形成した後、前記第１の素子形成領域の前記第１の導電性膜を前記ＭＯＳトランジスタのゲート電極の形状にパターニングするとともに、前記第２の素子形成領域の前記第１の導電性膜を前記浮遊ゲートの形状にパターニングする工程と、前記ＭＯＳトランジスタの前記ゲート電極の両側の前記第１の素子形成領域及び前記浮遊ゲートの両側の前記第２の素子形成領域にイオン注入を行って、前記第１の素子形成領域及び前記第２の素子形成領域に一対の不純物拡散層をそれぞれ形成する工程と、前記半導体基板の全面に第２の絶縁膜を形成した後、前記第１の素子形成領域において前記不純物拡散層の一方に達する第１の開孔を前記第２の絶縁膜に形成する工程と、前記第１の開孔を埋め込むように形成した第２の導電性膜をパターニングすることにより、前記第１の開孔から前記第２の絶縁膜の上に延びる前記第２の導電性膜のパターンを形成する工程と、前記第２の素子形成領域において前記第１の導電性膜に達する第２の開孔を前記第２の絶縁膜に形成する工程と、前記第１の素子形成領域の前記第２の導電性膜の上及び前記第２の素子形成領域の前記第２の開孔における前記第１の導電性膜の上に誘電体膜を形成してから前記誘電体膜の上に第３の導電性膜を形成し、前記第１の素子形成領域の前記第３の導電性膜と前記第２の素子形成領域の前記第３の導電性膜とを分離するようにパターニングする工程とを備えている。
【００２７】
本発明の一態様においては、前記第１の素子形成領域の前記第２の導電性膜の上及び前記第２の素子形成領域の前記第２の開孔における前記第１の導電性膜の上に前記誘電体膜を形成した後、前記誘電体膜をパターニングすることにより、前記第１の素子形成領域の前記誘電体膜と、前記第２の素子形成領域の前記誘電体膜とを分離する。
【００２８】
【作用】
本発明の半導体記憶装置においては、電気的に書き換えが可能な不揮発性のメモリセルをヒューズの代わりに用いるので、従来のようなヒューズ切断の際の周辺回路や基板へのダメージがなくなる。
【００２９】
また、本発明の半導体記憶装置の製造方法によれば、浮遊ゲート型の不揮発性のメモリセルを、特に工程数を増やすことなく、例えばＤＲＡＭメモリセルと同時に製造することができる。
【００３０】
【実施例】
以下、本発明をＤＲＡＭに適用した実施例につき添付図面を参照して説明する。
【００３１】
本発明の半導体記憶装置の第１実施例によるＤＲＡＭは、図１に示すように、アレイ状に配置された複数個のＤＲＡＭメモリセル２３（図２参照）からなるＤＲＡＭメモリセルアレイ１０１を備えた本体部１００と、アレイ状に配置された複数個のＤＲＡＭメモリセル２３からなる予備用ＤＲＡＭメモリセルアレイ１１１を備えた、冗長回路を構成する予備部１１０と、ＤＲＡＭメモリセルアレイ１０１および予備用ＤＲＡＭメモリセルアレイ１１１のアドレスを指定するためのアドレスデコーダ１２０と、アドレスデコーダ１２０に接続された、電気的に書き換えが可能な複数個の不揮発性メモリセル２４（図３参照）からなる不良ビット切り換え制御回路１３０とからなる。
【００３２】
ＤＲＡＭメモリセル２３は、図２に示すように、ゲート酸化膜４、ゲート酸化膜４上に形成されたゲート電極５、ゲート電極５の両側に形成されたサイドウォールスペーサー９、シリコン基板１内のサイドウォールスペーサー９下に形成された一対のＮ^-不純物拡散層８およびＮ^-不純物拡散層８の両側に形成された一対のＮ⁺型不純物拡散層１０からなる１個のＭＯＳトランジスタと、キャパシタ下部電極１３、キャパシタ誘電体膜１５およびキャパシタ上部電極１７からなる１個のキャパシタとで構成されている。
【００３３】
また、不揮発性メモリセル２４は、図３に示すように、トンネル酸化膜６と、トンネル酸化膜６上に形成された浮遊ゲート下部７′と、浮遊ゲート下部７′上に形成された浮遊ゲート上部７″と、浮遊ゲート上部７″上に形成された誘電体膜１６と、誘電体膜１６上に形成された制御ゲート１８と、浮遊ゲート下部７′の両側に形成されたサイドウォールスペーサー９と、シリコン基板１内のサイドウォールスペーサー９下に形成された一対のＮ^-不純物拡散層８と、Ｎ^-不純物拡散層８の両側に形成された一対のＮ⁺型不純物拡散層１０とからなる。
【００３４】
本実施例のＤＲＡＭにおいては、本体部１００のＤＲＡＭメモリセルアレイ１０１を構成する複数個のＤＲＡＭメモリセル２３のうちの１個に欠陥が生じた場合には、欠陥が生じたＤＲＡＭメモリセル２３のアドレス指定用のワードライン（又はビットライン）とアドレスデコーダ１２０とを切り離すため、複数個の不揮発性メモリセル２４のうちの対応する不揮発性メモリセル２４が、不良ビット切り換え制御回路１３０に入力される不良ビット切り換え信号１５０でＯＮからＯＦＦに切り換えられる。また、欠陥が生じたＤＲＡＭメモリセル２３の代わりに用いる予備用のＤＲＡＭメモリセルアレイ１１１のＤＲＡＭメモリセル２３のアドレス指定用のワードライン（又はビットライン）とアドレスデコーダ１２０とを接続するため、複数個の不揮発性メモリセル２４のうちの別の対応する不揮発性メモリセル２４が、不良ビット切り換え制御回路１３０に入力される不良ビット切り換え信号１５０でＯＦＦからＯＮに切り換えられる。
【００３５】
尚、上に説明した実施例では、不揮発性メモリセルとして、フローティングゲート型のものを示したが、不揮発性メモリセルとしては、シリコン窒化膜とシリコン酸化膜との界面に電荷を蓄積するＭＮＯＳ型のメモリセルを用いることもできる。
【００３６】
次に、図２に示すＤＲＡＭメモリセル２３をシリコン基板１の第１の素子形成領域Ｒ１に形成するとともに、図３に示す不揮発性メモリセル２４をシリコン基板１の第２の素子形成領域Ｒ２に形成することにより、図１に示したＤＲＡＭを製造する方法について、図４及び図５を参照して説明する。
【００３７】
Ｐ型のシリコン基板１上にパッド用のシリコン酸化膜及びシリコン窒化膜（いずれも図示せず）を順次形成し、素子形成領域Ｒ１、Ｒ２以外のシリコン窒化膜をフォトレジスト（図示せず）をマスクとした異方性ドライエッチングにより除去する。不純物、例えばＢＦ₂ をシリコン基板１にイオン注入して、図４（ａ）に示すように、チャネルストッパーとなるＰ⁺不純物拡散層２を形成する。フォトレジストを除去した後、表面を洗浄する。Ｈ₂ Ｏ雰囲気において温度１１００℃の熱処理を行い、シリコン基板１を選択酸化（ＬＯＣＯＳ）することによって、素子形成領域以外の素子分離領域Ｒ１、Ｒ２に素子分離絶縁膜３を形成する。しかる後、熱処理のマスクとなったシリコン窒化膜を除去する。
【００３８】
次に、図４（ｂ）に示すように、犠牲酸化膜（図示せず）を形成除去した後、第１の素子形成領域Ｒ１ではゲート酸化膜４となり第２の素子形成領域Ｒ２では不揮発性メモリセルのトンネル酸化膜６となる膜厚１０〜２０ｎｍ程度のシリコン酸化膜を素子形成領域Ｒ１、Ｒ２の全面に形成する（第１の工程）。その後、閾値制御用の不純物、例えばＢＦ₂ をシリコン基板１にイオン注入した後、全面に多結晶シリコン膜を形成する。この多結晶シリコン膜にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜をＮ型にする。Ｎ型にした多結晶シリコン膜上にフォトレジスト（図示せず）を塗布し、そのフォトレジストをパターニングする。パターニングされたフォトレジストをマスクとして多結晶シリコン膜を異方性ドライエッチングし、第１の素子形成領域Ｒ１にはＭＯＳトランジスタのゲート電極５を形成するとともに、第２の素子形成領域Ｒ２には不揮発性メモリセル２４のフローティングゲート（浮遊ゲート）の下部７′を形成する（第２の工程）。
【００３９】
次に、図４（ｃ）に示すように、フォトレジストを除去した後、素子分離絶縁膜３、ゲート電極５及び浮遊ゲートの下部７′をマスクとしてＮ型の不純物、例えばリン（Ｐ）をシリコン基板１の全面にイオン注入し、第１の素子形成領域Ｒ１及び第２の素子形成領域Ｒ２に一対のＮ^-不純物拡散層８をそれぞれ形成する。シリコン基板１の全面にシリコン酸化膜を形成し、このシリコン酸化膜を異方性ドライエッチングすることにより、ゲート電極５及び浮遊ゲート下部７′の両側にサイドウォールスペーサー９をそれぞれ形成する。その後、素子分離絶縁膜３、ゲート電極５、浮遊ゲート下部７′及びサイドウォールスペーサー９をマスクとしてＮ型の不純物、例えばリン（Ｐ）をシリコン基板１の全面にイオン注入し、第１の素子形成領域Ｒ１及び第２の素子形成領域Ｒ２に一対のＮ⁺不純物拡散層１０をそれぞれ形成する（第３の工程）。これにより、シリコン基板１内にＬＤＤ（Lightly Doped Drain)構造の不純物拡散層が形成される。
【００４０】
次に、図４（ｄ）に示すように、シリコン基板１の全面にシリコン酸化膜１１を形成する（第４の工程）。その後、フォトレジスト（図示せず）をマスクとした異方性ドライエッチングを行い、第１の素子形成領域Ｒ１ではドレインとなる不純物拡散層１０の上、第２の素子形成領域Ｒ２では浮遊ゲート下部７′の上に存在するシリコン酸化膜１１を除去して、コンタクト孔１２、１２′を同時に開孔する（第５の工程）。そして、フォトレジストを除去した後、シリコン基板１の全面に多結晶シリコン膜を形成し、この多結晶シリコン膜にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜をＮ型にする。しかる後、Ｎ型多結晶シリコン膜上にフォトレジスト（図示せず）をパターン形成し、そのフォトレジストをマスクとして多結晶シリコン膜をエッチング除去して、第１の素子形成領域Ｒ１にキャパシタ下部電極１３、第２の素子形成領域Ｒ２に浮遊ゲート上部７″をそれぞれ形成する（第６の工程）。しかる後、フォトレジストを除去する。
【００４１】
次に、図５（ａ）に示すように、シリコン酸化膜とシリコン窒化膜とシリコン酸化膜とからなるＯＮＯ膜により、第１の素子形成領域Ｒ１では、キャパシタ下部電極１３の上にキャパシタ誘電体膜１５、第２の素子形成領域Ｒ２では、浮遊ゲート上部７″の上に誘電体膜１６をそれぞれ形成する（第７の工程）。この時、ＯＮＯ膜の代わりに、タンタルオキサイド（Ｔａ₂ Ｏ₅ ）やＰＺＴを含む強誘電体膜を形成してもよい。
【００４２】
次に、図５（ｂ）に示すように、シリコン基板１の全面に多結晶シリコン膜を形成した後、この多結晶シリコン膜にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜をＮ型にする。Ｎ型にした多結晶シリコン膜上にフォトレジスト（図示せず）をパターン形成し、そのフォトレジストをマスクとして多結晶シリコン膜をエッチング除去して、第１の素子形成領域Ｒ１にキャパシタ上部電極１７、第２の素子形成領域Ｒ２にコントロールゲート（制御ゲート）１８をそれぞれ形成する（第８の工程）。しかる後、フォトレジストを除去し、シリコン基板１の全面にシリコン酸化膜１９を形成する。
【００４３】
次に、図５（ｃ）に示すように、シリコン基板１の全面にフォトレジスト（図示せず）を形成した後、そのフォトレジストをパターニングする。そのフォトレジストをマスクとした異方性ドライエッチングを行い、第１の素子形成領域Ｒ１のソースとなる不純物拡散層１０の上、第２の素子形成領域Ｒ２のソース／ドレインとなる一対の不純物拡散層１０の上にそれぞれコンタクト孔２０、２０′、２０″を開孔する。
【００４４】
次に、図５（ｄ）に示すように、フォトレジストを除去した後、スパッタ法によりアルミニウム膜をシリコン基板１の全面に形成し、このアルミニウム膜の上にフォトレジスト（図示せず）をパターン形成して、そのフォトレジストをマスクとして所定パターンのアルミ配線２１を形成する。そして、フォトレジストを除去した後、シリコン基板１の全面にシリコン酸化膜２２を形成する。
【００４５】
以上の工程により、第１の素子形成領域Ｒ１に１トランジスタ／１キャパシタ型のＤＲＡＭメモリセル２３が、第２の素子形成領域Ｒ２に、電気的に書き換えが可能な不揮発性メモリセル２４が形成される。
【００４６】
以上に説明したＤＲＡＭの製造方法によれば、ＤＲＡＭメモリセル２３を形成する通常のＭＯＳプロセスの工程数を特に増やすことなく、同一シリコン基板１上に浮遊ゲート型の不揮発性のメモリセル２４を形成することができる。
【００４７】
次に、本発明の半導体記憶装置の第２実施例につき図６〜図９を参照して説明する。
【００４８】
本実施例のＤＲＡＭの構成は、図１の構成と同じであり、またＤＲＡＭメモリセルも図６に示すように図２のＤＲＡＭメモリセル２３と同じである。しかし、不揮発性メモリセル２４′は図７に示すように浮遊ゲート７上に誘電体膜１６を形成する点で、浮遊ゲート７に相当する浮遊ゲート下部７′上に浮遊ゲート上部７″を介して誘電体膜１６を形成する図３の不揮発性メモリセル２４と異なる。
【００４９】
図７の不揮発性メモリセル２４′では、浮遊ゲート７上に誘電体膜１６を形成するため、浮遊ゲートの容量が図３の不揮発性メモリセル２４のそれよりも小さくなる。従って、図３の不揮発性メモリセル２４は通常ＯＮ状態で使用されるのが好ましく、図７の不揮発性メモリセル２４′は通常時ＯＦＦ状態で使用されるのが好ましい。
【００５０】
以下、図８及び図９を参照して本実施例のＤＲＡＭ製造方法について説明するが、ＤＲＡＭメモリセルの構成要素については図２で用いた符号を用い、不揮発性メモリセル２４′の構成要素については浮遊ゲート７以外は図３で用いた符号を用いる。また、本実施例でも、図６に示すＤＲＡＭメモリセル２３をシリコン基板１の第１の素子形成領域Ｒ１に形成するとともに、図７に示す不揮発性メモリセル２４′をシリコン基板１の第２の素子形成領域Ｒ２に形成する。
【００５１】
Ｐ型のシリコン基板１上にパッド用のシリコン酸化膜及びシリコン窒化膜（いずれも図示せず）を順次形成し、素子形成領域Ｒ１、Ｒ２以外のシリコン窒化膜をフォトレジスト（図示せず）をマスクとした異方性ドライエッチングにより除去する。そして、不純物、例えばＢＦ₂ をシリコン基板１にイオン注入して、図８（ａ）に示すように、チャネルストッパーとなるＰ⁺不純物拡散層２を形成する。フォトレジストを除去した後、表面を洗浄する。この後、Ｈ₂ Ｏ雰囲気において温度１１００℃の熱処理を行い、シリコン基板１を選択酸化（ＬＯＣＯＳ）することによって、素子形成領域Ｒ１、Ｒ２以外の素子分離領域に素子分離絶縁膜３を形成する。しかる後、熱処理のマスクとなったシリコン窒化膜を除去する。
【００５２】
次に、図８（ｂ）に示すように、犠牲酸化膜（図示せず）を形成除去した後、第１の素子形成領域Ｒ１ではゲート酸化膜４、第２の素子形成領域Ｒ２では不揮発性メモリセルのトンネル酸化膜６となる膜厚１０〜２０ｎｍ程度のシリコン酸化膜を素子形成領域Ｒ１、Ｒ２の全面に形成する（第１の工程）。その後、閾値制御用の不純物、例えばＢＦ₂ をシリコン基板１にイオン注入する。しかる後、シリコン基板１の全面に多結晶シリコン膜を形成し、この多結晶シリコン膜にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜をＮ型にする。この後、Ｎ型にした多結晶シリコン膜上にフォトレジスト（図示せず）を塗布し、そのフォトレジストをパターニングする。そして、そのパターニングされたフォトレジストをマスクとして多結晶シリコン膜を異方性ドライエッチングし、第１の素子形成領域Ｒ１にはＭＯＳトランジスタのゲート電極５、第２の素子形成領域Ｒ２には不揮発性メモリセル２４′のフローティングゲート（浮遊ゲート）７を同時に形成する（第２の工程）。
【００５３】
次に、図８（ｃ）に示すように、フォトレジストを除去した後、素子分離絶縁膜３、ゲート電極５及び浮遊ゲート７をマスクとしてＮ型の不純物、例えばリン（Ｐ）をシリコン基板１の全面にイオン注入し、第１の素子形成領域Ｒ１及び第２の素子形成領域Ｒ２に一対のＮ^-不純物拡散層８をそれぞれ形成する。しかる後、シリコン基板１の全面にシリコン酸化膜を形成し、このシリコン酸化膜を異方性ドライエッチングすることにより、ゲート電極５及び浮遊ゲート７のそれぞれにサイドウォールスペーサー９を形成する。そして、素子分離絶縁膜３、ゲート電極５、浮遊ゲート７及びサイドウォールスペーサー９をマスクとしてＮ型の不純物、例えばリン（Ｐ）をシリコン基板１の全面にイオン注入し、第１の素子形成領域Ｒ１及び第２の素子形成領域Ｒ２のそれぞれに一対のＮ⁺不純物拡散層１０を形成する（第３の工程）。これにより、シリコン基板１内にＬＤＤ構造の不純物拡散層が形成される。
【００５４】
次に、図８（ｄ）に示すように、シリコン基板１の全面にシリコン酸化膜１１を形成する（第４の工程）。その後、フォトレジスト（図示せず）をマスクとした異方性ドライエッチングを行い、第１の素子形成領域Ｒ１ではドレインとなる不純物拡散層１０の上、第２の素子形成領域Ｒ２では浮遊ゲート７の上に存在するシリコン酸化膜１１を除去して、コンタクト孔１２、１２′を同時に開孔する（第５の工程）。そして、フォトレジストを除去した後、シリコン基板１の全面に多結晶シリコン膜を形成し、この多結晶シリコン膜にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜をＮ型にする。しかる後、Ｎ型にした多結晶シリコン膜上にフォトレジスト（図示せず）をパターン形成し、そのフォトレジストをマスクとして多結晶シリコン膜をエッチング除去して、第１の素子形成領域Ｒ１にキャパシタの下部電極１３を形成する（第６の工程）。この時、本実施例では、第２の素子形成領域Ｒ２の浮遊ゲート７の上に形成した多結晶シリコン膜を実質上全て除去する。しかる後、フォトレジストを除去する。
【００５５】
次に、図９（ａ）に示すように、シリコン酸化膜とシリコン窒化膜とシリコン酸化膜とからなるＯＮＯ膜により、第１の素子形成領域Ｒ１では、キャパシタの下部電極１３の上にキャパシタ誘電体膜１５、第２の素子形成領域Ｒ２では、浮遊ゲート７の上に誘電体膜１６をそれぞれ形成する（第７の工程）。この時、ＯＮＯ膜の代わりに、タンタルオキサイド（Ｔａ₂ Ｏ₅ ）やＰＺＴを含む強誘電体膜を形成してもよい。
【００５６】
次に、図９（ｂ）に示すように、全面に多結晶シリコン膜を形成した後、この多結晶シリコン膜にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜をＮ型にする。しかる後、Ｎ型にした多結晶シリコン膜上にフォトレジスト（図示せず）をパターン形成し、そのフォトレジストをマスクとして多結晶シリコン膜をエッチング除去して、第１の素子形成領域Ｒ１にキャパシタの上部電極１７、第２の素子形成領域Ｒ２に制御ゲート１８をそれぞれ形成する（第８の工程）。しかる後、フォトレジストを除去し、シリコン基板１の全面にシリコン酸化膜１９を形成する。
【００５７】
次に、図９（ｃ）に示すように、シリコン基板１の全面にフォトレジスト（図示せず）を形成した後、そのフォトレジストをパターニングする。そして、そのフォトレジストをマスクとした異方性ドライエッチングを行い、第１の素子形成領域Ｒ１のソースとなる不純物拡散層１０の上、第２の素子形成領域Ｒ２のソース／ドレインとなる一対の不純物拡散層１０の上にそれぞれコンタクト孔２０、２０′、２０″を開孔する。
【００５８】
次に、図９（ｄ）に示すように、フォトレジストを除去した後、スパッタ法によりアルミニウム膜をシリコン基板１の全面に形成し、その上にフォトレジスト（図示せず）をパターン形成して、そのフォトレジストをマスクとして所定パターンのアルミ配線２１を形成する。そして、フォトレジストを除去した後、シリコン基板１の全面にシリコン酸化膜２２を形成する。
【００５９】
以上の工程により、第１の素子形成領域Ｒ１に１トランジスタ／１キャパシタ型のＤＲＡＭメモリセルが形成されるとともに、第２の素子形成領域Ｒ２に電気的に書き換えが可能な不揮発性メモリセル２４′が形成される。
【００６０】
なお、本実施例の製造方法において、図８（ｄ）の第５の工程でコンタクト孔１２、１２′を同時に開孔せず、以下の工程を行ってから図９（ａ）の工程に進んでもよい。
【００６１】
まず、シリコン基板１の全面にシリコン酸化膜１１を形成する第４の工程後にシリコン酸化膜１１上にフォトレジスト（図示せず）を形成した後、このフォトレジストをマスクとして異方性ドライエッチングを行い、第１の素子形成領域Ｒ１ではドレインとなる不純物拡散層１０上に存在するシリコン酸化膜１１を除去してコンタクト孔１２を開孔する。フォトレジストを除去した後、シリコン基板１の全面に多結晶シリコン膜を形成する。この多結晶シリコン膜をＮ型にしてから多結晶シリコン膜上にフォトレジスト（図示せず）をパターン形成し、そのフォトレジストをマスクとして多結晶シリコン膜をエッチング除去して第１の素子形成領域Ｒ１にキャパシタの下部電極１３を形成する。このとき、第２の素子形成領域Ｒ２上に形成した多結晶シリコン膜は実質的に総て除去する。
【００６２】
しかる後、フォトレジストを除去し、シリコン基板１の全面にフォトレジスト（図示せず）を形成し、このフォトレジストをマスクとして異方性ドライエッチングを行い、第２の素子形成領域Ｒ２では浮遊ゲート７上に存在するシリコン酸化膜１１を除去してコンタクト孔１２′を開孔する。その後、フォトレジストを除去し、図９（ａ）に進む。
【００６３】
次に、本発明の第３実施例につき図１０〜図１１を参照して説明する。尚、図１０（ａ）〜（ｃ）の工程は第１実施例の図４（ａ）〜（ｃ）と同じ工程であるので、ここではその説明を省略し、図１０（ｄ）の工程から説明する。
【００６４】
図１０（ｄ）に示すように、シリコン基板１の全面にシリコン酸化膜１１を形成する。その後、フォトレジスト（図示せず）をマスクとした異方性ドライエッチングを行い、第１の素子形成領域Ｒ１ではドレインとなる不純物拡散層１０の上、第２の素子形成領域Ｒ２では浮遊ゲート下部７′の上に存在するシリコン酸化膜１１を除去して、コンタクト孔１２、１２′を同時に開孔する。そして、フォトレジストを除去した後、シリコン基板１の全面に多結晶シリコン膜３１を形成する。この多結晶シリコン膜３１にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜３１をＮ型にする。なお、コンタクト孔１２、１２′は同時に開孔しなくてもよく、どちらかを先に開孔してもよい。
【００６５】
次に、Ｎ型多結晶シリコン膜３１上に、シリコン酸化膜とシリコン窒化膜とシリコン酸化膜とからなるＯＮＯ膜により、第１の素子形成領域Ｒ１及び第２の素子形成領域Ｒ２に誘電体膜３２をそれぞれ形成する。この時、ＯＮＯ膜の代わりに、タンタルオキサイド（Ｔａ₂ Ｏ₅ ）やＰＺＴを含む強誘電体膜を形成してもよい。
【００６６】
次に、シリコン基板１の全面に多結晶シリコン膜３３を形成した後、この多結晶シリコン膜３３にＮ型の不純物、例えばリン（Ｐ）をイオン注入して、この多結晶シリコン膜３３をＮ型にする。
【００６７】
次に、図１１（ａ）に示すように、Ｎ型にした多結晶シリコン膜３３上にフォトレジスト（図示せず）をパターン形成し、そのフォトレジストをマスクとして多結晶シリコン膜３３、誘電体膜３２及び多結晶シリコン膜３１をエッチング除去して、第１の素子形成領域Ｒ１に多結晶シリコン膜３３からなるキャパシタ上部電極１７と、誘電体膜３２からなるキャパシタ誘電体膜１５と、多結晶シリコン膜３３からなるキャパシタ下部電極１３をそれぞれ形成する。また、第２の素子形成領域Ｒ２には多結晶シリコン膜３３からなる制御ゲート１８と、誘電体膜３２からなる誘電体膜１６と、多結晶シリコン膜３１からなる浮遊ゲート上部１７″をそれぞれ形成する。しかる後、フォトレジストを除去する。なお、多結晶シリコン膜３３、誘電体膜３２及び多結晶シリコン膜３１は同時にパターニングしてもよく、多結晶シリコン膜３３と誘電体膜３２だけを同時にパターニングしてもよい。また、誘電体膜３２及び多結晶シリコン膜３１の少なくとも一方を予め第１の素子形成領域Ｒ１と第２の素子形成領域Ｒ２とで分離してから、これらをパターニングしてもよい。
【００６８】
次に、図１１（ｂ）に示すように、シリコン基板１の全面にシリコン酸化膜１９を形成する。
【００６９】
次に、図１１（ｃ）に示すように、シリコン基板１の全面にフォトレジスト（図示せず）を形成した後、そのフォトレジストをパターニングする。そのフォトレジストをマスクとした異方性ドライエッチングを行い、第１の素子形成領域Ｒ１のソースとなる不純物拡散層１０の上、第２の素子形成領域Ｒ２のソース／ドレインとなる一対の不純物拡散層１０の上にそれぞれコンタクト孔２０、２０′、２０″を開孔する。
【００７０】
次に、図１１（ｄ）に示すように、フォトレジストを除去した後、スパッタ法によりアルミニウム膜をシリコン基板１の全面に形成し、このアルミニウム膜の上にフォトレジスト（図示せず）をパターン形成して、そのフォトレジストをマスクとして所定パターンのアルミ配線２１を形成する。そして、フォトレジストを除去した後、シリコン基板１の全面にシリコン酸化膜２２を形成する。
【００７１】
以上の工程により、第１の素子形成領域Ｒ１に１トランジスタ／１キャパシタ型のＤＲＡＭメモリセル２３′が、第２の素子形成領域Ｒ２に、電気的に書き換えが可能な不揮発性メモリセル２４″が形成される。なお、第２実施例のように浮遊ゲートを上部・下部別々に形成しない場合も、本実施例のように多結晶シリコン膜３３、誘電体膜３２及び多結晶シリコン膜３１を同時にエッチング除去する手法を採用することができる。
【００７２】
以上に説明したＤＲＡＭの製造方法によれば、ＤＲＡＭメモリセル２３′を形成する通常のＭＯＳプロセスの工程数を特に増やすことなく、同一シリコン基板１上に浮遊ゲート型の不揮発性のメモリセル２４″を形成することができる。
【００７３】
【発明の効果】
本発明によれば、例えばＤＲＡＭの冗長回路への切り換え部分に従来のようなヒューズではなく電気的に書き換えが可能な不揮発性のメモリセルを用いているので、ヒューズ切断の際の周辺回路や基板へのダメージがなくなる。従って、装置の信頼性が向上する。
【００７４】
また、本発明の製造方法によれば、浮遊ゲート型の不揮発性のメモリセルを、特に工程数を増やすことなく、例えばＤＲＡＭメモリセルと同時に製造することができる。
【図面の簡単な説明】
【図１】本発明の第１実施例によるＤＲＡＭのブロック図である。
【図２】本発明の第１実施例によるＤＲＡＭメモリセルを示す概略断面図である。
【図３】本発明の第１実施例による不揮発性メモリセルを示す概略断面図である。
【図４】本発明の第１実施例によるＤＲＡＭの製造工程を示す概略断面図である。
【図５】本発明の第１実施例によるＤＲＡＭの製造工程を示す概略断面図である。
【図６】本発明の第２実施例によるＤＲＡＭメモリセルを示す概略断面図である。
【図７】本発明の第２実施例による不揮発性メモリセルを示す概略断面図である。
【図８】本発明の第２実施例によるＤＲＡＭの製造工程を示す概略断面図である。
【図９】本発明の第２実施例によるＤＲＡＭの製造工程を示す概略断面図である。
【図１０】本発明の第３実施例によるＤＲＡＭの製造工程を示す概略断面図である。
【図１１】本発明の第３実施例によるＤＲＡＭの製造工程を示す概略断面図である。
【符号の説明】
１シリコン基板
３素子分離絶縁膜
４ゲート酸化膜
５ゲート電極
６トンネル酸化膜
７浮遊ゲート
７′ 浮遊ゲート下部
７″ 浮遊ゲート上部
８Ｎ^-不純物拡散層
９サイドウォールスペーサー
１０Ｎ⁺不純物拡散層
１１シリコン酸化膜
１３キャパシタ下部電極
１５、１６誘電体膜
１７キャパシタ上部電極
１８制御ゲート
２３ＤＲＡＭメモリセル
２４不揮発性メモリセル[0001]
[Industrial application fields]
The present invention relates to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a manufacturing method thereof.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a semiconductor memory device such as a DRAM, a redundant circuit system has been adopted in order to prevent a decrease in yield due to a random defect in a manufacturing process. That is, in a DRAM or the like, the storage capacity is increased by integrating a huge number of memory cells in one chip, but the chip becomes defective only by having one defective memory cell in the chip. , Yield decreases.
[0003]
In the redundant circuit system, for example, the addressing word line or bit line connected to the defective memory cell is disconnected from the address decoder, and the addressing word line or bit line connected to the spare memory cell is used. Are connected to the address decoder. As a result, the defective memory cell can be replaced with a spare memory cell, and the yield is improved.
[0004]
As a specific method for switching to a spare memory cell, for example, a laser fuse method is widely used in which a fuse is cut by a laser beam spot and a defective memory cell is replaced with a spare memory cell. Yes.
[0005]
In addition, an electric fuse method for electrically fusing fuses is also widely used, and is disclosed in, for example, Japanese Patent Application Laid-Open Nos. 60-65545, 62-139198, and 4-14700. ing.
[0006]
[Problems to be solved by the invention]
However, in the laser fuse method described above, the process of irradiating the laser beam by controlling the laser beam position based on information from the tester is relatively complicated, and a laser beam spot irradiation device having a highly accurate position control function is required. There was a problem that there was. Furthermore, there has been a problem of damage to peripheral circuits when the fuse is blown.
[0007]
On the other hand, even in the electric fuse method, the influence on the peripheral circuit and the damage to the substrate when the fuse is electrically blown are problematic.
[0008]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, which can switch a redundant circuit to a memory cell without damaging a peripheral circuit or a substrate.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problem, in the present invention, a first insulating film and a first conductive film are sequentially formed in a first element formation region of a semiconductor substrate, and a second element formation of the semiconductor substrate is performed. A second insulating film and a second conductive film are sequentially formed in the region, and a MOS transistor and a lower electrode connected to one of the pair of impurity diffusion layers of the MOS transistor are formed in the first element formation region. In the method of manufacturing a semiconductor memory device, in which a capacitor having a capacitor is formed, and an electrically rewritable non-volatile floating gate transistor is formed in the second element formation region, the second element formation region includes: Forming a third conductive film in contact with the second conductive film and in contact with one of the impurity diffusion layers in the first element formation region; and the first element formation region and the second element formation region of Forming a dielectric film on the third conductive film in the child forming area; and forming a fourth film on the dielectric film in the first element forming area and the second element forming area. Forming the conductive film, patterning the fourth conductive film, the dielectric film, and the third conductive film, and forming the fourth conductive film in the first element formation region. The capacitor is formed using the conductive film as an upper electrode and the third conductive film as the lower electrode, and in the second element formation region, the fourth conductive film is used as a control gate, Forming a composite gate portion of the floating gate type transistor using the second conductive film and the third conductive film as a floating gate.
[0014]
In one aspect of the present invention, in the step of forming the composite gate portion after forming the fourth conductive film on the dielectric film, the dielectric film, the fourth conductive film, Are simultaneously patterned.
[0015]
In one aspect of the present invention, in the step of forming the composite gate portion after forming the fourth conductive film on the dielectric film, the third conductive film, the dielectric film, The fourth conductive film is patterned simultaneously.
[0016]
In one embodiment of the present invention, after the third conductive film is formed, at least the third conductive film is patterned to be in contact with one of the impurity diffusion layers in the first element formation region. Separating the third conductive film and the third conductive film in contact with the second conductive film in the second element formation region.
[0017]
In one aspect of the present invention, after the dielectric film is formed on the third conductive film, the dielectric film is patterned to obtain the dielectric film in the first element formation region and And a step of separating the dielectric film in the second element formation region.
[0018]
In one aspect of the present invention, before forming the third conductive film, the first contact hole reaching one of the impurity diffusion layers of the MOS transistor in the first element formation region, An interlayer insulating film having the second contact hole reaching the second conductive film is formed in a second element formation region, and the third conductive film serves as the first contact hole and the second contact hole. The contact hole is formed to extend from the inner surface of the contact hole to the interlayer insulating film.
[0019]
In one embodiment of the present invention, a first insulating film and a first conductive film are sequentially formed in a first element formation region of a semiconductor substrate, and a second element formation region of the semiconductor substrate is a second element formation region. An insulating film and a second conductive film are sequentially formed, and a capacitor having a MOS transistor and a lower electrode connected to one of a pair of impurity diffusion layers of the MOS transistor is formed in the first element formation region. In the method of manufacturing a semiconductor memory device in which an electrically rewritable nonvolatile floating gate transistor is formed in the second element formation region, the first element formation region and the second element formation An interlayer insulating film is formed in the region, and a first contact hole reaching one of the impurity diffusion layers of the MOS transistor in the first element forming region is formed in the interlayer insulating film; Forming a second contact hole reaching the second conductive film in the interlayer insulating film in the element formation region, and forming a third conductive layer in the first element formation region and the second element formation region. Forming a pattern of the third conductive film extending from the first contact hole onto the interlayer insulating film by forming a conductive film and patterning the third conductive film; Forming a dielectric film on the second conductive film in the second contact hole in the second element formation region and on the third conductive film in the first element formation region; Forming a fourth conductive film on the dielectric film; and patterning the dielectric film and the fourth conductive film to form the first element formation region in the first element formation region. 4 as the upper electrode, and the third conductive film The capacitor having the film as the lower electrode is formed, and the second element formation region includes the floating electrode having the fourth conductive film as a control gate and the second conductive film as a floating gate. Forming a composite gate portion of the gate transistor.
[0020]
In one aspect of the present invention, the fourth conductive film is formed on the dielectric film after patterning the dielectric film.
[0021]
In one aspect of the present invention, in the step of forming the composite gate portion after forming the fourth conductive film on the dielectric film, the dielectric film, the fourth conductive film, Are simultaneously patterned.
[0022]
In one aspect of the present invention, after the dielectric film is formed on the third conductive film, the dielectric film is patterned to obtain the dielectric film in the first element formation region and And a step of separating the dielectric film in the second element formation region.
[0023]
In one embodiment of the present invention, the first insulating film and the second insulating film are simultaneously formed of the same material, and the first conductive film and the second conductive film are simultaneously formed of the same material. To do.
[0024]
In one embodiment of the present invention, a first memory cell array including a first memory cell including one MOS transistor and one capacitor is provided in a first element formation region of a semiconductor substrate and electrically In the method of manufacturing a semiconductor memory device, the second element cell formation region of the semiconductor substrate includes a second memory cell array composed of a nonvolatile second memory cell that can be rewritten and has a floating gate and a control gate. Forming a first insulating film on the semiconductor substrate in the first element formation region and on the semiconductor substrate in the second element formation region; and After forming a first conductive film on the first insulating film and on the first insulating film in the second element forming region, the first conductive film in the first element forming region is formed. Before the sex membrane Patterning into the shape of the gate electrode of the MOS transistor, patterning the first conductive film in the second element formation region into the shape of the floating gate, and forming the gate electrode on both sides of the gate electrode of the MOS transistor. Ion implantation is performed on the first element formation region and the second element formation region on both sides of the floating gate, and a pair of impurity diffusion layers are formed in the first element formation region and the second element formation region, respectively. Forming a second insulating film on the entire surface of the semiconductor substrate, and then forming a first opening reaching one of the impurity diffusion layers in the first element formation region in the second insulating film. Forming a second opening reaching the first conductive film in the second element formation region, and forming the second opening and the second opening. After forming the second conductive film so as to embed each of the first conductive film, the second conductive film in the first element formation region and the second conductive film in the second element formation region are separated. Patterning, and forming a dielectric film on the second conductive film, then forming a third conductive film on the dielectric film, and forming the first element formation region And patterning the third conductive film so as to separate the third conductive film in the second element formation region.
[0025]
In one aspect of the present invention, the dielectric film is formed on the second conductive film, and then the dielectric film is patterned to obtain the dielectric film in the first element formation region and Then, the dielectric film in the second element formation region is separated.
[0026]
In one embodiment of the present invention, a first memory cell array including a first memory cell including one MOS transistor and one capacitor is provided in a first element formation region of a semiconductor substrate and electrically In the method of manufacturing a semiconductor memory device, the second element cell formation region of the semiconductor substrate includes a second memory cell array composed of a nonvolatile second memory cell that can be rewritten and has a floating gate and a control gate. Forming a first insulating film on the semiconductor substrate in the first element formation region and on the semiconductor substrate in the second element formation region; and the first in the first element formation region. After forming a first conductive film on the first insulating film and on the first insulating film in the second element formation region, the first conductive film in the first element formation region is formed. MOS transistors Patterning the first conductive film of the second element formation region into the shape of the floating gate, and patterning the first conductive film on both sides of the gate electrode of the MOS transistor. Ion implantation is performed on the element formation region and the second element formation region on both sides of the floating gate to form a pair of impurity diffusion layers in the first element formation region and the second element formation region, respectively. And after forming a second insulating film on the entire surface of the semiconductor substrate, a first opening reaching one of the impurity diffusion layers in the first element formation region is formed in the second insulating film. Patterning a second conductive film formed so as to embed the first opening, and the second conductive film extending from the first opening onto the second insulating film. Forming a pattern of the film; forming a second opening in the second insulating film in the second element formation region; and a second opening reaching the first conductive film. Forming a dielectric film on the second conductive film in the region and on the first conductive film in the second opening in the second element formation region; A third conductive film is formed thereon, and patterned so as to separate the third conductive film in the first element formation region and the third conductive film in the second element formation region. And a process of performing.
[0027]
In one aspect of the present invention, over the second conductive film in the first element formation region and over the first conductive film in the second opening in the second element formation region. After forming the dielectric film, the dielectric film is patterned to separate the dielectric film in the first element formation region from the dielectric film in the second element formation region. .
[0028]
[Action]
In the semiconductor memory device of the present invention, electrically rewritable non-volatile memory cells are used instead of fuses, so that there is no damage to peripheral circuits and substrates during fuse cutting as in the prior art.
[0029]
Further, according to the method for manufacturing a semiconductor memory device of the present invention, a floating gate type nonvolatile memory cell can be manufactured simultaneously with, for example, a DRAM memory cell without increasing the number of steps.
[0030]
【Example】
Embodiments in which the present invention is applied to a DRAM will be described below with reference to the accompanying drawings.
[0031]
The DRAM according to the first embodiment of the semiconductor memory device of the present invention comprises a DRAM memory cell array 101 comprising a plurality of DRAM memory cells 23 (see FIG. 2) arranged in an array as shown in FIG. A spare part 110 constituting a redundant circuit, a DRAM memory cell array 101 and a spare DRAM memory cell array 111, each comprising a spare DRAM memory cell array 111 comprising a plurality of DRAM memory cells 23 arranged in an array. An address decoder 120 for designating the address of the memory, and a defective bit switching control circuit 130 connected to the address decoder 120 and comprising a plurality of electrically rewritable nonvolatile memory cells 24 (see FIG. 3). Become.
[0032]
As shown in FIG. 2, the DRAM memory cell 23 includes a gate oxide film 4, a gate electrode 5 formed on the gate oxide film 4, sidewall spacers 9 formed on both sides of the gate electrode 5, A pair of N formed under the sidewall spacer 9 ^- Impurity diffusion layer 8 and N ^- A pair of N formed on both sides of the impurity diffusion layer 8 ⁺ It is composed of one MOS transistor composed of the type impurity diffusion layer 10 and one capacitor composed of the capacitor lower electrode 13, the capacitor dielectric film 15 and the capacitor upper electrode 17.
[0033]
As shown in FIG. 3, the nonvolatile memory cell 24 includes a tunnel oxide film 6, a floating gate lower portion 7 'formed on the tunnel oxide film 6, and a floating gate formed on the floating gate lower portion 7'. An upper portion 7 ″, a dielectric film 16 formed on the floating gate upper portion 7 ″, a control gate 18 formed on the dielectric film 16, and sidewall spacers 9 formed on both sides of the floating gate lower portion 7 ′. And a pair of N formed under the sidewall spacer 9 in the silicon substrate 1 ^- Impurity diffusion layer 8 and N ^- A pair of N formed on both sides of the impurity diffusion layer 8 ⁺ Type impurity diffusion layer 10.
[0034]
In the DRAM of this embodiment, when a defect occurs in one of the plurality of DRAM memory cells 23 constituting the DRAM memory cell array 101 of the main body 100, the address of the DRAM memory cell 23 in which the defect has occurred. In order to separate the designated word line (or bit line) from the address decoder 120, the corresponding nonvolatile memory cell 24 among the plurality of nonvolatile memory cells 24 is input to the defective bit switching control circuit 130. The bit switching signal 150 switches from ON to OFF. Further, in order to connect the address designation word line (or bit line) of the DRAM memory cell 23 of the spare DRAM memory cell array 111 used in place of the defective DRAM memory cell 23 and the address decoder 120, a plurality of addresses are connected. Another corresponding non-volatile memory cell 24 among the non-volatile memory cells 24 is switched from OFF to ON by a defective bit switching signal 150 input to the defective bit switching control circuit 130.
[0035]
In the embodiment described above, a floating gate type is shown as the nonvolatile memory cell. However, as the nonvolatile memory cell, an MNOS type that accumulates charges at the interface between the silicon nitride film and the silicon oxide film is used. These memory cells can also be used.
[0036]
Next, the DRAM memory cell 23 shown in FIG. 2 is formed in the first element formation region R1 of the silicon substrate 1, and the nonvolatile memory cell 24 shown in FIG. 3 is formed in the second element formation region R2 of the silicon substrate 1. A method of manufacturing the DRAM shown in FIG. 1 by forming the structure will be described with reference to FIGS.
[0037]
A silicon oxide film for pad and a silicon nitride film (both not shown) are sequentially formed on a P-type silicon substrate 1, and a silicon nitride film other than the element formation regions R1 and R2 is formed with a photoresist (not shown). It is removed by anisotropic dry etching using a mask. Impurities such as BF ₂ Is ion-implanted into the silicon substrate 1 to form a channel stopper P as shown in FIG. ⁺ Impurity diffusion layer 2 is formed. After removing the photoresist, the surface is washed. H ₂ By performing heat treatment at a temperature of 1100 ° C. in an O atmosphere and selectively oxidizing (LOCOS) the silicon substrate 1, the element isolation insulating film 3 is formed in the element isolation regions R1 and R2 other than the element formation region. Thereafter, the silicon nitride film that has become a mask for the heat treatment is removed.
[0038]
Next, as shown in FIG. 4B, after the sacrificial oxide film (not shown) is formed and removed, the first element formation region R1 becomes the gate oxide film 4, and the second element formation region R2 is non-volatile. A silicon oxide film having a thickness of about 10 to 20 nm to be the tunnel oxide film 6 of the memory cell is formed on the entire surface of the element formation regions R1 and R2 (first step). Thereafter, impurities for threshold control, such as BF ₂ Is implanted into the silicon substrate 1, and then a polycrystalline silicon film is formed on the entire surface. N-type impurities such as phosphorus (P) are ion-implanted into the polycrystalline silicon film to make the polycrystalline silicon film N-type. A photoresist (not shown) is applied on the N-type polycrystalline silicon film, and the photoresist is patterned. Using the patterned photoresist as a mask, the polycrystalline silicon film is anisotropically dry-etched to form the gate electrode 5 of the MOS transistor in the first element formation region R1 and non-volatile in the second element formation region R2. The lower portion 7 'of the floating gate (floating gate) of the volatile memory cell 24 is formed (second step).
[0039]
Next, as shown in FIG. 4C, after removing the photoresist, an N-type impurity such as phosphorus (P) is used with the element isolation insulating film 3, the gate electrode 5 and the lower portion 7 'of the floating gate as a mask. Ions are implanted into the entire surface of the silicon substrate 1, and a pair of N is formed in the first element formation region R1 and the second element formation region R2. ^- Impurity diffusion layers 8 are respectively formed. By forming a silicon oxide film on the entire surface of the silicon substrate 1 and anisotropically etching the silicon oxide film, sidewall spacers 9 are formed on both sides of the gate electrode 5 and the floating gate lower portion 7 '. Thereafter, an N-type impurity, for example, phosphorus (P) is ion-implanted over the entire surface of the silicon substrate 1 using the element isolation insulating film 3, the gate electrode 5, the floating gate lower portion 7 ', and the sidewall spacer 9 as a mask. A pair of N is formed in the formation region R1 and the second element formation region R2. ⁺ Impurity diffusion layers 10 are respectively formed (third step). As a result, an impurity diffusion layer having an LDD (Lightly Doped Drain) structure is formed in the silicon substrate 1.
[0040]
Next, as shown in FIG. 4D, a silicon oxide film 11 is formed on the entire surface of the silicon substrate 1 (fourth step). Thereafter, anisotropic dry etching is performed using a photoresist (not shown) as a mask, and the impurity diffusion layer 10 serving as the drain is formed in the first element formation region R1, and the floating gate lower portion is formed in the second element formation region R2. The silicon oxide film 11 existing on 7 'is removed, and contact holes 12 and 12' are opened simultaneously (fifth step). Then, after removing the photoresist, a polycrystalline silicon film is formed on the entire surface of the silicon substrate 1, and an N-type impurity such as phosphorus (P) is ion-implanted into the polycrystalline silicon film. To N type. Thereafter, a photoresist (not shown) is patterned on the N-type polycrystalline silicon film, and the polycrystalline silicon film is removed by etching using the photoresist as a mask. The capacitor lower electrode is formed in the first element formation region R1. 13. Floating gate upper portions 7 ″ are respectively formed in the second element formation region R2 (sixth step). Thereafter, the photoresist is removed.
[0041]
Next, as shown in FIG. 5A, a capacitor dielectric is formed on the capacitor lower electrode 13 in the first element formation region R1 by an ONO film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. In the film 15 and the second element formation region R2, the dielectric film 16 is formed on the floating gate upper portion 7 ″ (seventh step). At this time, in place of the ONO film, tantalum oxide (Ta ₂ O _Five Or a ferroelectric film containing PZT.
[0042]
Next, as shown in FIG. 5B, after a polycrystalline silicon film is formed on the entire surface of the silicon substrate 1, N-type impurities such as phosphorus (P) are ion-implanted into the polycrystalline silicon film. This polycrystalline silicon film is made N-type. A photoresist (not shown) is patterned on the N-type polycrystalline silicon film, and the polycrystalline silicon film is etched away using the photoresist as a mask. The capacitor upper electrode 17 is formed in the first element formation region R1. Then, a control gate (control gate) 18 is formed in each of the second element formation regions R2 (eighth step). Thereafter, the photoresist is removed, and a silicon oxide film 19 is formed on the entire surface of the silicon substrate 1.
[0043]
Next, as shown in FIG. 5C, after forming a photoresist (not shown) on the entire surface of the silicon substrate 1, the photoresist is patterned. By performing anisotropic dry etching using the photoresist as a mask, a pair of impurity diffusions serving as the source / drain of the second element formation region R2 on the impurity diffusion layer 10 serving as the source of the first element formation region R1 Contact holes 20, 20 ', 20 "are opened on the layer 10, respectively.
[0044]
Next, as shown in FIG. 5D, after removing the photoresist, an aluminum film is formed on the entire surface of the silicon substrate 1 by sputtering, and a photoresist (not shown) is patterned on the aluminum film. Then, an aluminum wiring 21 having a predetermined pattern is formed using the photoresist as a mask. Then, after removing the photoresist, a silicon oxide film 22 is formed on the entire surface of the silicon substrate 1.
[0045]
Through the above steps, the 1-transistor / 1-capacitor DRAM memory cell 23 is formed in the first element formation region R1, and the electrically rewritable nonvolatile memory cell 24 is formed in the second element formation region R2. The
[0046]
According to the DRAM manufacturing method described above, the floating gate type nonvolatile memory cell 24 is formed on the same silicon substrate 1 without particularly increasing the number of steps of a normal MOS process for forming the DRAM memory cell 23. can do.
[0047]
Next, a second embodiment of the semiconductor memory device of the present invention will be described with reference to FIGS.
[0048]
The configuration of the DRAM of this embodiment is the same as the configuration of FIG. 1, and the DRAM memory cell is also the same as the DRAM memory cell 23 of FIG. 2 as shown in FIG. However, in the nonvolatile memory cell 24 ', a dielectric film 16 is formed on the floating gate 7 as shown in FIG. 7, and the floating gate upper portion 7 "is interposed on the floating gate lower portion 7' corresponding to the floating gate 7. 3 is different from the nonvolatile memory cell 24 of FIG. 3 in which the dielectric film 16 is formed.
[0049]
In the nonvolatile memory cell 24 ′ of FIG. 7, since the dielectric film 16 is formed on the floating gate 7, the capacity of the floating gate is smaller than that of the nonvolatile memory cell 24 of FIG. Therefore, the nonvolatile memory cell 24 of FIG. 3 is preferably used in the normal ON state, and the nonvolatile memory cell 24 ′ of FIG. 7 is preferably used in the OFF state at the normal time.
[0050]
Hereinafter, the DRAM manufacturing method of the present embodiment will be described with reference to FIGS. 8 and 9. The components used in the DRAM memory cell are the same as those used in FIG. The symbols used in FIG. 3 are used except for the floating gate 7. Also in this embodiment, the DRAM memory cell 23 shown in FIG. 6 is formed in the first element formation region R1 of the silicon substrate 1, and the nonvolatile memory cell 24 ′ shown in FIG. It is formed in the element formation region R2.
[0051]
A silicon oxide film for pad and a silicon nitride film (both not shown) are sequentially formed on a P-type silicon substrate 1, and a silicon nitride film other than the element formation regions R1 and R2 is formed with a photoresist (not shown). It is removed by anisotropic dry etching using a mask. And impurities such as BF ₂ Is ion-implanted into the silicon substrate 1 to form a channel stopper P as shown in FIG. ⁺ Impurity diffusion layer 2 is formed. After removing the photoresist, the surface is washed. After this, H ₂ By performing heat treatment at a temperature of 1100 ° C. in an O atmosphere and selectively oxidizing (LOCOS) the silicon substrate 1, the element isolation insulating film 3 is formed in the element isolation regions other than the element formation regions R1 and R2. Thereafter, the silicon nitride film that has become a mask for the heat treatment is removed.
[0052]
Next, as shown in FIG. 8B, after the sacrificial oxide film (not shown) is formed and removed, the gate oxide film 4 is formed in the first element formation region R1, and the nonvolatile structure is formed in the second element formation region R2. A silicon oxide film having a thickness of about 10 to 20 nm to be the tunnel oxide film 6 of the memory cell is formed on the entire surface of the element formation regions R1 and R2 (first step). Thereafter, impurities for threshold control, such as BF ₂ Are ion-implanted into the silicon substrate 1. Thereafter, a polycrystalline silicon film is formed on the entire surface of the silicon substrate 1, and an N-type impurity such as phosphorus (P) is ion-implanted into the polycrystalline silicon film to make the polycrystalline silicon film N-type. Thereafter, a photoresist (not shown) is applied on the N-type polycrystalline silicon film, and the photoresist is patterned. Then, the polysilicon film is anisotropically dry-etched using the patterned photoresist as a mask, and the gate electrode 5 of the MOS transistor is formed in the first element formation region R1, and the nonvolatile is formed in the second element formation region R2. The floating gate (floating gate) 7 of the memory cell 24 'is formed at the same time (second step).
[0053]
Next, as shown in FIG. 8C, after removing the photoresist, an N-type impurity such as phosphorus (P), for example, phosphorus (P) is used as a mask with the element isolation insulating film 3, the gate electrode 5 and the floating gate 7 as a mask. Are ion-implanted into the entire surface of the first element forming region R1 and the second element forming region R2. ^- Impurity diffusion layers 8 are respectively formed. Thereafter, a silicon oxide film is formed on the entire surface of the silicon substrate 1, and this silicon oxide film is anisotropically etched to form sidewall spacers 9 on the gate electrode 5 and the floating gate 7, respectively. Then, an N-type impurity, for example, phosphorus (P) is ion-implanted over the entire surface of the silicon substrate 1 using the element isolation insulating film 3, the gate electrode 5, the floating gate 7 and the sidewall spacer 9 as a mask to form a first element formation region. Each of R1 and second element formation region R2 has a pair of N ⁺ Impurity diffusion layer 10 is formed (third step). Thereby, an impurity diffusion layer having an LDD structure is formed in the silicon substrate 1.
[0054]
Next, as shown in FIG. 8D, a silicon oxide film 11 is formed on the entire surface of the silicon substrate 1 (fourth step). Thereafter, anisotropic dry etching is performed using a photoresist (not shown) as a mask, and the floating gate 7 is formed on the impurity diffusion layer 10 serving as a drain in the first element formation region R1 and on the second element formation region R2. Then, the silicon oxide film 11 existing on the upper surface is removed, and contact holes 12 and 12 'are opened simultaneously (fifth step). Then, after removing the photoresist, a polycrystalline silicon film is formed on the entire surface of the silicon substrate 1, and an N-type impurity such as phosphorus (P) is ion-implanted into the polycrystalline silicon film. To N type. Thereafter, a photoresist (not shown) is patterned on the N-type polycrystalline silicon film, and the polycrystalline silicon film is removed by etching using the photoresist as a mask. The capacitor is formed in the first element formation region R1. Lower electrode 13 is formed (sixth step). At this time, in this embodiment, substantially all of the polycrystalline silicon film formed on the floating gate 7 in the second element formation region R2 is removed. Thereafter, the photoresist is removed.
[0055]
Next, as shown in FIG. 9A, the capacitor dielectric is formed on the lower electrode 13 of the capacitor in the first element formation region R1 by an ONO film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. In the body film 15 and the second element formation region R2, the dielectric film 16 is formed on the floating gate 7 (seventh step). At this time, tantalum oxide (Ta ₂ O _Five Or a ferroelectric film containing PZT.
[0056]
Next, as shown in FIG. 9B, after a polycrystalline silicon film is formed on the entire surface, an N-type impurity such as phosphorus (P) is ion-implanted into the polycrystalline silicon film, and this polycrystalline silicon film is formed. The film is made N-type. Thereafter, a photoresist (not shown) is patterned on the N-type polycrystalline silicon film, and the polycrystalline silicon film is removed by etching using the photoresist as a mask. The capacitor is formed in the first element formation region R1. The control gates 18 are respectively formed in the upper electrode 17 and the second element formation region R2 (eighth step). Thereafter, the photoresist is removed, and a silicon oxide film 19 is formed on the entire surface of the silicon substrate 1.
[0057]
Next, as shown in FIG. 9C, a photoresist (not shown) is formed on the entire surface of the silicon substrate 1, and then the photoresist is patterned. Then, anisotropic dry etching is performed using the photoresist as a mask, and a pair of source / drains serving as the source / drain of the second element forming region R2 is formed on the impurity diffusion layer 10 serving as the source of the first element forming region R1. Contact holes 20, 20 ′, 20 ″ are opened on the impurity diffusion layer 10, respectively.
[0058]
Next, as shown in FIG. 9D, after removing the photoresist, an aluminum film is formed on the entire surface of the silicon substrate 1 by sputtering, and a photoresist (not shown) is formed thereon by patterning. Then, an aluminum wiring 21 having a predetermined pattern is formed using the photoresist as a mask. Then, after removing the photoresist, a silicon oxide film 22 is formed on the entire surface of the silicon substrate 1.
[0059]
Through the above steps, a 1-transistor / 1-capacitor DRAM memory cell is formed in the first element formation region R1, and a non-volatile memory cell 24 ′ that can be electrically rewritten in the second element formation region R2. Is formed.
[0060]
In the manufacturing method of this embodiment, the contact holes 12 and 12 'are not simultaneously opened in the fifth step of FIG. 8D, and the following steps are performed before proceeding to the step of FIG. 9A. But you can.
[0061]
First, after a fourth step of forming the silicon oxide film 11 on the entire surface of the silicon substrate 1, a photoresist (not shown) is formed on the silicon oxide film 11, and then anisotropic dry etching is performed using the photoresist as a mask. Then, in the first element formation region R1, the silicon oxide film 11 existing on the impurity diffusion layer 10 serving as the drain is removed, and the contact hole 12 is opened. After removing the photoresist, a polycrystalline silicon film is formed on the entire surface of the silicon substrate 1. After making this polycrystalline silicon film N-type, a photoresist (not shown) is patterned on the polycrystalline silicon film, and the polycrystalline silicon film is removed by etching using the photoresist as a mask. The lower electrode 13 of the capacitor is formed on R1. At this time, substantially all of the polycrystalline silicon film formed on the second element formation region R2 is removed.
[0062]
Thereafter, the photoresist is removed, a photoresist (not shown) is formed on the entire surface of the silicon substrate 1, and anisotropic dry etching is performed using this photoresist as a mask. In the second element formation region R2, a floating gate is formed. 7 is removed to form a contact hole 12 '. Thereafter, the photoresist is removed, and the process proceeds to FIG.
[0063]
Next, a third embodiment of the present invention will be described with reference to FIGS. 10A to 10C are the same as those in FIGS. 4A to 4C of the first embodiment, so the description thereof is omitted here, and the process in FIG. It explains from.
[0064]
As shown in FIG. 10D, a silicon oxide film 11 is formed on the entire surface of the silicon substrate 1. Thereafter, anisotropic dry etching is performed using a photoresist (not shown) as a mask, and the impurity diffusion layer 10 serving as the drain is formed in the first element formation region R1, and the floating gate lower portion is formed in the second element formation region R2. The silicon oxide film 11 existing on 7 'is removed, and contact holes 12, 12' are opened simultaneously. Then, after removing the photoresist, a polycrystalline silicon film 31 is formed on the entire surface of the silicon substrate 1. N-type impurities such as phosphorus (P) are ion-implanted into the polycrystalline silicon film 31 to make the polycrystalline silicon film 31 N-type. Note that the contact holes 12 and 12 'do not have to be opened at the same time, and one of them may be opened first.
[0065]
Next, a dielectric film is formed on the first element formation region R1 and the second element formation region R2 by an ONO film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film on the N-type polycrystalline silicon film 31. 32 are formed. At this time, tantalum oxide (Ta ₂ O _Five Or a ferroelectric film containing PZT.
[0066]
Next, after a polycrystalline silicon film 33 is formed on the entire surface of the silicon substrate 1, an N-type impurity such as phosphorus (P) is ion-implanted into the polycrystalline silicon film 33, and the polycrystalline silicon film 33 is converted to N Make a mold.
[0067]
Next, as shown in FIG. 11A, a photoresist (not shown) is patterned on the N-type polycrystalline silicon film 33, and the polycrystalline silicon film 33, dielectrics are formed using the photoresist as a mask. The film 32 and the polycrystalline silicon film 31 are removed by etching, and the capacitor upper electrode 17 made of the polycrystalline silicon film 33, the capacitor dielectric film 15 made of the dielectric film 32, and the polycrystalline film are formed in the first element formation region R1. The capacitor lower electrodes 13 made of the silicon film 33 are formed. Further, the control gate 18 made of the polycrystalline silicon film 33, the dielectric film 16 made of the dielectric film 32, and the floating gate upper portion 17 ″ made of the polycrystalline silicon film 31 are formed in the second element formation region R2. Thereafter, the photoresist is removed, and the polycrystalline silicon film 33, the dielectric film 32, and the polycrystalline silicon film 31 may be patterned at the same time, and only the polycrystalline silicon film 33 and the dielectric film 32 are simultaneously patterned. Alternatively, at least one of the dielectric film 32 and the polycrystalline silicon film 31 is separated in advance into the first element formation region R1 and the second element formation region R2, and then these are patterned. Also good.
[0068]
Next, as shown in FIG. 11B, a silicon oxide film 19 is formed on the entire surface of the silicon substrate 1.
[0069]
Next, as shown in FIG. 11C, after forming a photoresist (not shown) on the entire surface of the silicon substrate 1, the photoresist is patterned. By performing anisotropic dry etching using the photoresist as a mask, a pair of impurity diffusions serving as the source / drain of the second element formation region R2 on the impurity diffusion layer 10 serving as the source of the first element formation region R1 Contact holes 20, 20 ', 20 "are opened on the layer 10, respectively.
[0070]
Next, as shown in FIG. 11D, after removing the photoresist, an aluminum film is formed on the entire surface of the silicon substrate 1 by sputtering, and a photoresist (not shown) is patterned on the aluminum film. Then, an aluminum wiring 21 having a predetermined pattern is formed using the photoresist as a mask. Then, after removing the photoresist, a silicon oxide film 22 is formed on the entire surface of the silicon substrate 1.
[0071]
Through the above process, the 1-transistor / 1-capacitor DRAM memory cell 23 'is formed in the first element formation region R1, and the electrically rewritable nonvolatile memory cell 24 "is formed in the second element formation region R2. Even when the floating gate is not formed separately on the upper and lower sides as in the second embodiment, the polycrystalline silicon film 33, the dielectric film 32 and the polycrystalline silicon film 31 are simultaneously formed as in the present embodiment. A technique for removing the etching can be employed.
[0072]
According to the DRAM manufacturing method described above, the floating gate type nonvolatile memory cell 24 ″ is formed on the same silicon substrate 1 without particularly increasing the number of steps of a normal MOS process for forming the DRAM memory cell 23 ′. Can be formed.
[0073]
【The invention's effect】
According to the present invention, for example, a nonvolatile memory cell that can be electrically rewritten is used instead of a conventional fuse in a switching portion of a DRAM to a redundant circuit. No damage to Therefore, the reliability of the apparatus is improved.
[0074]
Further, according to the manufacturing method of the present invention, a floating gate type nonvolatile memory cell can be manufactured simultaneously with, for example, a DRAM memory cell without increasing the number of steps.
[Brief description of the drawings]
1 is a block diagram of a DRAM according to a first embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view showing a DRAM memory cell according to a first embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view showing a nonvolatile memory cell according to a first embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view showing a manufacturing process of the DRAM according to the first embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view showing a manufacturing process of the DRAM according to the first embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view showing a DRAM memory cell according to a second embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a nonvolatile memory cell according to a second embodiment of the present invention.
FIG. 8 is a schematic cross-sectional view showing a manufacturing process of a DRAM according to the second embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view showing a manufacturing process of the DRAM according to the second embodiment of the present invention;
FIG. 10 is a schematic sectional view showing a manufacturing process of a DRAM according to a third embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view showing a manufacturing process of the DRAM according to the third embodiment of the present invention;
[Explanation of symbols]
1 Silicon substrate
3 Element isolation insulating film
4 Gate oxide film
5 Gate electrode
6 Tunnel oxide film
7 Floating gate
7 'Bottom of floating gate
7 "floating gate top
8 N ^- Impurity diffusion layer
9 Sidewall spacer
10 N ⁺ Impurity diffusion layer
11 Silicon oxide film
13 Capacitor lower electrode
15, 16 Dielectric film
17 Capacitor upper electrode
18 Control gate
23 DRAM memory cell
24 Nonvolatile memory cell

Claims

A first insulating film and a first conductive film are sequentially formed in a first element formation region of the semiconductor substrate, and a second insulating film and a second conductivity are formed in the second element formation region of the semiconductor substrate. And a capacitor having a lower electrode connected to one of a pair of impurity diffusion layers of the MOS transistor is formed in the first element formation region, and the second element formation region is formed. In a method for manufacturing a semiconductor memory device in which a nonvolatile floating gate transistor that is electrically rewritable is formed,
Forming a third conductive film in contact with the second conductive film in the second element formation region and in contact with one of the impurity diffusion layers in the first element formation region;
Forming a dielectric film on the third conductive film in the first element formation region and the second element formation region;
Forming a fourth conductive film on the dielectric film in the first element formation region and the second element formation region;
The fourth conductive film, the dielectric film, and the third conductive film are patterned, and the fourth conductive film is used as an upper electrode in the first element formation region. The capacitor having the conductive film as the lower electrode is formed, and the second conductive film and the third conductive film are formed in the second element formation region using the fourth conductive film as a control gate. And a step of forming a composite gate portion of the floating gate transistor using the conductive film as a floating gate.

In the step of forming the composite gate portion after forming the fourth conductive film on the dielectric film, the dielectric film and the fourth conductive film are simultaneously patterned. A method of manufacturing a semiconductor memory device according to claim 1.

In the step of forming the composite gate portion after forming the fourth conductive film on the dielectric film, the third conductive film, the dielectric film, and the fourth conductive film The method of manufacturing a semiconductor memory device according to claim 1, wherein patterning is simultaneously performed.

After forming the third conductive film, by patterning at least the third conductive film, the third conductive film in contact with one of the impurity diffusion layers in the first element formation region; The method of manufacturing a semiconductor memory device according to claim 1, further comprising a step of separating the third conductive film in contact with the second conductive film in the second element formation region.

The dielectric film is formed on the third conductive film, and then the dielectric film is patterned to thereby form the dielectric film in the first element formation region and the second element formation region. The method of manufacturing a semiconductor memory device according to claim 1, further comprising a step of separating the dielectric film.

Before forming the third conductive film, the first contact hole reaching one of the impurity diffusion layers of the MOS transistor in the first element formation region, and the second element formation region in the first element formation region. Forming an interlayer insulating film having the second contact hole reaching the second conductive film;
2. The semiconductor memory device according to claim 1, wherein the third conductive film is formed so as to extend from the inner surfaces of the first contact hole and the second contact hole onto the interlayer insulating film. Manufacturing method.

A first insulating film and a first conductive film are sequentially formed in a first element formation region of the semiconductor substrate, and a second insulating film and a second conductivity are formed in the second element formation region of the semiconductor substrate. And a capacitor having a lower electrode connected to one of a pair of impurity diffusion layers of the MOS transistor is formed in the first element formation region, and the second element formation region is formed. In a method for manufacturing a semiconductor memory device in which a nonvolatile floating gate transistor that is electrically rewritable is formed,
An interlayer insulating film is formed in the first element formation region and the second element formation region, and a first contact hole reaching one of the impurity diffusion layers of the MOS transistor is formed in the first element formation region. Forming a second contact hole in the interlayer insulating film, and forming a second contact hole reaching the second conductive film in the second element formation region;
A third conductive film is formed in the first element formation region and the second element formation region, and the third conductive film is patterned, so that the interlayer insulating film is formed from the first contact hole. Forming a pattern of the third conductive film extending on the substrate;
Forming a dielectric film on the second conductive film in the second contact hole in the second element formation region and on the third conductive film in the first element formation region; When,
Forming a fourth conductive film on the dielectric film;
By patterning the dielectric film and the fourth conductive film, the fourth conductive film is used as an upper electrode and the third conductive film is used as the lower electrode in the first element formation region. The capacitor as an electrode is formed, and in the second element formation region, the fourth conductive film is used as a control gate, and the second conductive film is used as a floating gate. And a step of forming a composite gate portion.

8. The method of manufacturing a semiconductor memory device according to claim 7, wherein the fourth conductive film is formed on the dielectric film after patterning the dielectric film.

In the step of forming the composite gate portion after forming the fourth conductive film on the dielectric film, the dielectric film and the fourth conductive film are simultaneously patterned. A method of manufacturing a semiconductor memory device according to claim 7.

The dielectric film is formed on the third conductive film, and then the dielectric film is patterned to thereby form the dielectric film in the first element formation region and the second element formation region. The method of manufacturing a semiconductor memory device according to claim 7, further comprising a step of separating the dielectric film.

The first insulating film and the second insulating film are simultaneously formed of the same material, and the first conductive film and the second conductive film are simultaneously formed of the same material. 8. A method for manufacturing a semiconductor memory device according to 1 or 7.

A first memory cell array composed of a first memory cell composed of one MOS transistor and one capacitor is provided in the first element formation region of the semiconductor substrate, and is electrically rewritable and has a floating gate, In a method for manufacturing a semiconductor memory device, comprising: a second memory cell array including a second nonvolatile memory cell having a control gate; and a second element formation region of the semiconductor substrate.
Forming a first insulating film on the semiconductor substrate in the first element formation region and on the semiconductor substrate in the second element formation region;
After forming a first conductive film on the first insulating film in the first element forming region and on the first insulating film in the second element forming region, the first conductive film is formed. Patterning the first conductive film in the element formation region into the shape of the gate electrode of the MOS transistor and patterning the first conductive film in the second element formation region into the shape of the floating gate When,
Ion implantation is performed on the first element formation region on both sides of the gate electrode of the MOS transistor and the second element formation region on both sides of the floating gate to thereby form the first element formation region and the second element formation region. Forming a pair of impurity diffusion layers in the element formation region,
After forming a second insulating film over the entire surface of the semiconductor substrate, a first opening reaching one of the impurity diffusion layers in the first element formation region is formed in the second insulating film, Forming a second hole reaching the first conductive film in the second insulating film in the second element formation region;
After forming the second conductive film so as to fill the first opening and the second opening, respectively, the second conductive film and the second element in the first element formation region Patterning so as to separate the second conductive film in the formation region;
A dielectric film is formed on the second conductive film, a third conductive film is formed on the dielectric film, and the third conductive film in the first element formation region is formed. And a step of patterning so as to separate the third conductive film in the second element formation region from each other.

After the dielectric film is formed on the second conductive film, the dielectric film is patterned, whereby the dielectric film in the first element formation region and the second element formation region 13. The method of manufacturing a semiconductor memory device according to claim 12, wherein the dielectric film is separated.

A first memory cell array composed of a first memory cell composed of one MOS transistor and one capacitor is provided in the first element formation region of the semiconductor substrate, and is electrically rewritable and has a floating gate, In a method for manufacturing a semiconductor memory device, comprising: a second memory cell array including a second nonvolatile memory cell having a control gate; and a second element formation region of the semiconductor substrate.
Forming a first insulating film on the semiconductor substrate in the first element formation region and on the semiconductor substrate in the second element formation region;
After forming a first conductive film on the first insulating film in the first element forming region and on the first insulating film in the second element forming region, the first element is formed. Patterning the first conductive film in the formation region into the shape of the gate electrode of the MOS transistor, and patterning the first conductive film in the second element formation region into the shape of the floating gate; ,
Ion implantation is performed on the first element formation region on both sides of the gate electrode of the MOS transistor and the second element formation region on both sides of the floating gate to thereby form the first element formation region and the second element formation region. Forming a pair of impurity diffusion layers in the element formation region,
Forming a second opening on the entire surface of the semiconductor substrate, and then forming a first opening in the second insulating film that reaches one of the impurity diffusion layers in the first element formation region;
Patterning the second conductive film extending from the first opening onto the second insulating film by patterning the second conductive film formed so as to fill the first opening. Forming a step;
Forming a second hole reaching the first conductive film in the second element formation region in the second insulating film;
Forming a dielectric film on the second conductive film in the first element formation region and on the first conductive film in the second opening in the second element formation region; To form a third conductive film on the dielectric film, the third conductive film in the first element formation region, and the third conductive film in the second element formation region; And a patterning process so as to separate the semiconductor memory device.

The dielectric film is formed on the second conductive film in the first element formation region and on the first conductive film in the second opening in the second element formation region. The dielectric film in the first element formation region and the dielectric film in the second element formation region are separated from each other by patterning the dielectric film. A manufacturing method of the semiconductor memory device according to the above.

The method of manufacturing a semiconductor memory device according to claim 1, wherein the dielectric film is a ferroelectric film.