JP3859213B2 - Dielectric memory and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a dielectric memory and a manufacturing method thereof, and more particularly to a ferroelectric memory and a high dielectric memory that require high-temperature sintering.
[0002]
[Prior art]
  Ferroelectric memory development has started mass production of small-capacity 1 to 64 kbits using a planar type structure, and recently has been centered on development of large-capacity types 256 to 4 Mbit using a stack type structure. ing. The structure of this stacked ferroelectric memory is aimed at reducing the cell size and greatly improving the degree of integration by arranging a contact plug electrically connected to the semiconductor substrate immediately below the lower electrode. In order to realize such a stack type structure, it is important to devise a method for preventing the contact plug from being oxidized by high-temperature heat treatment in an oxygen atmosphere for crystallizing the ferroelectric film. Conventionally, an oxygen barrier film is stacked under the electrode material to realize a structure that prevents contact plug oxidation (for example, Patent Document 1).
[0003]
  Hereinafter, a ferroelectric capacitor structure in a conventional ferroelectric memory will be described with reference to the drawings. 8A to 8C are diagrams showing the main part of a conventional dielectric memory, in which A is a cross-sectional view taken along line VV of C, B is a cross-sectional view taken along line VI-VI of C, and C is a plan view. A ferroelectric capacitor is formed on the first interlayer insulating film 2 on the semiconductor substrate 1. The ferroelectric capacitor is composed of a lower electrode 3 having a laminated structure made of conductive oxygen barrier film (for example, Ru, Ir or oxide thereof) and Pt, a capacitive insulating film 4 made of a ferroelectric film, and an upper electrode 5. The lower electrode 3 is electrically connected via a contact plug 6 to the semiconductor substrate 1 on which the memory cell transistor is formed. Although omitted here, the ferroelectric capacitor is formed with a wiring process after the capacitor interlayer insulating film is formed.
[0004]
  With the above structure, even during high-temperature heat treatment in an oxygen atmosphere when crystallizing the ferroelectric film, the oxygen diffused in the lower electrode is blocked by the oxygen barrier film, and the contact plug is oxidized. Therefore, it is possible to realize a ferroelectric memory with high yield and high reliability.
[0005]
[Patent Document 1]
  JP-A-10-93036
[0006]
[Problems to be solved by the invention]
  However, in the conventional example shown above, oxidation (so-called side oxidation) from the lateral direction of the contact plug during the ferroelectric sintering cannot be completely prevented. Therefore, as miniaturization progresses, that is, as the lower electrode becomes smaller, the problem of reduction in contact yield due to side oxidation has become apparent.
[0007]
  Also, at the interface between the lower electrode and the contact plug or when the lower electrode and the oxygen barrier film are laminated, due to differences in the thermal expansion coefficient of each material, the behavior of the film stress with respect to temperature, or differences in the degree of oxidation There has also been a new problem that peeling occurs at the interface during ferroelectric sintering.
[0008]
  In particular, during the crystallization of a ferroelectric film, in addition to high-temperature heat treatment at 650 ° C or higher, removal of organic components in the ferroelectric film and crystal growth process cause shrinkage of the ferroelectric film and large stress migration occurs. . Similarly, stress migration due to heat treatment occurs in the upper electrode. Although depending on the manufacturing method, when the upper electrode and the ferroelectric film are sintered on the entire wafer surface, the amount of stress change is large, and the upper electrode and the ferroelectric film are baked after patterning. Even if the bonding is performed, for example, the amount of stress change remains in the cell plate direction, and this causes the above-described peeling when the stress concentrates on one lower electrode.
[0009]
  In order to solve the above-mentioned conventional problems, the present invention prevents the oxidation of the contact plug of the stacked ferroelectric capacitor or the peeling of the lower electrode, oxygen barrier film, and contact plug interface due to stress, and can be highly integrated. An object of the present invention is to provide a body memory and a method for manufacturing the same.
[0010]
[Means for Solving the Problems]
  To achieve the above object, the present inventionInvitationThe electric memory is a dielectric memory composed of a lower electrode, a capacitor insulating film, and an upper electrode, which are formed on a substrate in order from below, and the lower electrode has a contact plug electrically connected to the substrate. The upper electrode is formed so as to cover and spread around the first direction.connectedFormed to extend,The shortest distance b between the end surface of the lower electrode in the first direction and the contact plug is smaller than the shortest distance a between the end surface of the lower electrode in the direction orthogonal to the first direction and the contact plug.It is characterized by that.
[0011]
  The long side of the lower electrode is preferably orthogonal to the first direction. The distance a is preferably longer than the distance b by 0.1 μm or more.
[0012]
  The long side of the contact plug is preferably parallel to the first direction. The distance b is preferably 0.25 μm or less.
[0013]
  The length of the upper electrode in the first direction is preferably 500 μm or less. Preferably, the upper electrode is divided and formed with a length of 500 μm or less as a unit so as to extend in the first direction, and the adjacent upper electrodes are electrically connected via the substrate.
[0014]
  in frontIt is preferable that the upper electrode is divided and formed with a length of 500 μm or less as a unit so as to extend in the first direction, and the adjacent upper electrodes are electrically connected via a wiring layer.
[0015]
  It is preferable that an oxygen barrier film is included in at least a part of the lower electrode.
[0016]
  It is preferable that at least a part of the upper electrode includes an oxygen barrier film.
[0017]
  In the first dielectric memory manufacturing method of the present invention, an insulating film is formed on a substrate.And
  Opening a predetermined region of the insulating film to form a contact plug;
  Forming a lower electrode so as to cover and spread around the contact plug;
  Forming a dielectric film on the lower electrode;
  Forming an upper electrode on the dielectric film so as to extend in a first direction;
  After the step of forming the dielectric film, the dielectric is crystallized by heat treatment,
  In the step of forming the lower electrode,The long side of the lower electrode is orthogonal to the first direction, and the shortest distance b between the end surface of the lower electrode and the contact plug is the first direction of the lower electrode. Less than the shortest distance a between the end face in the orthogonal direction and the contact plugIt forms so that it may become.
[0018]
  In a second method of manufacturing a dielectric memory according to the present invention, an insulating film is formed on a substrate,
  Opening a predetermined region of the insulating film to form a contact plug;
  Forming a lower electrode so as to cover and spread around the contact plug;
  Forming a dielectric film on the lower electrode;
  Forming an upper electrode on the dielectric film so as to extend in a first direction;
  After the step of forming the dielectric film, the dielectric is crystallized by heat treatment,
  Contact plugThe long side of the contact plug is parallel to the first direction, and the shortest distance b between the end surface of the first electrode and the contact plug is the lower electrode. Smaller than the shortest distance a between the end face in the direction orthogonal to the first direction and the contact plug.It forms so that it may become.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
  The present inventionInvitationIn the electric memory, the lower electrode is formed so as to cover and cover the contact plug electrically connected to the substrate, and the upper electrode is formed to extend in the first direction. The length extending above is longer in the direction perpendicular to the first direction than in the first direction. By adopting such a configuration, it is possible to prevent contact plug defects and realize cell miniaturization.
[0020]
  In addition, the present inventionInvitationIn the electric memory, it is preferable that the length of the lower electrode extending beyond the contact plug is longer than the first direction by 0.1 μm or more in the direction orthogonal to the first direction. With such a configuration, oxidation of the contact plug can be prevented more reliably.
[0021]
  The present inventionInvitationThe electric memory is formed such that a lower electrode covers a contact plug that is electrically connected to a substrate and spreads around the lower electrode, and an upper electrode is formed to extend in a first direction. The length extending beyond the top is set to a length in which the contact plug is not oxidized by oxygen intrusion from the direction in the direction orthogonal to the first direction. By adopting such a configuration, it is possible to prevent defects due to side oxidation of the contact plug.
[0022]
  The present inventionInvitationThe electric memory is formed such that a lower electrode covers a contact plug that is electrically connected to a substrate and spreads around the lower electrode, and an upper electrode is formed to extend in a first direction. The length extending beyond the top is set to a length that does not cause peeling of the lower electrode due to stress of the capacitive insulating film in the first direction. By adopting such a configuration, it is possible to prevent shape defects such as peeling due to stress of the contact plug.
[0023]
  The present inventionInvitationIn the electric memory, it is preferable that a length of the lower electrode extending beyond the contact plug is 0.25 μm or less in the first direction. By adopting such a configuration, it is possible to reliably prevent peeling due to stress of the contact plug.
[0024]
  The present inventionInvitationThe electric memory is formed such that the lower electrode covers a contact plug electrically connected to the substrate and extends around the lower electrode, the upper electrode is formed to extend in the first direction, and the contact plug is formed of the first plug. The cross-sectional shape is longer in the first direction than in the direction orthogonal to the direction. By adopting such a configuration, it is possible to prevent contact plug defects and realize cell miniaturization.
[0025]
  The present inventionInvitationIn the electric memory, the upper electrode is formed to extend in the first direction, and the length of the upper electrode in the first direction is 500 μm or less. With such a configuration, it is possible to suppress stress applied to the contact plug from the cell plate direction.
[0026]
  The present inventionInvitationIn the electric memory, the upper electrode is divided and formed with a length of 500 μm or less as a unit so as to extend in the first direction, and the adjacent upper electrodes are electrically connected through the substrate. In the seventh dielectric memory of the present invention, the upper electrode is divided and formed with a length of 500 μm or less as a unit so as to extend in the first direction, and the adjacent upper electrodes are electrically connected through a wiring layer. Has been. By adopting such a configuration, it is possible to suppress only stress without being restricted by the regulation in the length direction of the cell plate.
[0027]
  The present inventionInvitationIn the electric memory, it is preferable that at least a part of the lower electrode includes an oxygen barrier film. With such a configuration, oxygen diffused through the lower electrode can be reliably prevented by the oxygen barrier film, and a better effect is produced by suppressing oxidation of the contact plug.
[0028]
  In addition, the present inventionInvitationIn the electric memory, it is preferable that an oxygen barrier film is included in at least a part of the upper electrode. With such a configuration, oxygen diffused through the upper electrode can be reliably prevented by the oxygen barrier film, and a better effect can be obtained by suppressing oxidation of the contact plug.
[0029]
  According to the first and second dielectric memory manufacturing methods of the present invention, the side oxidation of the contact plug can be prevented efficiently and rationally.
[0030]
  Embodiments of the present invention will be described below with reference to the drawings.
[0031]
  (First embodiment)
  FIG. 1A is a cross-sectional view of an upper electrode extension direction (cell plate direction) that is a direction in which upper electrodes of a dielectric memory according to the first embodiment of the present invention are connected and extended, and FIG. 1B is a direction orthogonal to the upper electrode extension direction. FIG. 1C shows a cross-sectional view of the upper electrode in the non-extending direction (bit line direction) and FIG. 1C.
[0032]
  SiO with B, P, etc. added on the semiconductor substrate 1₂A first interlayer insulating film 2 (film thickness 500 to 800 nm) made of a film (commonly referred to as BPSG) is formed, and a ferroelectric capacitor is formed on the first interlayer insulating film 2 (film thickness 200 to 200 nm). ~ 400nm), SBT (SrBi as an example₂Ta₂O₉The capacitor insulating film 4 (film thickness 50 to 200 nm) made of a ferroelectric film and the upper electrode 5 (film thickness 50 to 200 nm). The lower electrode 3 of the ferroelectric capacitor here is connected to the semiconductor substrate 1 via a contact plug 6 made of tungsten (W). Reference numeral 12 denotes an element isolation insulating film (STI).
[0033]
  In general, the crystallization of the ferroelectric film is performed in a high-temperature oxygen atmosphere of 650 ° C. or more. At this time, yield problems such as an increase in resistance of the contact plug and an abnormal shape (peeling) occur. The cause is oxidation of the lower electrode due to oxygen sneaking from the outside and peeling of the lower electrode due to thermal stress change of the upper electrode and the capacitor insulating film. As for the former, since the upper electrode and the ferroelectric film extend in the long direction in the upper electrode extension direction, it becomes an oxygen barrier to some extent, but in the non-extension direction of the upper electrode, a silicon oxide film having high oxygen permeability is usually used. Since there is only an interlayer insulating film, more oxygen diffuses from this direction. Therefore, in the non-extension direction of the upper electrode, it is important to secure a margin for side oxidation by increasing the length (lower electrode extension amount) that the lower electrode end extends beyond the contact plug end when viewed in plan. It is. Regarding the latter, it is clear that the absolute amount of the upper electrode and capacitive insulating film against the thermal stress change is larger in the extension direction of the upper electrode, and this stress change amount concentrates on a specific lower electrode and causes peeling. Yes. In order to prevent this peeling, it is important to ensure adhesion. In addition, experiments by the present inventor have revealed that peeling occurs not in the region immediately above the contact plug but in a region other than the contact plug. This is because the contact plug material diffuses into the lower electrode immediately above the contact plug, and the adhesion is improved. Therefore, it is important to increase the overlap amount of the lower electrode and the contact plug in the direction of extension of the upper electrode where the stress change is large, that is, to further increase the region where the adhesion is improved by diffusion of the contact plug material.
[0034]
  For the above reasons, in the present embodiment, the lower electrode has a rectangular shape that is short in the upper electrode extending direction and long in the upper electrode non-extending direction. As a result, for the oxidation of contacts due to oxygen coming from the outside, which is not protected by the upper electrode or capacitive insulating film, the extension of the lower electrode is lengthened in the non-extension direction of the upper electrode, and the upper part where the stress changes greatly. By increasing the amount of overlap between the lower electrode and the contact plug in the electrode extension direction, contact failure can be prevented.
[0035]
  FIG. 2 shows that a conventional lower electrode having a square shape and a rectangular lower electrode in which the non-extension direction of the upper electrode of the present invention is 0.2 μm larger than the extension direction of the upper electrode, The contact resistance value with respect to the lower electrode extension amount in the upper electrode extension direction when heat treatment is performed in an atmosphere is shown. In the case of a square lower electrode, the lower electrode extension needs to be 0.20μm or more for the contact resistance to satisfy the standard value. When the lower electrode extension becomes 0.15μm or less, the resistance becomes higher (20Ω.cm or more and the upper limit standard) In contrast, the rectangular lower electrode does not begin to have a high resistance up to 0.10 μm.
[0036]
  From the above, the upper electrode non-extension direction is more susceptible to side oxidation than the upper electrode extension direction, and the upper electrode non-extension direction is 0.2 μm larger than the upper electrode extension direction. Thus, it can be seen that the same contact resistance value can be obtained even when the extension amount of the lower electrode in the extension direction of the upper electrode is shortened by 0.10 μm compared to the conventional square lower electrode.
[0037]
  FIG. 3 shows the relationship between the extension amount of the lower electrode with respect to the contact plug of the lower electrode in the extension direction of the upper electrode and the number of occurrences of peeling of the lower electrode. When the extension amount of the lower electrode is 0.25 μm or less, peeling of the lower electrode does not occur. However, peeling occurs between 0.3 μm and 0.4 μm, and peeling does not occur at 0.5 μm or more.
[0038]
  This phenomenon occurs similarly even when stress migration occurs in the direction of extension of the upper electrode. The cause is considered as follows.
(1) When the thickness is 0.25 μm or less, the interface with better adhesion directly above the contact plug occupies a high proportion of the whole, and peeling is less likely to occur.
(2) Although 0.3 to 0.45 μm reduces the effective ratio of the area with good adhesion directly above the contact plug, only the area exposed to the side oxidation area increases, contributing to effective adhesion improvement. And peeling is likely to occur.
(3) If the thickness is 0.5 μm or more, a sufficient area not exposed to the side oxidation area is secured, which leads to an improvement in adhesion.
[0039]
  From the above, in consideration of cell miniaturization, it is desirable that the extension amount of the lower electrode in the extension direction of the upper electrode be 0.25 μm or less.
[0040]
  Next, a method for manufacturing the dielectric memory according to the present embodiment will be described with reference to FIGS. 1A to 1C are diagrams showing a main part of the dielectric memory according to the first embodiment of the present invention. FIG. 1A is a cross-sectional view taken along line II of FIG. 1C, and FIG. 1B is a line II-II of FIG. Sectional drawing C is a top view. 7A to 7E are process cross-sectional views illustrating a method for manufacturing a dielectric memory according to an embodiment of the present invention.
[0041]
  In FIG. 7A, an interlayer insulating film (for example, BPSG) 2 is formed on a semiconductor substrate 1 formed of a high concentration impurity diffusion layer and an isolation region. Next, in FIG. 7B, using a desired mask, a contact is opened in the interlayer insulating film 2 to electrically connect the semiconductor substrate and the lower electrode of the ferroelectric capacitor (W, Poly Si). Form. Next, in FIG. 7C, a film (Pt) for promoting crystal growth of the ferroelectric film and a conductive film made of an oxygen barrier layer (IrO / Ir / TiAlN) are stacked, and a desired mask, that is, an upper portion formed above. The lower electrode 3 as shown in FIG. 1C is patterned by covering the first contact plug 3 with a lower electrode mask having a small width in the extending direction of the electrode and a large width in the non-extending direction. Form. Next, a lower inter-electrode buried insulating film 11 (for example, O3TEOS, O_ThreeAnd Si (OC₂H_Five)_Four : A raw material of Tetraethylorthosilicate is formed by a CVD method), and the surface of the lower electrode 3 is exposed using a CMP (chemical mechanical polishing) method. Here, the lower electrode is embedded in the insulating film, but the present invention is not restricted. Next, as shown in FIG. 7D, a ferroelectric solution is applied by spin coating to form a ferroelectric film 4A. Ferroelectric film is baked at a low temperature of 400 ° C or less to remove organic components, and then RTP (Rapid Thermal Process) is performed at 650 ° C for 1 minute in an oxygen atmosphere as a nucleus for subsequent crystallization. Is desirable. A conductive film 5A made of Pt is formed thereon. Finally, as shown in FIG. 7E, the ferroelectric film 4 and the upper electrode 5 are formed by patterning so as to cover the lower electrode 3 using a desired mask. Here, the ferroelectric film and the upper electrode are patterned using the same mask, but they may be formed using different masks. After patterning, the ferroelectric film is heat-treated at high temperature to be crystallized. In the case of SBT material, the heat treatment temperature is about 650 ° C to 800 ° C. By performing sintering after patterning, stress migration of the upper electrode and the ferroelectric film can be limited to the direction of extension of the upper electrode, and at the same time, the lower electrode is in the direction of non-extension of the upper electrode against side oxidation from the non-extension direction. A sufficient lower electrode extension amount can be secured.
[0042]
  (Second Embodiment)
  4A to 4C are diagrams showing the main part of the dielectric memory according to the second embodiment of the present invention. FIG. 4A is a sectional view taken along line III-III in FIG. 4C, and FIG. 4B is a sectional view taken along line IV-IV in FIG. Sectional drawing C is a top view. That is, a sectional view of an upper electrode extending direction (cell plate direction) that is a direction in which the upper electrodes of the dielectric memory are connected and extending, and an upper electrode non-extending direction (bit line direction) that is a direction orthogonal to the upper electrode extending direction; A plan view is shown.
[0043]
  A ferroelectric capacitor is formed on the first interlayer insulating film 2 (film thickness 500 to 800 nm) made of a BPSG film on the semiconductor substrate 1, and the ferroelectric capacitor is formed on the lower electrode 3 (film thickness 200 to 400 nm). ), A capacitive insulating film 4 (film thickness 50 to 200 nm) made of an SBT ferroelectric film, and an upper electrode 5 (film thickness 50 to 200 nm). The lower electrode 3 of the ferroelectric capacitor here is connected to the semiconductor substrate 1 via a contact plug 6 made of W.
[0044]
  In contrast to the problem described in the first embodiment, in this embodiment, the contact plug has a rectangular shape that is long in the upper electrode extension direction and short in the non-extension direction. As a result, for the oxidation of contacts due to oxygen coming from the outside, which is not protected by the upper electrode or capacitive insulating film, the extension of the lower electrode is lengthened in the non-extension direction of the upper electrode, and the upper part where the stress changes greatly. By increasing the amount of overlap between the lower electrode and the contact plug in the electrode extension direction, contact failure can be prevented.
[0045]
  Next, a method for manufacturing the dielectric memory according to this embodiment will be described with reference to FIGS. 4A to 4B and FIGS.
[0046]
  In FIG. 7A, an interlayer insulating film (for example, BPSG) 2 is formed on a semiconductor substrate 1 formed of a high concentration impurity diffusion layer and an isolation region. Next, in FIG. 7B, using a desired mask, a contact is opened in the interlayer insulating film 2 to electrically connect the semiconductor substrate and the lower electrode of the ferroelectric capacitor as shown in FIG. 4C. 6 (W, Poly Si) is formed. Next, in FIG. 7C, a film (Pt) for promoting crystal growth of a ferroelectric film and a conductive film made of an oxygen barrier layer (IrO / Ir / TiAlN) are stacked, and a desired mask, that is, a lower part having a square shape. The lower electrode 3 is formed by patterning to cover the first contact plug 3 using an electrode mask. Next, a lower inter-electrode buried insulating film 11 (for example, O3TEOS) is formed on the lower electrode 3, and the surface of the lower electrode 3 is exposed using CMP. Here, the lower electrode is embedded in the insulating film, but the present invention is not restricted. Next, as shown in FIG. 7D, a ferroelectric solution is applied by spin coating to form a ferroelectric film 4A. The ferroelectric film is preferably baked at a low temperature of 400 ° C. or lower for removing organic components, and RTP is performed in an oxygen atmosphere at 650 ° C. for 1 minute as a nucleus for subsequent crystallization. A conductive film 5A made of Pt is formed thereon. Finally, as shown in FIG. 7E, the ferroelectric film 4 and the upper electrode 5 are formed by patterning so as to cover the lower electrode 3 using a desired mask. Here, the ferroelectric film and the upper electrode are patterned using the same mask, but they may be formed using different masks. After patterning, the ferroelectric film is heat-treated at high temperature to be crystallized. The SBT material is about 650 ° C to 800 ° C. By performing sintering after patterning, stress migration of the upper electrode and the ferroelectric film can be limited to the direction of extension of the upper electrode, and at the same time, the lower electrode is in the direction of non-extension of the upper electrode against side oxidation from the non-extension direction. A sufficient lower electrode extension amount can be secured.
[0047]
  In the first and second embodiments, at least a part of the lower electrode and / or at least a part of the upper electrode is provided with, for example, Ir, IrO, Ru, RuO, TiAlN, TaAlN, TaN, TaSiN, or a stacked structure thereof. It is desirable to include an oxygen barrier film made of Thereby, the diffusion of oxygen from directly above the contact plug can be prevented.
[0048]
  (Third embodiment)
  FIG. 5 shows the number of occurrences of peeling of the lower electrode relative to the total extension in the upper electrode extension direction. Here, the lower electrode is subjected to RTP heat treatment in an oxygen atmosphere at 800 ° C. for 1 minute using a conventional structure in which the lower electrode extension amount with respect to the contact plug is the same in both the upper electrode extension direction and the upper electrode non-extension direction.
[0049]
  From FIG. 5, it can be seen that the total extension in the upper electrode extension direction is preferably 500 μm or less because peeling is observed from a region where the total extension in the upper electrode extension direction is larger than 500 μm.
[0050]
  6A and 6B are cross-sectional views showing a connection portion between upper electrodes in which the total extension in the upper electrode extension direction of the dielectric memory according to the third embodiment of the present invention is defined as 500 μm.
[0051]
  A ferroelectric capacitor is formed on a first interlayer insulating film 2 made of a BPSG film on a semiconductor substrate 1, and the ferroelectric capacitor is composed of a lower electrode 3 and a capacitive insulating film 4 made of an SBT ferroelectric film. The upper electrode 5 is constituted. The lower electrode 3 of the ferroelectric capacitor here is connected to the semiconductor substrate 1 via a contact plug 6 made of W.
[0052]
  In FIG. 6A, a contact opening 7 is provided at a specific location of the capacitive insulating film, and the adjacent upper electrode is electrically connected via the contact opening 7, the lower electrode 3, and the diffusion layer in the semiconductor substrate 1. It is connected.
[0053]
  In FIG. 6B, a contact plug 9 is formed at a specific location in the interlayer insulating film 8 formed on the capacitor, and the adjacent upper portion is connected via the adjacent contact plug 9 and the wiring 10 formed on the interlayer insulating film 8. The electrodes 7 are electrically connected.
[0054]
  From the above, even if the total extension in the upper electrode extension direction is restricted, by connecting the adjacent upper electrode via another conductive layer, the restriction on the total extension in the upper electrode extension direction is effectively eliminated, and free It becomes possible to lay out.
[0055]
【The invention's effect】
  As described above, according to the dielectric memory of the present invention and the manufacturing method thereof, the oxidation from the side wall direction from the lower electrode to the contact plug by oxygen, so-called side oxidation is prevented, and the stress applied in the upper electrode extension direction is also prevented. It is possible to prevent peeling inside the lower electrode due to migration and peeling at the contact plug interface.
[Brief description of the drawings]
FIGS. 1A to 1C are views showing a main part of a dielectric memory according to a first embodiment of the present invention, wherein A is a sectional view taken along line II of C, and B is a sectional view taken along line II-II of C; , C is a plan view.
FIG. 2 is a view showing a relationship between a lower electrode extension amount and contact resistance in the dielectric memory according to the first embodiment of the present invention;.
FIG. 3 is a view showing the relationship between the lower electrode extension amount (upper electrode non-extension direction) and the number of peeling occurrences in the dielectric memory according to the first embodiment of the present invention.
FIGS. 4A to 4C are views showing a main part of a dielectric memory according to a second embodiment of the present invention, wherein A is a cross-sectional view taken along line III-III of C, and B is a cross-sectional view taken along line IV-IV of C; FIGS. , C is a plan view.
FIG. 5 is a view showing the relationship between the length in the extension direction of the upper electrode and the number of peeling occurrences in the dielectric memory according to the third embodiment of the present invention..
6A and 6B are cross-sectional views showing connection means between adjacent upper electrodes in a dielectric memory according to a third embodiment of the present invention..
7A to 7E are process cross-sectional views illustrating a method of manufacturing a dielectric memory according to the first and second embodiments of the present invention..
FIGS. 8A to 8C are diagrams showing a main part of a conventional dielectric memory, wherein A is a cross-sectional view taken along line VV of C, B is a cross-sectional view taken along line VI-VI of C, and C is a plan view..
[Explanation of symbols]
  1 Semiconductor substrate
  2 Interlayer insulation film
  3 Lower electrode
  4 Ferroelectric film (capacitive insulating film)
  4A Ferroelectric film
  5 Upper electrode
  5A conductive layer
  6 Contact plug (between semiconductor substrate and lower electrode)
  7 Contact (capacitive insulating film)
  8 Interlayer insulation film on capacitor
  9 Contact plug (upper electrode and wiring)
  10 AL wiring
  11 Lower electrode spacer film
  12 Device isolation insulating film (STI)

Claims (12)

A dielectric memory composed of a lower electrode, a capacitor insulating film and an upper electrode, which are formed by laminating on a substrate in order from below,
The lower electrode is formed so as to cover a contact plug electrically connected to the substrate and spread around the contact plug,
The upper electrode is formed so as to extend led to the first direction,
The shortest distance b between the end surface of the lower electrode in the first direction and the contact plug is smaller than the shortest distance a between the end surface of the lower electrode in the direction orthogonal to the first direction and the contact plug. Characteristic dielectric memory. The dielectric memory according to claim 1, wherein a long side of the lower electrode is orthogonal to the first direction. The dielectric memory according to claim 1, wherein the distance a is longer than the distance b by 0.1 μm or more. The dielectric memory according to claim 1, wherein a long side of the contact plug is parallel to the first direction. The dielectric memory according to claim 1 , wherein the distance b is 0.25 μm or less. Ferroelectric memory according to claim 1, the length of the upper electrode before Symbol first direction is 500μm or less. Before SL upper electrode is divided form as a unit length less than 500μm so as to extend in the first direction, it is between the upper electrode adjacent according to claim 1 which is electrically connected through said substrate Dielectric memory. Before SL upper electrode is divided form as a unit length less than 500μm so as to extend in the first direction, it is between the upper electrode adjacent according to claim 1 which is electrically connected through a wiring layer Dielectric memory. Ferroelectric memory according to any one of claims 1 to 8 contains oxygen barrier film on at least a portion of the lower electrode. Ferroelectric memory according to any one of claims 1 to 9 contains an oxygen barrier film on at least a portion of the upper electrode. An insulating film is formed on the substrate ,
Opening a predetermined region of the insulating film to form a contact plug;
Forming a lower electrode so as to cover and spread around the contact plug;
Forming a dielectric film on the lower electrode;
Forming an upper electrode on the dielectric film so as to extend in a first direction;
After the step of forming the dielectric film, the dielectric is crystallized by heat treatment,
In the step of forming the lower electrode, the long side of the lower electrode is orthogonal to the first direction, and the shortest distance b between the end surface of the lower electrode in the first direction and the contact plug is A method for manufacturing a dielectric memory, comprising: forming a lower electrode so as to be smaller than a shortest distance a between an end face of the lower electrode in a direction orthogonal to the first direction and the contact plug . An insulating film is formed on the substrate,
Opening a predetermined region of the insulating film to form a contact plug;
Forming a lower electrode so as to cover and spread around the contact plug;
Forming a dielectric film on the lower electrode;
Forming an upper electrode on the dielectric film so as to extend in a first direction;
After the step of forming the dielectric film, the dielectric is crystallized by heat treatment,
In the step of forming the contact plug, a long side of the contact plug is parallel to the first direction, and a shortest distance b between the end surface of the lower electrode in the first direction and the contact plug is A method of manufacturing a dielectric memory, wherein the lower electrode is formed so as to be smaller than a shortest distance a between an end surface of the lower electrode in a direction orthogonal to the first direction and the contact plug .

Images