JP3858905B2 - Sound generator using memory - Google Patents

Description

  The present invention relates to a memory-use sound generator for generating a musical sound waveform by reading waveform data stored in a waveform memory.

A conventional waveform memory sound source generates a musical sound signal by sequentially reading waveform data from a waveform memory that stores musical sound waveform sample value data based on phase data corresponding to the pitch of the musical sound to be generated. Yes.
In an electronic musical instrument equipped with such a waveform memory, a technique called time-division channel processing is used to simultaneously generate a plurality of musical tone signals. This time division channel processing divides a certain time into a plurality of time slots, reads waveform data for each time slot, and accumulates the waveform data read in the plurality of time slots within the certain time. This means that a plurality of waveform data is simultaneously read from the waveform memory at regular intervals.

  In the conventional time division channel processing, a certain time is divided into as many time slots as possible, and generally, the waveform memory sound source operates asynchronously with the operation clock of a processing device such as a CPU. Therefore, when the waveform memory sound source is performing time-division channel sound generation processing, the waveform memory cannot be accessed by a processing device such as a CPU.

  The present invention has been made in view of the above-described points, and an object of the present invention is to provide a memory-use sound source device in which a method of exchanging data with a processing device is devised.

A sound source device using a memory according to the present invention is a sound source device that performs time division operation of a plurality of channels, and stores a memory that stores sound source data and control data for controlling the operation of each channel of the plurality of channels in the sound source device. A control register for storing and writing the control data by the processing means, and an address counter means for generating a memory read / write address for each channel based on address information included in the control data of the control register; Including a latch capable of inputting and holding data to be stored in the memory as new sound source data by the processing means, and excluding specific channels that are not used for generating musical sounds from the plurality of channels in the remaining time of each channel, to be generated in the rest of the channels Reads the data for the sound source from the memory based on the address for reading generated by the address counter means in response to the sound, the timing of the particular channel, the new sound source is held in the latch Memory access means for writing data to the memory based on the write address generated corresponding to the specific channel, and reading the remaining channels according to the tone to be generated And a tone generator for generating a tone signal based on the sound source data and the control data.
According to the present invention, the address for memory read / write is generated for each channel based on the address information included in the control data supplied from the processing means, and a specific channel that is not used for generating a musical sound among a plurality of channels is excluded. in the remaining time of each channel, said based on the remaining address for reading generated according to the musical tone to be generated in each channel reads data for the sound source from the memory, generates a tone signal based on this . On the other hand, when writing sound source data from the processing means to the memory, an address for data writing is generated corresponding to a specific channel in accordance with an instruction from the processing means, and the data to be written is temporarily stored in the latch. Saved. Therefore, in the memory access means, it is only necessary to write the data of the latch into the memory based on the generated address using a specific channel that is not used for generating a musical sound among a plurality of time division channels. Since there is no interference with the time-division channel timing for generation processing, a margin can be given to the writing processing. Therefore, even if the processing means operates asynchronously with the memory-use sound source device, control without problems can be performed. In that case, a plurality of data is supplied by a single write instruction, these are temporarily stored in the latch, and control is performed so that the data is sequentially written in the latch, so that the processing means can efficiently use the bus. .
According to an embodiment of the present invention, the processing means holds the data for the sound source to be written in the latch, writes address information indicating an address at which the data is written to the memory, and writes to the control register. The address counter means generates an address of the specific channel based on the address information written in the control register, and the memory access means generates the latch at the timing of the specific channel. The data held in the memory is written into the memory based on the address.
As an embodiment of claim 3, the latch can hold a plurality of data, the processing means holds a plurality of data to be written in the latch, and the address counter means A plurality of addresses are sequentially generated as addresses of the specific channel at a specific channel timing, and the memory access means generates a plurality of data held in the latch based on the generated plurality of addresses. The writing is sequentially performed on the memory, and when the sequential writing is completed, a writing end notification is generated.

A memory-use sound source device according to still another aspect of the present invention is a sound source device that performs time division operation of a plurality of channels, and controls a memory that stores data for sound sources and operation of each channel of the plurality of channels in the sound source device. A control register in which control data can be stored and written by the processing means, and an address for generating a memory read / write address for each channel based on address information included in the control data of the control register and counter means comprises a latch that can retrieve data by said processing means, the remaining time of each channel except the particular channel that is not used for tone generation of said plurality of channels generated in the rest of the channels generated by the address counter means in response to should do tone Together based on the address for the out look reads the data for the sound source from the memory, the memory at the timing of the specific channel, based on the address for reading that is generated corresponding to the particular channel From the memory access means for reading out the data for the sound source and inputting it to the latch and holding it, so that the data held in the latch is retrieved by the processing means, and the remaining channels, And a tone generator for generating a tone signal based on the sound source data and the control data read according to the tone to be generated.
According to the present invention, the address for memory read / write is generated for each channel based on the address information included in the control data supplied from the processing means, and a specific channel that is not used for generating a musical sound among a plurality of channels is excluded. in the remaining time of each channel, said based on the remaining address for reading generated according to the musical tone to be generated in each channel reads data for the sound source from the memory, generates a tone signal based on this . On the other hand, when reading sound source data from the memory to the processing means, an address for data reading is generated corresponding to a specific channel in accordance with an instruction from the processing means, so that a musical sound is generated in a plurality of time-division channels. The sound source data is read from the memory based on the generated address using a specific channel that is not used and held in the latch, and the data held in the latch is retrieved by the processing means. To do. Therefore, since the processing means only needs to capture the data stored in the latch, and it does not interfere with the time-division channel timing for the tone generation processing even when reading from the memory, it is possible to give a margin to the capture processing. . Therefore, even if the processing means operates asynchronously with the memory-use sound source device, control without problems can be performed. In that case, if data for a plurality of sound sources are read out by a single read instruction, these are temporarily stored in a buffer, and transferred to the processing means, the efficient use of the processing means bus can be achieved. .
According to an embodiment of the present invention, the processing means writes address information indicating an address from which the sound source data is to be read from the memory to the control register and generates a read instruction, thereby generating the address. The counter means generates the address of the specific channel based on the address information written in the control register, and the memory access means generates the sound source for the sound source from the memory based on the address at the timing of the specific channel. Is read and held in the latch, and when the read is completed, a read end notification is generated, and in response to the end notification, the processing means reads the data read from the memory and held in the latch. It is characterized by being taken out from the latch.
As an embodiment of claim 6, the latch is capable of holding a plurality of data, and the address counter means sets a plurality of addresses as the address of the specific channel at the timing of the specific channel. The memory access means sequentially reads out a plurality of data from the memory based on the generated plurality of addresses and sequentially holds the data in the latch, and the processing means is read from the memory. A plurality of data held in the latch are sequentially extracted from the latch.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 2 is a diagram showing an overall configuration of an electronic musical instrument incorporating a sampler type waveform memory sound source according to an embodiment of the present invention.
The microprocessor unit (CPU) 20 controls the operation of the entire electronic musical instrument. The CPU 20 is connected to the ROM 21, RAM 22, keyboard 23, panel switch 24, panel display 25, interface 26, analog-digital converter (ADC) 27, and sound source circuit 2A via the data and address bus 2J. ing.
The ROM 21 stores various programs and various data of the CPU 20, and is composed of a read only memory (ROM).
The RAM 22 temporarily stores various data generated when the CPU 20 executes a program. Each RAM 22 is assigned a predetermined address area of a random access memory (RAM) and is used as a register, flag, buffer, or the like. The

The keyboard 23 is provided with a plurality of keys for selecting the pitches of musical tones to be generated, and various data such as note-on, note-off, velocity, pitch data, etc. according to the operation of each key. The data is output to the CPU 20 via 2J. Instead of the keyboard 23, a computer or the like may be connected to input desired performance data.
The panel switch 24 includes various operators for selecting, setting, and controlling a timbre, volume, effect, and the like.
The panel display 25 displays various information such as the control state of the CPU 20 and the contents of setting data on a liquid crystal panel (LCD) or the like.
The microphone 28 converts an audio signal, a musical instrument sound, and the like into an analog voltage signal and outputs the analog voltage signal to the ADC 27. The ADC 27 converts the analog voltage signal from the microphone 28 into a digital signal and outputs it to the data and address bus 2J.
The hard disk 29 has a storage capacity of several tens to several hundreds of megabytes (MB), and is connected to the data and address bus 2J via the interface 26.

  The tone generator circuit 2A generates a tone signal by a memory read system that sequentially reads tone waveform data from the waveform memory 2D in the tone generator circuit 2A in accordance with frequency data that changes according to the pitch of the tone to be generated. Yes, music signals can be generated simultaneously on multiple channels. Data and performance data (data based on the MIDI standard, etc.) given via the address bus 2J are input, and music signals are output based on this data. appear. In this embodiment, the electronic musical instrument operates in a time-sharing manner of 32 channels, of which 31 channels are used for simultaneous sound generation and the remaining one channel is used for data reading / writing by the CPU 20.

  The tone generator circuit 2A can simultaneously generate musical tone signals in a plurality of channels, and performance data (pitch data, note-on, waveform start address (WSA), loop start address) provided via the data and address bus 2J. (LPS), loop end address (LPE), rate, level, other parameters, data conforming to the MIDI standard, etc.) are input, and a tone signal is generated based on these data and output to the sound system 2H. .

The sound source circuit 2A includes a sound source I / O 2B, a waveform generation unit 2C, a waveform memory 2D, an envelope applying unit 2E, a channel accumulation unit 2F, and a digital-analog converter (DAC) 2G.
The sound source I / O 2B inputs performance data supplied from the CPU 20 via the data and address bus 2J to the sound source side, and outputs data on the sound source side to the CPU 20 via the data and address bus 2J.

The waveform generator 2C reads the waveform data from the waveform memory 2D based on the performance data input via the sound source I / O 2B, and outputs a musical sound signal corresponding to the read waveform data to the envelope applying unit 2E.
The waveform memory 2D is a waveform sampled by the microphone 28 or waveform data consisting of data for a plurality of periods constituting the rising part (attack part) and data for one period constituting the subsequent sustaining part (loop part). Data and the like are stored, an address signal from the waveform generator 2C is input, and waveform data stored in an area corresponding to the address signal is output.

The envelope assigning unit 2E adds an envelope having a shape based on performance data such as rate and level input via the sound source I / O 2B to the musical tone signal from the waveform generating unit 2C, and synchronizes it with the key-on input. Output to the channel accumulation unit 2F at the timing.
The channel accumulating unit 2F performs accumulating processing on the tone signal of each channel output from the envelope applying unit 2E in a time-sharing manner of 32 channels and outputs it to the DAC 2G.

The DAC 2G converts a digital musical tone signal into an analog musical tone signal and outputs it to the sound system 2H.
The musical sound signal output from the sound source circuit 2A is generated from the speaker via the sound system 2H.

FIG. 1 is a diagram showing a detailed configuration of the sound source I / O 2B of FIG.
In this embodiment, the tone generator I / O 2B includes a CPU bus control unit 11, an address latch (A latch) 12, a data latch (D latch) 13, a write buffer amplifier 14, a read buffer amplifier 15, and a write decoder. 16, write pulse generator 17, read decoder 18, channel latch (ch latch) 19, channel converter (ch converter) 1A, channel counter (ch counter) 1B, selector 1C, tone control register 1D, waveform memory It consists of I / O1E.

  The sound source I / O 2B receives the lower address ADR (8-bit configuration), data DATA (8-bit configuration), write control signal * WR, and read control signal * RD from the CPU 20 via the data and address bus. Here, “*” in the write control signal * WR and the read control signal * RD indicates active low enabled at the low level “0”. Since the upper address among the addresses output by the CPU 20 is used as an address for designating each device, only the lower address ADR is input to the sound source I / O 2B.

  When the write control signal * WR is at the low level “0”, the CPU bus control unit 11 supplies an enable signal to the write buffer amplifier 14, and conversely, the read control signal * RD is at the low level “0”. In the case of “,” an enable signal is supplied to the read buffer amplifier 15. That is, the CPU bus control unit 11 operates so as to enable only one of the write buffer amplifier 14 and the read buffer amplifier 15. In addition, when the write control signal * WR or the read control signal * RD becomes the low level “0”, the CPU bus control unit 11 sends the latch pulse LW to the address latch 12 and the data latch 13 at the falling timing. Output.

The address latch 12 latches the lower address ADR by inputting the latch pulse LW from the CPU bus control unit 11. The data latch 13 latches data DATA by inputting a latch pulse LW from the CPU bus control unit 11.
The write buffer amplifier 14 outputs data DATA to the data latch 13 in response to the input of the enable signal from the CPU bus control unit 11. The read buffer amplifier 15 outputs read data WDR from the waveform memory I / O to the data bus DATA in response to an enable signal input from the CPU bus control unit 11.

The write decoder 16 decodes the address ADR latched in the address latch 12 when the write control signal * WR becomes the low level “0”, and sends the write decode signal to the write pulse generator 17. Output to.
The write pulse generator 17 supplies the write pulse signal WP1 corresponding to the write decode signal from the write decoder 16 to the write address terminal WAD of the waveform memory I / O1E, and the write pulse signal WP2 to the musical tone control register. In addition to outputting to 1D, the latch pulse LC is output to the channel latch 19. That is, when the address ADR latched in the address latch 12 is “0”, “1”, “3”, “4”, the write pulse generator 17 has the corresponding A0, A1, A3, and A4 respectively. One of the write pulse signals WP1 is output.

  The read decoder 18 decodes the address ADR latched in the address latch 12 when the read control signal * RD becomes low level “0”, and reads the read decode signal RP1 into the read address of the waveform memory I / O1E. Output to terminal RAD. That is, when the address ADR latched in the address latch 12 is “2”, “5”, “6”, the read decoder 18 is one of the corresponding read decode signals RP1 of A2, A5, and A6, respectively. Is output.

When the latch pulse LC is input from the write pulse generator 17, the channel latch 19 latches the data DATA from the data latch 13 accordingly. The data DATA is output to the channel conversion unit 1A as channel selection data CSD.
The channel conversion unit 1A receives the address ADR from the address latch 12 and the channel selection data CSD from the channel latch 19, and based on this, to which channel timing position of the musical tone control register 1D data is written, its channel designation address CDA Is generated.
The channel counter 1B sequentially counts from channel 0 to channel 31 and outputs the channel number to the selector 1C. The channel counter 1B outputs to the channel terminal ch of the waveform memory I / O a timing signal φ31ch that takes a high level “1” only for a period of one channel corresponding to the last 32nd 31st channel.

The selector 1C receives the channel designation address CDA from the channel conversion unit 1A and the channel number from the channel counter 1B, and outputs either one to the tone control register 1D based on a regular clock.
The musical tone control register 1D includes a plurality of types of data (pitch data for controlling the pitch, note-on for instructing the start and end of musical tone generation, waveform start address (WSA) for controlling the waveform generation operation in the waveform generator 2C. ), Loop start address (LPS), loop end address (LPE), and other data for controlling modulation effects and timbre changes due to touch, etc.) and multiple types of data for controlling the volume envelope applying operation in the envelope applying unit ( Each state rate data, level data, note-on, and other data required for generating an operational envelope is configured by a plurality of registers for storing in respective areas corresponding to each time division channel timing. Here, the data output from the selector 1C is used as instruction data for instructing a timing position for instructing which channel timing data to access among the data of the registers stored for a plurality of time-division channels.

In each time division channel of the sound source, the plurality of types of data stored in the tone control register 1D are supplied to the sound generator control register 1D in order to supply the plurality of types of data required by the waveform generation unit 2C and the envelope applying unit 2E, respectively. At the timing of each time division channel, the data is read out in parallel according to the channel number supplied from the channel counter 1B via the selector 1C, and the read-out plural types of data are respectively sent to the waveform generator 2C and the envelope applying unit 2E. Supplied in parallel.
On the other hand, writing to the musical tone control register 1D from the CPU 20 is performed while the selector 1C selects the channel designation address CDA output from the channel conversion unit 1A at a timing that does not overlap with the above-described reading by the channel counter 1B.

  By the way, since the address ADR latched by the A latch 12 is 8 bits, it is possible to designate addresses from “0” to “255” by this address. As described above, the addresses “0” to “6” are used as the write pulse signal WP1 and the read decode signal RP1, and when the address “7” of the latch pulse LC for the channel latch 19 is used, As addresses of the plurality of types of registers in the musical tone control register 1D, other addresses “8” to “255” can be used. For example, the address is assigned such that note-on is address “8”, pitch data is address “9”, attack state rate data is address “10”, and so on.

That is, when writing the musical tone control register 1D, the CPU 20 writes the number of the time division channel to be written in the channel latch 19 in advance, and then selects the type of the register in the musical tone control register 1D to be written as described above. A designated address is supplied to the A latch 12 and a value to be written is supplied to the D latch 13. In this state, the write signal * WR is enabled and the write is executed.
At this time, the channel instruction address CDA supplied as the instruction data from the channel conversion unit 1A to the musical tone control register 1D is the channel number written in the channel latch 19 of the register at the address designated by the A latch 12. The corresponding timing position is specified. Upon receiving the decode signal generated by the write decoder 16 when the write signal * WR is enabled, the write pulse generator 17 corresponds to the address specified for the A latch 12 in the plurality of signal lines of the write pulse signal WP2. A single write pulse is generated on the line. In response to this write pulse, latched in the D latch 13 at the timing position corresponding to the channel number latched in the channel latch 19 of the type of register designated by the address of the A latch 12 in the tone control register 1D. The value data is written.

  The waveform memory I / O1E has the timing signal φ31ch from the channel counter 1B as the channel terminal ch, the write waveform data WD from the data latch 13 as the data input terminal DI, and the write pulse signal from the write pulse generator 17. WP1 is input to the write address terminal WAD, and the read decode signal RP1 from the read decoder 18 is input to the read address terminal RAD. The read waveform data WDR and the read end data WED read from the waveform memory 2D (however, the bus Is shared with WRD) from the data output terminal DO to the read buffer amplifier 15. That is, the waveform memory I / O1E takes in the write waveform data WD to be written in the waveform memory 2D and writes it into the waveform memory 2D at a predetermined timing (timing at which the timing signal φ31ch is output from the channel counter 1B). The detailed configuration of the waveform memory I / O will be described later.

FIG. 3 is a diagram showing a detailed configuration of the waveform memory I / O1E of FIG.
In the channel control register 31, the write data WD from the data latch 13 is written and written in accordance with the write pulse signal A0 output from the write pulse generator 17 when the address ADR is "0". Among the data, the operating signal USE is output to the access count detector 35 and the 4 consecutive pulse generators 3E, and the write / read control signal W / * R is output to the control terminals of the 4 consecutive pulses generator 3E and the selector 3H. . The operating signal USE is also output to the frequency number generator (F number generator) 41 shown in FIG.

The pulse generator 32 outputs a one-sample read completion pulse RSP to the OR circuit 33 when the read decode signal A6 output from the read decoder 18 is input when the address ADR is “6”.
The OR circuit 33 receives the one-sample read completion pulse RSP from the pulse generator 32 and the write pulse signal A4 output from the write pulse generator 17 when the address ADR is “4”, and outputs a logical sum of both. Is output to the OR circuit 3F and the access count detector 35.

  The upper latch 34 latches the write waveform data WD from the data latch 13 when the write pulse signal A3 output from the write pulse generator 17 is input when the address ADR is "3", and It is output to the B terminal of the selector 3H in parallel with the write waveform data WD having a lower 8-bit configuration sent together with the next address ADR “4”. That is, the upper latch 34 extends the write waveform data WD having an 8-bit configuration to a 16-bit configuration.

  The access count detection unit 35 is in operation from the write pulse signal (hereinafter referred to as “start signal”) A1 output from the write pulse generation unit 17 and the channel control register 31 when the address ADR is “1”. The signal USE and the logical sum signal from the OR circuit 33 are input. The access number detection unit 35 is cleared by the start signal A1, and then counts the signal output from the OR circuit 33. If the access from the CPU 20 has been performed four times, that is, in the case of writing from the CPU 20, the four latches 3J, It is detected whether the write waveform data WD has been transferred to 3K, 3L, and 3M, respectively, and in the case of reading by the CPU 20, whether the four 16-bit data written in the four latches has been read. Then, the detection signal is output to the OR circuit 36.

The OR circuit 36 outputs a logical sum signal of the start signal A 1 and the detection signal from the access count detection unit 35 to the set terminal S of the flip-flop circuit 37.
The flip-flop circuit 37 inputs the logical sum signal from the OR circuit 36 to the set terminal S, the delay signal from the delay 3C to the reset terminal R, outputs the set output to the AND circuit 38, and outputs the inverted output to the gate circuit. Output to 3P.
When the address decode signal A2 output from the read decoder 18 is input when the address ADR is "2", the gate circuit 3P reads the inverted output of the flip-flop circuit 37 and the read end data WED from the data output terminal DO. The data is output to the CPU 20 via the buffer amplifier 15.

The AND circuit 38 outputs a logical product signal of the timing signal φ31ch from the channel counter 1B and the set output of the flip-flop circuit 37 to the delay 39.
The delay 39 delays the logical product signal from the AND circuit 38 by one channel period, and outputs it as a timing signal TS to the waveform generator 2C and the delay 3A.
The delay 3A delays the timing signal from the delay 39 by one channel period, and outputs it to the 4-continuous pulse generator 3E and the delay 3C.
The delay 3C delays the delayed signal from the delay 3A by one channel period and outputs it to the reset terminal R of the flip-flop circuit 37.

  The 4-continuous pulse generator 3E receives the in-operation signal USE and the write / read control signal W / * R from the channel control register 31 and the delay signal from the delay 3A, and this delay signal is at the high level “1”. In this case, four continuous pulses are generated during the time slot of the 31st channel, and are output to the OR circuit 3F and output to the waveform memory 2D as the write signal WS.

The OR circuit 3F receives the logical sum signal from the OR circuit 33 and the four continuous pulses from the four continuous pulse generator 3E, and sends the logical sum signal of both to the pulse generator 3G.
The feed pulse generator 3G sequentially outputs feed pulses L1 to L4 to the latches 3M, 3L, 3K, and 3J every time the logical sum signal from the OR circuit 3F is input.
The latch 3J latches the 16-bit data from the selector 3H at the time when the feed pulse L4 is input, and outputs the latched data to the latch 3K in the next stage. The latch 3K latches the data from the previous stage latch 3J at the time of input of the feed pulse L3, and outputs it to the next stage latch 3L. The latch 3L latches the data from the previous stage latch 3K at the input time of the transmission pulse L2, and outputs it to the next stage latch 3M. The latch 3M latches the data from the preceding latch 3L at the time of input of the transmission pulse L1, and outputs it to the selector 3N and the waveform generator 2B. The data output from the latch 3M to the selector 3N is the memory read data MRD read from the waveform memory 2C, while the data output from the latch 3M to the waveform generator 2C is the memory to be written to the waveform memory 2D. Write data MWD.

  The latch pulses L1 to L4 generate feed pulses that are slightly delayed in the time order of L1, L2, L3, and L4 each time a pulse from the AND circuit 3F is input. In response to the input of one pulse from 3F, the data in the latch 3L is in the latch 3M, the data in the latch 3K is in the latch 3L, the data in the latch 3J is in the latch 3K, and the data newly supplied from the selector 3H is in the latch 3J Latched and shifted by one data as a whole.

  The selector 3N inputs the upper 8 bits of the memory read data MRD from the latch 3M to the upper terminal H and the lower 8 bits to the lower terminal L, and is output from the read decoder 18 when the address ADR is "5". Read decode signal A5 is input to upper select terminal SH, and read decode signal A6 output from read decoder 18 when address ADR is "6" is input to lower select terminal SL. Therefore, when address ADR is “5”, the upper 8 bits of memory read data MRD are output as read waveform data WDR, and when address ADR is “6”, the lower 8 bits of memory read data MRD are read waveform. Output as data WDR.

FIG. 4 is a diagram showing a detailed configuration of the waveform generator 2C of FIG.
The frequency number (F number) generator 40 outputs a frequency number (F number) corresponding to the pitch data from the musical tone control register 1D to the address counter 41 and an operating signal USE from the channel control register 31 of FIG. The timing signal TS from the delay 39 is input. When the operating signal USE is at the high level “1”, the 31st channel is used for the CPU 20 access, and when the timing signal TS is “0”, the F number generator 40 has the F of the 31st channel. When “0” is output as the number and the timing signal TS is “1”, “4” is output to the address counter 41 as the F number of the 31st channel. This frequency number is data composed of an integer part and a decimal part.

  The address counter 41 receives the note-on pulse from the tone control register 1D of FIG. 1 and the start signal A1 from the write pulse generator 17 via the OR circuit 42, and also receives the waveform start address (from the tone control register 1D ( WSA), loop start address (LPS), loop end address (LPE), and frequency number from the frequency number generator 40 are input. Then, the address counter 41 sequentially counts the frequency number using the waveform start address (WSA) as an initial value in response to the start signal A1 or the input of a note-on pulse for instructing the start of tone generation of each time-division tone generation channel. .

  The address counter 41 is set to an initial address (waveform start address WSA) by inputting a note-on pulse or a start signal, and is sequentially counted up based on the waveform start address (WSA) according to the size of the frequency number. The address is output to the adders 43 and 44. The address counter 41 outputs the integer part data In of the read address to the adder 43, and outputs the decimal part data Dc to the adder 44. When the frequency number value is small, the amount of increase in the read address is small, so the pitch of the tone waveform signal output from the waveform memory 2D is relatively low, and when the frequency number is large, the read address is increased. Since the amount increases, the pitch of the musical sound waveform signal output from the waveform memory 2D increases.

The auxiliary counter 45 sequentially outputs “0”, “1”, “2”, and “3” to the adders 43 and 44 as auxiliary addresses AA in one of the time division channels.
The adder 43 sequentially adds “0”, “1”, “2”, “3” of the auxiliary address AA from the auxiliary counter 45 to the address In of the integer part from the address counter 41. Accordingly, the waveform memory 2D is sequentially supplied with four consecutive addresses InA within one time-division channel, and four consecutive waveform data corresponding to the address In in the waveform memory 2D are sequentially read out. On the other hand, the adder 44 adds “0”, “1”, “2”, “3” of the auxiliary address AA from the auxiliary counter 45 to the decimal part address Dc from the address counter 41, so that the interpolation coefficient memory 4A. Are sequentially supplied with four addresses DcA corresponding to the four consecutive waveform data corresponding to the address decimal part Dc in one channel, and the four coefficients are sequentially read out.

  The waveform memory 2D stores a plurality of cycles as waveform data of the rising portion (attack portion) and one cycle as waveform data of the subsequent sustain portion (loop portion), and corresponds to the address InA from the adder 43. The memory read data MRD (16-bit configuration) is output to the interpolation accumulator 4B via the buffer amplifier 48 and the multiplier 49, and also to the buffer amplifier 46. In the waveform memory 2D, four memory write data MWD input via the buffer amplifier 47 in accordance with the write signal WS from the four continuous pulse generator 3E in FIG. Are written to the four addresses InA.

  The buffer amplifier 46 outputs the memory read data MRD from the waveform memory 2D to the A terminal of the selector 3H in FIG. 3 according to the control signal from the AND circuit 4E. The buffer amplifier 47 outputs the memory write data MWD from the latch 3M in FIG. 3 to the waveform memory 2D and the buffer amplifier 48 according to the control signal from the AND circuit 4G. The buffer amplifier 48 outputs the memory read data MRD from the waveform memory 2D or the memory write data MWD from the buffer amplifier 47 to the multiplier 49 in accordance with the control signal from the inverting circuit 4J.

The interpolation coefficient memory 4A sequentially outputs interpolation coefficients corresponding to four addresses per channel output from the adder 44 to the multiplier 49.
The multiplier 49 multiplies each memory read data MRD by the interpolation coefficient from the interpolation coefficient memory 4A and outputs it to the interpolation accumulator 4B.
The interpolation accumulator 4B accumulates the values sequentially output from the multiplier 49 within one channel, and outputs the result to the envelope assigning unit 2E as one interpolation output sample value.

The buffer amplifiers 46, 47 and 48 are controlled by delays 4C and 4D, AND circuits 4E, 4F and 4G and inverting circuits 4H and 4J. The delays 4C and 4D are delay circuits for adjusting the timing with respect to the path (the AND circuit 38 and the delays 39 and 3A) through which the timing signal φ31ch passes.
The AND circuit 4E receives the operating signal USE and the timing signal φ31ch from the channel control register 31, and outputs a logical product signal of both to the AND circuits 4F and 4G and the inverting circuit 4J. The inverting circuit 4H receives the write / read control signal W / * R from the channel control register 31, and outputs the inverted output to the AND circuit 4F. The AND circuit 4F inputs the logical product signal of the AND circuit 4E and the inverted output of the write / read control signal W / * R, and outputs the logical product signal to the buffer amplifier 46. The AND circuit 4G receives the logical product signal of the AND circuit 4E and the write / read control signal W / * R, and outputs the logical product signal of both to the buffer amplifier 47. The inverting circuit 4J receives the logical product signal of the AND circuit 4E and outputs the inverted output to the buffer amplifier 48.

  The envelope applying unit 2E generates a waveform envelope signal (14-bit configuration) based on parameters preset in the sound source I / O 2B according to the note-on of each time division channel supplied from the register 1D, and the waveform generating unit Amplitude envelope control is performed on the interpolated sample value output from the 2C interpolation accumulator 4B in accordance with the envelope signal, and the amplitude-controlled sample value is output to the channel accumulation unit 2F.

Next, waveform data writing processing and reading processing performed by the electronic musical instrument according to the present invention will be described.
First, a process in which the CPU 20 reads the sampling waveform data written after the address “5F” from the waveform memory 2D will be described.
The CPU 20 sets “5F” as the waveform start address (WSA) of the timing signal φ31ch of the tone control register 1D in order to sequentially read the sampling waveform data from the address “5F” of the waveform memory 2D at the timing of the timing signal φ31ch. .

At the same time, the CPU 20 outputs “A0” as the address ADR, sets the operating signal USE of the channel control register 31 to the high level “1”, and sets the write / read control signal W / * R to the low level “0”. Data DATA is output. In response, write decoder 16 outputs a write decode signal corresponding to “A0” to write pulse generator 17. The write pulse generator 17 outputs a high level “1” write pulse signal A 0 to the channel control register 31. The channel control register 31 outputs a high-level “1” operating signal USE to the access count detection unit 35, the four continuous pulse generation unit 3E, the frequency number generator 40, and the AND circuit 4E, and writes the low level “0”. The read / in control signal W / * R is output to the four continuous pulse generator 3E, the selector 3H, the inverting circuit 4H, and the AND circuit 4G, respectively.
Next, the CPU 20 outputs “A1” as the address ADR. In response to this, the write decoder 16 outputs a write decode signal corresponding to “A1” to the write pulse generator 17, and the write pulse generator 17 accesses the start signal A1 of the high level “1”. The number is output to the number detection unit 35, the OR circuit 36 and the address counter 41.

When the CPU 20 performs the processing as described above, the waveform memory I / O 1E and the waveform generator 2C operate as follows.
Since the start signal A1 is input to the set terminal S of the flip-flop circuit 37 via the OR circuit 36, the flip-flop circuit 37 outputs the set output Q of the high level “1” to the AND circuit 38 and the low level “0”. The inverted output * Q is output to the gate 3P.
The access count detection unit 35 clears the detection count value in response to the input of the start signal A1.
When the start signal A1 is input to the address counter 41 via the OR circuit 42, the address counter 41 sets “5F” of the waveform start address (WSA) in the musical tone control register 1D as the initial value of the counter as the waveform memory read address.

  The channel counter 1B outputs a high level “1” timing signal φ31ch to the AND circuit 38 when the timing of the time division channel becomes the 32nd channel. The AND circuit 38 outputs the output Q (high level “1”) from the flip-flop circuit 37 to the delay 39 while the timing signal φ31ch is at the high level “1”. Accordingly, the high level “1” signal is delayed by one channel period by the delay 39 and input to the delay 3A and also input to the frequency number generator 40 as the timing signal TS.

  Further, the delay signal (timing signal TG) output from the delay 39 is further delayed by one channel period by the delay 3A and is input to the 4-continuous pulse generator 3E and the delay 3C. Since the write / read control signal W / * R is at the low level “0”, the four continuous pulse generator 3E that receives the high level “1” delay signal from the delay 3A has a continuous 4 in one channel from that point. The number of pulses is output to the OR circuit 3F. When the write / read control signal W / * R is at the high level “1”, the four continuous pulse generator 3E passes through the buffer 47 in response to the four pulses during the 32nd channel. A write signal WS is output to the waveform memory 2D at a timing synchronized with four write sample data (memory write data) MWD sequentially supplied to 2D.

  When the timing signal TS is input at the 31 channel timing, the frequency number generator 40 is “4” instead of the F number corresponding to the pitch data supplied from the normal musical tone control register 1D as the 31 channel frequency data. The F number having a value is output to the address counter 41. As a result, the address counter 41 outputs the address In incremented by 4 to the adders 43 and 44 when reading and writing by the CPU in the 31 channel.

  At this time, the auxiliary counter 45 outputs the auxiliary addresses AA of “0”, “1”, “2”, “3” to the adders 43 and 44 during one channel of the time division channel. An address InA obtained by adding the address In from the address counter 41 and the auxiliary address AA of the auxiliary counter 45 is input to the memory 2D as a read address. As a result, memory read data MRD corresponding to these four read addresses is sequentially output from the waveform memory 2D to the buffer amplifiers 46 and 48.

  At this time, a high level “1” write / read control signal W / * R is input to the AND circuit 4F via the inverting circuit 4H, and a low level “0” write / read control signal W is input to the AND circuit 4G. Since / * R is input, the gate of the AND circuit 4F is opened, and the gate of the AND circuit 4G is closed. Therefore, the logical product output of the AND circuit 4E is input to the buffer amplifier 46 via the AND circuit 4F. A high level “1” operating signal USE is input to one terminal of the AND circuit 4E, and a high level “1” timing signal is input to the other terminal after a delay of two channel periods via delays 4C and 4D. Since φ31ch is input, the logical product signal of high level “1” is input to the buffer amplifier 46 via the AND circuits 4E and 4F when two channel periods elapse after the timing signal φ31ch becomes high level “1”. To do. Thus, the memory read data MRD from the waveform memory 2D is input to the A terminal of the selector 3H via the buffer amplifier 46 in the waveform memory access period corresponding to the 31 channel.

  Since selector 3H receives write / read control signal W / * R of low level “0”, memory read data MRD input through buffer amplifier 46 is output to latch 3J. At this time, the pulse from the 4-continuous pulse generator 3E is input to the feed pulse generator 3G via the OR circuit 3F, and the data in the latches L1 to L4 are forwarded in accordance with the pulses, thereby causing the waveform memory The four memory read data MRD sequentially read from 2D are transferred to the latches 3J, 3K, 3L, and 3M one after another and latched.

When the four memory read data MRD are transferred to the latches 3J, 3K, 3L, and 3M and latched, a high level “1” output is output from the delay 3C to the reset terminal R of the flip-flop circuit 37 at the end of the fetching. Then, the set output Q of the flip-flop circuit 37 is set to low level “0” and the inverted output * Q is set to high level “1”.
The CPU 20 outputs “A2” as the address ADR. In response to this, the read decoder 18 outputs a read decode signal A2 corresponding to “A2” to the gate 3L, opens the gate 3L, reads the inverted output * Q of the flip-flop circuit 37, and the inverted output * Q is It is detected that the reading of the memory read data MRD from the waveform memory 2D into the latches 3J, 3K, 3L, 3M has been completed at the timing when it becomes “1”.

After the above processing is completed, the CPU 20 alternately outputs the address ADR (A5, A6) four times, selects the L terminal and the H terminal of the selector 3N, and outputs eight 8-bit read data WDR to the buffer amplifier. 15 are sequentially read out.
That is, when CPU 20 outputs “A5” as address ADR, read decoder 18 outputs read decode signal A5 to selector 3N. The selector 3N outputs the upper 8 bits of the memory read data MRD latched in the latch 3M as read data WDR to the read data bus, and the upper 8 bits are read by the CPU via the buffer 15. Next, when the CPU 20 outputs “A6” as the address ADR, the read decoder 18 outputs a read decode signal A6 to the selector 3N. The selector 3N outputs the lower 8 bits of the memory read data MRD latched in the latch 3M to the read data bus as read data WDR and is read by the CPU via the buffer 15.

At this time, every time the decode signal A6 is input, the pulse generator 32 outputs a one-sample read completion pulse RSP to the access count detector 35 via the OR circuit 33 and a feed pulse generator via the OR circuits 33 and 3F. Output to 3G. The access count detection unit 35 counts the number of times one sump read completion pulse RSP is input from the pulse generation unit 32, and detects whether the count value is “4”, that is, whether the CPU 20 has read access four times. To do. At this point, the CPU 20 has accessed only once.
On the other hand, the feed pulse generator 3G shifts the data of the latches 3J, 3K, 3L, and 3M to the latch 3M side by one stage in response to the input of the one-sample read completion pulse RSP.

The CPU 20 reads the data for 4 words in the waveform memory 2D by repeating the above operation (operation for alternately outputting the addresses ADR (A5, A6)) four times.
When this read operation is completed, the access count detector 35 counts the one-sample read completion pulse RSP output from the OR circuit 33, detects that data read for four words has been completed, and has a high level “1”. Is output to the set terminal S of the flip-flop circuit 37 via the OR circuit 36. As a result, the flip-flop circuit 37 is set again and outputs the set output Q of the high level “1” to the AND circuit 38. Then, during the next timing signal φ31ch, data of 4 words is sequentially read from the waveform memory 2D from the waveform memory 2D and taken into the four-stage latches 3J, 3K, 3L, 3M, and then The flip-flop circuit 37 is reset again. In this case, the waveform start address (WSA) is not written to the address counter 41 of the waveform generator 2C, and the previous count value is continuously used.

By repeatedly executing the above operation, the CPU 20 can successively read out the data stored in the corresponding address while sequentially increasing the address by 4 from “5F” of the waveform start address (WSA). .
When ending the process of reading data from the waveform memory 2D, the CPU 20 outputs “A0” as the address ADR with the flip-flop circuit 37 being reset (the set output Q is at the low level “0”). Then, the write pulse signal A0 is output to the channel control register 31, and the data DATA that sets the operation signal USE of the channel control register 31 to the low level “0” is output. As a result, the channel control register 31 outputs the in-operation signal USE of the low level “0” to the access count detection unit 35, the 4 continuous pulse generation unit 3E, the frequency number generator 40, and the AND circuit 4E. Subsequent data read operations are not performed.

Next, a process in which the CPU 20 writes sampling waveform data in, for example, an area after the address “6F” in the waveform memory 2D will be described.
In order to write the sampling waveform data in order from the address “6F” of the waveform memory 2D at the timing of the timing signal φ31ch, the CPU 20 writes the waveform start address (WSA) of the timing signal φ31ch of the musical tone control register 1D, that is, the write head of the waveform memory 2D. Set “6F” in the address.

At the same time, the CPU 20 outputs “A0” as the address ADR, and outputs data DATA that sets the write / read control signal W / * R of the channel control register 31 to the high level “1”. In response to this, the write decoder 16 outputs a write decode signal corresponding to “A0” to the write pulse generator 17, and the write pulse generator 17 outputs the write pulse signal A0 of high level “1”. Is output to the channel control register 31. The channel control register 31 outputs a high level “1” write / read control signal W / * R to each of the four continuous pulse generator 3E, the selector 3H, the inverting circuit 4H, and the AND circuit 4G.
At this time, the operating signal USE is set to the low level “0”.

After this processing is completed, the CPU 20 alternately outputs the address ADR (A3, A4) four times, and writes the write waveform data WD in the latches 3J, 3K, 3L, 3M.
That is, when the CPU 20 outputs “A3” as the address ADR together with the upper 8 bits of the first waveform data, the write decoder 16 outputs a write decode signal corresponding to “A3” to the write pulse generator 17, The write pulse generator 17 outputs the high level “1” write pulse signal A 3 to the upper latch 34. The upper latch 34 latches the upper 8-bit write waveform data from the data latch 13. Next, when the CPU 20 outputs “A4” as the address ADR together with the lower 8 bits of the waveform data, the write decoder 16 outputs a write decode signal corresponding to “A4” to the write pulse generator 17, The write pulse generator 17 outputs a high level “1” write pulse signal A4 to the feed pulse generator 3G via the OR circuits 33 and 3F.

Since the selector 3H receives the high level “1” write / read control signal W / * R, the selector 3H is composed of a total of 16 bits, the lower 8 bits from the data latch 13 and the upper 8 bits from the latch 34. Write waveform data WD is output to latch 3J. At this time, since the write pulse signal A4 is input to the feed pulse generator 3G via the OR circuits 33 and 3F, the upper 8 bits of data latched in the upper latch 34 and the lower 8 bits supplied this time are supplied. The 16-bit write waveform data WD combined with the data is taken into the latch 3J, and the data originally latched in the latches 3J, 3K, 3L are latched in the latches 3K, 3L, 3M, respectively, and latched as a whole The data that is being processed is forwarded one by one.
The CPU 20 stores the write waveform data WD for four words in the latches 3J, 3K, 3L, and 3M by repeating the above-described operation (operation for alternately outputting the addresses ADR (A3, A4)) four times.

  Next, the CPU 20 writes “1” in the operating signal USE of the channel control register 31 of the address “A1”. Then, the CPU 20 outputs “A1” as the address ADR. In response to this, the write decoder 16 outputs a write decode signal corresponding to “A1” to the write pulse generator 17, and the write pulse generator 17 accesses the start signal A1 of the high level “1”. The number is output to the number detection unit 35, the OR circuit 36, and the address counter 41.

The flip-flop circuit 37 inputs the start signal A1 to the set terminal S via the OR circuit 36, thereby causing the set output Q of the high level “1” to the AND circuit 38 and the inverted output * Q of the low level “0”. Is output to the gate 3L.
The access count detection unit 35 clears the detection count value in response to the input of the start signal A1.
The address counter 41 inputs the start signal A1 through the OR circuit 42, and stores “6F” of the waveform start address (WSA) in the tone control register 1D as the initial value of the counter as the waveform memory write address.

  The channel counter 1B outputs a high level “1” timing signal φ31ch to the AND circuit 38 when the timing of the time division channel becomes the 32nd channel. The AND circuit 38 outputs the set output Q (high level “1”) from the flip-flop circuit 37 to the delay 39 while the timing signal φ31ch is at the high level “1”. This high level “1” signal is delayed by one channel period by the delay 39 and input to the delay 3A and also input to the frequency number generator 40 as the timing signal TS.

Further, the delay signal (timing signal TG) output from the delay 39 is further delayed by one channel period by the delay 3A and is input to the 4-continuous pulse generator 3E and the delay 3C. Since the write / read control signal W / * R is at the high level “1”, the 4-continuous pulse generator 3E to which the delay signal at the high level “1” from the delay 3A is input has a continuous 3 in one channel from that point. The number of pulses is sent to the pulse generator 3G via the OR circuit 3F, and while the timing signal φ31ch is at the high level “1”, four consecutive pulses are output to the waveform memory 2D as the write signal WS.
The three pulses in this case are the remaining ones except for the first one of the four pulses generated at the time of reading (when the writing / reading control signal W / * R is “0”). It occurs at three timings.

The frequency number generator 40 outputs an F number having a value of “4” instead of the F number corresponding to the 31-channel pitch data normally output to the address counter 41 every time the timing signal TS is input. . As a result, the address counter 41 outputs the address In incremented by 4 to the adders 43 and 44 for 31 channels.
At this time, the auxiliary counter 45 outputs the auxiliary addresses AA of “0”, “1”, “2”, “3” to the adders 43 and 44 during one channel of the time division channel. Four consecutive addresses InA obtained by adding the address In from the address counter 41 and the auxiliary address AA of the auxiliary counter 45 are input to the memory 2D as a write address.

  A low level “0” write / read control signal W / * R is input to the AND circuit 4F via the inverting circuit 4H, and a high level “1” write / read control signal W / * R is input to the AND circuit 4G. Therefore, the gate of the AND circuit 4F is closed and the gate of the AND circuit 4G is opened. Therefore, the logical product output of the AND circuit 4E is input to the buffer amplifier 47 via the AND circuit 4G. The high-level “1” operating signal USE is input to one terminal of the AND circuit 4E, and the high-level “1” timing is delayed to the other terminal by two channel periods via the delays 4C and 4D. Since the signal φ31ch is input, the logical product signal of the high level “1” is supplied to the buffer amplifier 47 via the AND circuits 4E and 4G when two channel periods have elapsed after the timing signal φ31ch has become the high level “1”. input. Accordingly, the memory write data MWD from the latch 3M is input to the data input terminal of the waveform memory 2D and the buffer amplifier 48 via the buffer amplifier 47 in the access period of the waveform memory 2D corresponding to 31 channels.

Three continuous pulses from the four continuous pulse generator 3E are input to the feed pulse generator 3G via the OR circuit 3F. The feed pulse generator 3G shifts the data of the latches 3J, 3K, 3L, and 3M to the latch 3M side by one stage according to the pulse input. The memory write data MWD latched in the latches 3J, 3K, 3L, and 3M are successively transferred to the latch 3M and input to the waveform memory 2 from the latch 3M via the buffer amplifier 47. At the same time, four consecutive write signals WS and four consecutive addresses InA are input to the waveform memory 2D from the four consecutive pulse generators 3E, so that write waveform data WD for four words is input to this address area. Written sequentially.
When the four memory write data MWD stored in the latches 3J, 3K, 3L, and 3M are written to the waveform memory 2D, the output of the high level “1” from the delay 3C is reset to the flip-flop circuit 37 accordingly. Input to the terminal R, the set output Q of the flip-flop circuit 37 is set to the low level “0”, and the inverted output * Q is set to the high level “1”.

The CPU 20 reads the data at the address “A2” in order to detect the completion of the writing of the four data to the waveform memory 2D. At this time, the read decoder 18 outputs a read decode signal A2 corresponding to “A2” to the gate 3P, opens the gate 3P, and the CPU 20 reads the inverted output * Q of the flip-flop circuit 37 and reads the memory write data MWD. It is detected that the writing process from the latches 3J, 3K, 3L, 3M to the waveform memory 2D has been completed.
The CPU 20 that detects the end of the writing process outputs the address ADR (A3, A4) alternately four times, stores the write waveform data WD for four new words in the latches 3J, 3K, 3L, 3M, The above operation is repeatedly executed to write the memory write data MWD to the waveform memory 2D. The CPU 20 writes the memory write data MWD to the corresponding address while increasing the address sequentially by 4 from “6F” of the waveform start address (WSA) by repeatedly executing the above operation.

  When ending the data writing process to the waveform memory 2D, the CPU 20 sets “A0” as the address ADR in a state where the flip-flop circuit 37 is reset (the set output Q is at the low level “0”). The write pulse signal A0 is output to the channel control register 31, and the data DATA that sets the operation signal USE and the write / read control signal W / * R of the channel control register 31 to the low level “0” is output. To do. As a result, the channel control register 31 outputs the in-operation signal USE of the low level “0” to the access count detection unit 35, the 4 continuous pulse generation unit 3E, the frequency number generator 40, and the AND circuit 4E. Subsequent data write operations are not performed.

  According to the embodiment described above, there is an effect that the CPU can access the waveform memory even when the waveform memory sound source performs the time division channel sound generation process.

It is a figure which shows the detailed structure of the sound source I / O of FIG. It is a figure which shows the whole structure of the electronic musical instrument which incorporated the sampler type waveform memory sound source which concerns on one Example of this invention. It is a figure which shows the detailed structure of the waveform memory I / O of FIG. It is a figure which shows the detailed structure of the waveform generation part of FIG.

Explanation of symbols

11 CPU bus controller 12 Address latch 13 Data latch 14 Write buffer 15 Read buffer amplifier 16 Write decoder 17 Write pulse generator 18 Read decoder 19 Channel latch 1A Channel converter 1B Channel counter 1C Selector 1D Musical tone Control register 1E Waveform memory I / O

Claims (6)

A sound source device that operates in a time-sharing manner for multiple channels,
A memory for storing data for the sound source;
Storing control data for controlling the operation of each of the plurality of channels in the sound source device, and a control register capable of writing the control data by a processing unit;
Based on address information included in the control data of the control register, address counter means for generating an address for memory read / write for each channel;
Including a latch capable of inputting and holding data to be stored in the memory as new sound source data by the processing means, and excluding specific channels that are not used for generating musical sounds from the plurality of channels At the timing of each remaining channel, the sound source data is read from the memory based on the read address generated by the address counter means according to the musical sound to be generated on each remaining channel , and Memory access means for writing the data for the new sound source held in the latch to the memory based on the address for writing generated corresponding to the specific channel at the timing of the specific channel ;
Wherein for each remaining channel, memory usage tone generator comprising a tone generating means for generating a respective tone signal based on the data and the control data for the tone generator which is read in accordance with the musical tone to be the generation. The processing means holds the data for the sound source to be written in the latch, writes address information indicating an address for writing the data to the memory in the control register, and generates a write instruction.
The address counter means generates an address of the specific channel based on the address information written in the control register,
2. The memory-use sound source device according to claim 1, wherein the memory access means writes the data held in the latch to the memory based on the address at the timing of the specific channel. The latch can hold a plurality of data,
The processing means holds a plurality of data to be written in the latch,
The address counter means sequentially generates a plurality of addresses as the address of the specific channel at the timing of the specific channel,
The memory access means sequentially writes a plurality of data held in the latch to the memory based on the plurality of generated addresses, and generates a write end notification when the sequential writing is completed. The memory-use sound source device according to claim 2. A sound source device that operates in a time-sharing manner for multiple channels,
A memory for storing data for the sound source;
Storing control data for controlling the operation of each of the plurality of channels in the sound source device, and a control register capable of writing the control data by a processing unit;
Based on address information included in the control data of the control register, address counter means for generating an address for memory read / write for each channel;
A latch that can extract data by the processing means, and at the timing of each remaining channel excluding a specific channel that is not used for generating a tone among the plurality of channels, the tone to be generated in each remaining channel In response , the data for the sound source is read from the memory based on the read address generated by the address counter means, and the read generated corresponding to the specific channel at the timing of the specific channel Memory access means for reading out the data for the sound source from the memory based on the address for use, inputting the data to the latch and holding it, and as a result, the data held in the latch being retrieved by the processing means When,
Wherein for each remaining channel, memory usage tone generator comprising a tone generating means for generating a respective tone signal based on the data and the control data for the tone generator which is read in accordance with the musical tone to be the generation. The processing means writes address information indicating an address from which the sound source data is to be read from the memory to the control register and generates a read instruction.
The address counter means generates an address of the specific channel based on the address information written in the control register,
The memory access means reads the data for the sound source from the memory based on the address at the timing of the specific channel and holds the data in the latch, and generates a read end notification when the read is completed,
5. The memory-use sound source device according to claim 4, wherein, in response to the end notification, the processing unit extracts data read from the memory and held in the latch from the latch. The latch can hold a plurality of data,
The address counter means sequentially generates a plurality of addresses as the address of the specific channel at the timing of the specific channel,
The memory access means sequentially reads a plurality of data from the memory based on the generated plurality of addresses and sequentially holds the data in the latch.
6. The memory-use sound source device according to claim 5, wherein the processing means sequentially extracts a plurality of data read from the memory and held in the latch from the latch.

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