JP3856911B2 - Lead width detector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a lead width detecting device, and more particularly, to an outer lead of an external connection portion formed by parallel arrangement of semiconductor chip position shifts on a lead frame on which a semiconductor chip is mounted. Detecting based on the image acquired by the imaging device that takes a bird's-eye view with an imaging camera, ensuring the correct position alignment of the semiconductor chip, and enabling wire bonding processing as correct wiring processing for semiconductor chip leads The present invention relates to a lead width detection device that significantly simplifies lead width detection processing for positioning in a wire bonder with an image processing device.
[0002]
[Prior art]
2. Description of the Related Art A wire bonder that correctly positions and mounts a semiconductor chip with respect to a lead frame and performs wire bonding as a wiring process is well known recently. The wire bonder is provided with an image processing device that uses an imaging device that uses an imaging sensor such as a CCD camera, and a bird's-eye view of an object including a semiconductor chip such as an IC mounted on a lead frame is obtained. The relative displacement with respect to the lead frame is detected based on the lead width detection of a lead that is connected to the outside in parallel arrangement of the leads, so-called outer leads. A bonder called a so-called full-auto bonder that performs bonding by automating a positioning operation for correcting the shift amount is also frequently used in the field of semiconductor manufacturing recently.
[0003]
The image processing apparatus provided in such a full-auto bonder shares a role as a visual device for determining pass / fail in the wire bonder positioning mechanism, and the functions are diversified as the semiconductor chip is miniaturized and the number of pins is increased. .
[0004]
FIG. 5 is a block diagram showing a configuration of a conventional lead width detecting device. The lead width detection device shown in FIG. 5 reads an image of an imaging device 1 that captures an image of an imaging target from an imaging sensor, for example, a CCD camera, and an image of a lead (outer lead) output from the imaging device 1 using a reference sampling clock. The A / D converter 2 that performs sampling and digitization in units of pixels for width detection, and the input of the data string output from the A / D converter 2 are compared with a reference level 301 that is set in advance. A comparator 3 that outputs a digitized serial signal, and a binary serial signal that is output from the comparator 3 are parallelized by the number of bits in a data bus bit width unit as a data array bit width in the horizontal direction of the video memory 5. A shift register 4 as a serial / parallel converter that converts the signal into a signal in synchronization with the reference sampling clock and outputs the signal; A video memory 5 that stores a binary image of one frame and stores a predetermined number of bits in each of the horizontal and vertical directions while updating it, and a control program are incorporated, and a read width based on data stored in the video memory 5 A CPU 6 that performs detection and controls the operation of the entire system, a timing signal generator 7 that generates a control timing signal for controlling the control timing of the entire apparatus under the control of the CPU 6, and binarized image data in the video memory 5 A video memory coordinate output unit 8 that secures a prescribed area for storage and outputs coordinates of an address included in the secured area as an address signal.
[0005]
The image pickup apparatus 1 takes a bird's-eye view of an image pickup target including a semiconductor chip to be bonded, a lead, and a lead frame with a CCD camera, and sends image data of outer leads arranged in parallel to the A / D converter 2. In this case, the imaging timing of the imaging apparatus 1 is controlled by a timing signal sent from the timing signal generator 7 that operates under the control of the CPU 6.
[0006]
The A / D converter 2 compares the output of the A / D converter 2 with the reference level 301 and binarizes it, and sends it to the shift register 4 as a bit string of serial data.
The shift register 4 sends the input serial data to the video memory 5 as parallel data in units of data bus bit width as the number of array bits in the column direction (horizontal direction) of the video memory 5. The parallel data thus provided is stored in the video memory 5 under the control of the CPU 6 in accordance with the designation of the address output from the video memory coordinate output unit 8.
[0007]
The CPU 6 uses the detection target data necessary for detection of the read width read from the video memory 5 and calculates the read width based on the built-in program. From the calculated data, the state between the lead to be bonded and the semiconductor chip is calculated. This positional deviation data is sent to a position correction device (not shown), the relative position of the lead frame with respect to the semiconductor package is aligned with the desired state, and then automatic bonding processing is performed.
[0008]
FIG. 6 is an explanatory diagram of a conventional lead width detection operation. FIG. 6A shows an example of lead width detection for a lead imaged in the horizontal direction, and FIG. 6B shows an image imaged in the vertical direction. An example of lead width detection with respect to a lead is shown.
[0009]
6A shows a horizontal imaging lead 101a, a data bus bit width 103 representing the number of horizontal arrangement bits of the storage area on the video memory 5 in FIG. A detection target column 102a to be extracted for the lead width detection process, eight detection target data 102b corresponding to pixels indicated by diagonal lines, and read data 104 as all read data necessary for reading the detection target data 102b Is shown. In this case, the detection target data 102b includes 8 pixels (pixels) from the pixel P1 to the pixel P2 read as the read data 104. Of these, the data regarding the pixels P1 and P2 are Each provides information on the edge (edge) of actual data necessary for lead width detection.
It should be noted that which pixel column including the data bus bit width 103 is the detection target column 102a that is the target of bit width detection is set in advance.
[0010]
6B shows a lead 101b imaged in the vertical direction, a detection target row 105a used for bit width extraction from a storage area corresponding to the data bus bit width of the video memory 5, and detection. The detection target data 105b corresponding to the eight pixels from the pixels Q1 to Q2 as the pixel area included in the target row 105a is shown, and the read data 107 as all the read data necessary for the read width detection processing by the CPU 6 is also shown. Show.
Note that it is set in advance which row is to be detected.
[0011]
In the conventional read width detecting device, the binarized image data stored in the video memory 5 is imaged in the horizontal direction under the control of the CPU 6, and in the case of FIG. In the case of FIG. 6B imaged in the direction, the lead edge in the horizontal direction is detected via the pixels P1, P2, and Q1, Q2, respectively, and the lead width is detected and the lead in the search direction in the lead width detection. The center point is detected, and thereby the deviation from the reference center axis L is also determined, and these pieces of information are provided to a position correction device (not shown) for automatic position alignment.
[0012]
[Problems to be solved by the invention]
However, the conventional lead width detecting device described above has the following problems. That is, as shown in FIG. 6A, in the case of the lead width detection processing of the lead imaged in the horizontal direction, the CPU 6 shown in FIG. That is, since it is necessary to perform the number of times corresponding to the read width of the detection target column 102a, there is a problem that a lot of processing time is required.
[0013]
When this is compared with the case of the lead width detection processing of the lead imaged in the vertical direction as shown in FIG. 6B, the CPU 6 reads the data from the video memory 5 and corresponds to the detection target row 105a. Only the read data 107 as continuous bit data can be used. In this case, the processing time can be remarkably shortened because only one read operation is required.
[0014]
More specifically, in the case of performing the lead width detection of a lead imaged in the horizontal direction, that is, the lead width detection process in the vertical direction, the image information of the detection target column 102a is corresponded from the video memory 5 to the necessary lead width. It was necessary to read as many times as possible.
[0015]
This is because, as shown in FIG. 6B, the number of times of reading data from the video memory 5 when the horizontal lead width of the lead 101b imaged in the vertical direction on the initial image is detected is determined by the read width. Is taken once when the data bus bit width of the video memory 5 is smaller than the data bus bit width of the video memory 5, and even when it is larger than the number of times (read width / data bus bit width), the image is picked up horizontally on the initial image When the lead width in the vertical direction of the lead 101a is detected, the number of times of reading data from the video memory 5 of <lead width / pixel width + two times (for edge pixels)> is necessary, and the number of reading times increases, and the detection process is increased. There was a problem in that it took time to complete the process and could not satisfy the demand for high-speed processing.
[0016]
An object of the present invention is to provide a lead width detection apparatus that can solve the above-described problems and can significantly shorten the lead width detection time for a lead that is initially imaged in the horizontal direction. That is, based on the detection of the lead width of the outer leads arranged in parallel among the leads arranged on the lead frame, when the positional shift of the semiconductor chip relative to the lead frame occurs, the center line of the lead An object of the present invention is to provide a lead width detecting device that detects a deviation from a center line, and ensures correct alignment with respect to a lead frame of a semiconductor chip based on the detected data, thereby enabling correct wire bonding. is there.
[0017]
[Means for Solving the Problems]
In order to achieve the above-described object, the present invention has the following configuration.
In other words, the apparatus of the present invention is an external image obtained by taking a bird's-eye view of a rectangular lead frame in which electrodes of a mounted semiconductor chip and leads to be wired by automatic bonding are arranged by an imaging device and arranging them in parallel with the lead frame. A lead obtained by reading out data necessary to detect the width of the lead from the first video memory as a frame memory storing the binary image data of the imaging data of the lead for the outer lead as the connection portion In a lead width detecting device that ensures the positional alignment between a semiconductor chip and a lead necessary for automatic bonding based on the width, a 90 degree conversion 2 in which the array direction of the binarized image data stored in the video memory is rotated 90 degrees to the right. A second video memory having the same storage area as the first video memory storing the binarized image data; The detection target data necessary for detecting the width of the lead imaged in the horizontal direction is read from the second video memory, and the lead imaged in the horizontal direction is effectively imaged in the vertical direction. By making it possible to handle in the same way as the lead, it is possible to reduce the number of times of reading of the detection target data necessary for lead width detection in the same manner as the lead width detection of the lead imaged in the horizontal direction. It has a configuration provided with read count suppression means.
[0018]
Further, in the apparatus according to the present invention, the number-of-reads suppression means uses a line memory having a storage capacity equal to the number of arrangement bits in the horizontal direction of the second video memory to be equal to the number of arrangement bits in the vertical direction of the video memory. One bin is stored in parallel, and the binary image data is stored in the n line memories sequentially from the preceding data by the number of arrangement bits in the horizontal direction of the second video memory. Data is read from the n line memories in parallel and simultaneously in a time-sequential order one bit at a time, and this is written in the second video memory in the order of reading, thereby generating the 90-degree converted binary image data. .
[0019]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor chip is mounted on a lead frame, and an image pickup device that detects misalignment between the semiconductor chip and the lead frame is aligned with a bonder that wire bonds (wire connection) the electrodes of the semiconductor chip and the leads of the lead frame. The lead width detection device in the wire bonder with an image processing device that detects the difference between the center line of the lead and the reference line that should be based on the lead width detection of the outer leads that are arranged in parallel among the leads, Based on the detected data, a positional deviation between the semiconductor chip and the lead frame is detected, and the positional alignment between the two is automatically performed by the position correcting device.
[0020]
The lead width detection device detects the lead width by using the image data of the lead imaged in an overhead view by an imaging device using an imaging sensor such as a CCD camera, but is acquired by the imaging device and binarized. The image data is temporarily stored in the video memory while being updated for each frame, and is read out and used for lead width detection.
[0021]
In this case, there is a significant difference in the number of times data is read from the video memory depending on whether the initial image of the lead is imaged (drawn) in the horizontal direction or in the vertical direction. The number of times of reading in the case of being taken is that the amount of processing is inevitably increased as compared with the case where the image is taken in the vertical direction.
[0022]
In the present invention, attention is paid to the fact that the above-mentioned problems can be avoided by performing the lead width detection processing of the lead imaged in the horizontal direction using the image data obtained by performing the image conversion of 90 degrees with respect to the initial image. 90 degree image conversion based on the array conversion of binarized image data is realized.
[0023]
1 includes a video memory 5a, a CPU 6a, a timing signal generator 7a, a video memory coordinate output unit 8a, a line memory coordinate output unit 9, and n line memories 10a, 10b,. The line memories 10a, 10b,..., 10n are data as array bit numbers in the column direction (horizontal direction) of the video memory 5a. It is a line memory having a storage capacity equal to the number of array bits of the bus bit width, and has n stages equal to the number of array bits in the row direction (vertical direction), and the coordinates of each line memory on the video memory 5a are Given from the line memory coordinate output unit 9, under the control of the CPU 6a, the video memory 5 is designated by the coordinate designation of the video memory coordinate output unit 8a. Stored, it is performed by 90 degrees conversion effective image based on the sequence data conversion.
[0024]
Thus, the read data of the video memory 5 is used as detection target data for detecting the read width of the lead imaged in the vertical direction, and the read data of the video memory 5 is used for detecting the read width of the lead imaged in the horizontal direction. It is possible to suppress the number of readings of the video memory for detecting the lead width to the same level as the vertical direction for both horizontal and vertical imaging leads.
Note that which of the video memories 5 and 5a is to be read is determined according to the input data under the control of the internal program of the CPU 6a.
[0025]
【Example】
Next, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The configuration of the embodiment shown in FIG. 1 is the same as that of the conventional example shown in FIG. 5, the A / D converter 2, the comparator 3, the shift register 4, the video memory 5, and the video memory coordinate output. In addition to the unit 8, the video memory 5a, the CPU 6a, the timing signal generator 7a, the video memory coordinate output unit 8a, the line memory coordinate output unit 9, the line memory directly constituting the present invention and constituting the reading number suppression means, Memory 10a, 10b, ... 10n.
[0026]
Next, the operation of this embodiment will be described.
The read image data acquired by the imaging apparatus 1 is a pixel unit having a size for detecting the read width by the reference sampling clock at the control timing of the timing signal output by the A / D converter 2 and the timing signal generator 7a. Is sampled and digitized.
[0027]
The comparator 3 compares the digital data output from the A / D converter 2 with the reference level 301, binarizes it, and sends it as binary image data. The shift register 4 performs serial / parallel conversion of the binarized image data, and synchronizes the parallel data of the bit number unit of the data bus bit width (the number of arrangement bits in the horizontal direction) of the video memory 5 in synchronization with the reference sampling clock. The converted data is stored in the video memory 5 under the control of the CPU 6a that controls the operation of the entire system.
[0028]
In the video memory 5, the initial binarized image data is stored in units of one frame in the arrangement state with the data bus bit width and the arrangement bit number n in the vertical direction. On the other hand, in the video memory 5a, the 90-degree converted binary image data obtained by converting the initial binary image data by 90-degree arrangement is stored simultaneously with the storage of the video memory 5 as follows. Note that these two video memories 5 and 5a are subjected to area setting and coordinate designation by the video memory coordinate output units 8 and 8a, respectively.
[0029]
Initial binary image data in the serial format output from the comparator 3 is sequentially stored in n line memories 10a, 10b,..., 10n each having a storage capacity corresponding to the data bus bit width, and is stored in one frame. Of the data, the first data string is stored in the line memory 10n and the last data string is stored in the line memory 10a. Thus, the binary image data stored in the n line memories is stored in the video memory under the control of the CPU 6a. The image is stored in the video memory 5a by an address designated by the coordinate output unit 8a. As a result, an image obtained by rotating the initial binarized image data by 90 degrees is stored on the video memory 5a.
[0030]
FIG. 2 is an explanatory diagram of the 90-degree array conversion operation of the binarized image data in the embodiment of FIG. FIG. 2A shows an initial binarized image data array 11, in which the horizontal array number (data bus bit width) is 16 pixels expressed as aa to ap, and the vertical array number is also 16 pixels. The case from aa to pa is taken as an example. Symbols aa to pp are given for convenience for identification of corresponding pixels, and pixels represented by these symbols are represented by binary logical values 1 or 0, respectively.
[0031]
FIG. 2B shows the line memory data array 12. The line memory data array 12 is 16 data strings stored in n, which is n = 16 line memories 10a to 10n, which is equal to the number in the vertical direction shown in FIG. The array of a certain line memory 10a to the array of the line memory 10n is shown. The top row is the data array of the line memory 10n, and the following shows that the array of the line memory 10a is stored in the order of preceding data. The line memory data array 12 is the same data for one frame as the initial binarized image data array 11.
[0032]
The line memory data array 12 is read out in parallel and simultaneously in the direction indicated by the arrow 122 from aa, ba,... Pa in the column indicated by the arrow 121 and written to the video memory 5a. Thus, the reading of the line memory data array 12 is performed in the form of parallel reading in the order of preceding data in the line memories 10a to 10n shown in FIG. As described above, the line memory 10n stores the preceding data string starting from aa and reaching ap, and the line memory 10a stores the last data string pa to pp in the frame. Parallel reading is possible.
[0033]
FIG. 2C shows the initial binarized image data read out in this manner, in which one frame is sequentially written in the video memory 5a by the data bus bit width in the same manner as the video memory 5, and this is 90 degrees. This is a converted binary image data array 13.
[0034]
That is, the 90 degree conversion binarized image data array 13 reads the line memory data array 12 shown in FIG. 2B in order of precedence from the aa to pa columns of the previous matrix to the ap to pp columns of the last column. As a result, the initial binarized image data array 11 shown in FIG. 2A is an array obtained by rotating the array direction by 90 degrees. In this way, a 90-degree converted image of the initial binarized image is obtained.
[0035]
It should be noted that which of the video memories 5 and 5a is to be read is switched at any time corresponding to the input data under the control of a built-in program of the CPU 6a so as to always ensure vertical data reading.
[0036]
FIG. 3 is an explanatory diagram of the 90-degree image conversion operation in the embodiment of FIG.
The lead 101 shown in FIG. 3A is a lead imaged in the horizontal direction, and detection target data 1012 binarized in units of pixels with respect to the detection target column 1011 to detect the width of the lead is 90. 3B, as shown in FIG. 3B, the same state as when processing the detection target data 1014 in the detection target row 1013 is the same as the case where the lead 101 is imaged in the vertical direction. The number of times can be suppressed.
[0037]
FIG. 4 is a diagram illustrating a specific example of the detection target data in FIG. 3. FIG. 4A shows detection target data obtained with respect to a lead imaged in the horizontal direction, and when this is converted by 90 degrees, an array state shown in FIG. 4B is obtained. In addition, 1a to 6r indicate binary data corresponding to each pixel, and in the lead width detection, detection target data for each pixel is added to the left and right of FIG. 4B for the purpose of lead edge detection. Will be.
In this way, the number of read times of stored data in read width detection can be significantly reduced.
[0038]
【The invention's effect】
As described above, according to the present invention, in the lead width detection by the image pickup apparatus performed to ensure the positional alignment between the semiconductor chip and the lead frame when the semiconductor chip is mounted on the lead frame and bonded, the horizontal direction is used as the initial image. The serialized binarized image of the read image is written in a line memory having a parallel configuration with a storage capacity equal to the number of bits of the horizontal arrangement width of the video memory and a number of arrangements equal to the vertical arrangement width of the video memory, Data stored in the line memory is read in parallel and written to the video memory in the order of preceding data, enabling 90 degree array conversion of the data image, significantly reducing the number of times image data is read in the read width detection process, and the read width detection process. Wire bonding as a semiconductor manufacturing equipment that can significantly reduce time It has an advantage of being able to significantly improve the bonding performance of.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a lead width detection apparatus according to an embodiment of the present invention.
2 is an explanatory diagram of a 90-degree array conversion operation of binarized image data in the embodiment of FIG.
FIG. 3 is an explanatory diagram of a read width detection operation of the embodiment of FIG. 1;
4 is a diagram illustrating a specific example of detection target data in FIG. 3; FIG.
FIG. 5 is a block diagram showing a configuration of a conventional lead width detection device.
FIG. 6 is an explanatory diagram of a conventional read width detection operation;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Imaging device 2 A / D converter 3 Comparator 4 Shift register 5, 5a Video memory 6, 6a CPU
7, 7a Timing signal generator 8, 8a Video memory coordinate output unit 9 Line memory coordinate output unit 10a-10n Line memory

Claims (2)

A rectangular lead frame in which the electrodes of the mounted semiconductor chip and the leads to be wired by automatic bonding are arranged is imaged from a bird's-eye view with an imaging device, and the outer lead as an external connection part arranged in parallel with the lead frame is targeted Necessary for automatic bonding based on the read width obtained by reading out the data necessary to detect the width of the lead from the first video memory as a frame memory storing the binary image data of the imaging data of the lead In a lead width detecting apparatus for ensuring alignment between a semiconductor chip and a lead, 90 degree converted binary image data obtained by rotating the array direction of the binarized image data stored in the video memory 90 degrees to the right is stored. A second video memory having the same storage area as the first video memory is provided and imaged in the horizontal direction. The detection target data necessary to detect the width of the lead is read from the second video memory, and the lead imaged in the horizontal direction is handled in the same manner as the lead imaged in the vertical direction effectively. The number of times of reading of the detection target data necessary for lead width detection can be reduced in the same manner as the lead width detection of the lead imaged in the horizontal direction. Lead width detection device characterized by the above. The number-of-reads suppression means is arranged in parallel with n line memories having a storage capacity of the number of arrangement bits in the horizontal direction of the second video memory as n equal to the number of arrangement bits in the vertical direction of the video memory, The n line memories store the binarized image data sequentially from the preceding data by the number of arrangement bits in the horizontal direction of the second video memory, and store the stored data for one frame. 2. The apparatus according to claim 1, further comprising a configuration in which the 90-degree converted binary image data is generated by reading one bit at a time in parallel in a time series from a memory, and writing the read data in the second video memory in the reading order. The lead width detecting device according to 1.

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