JP3855825B2 - Image reading apparatus and image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image reading apparatus of an image forming apparatus, and more particularly to an image reading apparatus and an image forming apparatus using a solid-state image sensor.
[0002]
[Prior art]
In recent years, copying machines have been remarkably increased in speed and resolution, and there has been a demand for further increases in the speed of electronic circuits inside the copying machines. In particular, when reading image information converted into an electrical signal from a solid-state image sensing device that senses light image information, the increase in the number of data points due to the increase in resolution and the two demands for speeding up further increase the speed. It is necessary to speed up the basic clock for reading image information.
[0003]
[Problems to be solved by the invention]
However, according to the above-described prior art, erroneous image information may be read when reading image information from the solid-state imaging device. That is, after analog-to-digital conversion of the analog signal output of the solid-state imaging device, latching that is sampling of a digital signal is performed. The latch timing may be shifted due to variations in the analog signal output timing, and incorrect image information may be sampled.
[0004]
In particular, in a solid-state imaging device represented by a CCD, the basic clock has been increased in frequency with the increase in speed, and consequently the latch cycle generated from the basic clock has also been shortened, and the distributed constant electrical factor is a sampling signal. Affects the transmission. For this reason, in order to accurately A / D convert the analog signal output, the timing of the analog signal output is adjusted, which further causes a shift in the latch timing.
[0005]
From these facts, it is extremely important how to realize that the image information digitized by A / D conversion is latched at an optimal timing and accurate image information is acquired.
[0006]
The present invention has been made in order to solve the above-described problems of the prior art, and latches image information digitized by A / D conversion at an optimal timing to obtain accurate image information. An object is to realize an apparatus and an image forming apparatus.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object, an image reading apparatus according to the first aspect of the present invention includes a solid-state imaging device that converts image information from an optical signal to an electrical signal, sampling the electrical signal, and An analog processing unit that amplifies and generates an analog processing signal, an A / D conversion unit that A / D converts the analog processing signal into a digital signal, a latch unit that latches the digital signal, the solid-state imaging device, An image reading apparatus comprising: a pulse generation unit that generates control pulses to the analog processing unit, the A / D conversion unit, and the latch unit; and a control unit that controls pulse generation timing of the pulse generation unit. The analog processing unit includes a clamp circuit that sets the output of the analog processing signal to a set voltage, and the pulse generation unit changes the latch timing. The latch unit includes a determination circuit that detects the latch information, compares the set voltage information with the set voltage information, and determines whether the set voltage matches, and the control unit changes the set voltage when the set voltage is changed. Judgment information is repeatedly obtained by changing the latch timing using the variable means, and optimization means is provided for optimizing the latch timing from the plurality of obtained judgment information.
[0008]
According to the first aspect of the present invention, the analog processing unit uses the clamp circuit to set the output of the analog processing signal to the set voltage, the pulse generating unit changes the latch timing using the variable means, and the latch unit includes the determination circuit. The latch unit detects the latch information, compares it with the set voltage information and determines whether it matches, and the control unit uses the variable unit to change the latch timing with the decision information when the set voltage is changed by the optimization unit. Since it is repeatedly acquired and the latch timing is optimized from the plurality of acquired determination information, the digital information of the A / D converted image can be latched by the latch unit without error.
[0009]
According to a second aspect of the present invention, in the image reading apparatus according to the second aspect of the present invention, the control unit includes a first voltage variable unit that changes the set voltage by the latch period by one bit or a plurality of bits of the digital signal. It is characterized by providing.
[0010]
According to the second aspect of the present invention, the control unit changes the set voltage by the first voltage variable means by one or more bits of the digital signal in the latch cycle. The D-converted digital signal can be switched by a latch cycle by one bit or a plurality of bits.
[0011]
According to a third aspect of the present invention, in the image reading apparatus according to the third aspect of the invention, the control unit has a gradient in which the set voltage changes by one bit or a plurality of bits of the digital signal in the latch period, and is proportional to time. A second voltage variable means that changes is provided.
[0012]
According to the third aspect of the present invention, the control unit has a gradient in which the set voltage is changed by one bit or a plurality of bits of the digital signal in the latch period by the second voltage variable means, and is proportional to time. Since it is supposed to change, it is possible to switch the A / D converted digital signal by one or a plurality of bits in a latch cycle by using voltage variable means that does not operate at high speed.
[0013]
An image reading apparatus according to a fourth aspect of the invention is characterized in that the determination circuit includes a detection unit that detects the 1-bit information or the multi-bit information of the digital signal.
[0014]
According to the fourth aspect of the present invention, the determination circuit detects one-bit information or multiple-bit information of the digital signal by the detection unit, and therefore separately detects the digital information sampled in the latch unit. Can do.
[0015]
An image reading apparatus according to a fifth aspect of the invention is characterized in that the detection unit detects the 1-bit information or the multi-bit information with the same latch signal as the latch.
[0016]
According to the fifth aspect of the present invention, since the detection unit detects one-bit information or multiple-bit information with the same latch signal as the latch of the latch unit, the digital information latched in the latch unit The same digital information can be detected separately.
[0017]
According to a sixth aspect of the present invention, in the image reading apparatus according to the sixth aspect, the determination circuit includes a comparison unit that compares the detection information with the set voltage information of the first or second voltage variable unit. It is characterized by.
[0018]
According to the sixth aspect of the present invention, the determination circuit uses the comparison means to compare the detection information with the set voltage information of the first or second voltage variable means. It can be determined whether or not the voltage indicated by the digital information after A / D conversion matches.
[0019]
According to a seventh aspect of the present invention, in the image reading apparatus according to the seventh aspect, when the latch timing is changed by the optimization unit, the latch timing having the determination information that matches the set voltage information is set as the optimum position. It is characterized by doing.
[0020]
According to the seventh aspect of the present invention, the optimization means sets the sampling position having the determination information that matches the set voltage information as the optimal position when the latch timing is changed. And the latch timing at which the voltage indicated by the digital information after A / D conversion matches can be set as the optimum position.
[0021]
An image reading apparatus according to an eighth aspect of the invention is characterized in that, when there are a plurality of the optimum positions, the optimization unit sets the latch timing existing at the center position as the optimum position.
[0022]
According to the eighth aspect of the present invention, the optimization means sets the latch timing existing at the center position as the optimum position when there are a plurality of optimum positions. The latch timing for latching can be set to the optimum position.
[0023]
The image reading apparatus according to the invention described in claim 9 is characterized in that the variable means changes the latch timing in two ways: a timing of the latch and a timing of one cycle from the latch. .
[0024]
According to the ninth aspect of the present invention, since the variable means changes the latch timing in two ways, that is, the latch and the one-cycle timing from the latch, the variable means can be simplified from the latch information of the two latch timings. The optimum position can be determined.
[0025]
The image forming apparatus according to claim 10 is characterized in that the variable means is configured using a delay line.
According to the tenth aspect of the invention, since the variable means is configured using the delay line, the latch timing can be changed with high accuracy.
[0026]
In an image forming apparatus according to an eleventh aspect of the present invention, the optimization unit includes an execution unit that is executed at an arbitrary time after power-on in accordance with an instruction from an operator.
[0027]
According to the eleventh aspect of the present invention, since the optimization means is executed at an arbitrary time after the power is turned on by the execution means according to an instruction from the operator, the sampling position changes due to a temperature change or the like. Even when the latch timing is not suitable, the latch timing can be optimized again.
[0028]
According to a twelfth aspect of the present invention, there is provided an image forming apparatus, wherein an operator inputs information, converts an original into an electrical analog signal as image information, and further converts the analog signal into a digital signal. An image forming apparatus comprising: an image reading unit that latches the digital signal; an image processing unit that performs image processing on the image information; and an image copying unit that copies the image information onto a transfer sheet. The reading unit detects a clamp circuit that uses the analog signal output as a set voltage, a variable unit that changes a latch timing of the latch, and latch information of the latch, and compares the set voltage information with each other and determines whether or not they match. The determination circuit to perform and the determination information when the set voltage is changed are repeatedly obtained by changing the latch timing using the variable means. And optimization means for optimizing said latch timing from the obtained plurality of the determination information is characterized by comprising a.
[0029]
According to the twelfth aspect of the invention, the image reading section sets the analog signal output by the clamp circuit, changes the latch timing of the latch by the variable means, detects the latch information by the determination circuit, and sets the set voltage. Comparison information and determination of coincidence are performed, and determination information when the setting voltage is changed by the optimization means is repeatedly acquired by changing the latch timing using the variable means. From the plurality of acquired determination information Since the latch timing is optimized, the digital information of the image can be latched without error, and a high-quality image can be copied.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of an image reading apparatus and an image forming apparatus according to the present invention will be described below with reference to the accompanying drawings. Note that the present invention is not limited thereby.
[0031]
First, the overall configuration of a copying machine 100 that is an image forming apparatus according to the present embodiment will be described with reference to FIG. The copying machine 100 copies characters or drawings written on a document as image information onto a transfer sheet, and includes an operation unit 110, an image reading unit 120, an image processing unit 130, an image forming unit 140, an image memory 150, and these. It consists of the control part 160 which controls.
[0032]
The operation unit 110 is an input unit for an operator to transmit information such as the number of transferred sheets, transfer density, or transfer sheet selection to the control unit 160, and includes a touch panel, operation keys, and the like. The image reading unit 120 is a part that reads image information written on a document and converts it from an analog signal to a digital signal. The image processing unit 130 performs image processing on the read image information to improve the quality of the transferred image information.
[0033]
The image forming unit 140 transfers the image information subjected to the image processing to a transfer sheet, and creates a transfer document. The image memory 150 stores and stores the image read by the image reading unit 120 and the image processed by the image processing unit 130. The control unit 160 controls each of the above units, and manages and operates the processes from reading the original to transferring the original.
[0034]
Next, a specific configuration of the image reading unit 120 will be described with reference to FIG. Here, in the figure, a solid line represents a signal line for transmitting information, and a dotted line is a control line for controlling operation timing. The image reading unit 120 has a function of converting image information of a document from an optical signal into an analog electric signal, and further converting it into a digital signal. The image reading unit 120, an analog signal processing unit 210, an A / D converter 220, a latch The unit 250 includes a gate array 230 and a pulse generator 240.
[0035]
The solid-state imaging device 200 includes a CCD (Charge Coupled Device) optical sensor, reads optical image information of a document illuminated by a lamp (not shown) with a photodiode array, and converts the information into an electrical signal. These electric signals are sequentially read out by a CCD and an analog signal register provided between the photodiode arrays.
[0036]
The analog signal processing unit 210 extracts a signal period including charge information accumulated in the photodiode from the electrical signal read from the solid-state imaging device 200, and performs sampling.
[0037]
The A / D converter 220 converts, for example, 10 bits of the electrical signal including the charge information sampled by the analog signal processing unit 210 from an analog signal to a digital signal.
[0038]
The latch unit 250 is connected to the A / D converter 220 through a communication line having the number of conversion bits, and includes a digitized electric signal sampling and holding circuit and a driver circuit to the next stage. Also included is a determination circuit that determines whether the electrical signal has been sampled normally.
[0039]
The gate array 230 serves as an interface between the image reading unit 120 and other processing units of the copying machine 100, and an electric signal converted from a digital signal into an image memory via the control unit 160 or a communication bus (not shown). Sort to 150 etc. and transfer.
[0040]
The control unit 160 includes a CPU and a transmitter that generates a basic clock, and generates a signal for controlling the entire image reading unit 120. In particular, signals that control the solid-state imaging device 200, the analog signal processing unit 210, the A / D converter 220, and the latch unit 250 are generated via the pulse generation unit 240 because highly accurate timing is required.
[0041]
The pulse generation unit 240 generates a signal for controlling the solid-state imaging device 200, the analog signal processing unit 210, the A / D converter 220, and the latch unit 250 based on the control signal from the control unit 160. Since this circuit needs to generate a control signal with high accuracy, for example, by combining a delay line and a selector, it is possible to generate a control pulse having highly accurate timing.
[0042]
Next, a specific configuration of the analog signal processing unit 210 will be described with reference to FIG. FIG. 3 is a block diagram illustrating a specific configuration of the analog signal processing unit 210. The output signal of the solid-state imaging device 200 is input to the clamp circuit 310, and the polarity of the electric signal in the signal period including the DC potential shift and the image information is inverted in synchronization with the pulse from the pulse generator 240.
[0043]
The sampling circuit 320 samples and holds the output signal of the clamp circuit 310 in synchronization with the pulse from the pulse generator 240. Note that this sampling timing extracts only a signal period including image information from the output signal of the solid-state image sensor 220.
[0044]
The amplification processing circuit 330 amplifies the sampled output of the sampling circuit 320 to a voltage suitable for A / D conversion by the A / D converter 220.
[0045]
The clamp circuit 340 shifts the DC potential in synchronization with the pulse from the pulse generator 240 and adjusts the DC component of the image information. Here, the configuration of the clamp circuit 340 will be described with reference to FIG. The clamp circuit 340 includes an adder 430, a D / A converter 410, and a driver 420. The D / A converter 410 performs D / A conversion by the clamp pulse from the pulse generator 240 to generate a DC voltage. Then, the controller 160 adds this DC voltage to the output signal of the amplification processing circuit 330. The DC voltage is set by digital bit information from the control unit 160 via the gate array 230. The output of the D / A converter 410 is connected to the adder 430 through the driver 420.
[0046]
Here, the DC voltage is switched at a cycle that is twice as long as the A / D conversion cycle, and the fixed voltage component is, for example, the black level when the lamp that provides optical information to the solid-state imaging device 200 is not lit. And the fluctuation voltage component has such a magnitude that the output of the A / D converter 220 changes by 1 bit.
[0047]
Next, the specific configuration of the latch unit 250 and the connection inside the image reading unit 120 will be described in detail with reference to FIG.
The latch unit 250 in FIG. 5A includes a driver circuit 570 and a determination circuit 510. The driver circuit 570 latches the A / D output signal of the A / D converter 220 via the signal line and outputs it to the gate array 230 via the driver. Note that the pulse generator 240 generates various timing signals based on the basic clock sent from the controller 160 to the pulse generator 240 via the gate array 230. That is, the sampling pulse to the sampling circuit 320, the clamp pulse to the clamp circuit 340, the A / D conversion pulse to the A / D converter 220, and the latch pulse to the latch unit 250. Here, the A / D conversion pulse changes in conjunction with the change in timing of the sampling pulse, but the latch pulse is generated from the basic clock separately from the sampling pulse.
[0048]
Moreover, the control part 160 has a 1st voltage variable means. In the voltage setting to the clamp circuit 340 via the gate array 230, the first voltage varying means repeatedly turns on and off the voltage at which the output of the A / D converter 220 changes by 1 bit at the cycle of the A / D conversion pulse.
[0049]
A block diagram of the determination circuit 510 is shown in FIG. The determination circuit 510 compares the A / D conversion pulses from the two flip-flops 520 and 540 and the comparator 550 and the pulse generator 240 that determine whether the outputs of the two flip-flops are the same. It consists of a frequency dividing circuit 530. The flip-flop 520 is a latch circuit that detects the same sampling signal as the driver circuit 570 detects. The flip-flop 540 sets the input signal of the A / D converter 220, that is, the output signal of the clamp circuit 340. It is a latch circuit that detects from information at a double cycle of A / D conversion. Therefore, by comparing the output signals of the two flip-flops 520 and 540 with the comparator 550, whether the input information of the A / D converter 220 has been accurately A / D converted and sampled by the driver circuit 570 or not. Judgment is made.
[0050]
Next, the control operation of the image reading unit 120 by the control unit 160 will be described using the flowchart of FIG. 6 and the time chart of FIG. In the time charts of FIGS. 7A to 7E, the horizontal axes all share the same time axis, and the vertical axis indicates a digital voltage signal generally composed of binary values of a high level and a low level. .
[0051]
First, the control unit 160 turns off the lamp of the image reading unit 120 (step S600), and sets the voltage in the clamp circuit using the first voltage varying unit. Then, the clamp circuit 340 outputs a set voltage at the timing of the clamp pulse from the pulse generator 240 (step S601). FIG. 7A shows an output waveform of the clamp circuit that is switched by the set voltage output. This output waveform represents the fluctuation voltage portion of the output of the clamp circuit, and the fixed voltage portion is set to a black level voltage, for example. By this fluctuation voltage portion, one bit of the A / D output signal detected by the determination circuit 510 is switched.
[0052]
Further, the fluctuation voltage is switched between a high level and a low level in a period twice as long as the A / D conversion repetition period. In addition, by including a bias voltage such as a black level voltage in the fixed voltage portion, the variable voltage portion can be set to a voltage level that is not affected by noise.
[0053]
Thereafter, the control unit 160 sets the latch timing (step S602) and performs A / D conversion (step S603). FIG. 7B shows the waveform of the A / D conversion pulse from the pulse generator 240. At the rising portion of this waveform, the A / D converter 220 performs A / D conversion. Then, the A / D output signal shown in FIG. 7C is output to the input portion of the driver circuit 570. This waveform appears later than the rising portion of the A / D conversion pulse from the pulse generator 240. This is an effect such as a conversion time of the A / D converter 220 and a transmission time required for the A / D conversion output to reach the input part of the driver circuit.
[0054]
Note that the setting of the latch timing in step S602 is set as a delay time from the basic clock. The latch timing is set at a plurality of points within a range within twice the A / D conversion cycle. Further, as shown in FIG. 7F, the flip-flop 540 of the determination circuit 510 latches the change bit information of the voltage setting signal from the gate array 230 at the rising portion of the A / D conversion pulse. This latch information is used as determination reference information when determining 1-bit information of the A / D output signal detected by the determination circuit 510.
[0055]
Thereafter, as shown in FIG. 7D, control unit 160 outputs the latch pulse having the delay time set in step S602 from pulse generation unit 240 to driver circuit 570 and determination circuit 510. Then, the driver circuit 570 latches all the bits of the A / D output signal, and the determination circuit 510 latches one bit that changes depending on the fluctuation voltage portion of the clamp circuit by the flip-flop 520 (step S604).
[0056]
Thereafter, the comparator 550 of the determination circuit 510 compares the outputs of the flip-flops 520 and 540, outputs a high level signal if they match, and outputs a low level signal if they do not match. This output signal is transmitted to the control unit 160 via the gate array 230.
[0057]
Thereafter, the control unit 160 determines whether or not the determination information at all the latch timings has been acquired (step S606), and if not acquired (No at step S606), the control unit 160 proceeds to step S603 and determines the delay time. Different latch timings are sequentially output to perform A / D conversion. When the determination information at all the latch timings is acquired (Yes at Step S606), the control unit 160, as shown in FIG. Information obtained by binarizing the A / D output waveform is acquired. From this information, a latch timing having a high level output is selected and set as an optimum value (step S607). When there are a plurality of optimum values, the latch timing existing at the center position of the latch timing having a high level output is set as the optimum value.
[0058]
Thereafter, the control unit 160 sets the optimum value acquired in step S607 as the latch timing for the pulse generation unit 240 (step S608), and ends the optimization of the latch timing.
[0059]
As described above, in this embodiment, the output of the analog signal processing unit 210 is voltage-set by the clamp circuit 340 and the input of the driver circuit 570 after A / D conversion by the A / D converter 220 is determined. Since the detection by the circuit 510 and comparison with the voltage setting information are repeatedly performed by changing the latch timing of the driver circuit 570 and the determination circuit 510, the optimum latch timing is obtained from a plurality of the determination information. Even when the output timing of the image information of the analog signal processing unit 210 fluctuates, the driver circuit 570 can latch only the image information, and can prevent erroneous image information from being latched.
[0060]
In addition, since the optimization of the latch timing according to the present embodiment is performed by the control unit 160, it can be performed at an arbitrary time after the power is turned on by giving an instruction from the operation unit 110 to the control unit 160 by the operator.
[0061]
In the present embodiment, only one bit of the A / D output signal is compared with the voltage setting signal by the determination circuit 510, but a plurality of bits can be compared and determined. In this case, the voltage setting signal of the first voltage varying means is also set to a voltage at which the A / D output signal changes by the plurality of bits. Then, it is assumed that the plurality of bits are compared by the plurality of determination circuits 510, and correct latching is performed when all the bits match the set voltage information.
[0062]
In this embodiment, the pulse generation unit 240 changes the delay time of the latch pulse a plurality of times and acquires the repeated determination information. However, the delay time is zero and two points of the cycle for performing A / D conversion. The optimum latch timing can be obtained from the determination information.
(Other examples of embodiment)
In the above embodiment, the variable voltage output of the clamp circuit 340 is a signal that repeats at a period twice that of the A / D conversion pulse output waveform. However, it may be a staircase waveform having a predetermined gradient. In another example of the present embodiment, a case where the fluctuation voltage output of the clamp circuit 340 is a staircase waveform is illustrated. Note that the configuration of the apparatus is the same as that of the above embodiment, and thus the description thereof is omitted.
[0063]
Here, the control part 160 has a 2nd voltage variable means. The second voltage varying means sequentially sets the voltage at which the output of the A / D converter 220 changes by one bit or a plurality of bits in the period of the A / D conversion pulse when setting the voltage to the clamp circuit 340 via the gate array 230. Set the voltage to increase or decrease.
[0064]
FIG. 8 is a time chart showing the operation of the present embodiment. FIG. 8A corresponds to FIG. 7A of the above embodiment, and shows a fluctuation voltage output waveform of the clamp circuit 340. This fluctuation voltage output waveform is a stepped voltage waveform in which the A / D output signal is switched by 1 bit or a plurality of bits in the pulse period of the A / D conversion pulse from the pulse generator 240 shown in FIG. 8B. .
[0065]
Thereafter, the control unit 160 performs the same operations as those in FIGS. 7C to 7F by detecting the A / D output signal and the operation of the latch pulse. The latch unit 250 includes one or more determination circuits 510 depending on whether the A / D output signal is switched to 1 bit or multiple bits.
[0066]
As described above, in the other example of the present embodiment, since the variable voltage output of the clamp circuit 340 has a stepped waveform, only the gradient needs to be specified, and control is easy. Further, since the rising portion of the staircase of this waveform does not affect the determination information, the ramp waveform output by the low-speed clamp circuit 340 can be realized.
[0067]
【The invention's effect】
As described above, according to the first aspect of the present invention, the analog processing unit sets the output of the analog processing signal to the set voltage by the clamp circuit, and the pulse generation unit changes the latch timing by the variable means, The detection unit detects the latch information by the determination circuit, compares it with the set voltage information, and determines whether or not it matches. The control unit latches the determination information when the set voltage is changed by the optimization unit using the variable unit. Since the timing is changed and repeatedly acquired, and the latch timing is optimized from the plurality of acquired determination information, the digital information of the A / D converted image can be latched by the latch unit without error. There is an effect.
[0068]
According to the second aspect of the present invention, since the control unit changes the set voltage by the first voltage variable means by one bit or a plurality of bits of the digital signal in the latch cycle, the A / D The converted digital signal can be switched by a latch period by one bit or a plurality of bits.
[0069]
According to the third aspect of the present invention, the control unit changes in proportion to time with a gradient in which the set voltage changes by one bit or a plurality of bits of the digital signal in the latch period by the second voltage variable means. Therefore, it is possible to switch the A / D converted digital signal by one or a plurality of bits in a latch cycle by using voltage varying means that does not operate at high speed.
[0070]
According to the fourth aspect of the present invention, the determination circuit detects 1-bit information or multiple-bit information of the digital signal by the detection unit, so that it can separately detect the digital information sampled in the latch unit. it can.
[0071]
According to the fifth aspect of the present invention, the detection unit detects the 1-bit information or the multi-bit information with the same latch signal as the latch of the latch unit. It is possible to separately detect the same digital information.
[0072]
According to the sixth aspect of the present invention, the determination circuit compares the detection information with the set voltage information of the first or second voltage variable means by the comparison means. It can be determined whether or not the voltage indicated by the digital information after / D conversion matches.
[0073]
According to the seventh aspect of the present invention, the optimization means sets the sampling position having the determination information that matches the set voltage information as the optimal position when the latch timing is changed. The latch timing at which the voltage indicated by the digital information after A / D conversion matches can be set as the optimum position.
[0074]
According to the eighth aspect of the present invention, the optimization means sets the latch timing existing at the center position as the optimum position when there are a plurality of optimum positions, so the set voltage information is latched most reliably. The latch timing to be performed can be set to the optimum position.
[0075]
According to the ninth aspect of the present invention, since the variable means changes the latch timing in two ways, that is, the latch and the timing of one cycle from the latch, the variable means can be simply calculated from the latch information of the two latch timings. An optimal position can be determined.
[0076]
According to the invention described in claim 10, since the variable means is configured using the delay line, the latch timing can be changed with high accuracy.
[0077]
According to the eleventh aspect of the invention, since the optimization means is executed at an arbitrary time after the power is turned on by the execution means according to an instruction from the operator, the sampling position changes due to a temperature change or the like and is latched. Even when the timing is not suitable, the latch timing can be optimized again.
[0078]
According to the twelfth aspect of the present invention, the image reading unit sets the voltage of the analog signal output by the clamp circuit, changes the latch timing of the latch by the variable means, detects the latch information by the determination circuit, and sets the set voltage information. And the decision information when the set voltage is changed by the optimization means is repeatedly obtained by changing the latch timing using the variable means, and latched from the obtained plurality of decision information Since the timing is optimized, the digital information of the image can be latched without error, and a high-quality image can be copied.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an overall configuration of an image forming apparatus.
FIG. 2 is a block diagram illustrating an image reading unit of the image forming apparatus.
FIG. 3 is a block diagram illustrating an analog signal processing unit of the image reading unit.
FIG. 4 is a block diagram illustrating a clamp circuit of an analog signal processing unit.
FIG. 5 is a block diagram illustrating a latch unit and a peripheral circuit of an image reading unit, and a determination circuit of the latch unit.
FIG. 6 is a flowchart showing an operation of a control unit.
FIG. 7 is a time chart illustrating the operation of each unit constituting the image reading unit.
FIG. 8 is a time chart illustrating an operation of a clamp circuit according to an example of an embodiment;
[Explanation of symbols]
100 copier
110 Operation unit
120 Image reading unit
130 Image processing unit
140 Image forming unit
150 Image memory
160 Control unit
200 Solid-state image sensor
210 Analog signal processor
220 A / D converter
230 Gate array
240 Pulse generator
250 Latch part
310, 340 Clamp circuit
320 Sampling circuit
330 Amplification processing circuit
410 D / A converter
420 Driver
430 Adder
510 judgment circuit
520, 540 flip-flop
530 divider circuit
550 comparator
570 Driver circuit

Claims (12)

A solid-state imaging device that converts image information from an optical signal to an electrical signal; an analog processing unit that samples and amplifies the electrical signal to generate an analog processing signal; and
An A / D converter for A / D converting the analog processing signal into a digital signal;
A latch unit for latching the digital signal;
A pulse generator for generating control pulses to the solid-state imaging device, the analog processing unit, the A / D conversion unit, and the latch unit;
A control unit for controlling the pulse generation timing of the pulse generation unit;
An image reading apparatus comprising:
The analog processing unit includes a clamp circuit that sets the output of the analog processing signal to a set voltage,
The pulse generator includes variable means for changing the latch timing,
The latch unit includes a determination circuit that detects the latch information, compares the set voltage information, and determines a match.
The control unit repeatedly acquires the determination information when the set voltage is changed by changing the latch timing using the variable unit, and optimizes the latch timing from the plurality of acquired determination information. An image reading apparatus comprising optimization means for converting the image reading apparatus. The image reading apparatus according to claim 1, wherein the control unit includes a first voltage varying unit that changes the set voltage by the latch period by one bit or a plurality of bits of the digital signal. The control unit includes second voltage variable means for changing the set voltage in proportion to time with a gradient that changes by one bit or a plurality of bits of the digital signal in the latch cycle. Item 2. The image reading apparatus according to Item 1. The image reading apparatus according to claim 2, wherein the determination circuit includes a detection unit that detects the 1-bit information or the multi-bit information of the digital signal. The image reading apparatus according to claim 4, wherein the detection unit detects the 1-bit information or the multi-bit information with a latch signal that is the same as the latch. The image reading apparatus according to claim 5, wherein the determination circuit includes a comparison unit that compares the detection information with the set voltage information by the first or second voltage variable unit. The image reading apparatus according to claim 6, wherein the optimization unit sets the latch timing of the determination information that matches the set voltage information as an optimal position when the latch timing is changed. The image reading apparatus according to claim 7, wherein the optimization unit sets the latch timing existing at a center position as an optimal position when a plurality of the optimal positions exist. The image reading apparatus according to claim 7, wherein the variable unit changes the latch timing in two ways: a timing of the latch and a timing of one cycle from the latch. The image reading apparatus according to claim 1, wherein the variable unit is configured using a delay line. The image reading apparatus according to claim 1, wherein the optimization unit includes an execution unit that is executed according to an instruction from an operator at an arbitrary time after power is turned on. An operation unit for an operator to input information;
An image reading unit that converts an original into an electrical analog signal as image information, further converts the analog signal into a digital signal, and latches the digital signal;
An image processing unit that performs image processing on the image information;
An image copying unit for copying the image information onto a transfer sheet;
An image forming apparatus comprising:
The image reading unit
A clamp circuit for setting the analog signal output to a set voltage;
Variable means for changing the latch timing of the latch;
A determination circuit that detects latch information of the latch, compares the set voltage information, and determines a match;
Optimizing means for repeatedly acquiring the determination information when the set voltage is changed by changing the latch timing using the variable means, and optimizing the latch timing from the plurality of acquired determination information When,
An image forming apparatus comprising:

Images