JP3851620B2 - Data transmission / reception system - Google Patents

Description

  In the present invention, for example, Ethernet (registered trademark) data which is asynchronous serial data is synchronized with a fixed-band communication path (in this specification, synchronous data is a clock on the transmission side on the reception side). This is related to a data transmission / reception system that transmits and receives data synchronized between the transmitting side and the receiving side.

  Traditionally, government agencies such as the Ministry of Land, Infrastructure, Transport and Tourism, the National Police Agency and the Cabinet Office, local governments such as prefectures and municipalities, and public utilities such as power companies and gas companies have built private lines for the purpose of disaster prevention work and power system protection. is doing.

  For this purpose, this private line needs to maintain its communication function even in the event of a disaster such as an earthquake, and the reliability is ensured by using a wireless line having a duplex configuration for current use and backup.

  As for the interface of the existing private line wireless device, the communication speed relating to the communication path of a specific fixed band is determined, and 1.544 [Mbps], 6.31 [Mbps], 51.84 [Mbps], 155 .52 [Mbps] and the like (referred to as Hierarchy and recommended in the international standard period ITU-T). In Japan, the communication capacity of this private line wireless device is currently standardized in the range of 3 to 208 [Mbps] (see Non-Patent Document 1).

Ministry of Land, Infrastructure, Transport and Tourism (former Ministry of Construction) “6.5 GHz band 128QAM multiplex radio equipment specifications”, Kenden Tsushin (Nippon Dentsu) No. 48, enacted July 4, 2000, p. 1-p. 18

  By the way, recently, IP (Internet Protocol) technology has been developed, and voice communication is spreading through IP telephones and Internet communication with IP addresses for image and data communication. That is, every terminal is gradually becoming an IP terminal having an IP address.

  The IP data is output from each terminal as Ethernet (registered trademark) data which is asynchronous serial data.

  Therefore, for example, it is desired to communicate each IP data such as 10 [Mbps] 10 BASE, 100 [Mbps] 100 BASE-TX, or 1000 [Mbps] 1000 BASE through the above private line.

  This applicant has proposed the data transmission / reception system 2 schematically shown in FIG. 11 in Japanese Patent Application No. 2003-273645. The data transmission / reception system 2 is a system capable of full duplex and bidirectional communication. However, in order to facilitate understanding, the data transmission / reception system 2 will be described in a one-way (unidirectional) communication mode.

  The data transmission / reception system 2 includes a transmission station 4, a relay station 6, and a reception station 8.

  The transmitting station 4 is provided with an IP converter (transmitting side converter) 12, which converts 100BASE-TX data supplied from a transmitting side terminal (not shown) into a fixed band (limited band). 6) of the baseband data BB1 to BB4 of 6.31 [Mbps] is multiplexed and supplied to the communication ports CH1 to CH4 corresponding to the four communication paths of the wireless device 10.

  The relay station 6 is installed on a high mountain or the like to perform good regenerative relay, and is multiplexed radio signals (transmitted through four fixed-band communication channels) modulated by microwaves from the antenna 61 of the radio apparatus 10. Signal) is received by the antenna 62 of the wireless device 14, and once returned to the original baseband data BB1 to BB4, the communication port CH1 to CH4 of the wireless device 14 and the communication port of the wireless device 16 through the cables CB1 to CB4 Supply to CH1 to CH4. Then, re-transmission is performed from the wireless device 16 through the antenna 63.

  The receiving station 8 receives the retransmitted multiplexed radio signal by the antenna 64 of the radio apparatus 18 and returns it to the original baseband data BB1 to BB4. The returned baseband signals BB1 to BB4 are supplied to the IP converter (reception side converter) 20 from the communication ports CH1 to CH4. The IP converter 20 restores the original IP data of 100BASE-TX. The restored IP data is supplied to a receiving terminal (not shown) with reference to an IP address or the like.

  By the way, in the data transmission / reception system 2 configured as described above, the relay station 6 is provided between the output port of the transmission side IP converter 12 in the transmission station 4 and the communication ports (input ports) CH1 to CH4 of the wireless device 10. Between the communication ports (output ports) CH1 to CH4 of the wireless device 14 and the communication ports (input ports) CH1 to CH4 of the wireless device 16 and the communication ports (output ports) CH1 to CH4 of the wireless device 18 at the receiving station 8. And the receiving side IP converter 20 are connected by four cables, respectively, and there is a possibility that incorrect wiring is made when the cables are connected.

  For example, as shown in FIG. 12, when communication is performed while the cables CB3 and CB4 are crossed (so-called leverage) between the communication ports CH1 to CH4 of the radio apparatuses 14 and 16 of the relay station 6, reception is performed. There is a problem in that the IP converter 20 on the side cannot restore the 100BASA-TX data to the correct order, that is, the original data.

  More specifically and schematically, for example, as shown in FIG. 13A, 100BASE-TX asynchronous serial data includes packet (a, b, c), packet (d, e, f), packet (g, h, i), packet (j, k, l), and packet (m, n, o) are supplied to the IP converter 12 on the transmission side in this order, the IP converter 12 multiplexes them, As shown to 13B, it divides | segments into the baseband data BB1-BB4 for communication ports CH1-CH4.

  If the cable CB3 and the cable CB4 of the relay station 6 are crossed, as shown in FIG. 13C, the baseband data BB3 and BB4 supplied to the communication ports CH3 and CH4 of the wireless device 16 of the relay station 6 are It will be replaced. Then, in this order, the data is transmitted from the wireless device 16 to the wireless device 18 as it is.

  Therefore, the asynchronous serial data demultiplexed by the IP converter 20 on the receiving side is converted into packet (a, b, d), packet (c, e, f), packet (h, g, i), packet (j , L, k) and packets (m, n,) are reproduced in this order. In this example, all packet data is corrupted by garbled data, and the data is transmitted to a receiving terminal (not shown). It becomes impossible.

  In practice, the wireless relay station 6 is installed at intervals of several tens of kilometers or the like, and the connection work of the cables CB1 to CB4 at the relay station 6 is performed by a construction worker based on the communication path configuration diagram. As a result, time and cost are high.

  If any of the relay stations 6 has a cross of the cables CB1 to CB4, it takes a long time to identify and repair the occurrence location.

  The present invention has been made in consideration of such a problem, and even when the cable is connected to the cross, the receiving side can correctly restore the data to the original order. An object of the present invention is to provide a data transmission / reception system.

  Another object of the present invention is to provide a data transmission / reception system capable of easily detecting a cross connection of cables.

The data transmission / reception system of the present invention multiplexes asynchronous serial data, converts it to a number of synchronous data corresponding to each fixed-band communication path, and transmits it, and the received plurality of synchronous data, A receiving-side converter that demultiplexes and restores the asynchronous serial data, and the transmitting-side converter converts the asynchronous serial data into the synchronous data for each communication path. Is inserted and converted, and the receiving-side converter refers to the identification code for each communication path in each of the synchronous data, demultiplexes and restores the asynchronous serial data, and the synchronous data the identification codes of the communication channel every time it is inserted into each of the synchronization data itself, characterized in that an identification code of a communication channel to be transmitted (claim 1 Symbol Of the invention).

  According to the present invention, in the transmission-side converter, when the asynchronous serial data is multiplexed and converted into a plurality of synchronous data, an identification code for each communication path is inserted into each synchronous data for conversion. The receiving-side converter side can restore asynchronous serial data in the correct order by demultiplexing with reference to the identification code in each synchronous data. That is, even if the cable is erroneously connected to the cross at any location, the asynchronous serial data can be restored to the normal order on the receiving side.

For example, the asynchronous serial data is Ethernet (registered trademark) data, and the synchronous data divides the Ethernet (registered trademark) data into time slots of predetermined bits, and the time slot includes a plurality of frames. When the synchronization data is configured, the identification code can be inserted into at least one time slot in the frame (the invention according to claim 2 ).

In this case, when the demultiplexer starts demultiplexing, when it detects the same number of identification codes equal to or greater than a threshold in a predetermined number of frames, it identifies the communication path and starts demultiplexing. By doing so, even if the number of time slots into which the identification code is inserted is equal to or less than (predetermined number−threshold), the data can be stochastically correct . Invention) .
In addition, the receiving-side converter specifies a communication channel through which the plurality of synchronization data has been transmitted based on the number of received identification codes, and receives only the synchronization data of the corresponding communication channel. And a sequence restoration means for restoring the plurality of synchronization data output by the reception channel selection circuit to the order transmitted by the transmitter converter (the invention according to claim 4). . Here, the order restoration means may be, for example, a logical sum circuit connected to the reception channel selection circuit (the invention according to claim 5).

  According to the present invention, even when there is a cable cross connection in a plurality of synchronization data communication paths, the data can be correctly restored to the original order on the receiving side while maintaining the cross connection. Can do.

  As a result, the reproduced asynchronous serial data can be restored to the normal order.

  In practice, even in a transmission / reception system in which data is transmitted from a transmission device to a reception device via a plurality of relay devices, each synchronization data is monitored by each device, so that the communication path is a cross ( It is easy to confirm whether it is in the “teleko” state or connected normally.

  That is, the correct communication path can be easily confirmed from the synchronization data. As a result, for example, at the time of starting up or changing the data transmission / reception system, or at the time of failure recovery, it is possible to shorten the time for confirming the correct communication path, thereby shortening the construction period.

  In addition, when a failure occurs and the line is disconnected, monitoring the synchronization data makes it possible to easily detect which communication channel has the failure. As a result, the line disconnection time can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of a microwave multiplex radio system (data transmission / reception system) 30 in which IP converters (also referred to as media converters) 32 and 34 according to this embodiment are incorporated in an A station 42 and a B station 44, respectively. The figure is shown.

  This microwave multiplex radio system 30 relays the radio devices 14 and 16 of the relay station 6 between the radio device 10 of the A station 42 and the radio device 18 of the B station 44, for example, 6.12 [Mbps] × 4. = 25.248 [Mbps] Information is configured to have a fixed-band communication path (spatial communication path) 100 (100A, 100B) capable of bidirectional communication with microwave-multiplexed radio.

  In other words, the microwave multiplex radio system 30 is a communication system that uses a full-duplex fixed-band communication path 100 composed of four sequences (CH1 to CH4) whose transmission band is 6.31 [Mbps] in both uplink and downlink.

  Note that 6.31 [Mbps] is an example, and instead of this, 1.544 [Mbps], 32.064 [Mbps], 97.728 [Mbps], 2.048 [Mbps], and 8.448 [Mbps], 34.368 [Mbps], 51.840 [Mbps], 155.520 [Mbps], and the like.

  Here, as shown in FIG. 2, the wireless fixed-band communication path 100 capable of bidirectional communication replaces the wireless devices 10, 14, 16, and 18 with multiplexing devices 10M, 14M, 16M, and 18M. A wired multiplex transmission system 30M using a metallic cable (or optical fiber cable) 100M that is a wired communication path can be substituted.

  In FIG. 1, a plurality of terminals 46 such as personal computers having a unique IP address and MAC (Media Access Control) address are connected to the IP converter 32 of the A station 42 through an L3SW (layer 3 switch) 50. Similarly, a terminal 48 is connected to the IP converter 34 of the B station 44 through the L3SW 52. In addition to the terminals 46 and 48, other terminals can be connected to the L3SWs 50 and 52 through a LAN (Local Area Network) (not shown). The L3SW is a switch that performs routing processing at high speed in the network layer (layer 3). However, the L3SW can be replaced with a network device such as an L2SW or a router.

  The terminal 46 and the L3SW 50, the L3SW 50 and the IP converter 32, the terminal 48 and the L3SW 52, and the L3SW 50 and the IP converter 32 are connected through a 100BASE-TX LAN cable, respectively. .

  The IP converters 32 and 34 transmit and receive 100BASE-TX data that is asynchronous serial data to and from the L3SWs 50 and 52, respectively. On the other hand, baseband data that is synchronous serial data between the wireless devices 10 and 18, respectively. BB1 to BB4 are transmitted and received. The band of each baseband data BB1 to BB4 is selected to be the same band as the band of each communication path constituting the fixed band communication path 100, in this embodiment, 6.312 [MHz].

  The radio apparatuses 10, 14, 16, and 18 include a signal processing unit (not shown), a transmission modulation unit, a reception demodulation unit, a transmission / reception switching unit, and transmission / reception antennas 61 to 64. The radio apparatuses 10, 14, 16, and 18 respectively digitally modulate the baseband data BB1 to BB4 to convert them into IF signals, and further convert them into microwave RF signals in the 6.5 [GHz] band. The received radio wave is converted into an IF signal, digitally demodulated, and demodulated into baseband data BB1 to BB4.

  In this embodiment, the cables CB1 and CB2 are correct among the cables CB1 to CB4 connecting the communication ports CH1 to CH4 of the wireless device 14 constituting the relay station 6 and the communication ports CH1 to CH4 of the wireless device 16. Although the connection is made, it is assumed that the cables CB3 and CB4 are connected by a cross.

  It is assumed that there is no cross (teleco) connection between the wireless device 10 and the IP converter 32 and between the wireless device 18 and the IP converter 34, and a correct connection is made. Even if there is a connection, in the microwave multiplex radio system 30 and the wired multiplex transmission system 30M of this embodiment, the data processing in the IP converters 32 and 34 is devised. The 100BASE-TX data supplied to the machine 32 can be restored in the correct order by the IP converter 34 of the B station 44. Of course, the 100BASE-TX data supplied from the L3SW 52 to the IP converter 34 in the B station 44 can be restored in the correct order by the IP converter 32 of the A station 42.

  FIG. 3 shows the configuration of the IP converters 32 and 34 in FIG. The configuration of the IP converters 32 and 33 is the same.

  The IP converters 32 and 34 have a LAN interface 72. The LAN interface 72 has a PHY (Physical Media Interface) unit, a GMI unit, and a MAC processing unit as viewed from the L3SW 50 side. 100BASE-TX serial data {LAN data that is asynchronous serial data and Ethernet (registered trademark) data} input to the PHY unit via L3SWs 50 and 52, and then converted into 8-bit parallel data and a transmission buffer On the other hand, the parallel data supplied from the reception buffer 76 is converted into serial data and supplied to the L3SWs 50 and 52. Needless to say, the LAN data can be applied to LAN data such as 10BASE-T or 1000BASE-T in addition to 100BASE-TX LAN data.

  As described above, one end of the IP converter 32 of the A station 42 is connected to the terminal 46 via the LAN interface 72 and the L3SW 50, and the other end of the IP converter 32 includes all four lines of the transmission band 6.312 [Mbps]. It is connected to communication ports CH1s to CH4s on the transmission side and communication ports CH1r to CH4r on the reception side of the wireless device 10 connected to the double fixed band communication path 100A.

  On the other hand, the IP converter 34 of the station B 44 has one end connected to the terminal 48 via the LAN interface 72 and the L3SW 52, and the other end is a full-duplex composed of four lines of the transmission band 6.31 [Mbps]. The wireless device 18 connected to the fixed band communication path 100B is connected to the communication ports CH1s to CH4s on the transmission side and the communication ports CH1r to CH4r on the reception side.

  The IP converters 32 and 34 multiplex the asynchronous serial data supplied from the terminals 46 and 48, and basebands that are the number of synchronization data (four in this embodiment) corresponding to each fixed-band communication path. The data is converted into data BB1 to BB4 and transmitted to the wireless devices 10 and 34, and the baseband data BB1 to BB4 supplied from the wireless devices 10 and 34 is demultiplexed and restored to asynchronous serial data, thereby the terminal 46, 48.

  In this embodiment, the synchronization data output from the IP converter 32 of the A station 42 to the communication ports CH1s to CH4s of the wireless device 10 correspond to the baseband data BB1 to BB4, respectively. The synchronization data output from the communication ports CH1r to CH4r of the wireless device 18 to the converter 34 is based on the fact that the cables CB3 and CB4 are crossed at the relay station 6, and the baseband data BB1, BB2, The order is different from BB3 and BB4.

  Hereinafter, in this specification, the transmission-side component drawn on the upper side of FIG. 3 is a component of the IP converter 32, and the reception-side component drawn on the lower side of FIG. 34 will be described as constituent elements.

  Even when the cables CB3 and CB4 are crossed between the input and output terminals of the wireless device 14, the data is processed by the IP converter 34 (32) on the receiving side from the LAN interface 72 to the L3SW 52 (50). In order to be able to restore the supplied asynchronous serial data to a normal order, a communication path automatic selection circuit 80 is provided in the IP converter 34 (32).

  In the following description, it is assumed that data is transmitted from the A station 42 side to the B station 44 side.

  FIG. 4 shows the configuration of the communication path automatic selection circuit 80. The communication channel automatic selection circuit 80 is supplied with baseband data BB1, BB2, BB4, BB3 output from the communication ports CH1r to CH4r of the wireless device 18, and receives channel selection circuits 81 to 84 for selecting a reception channel. The input side is connected to the four lines from all the reception channel selection circuits 81 to 84, respectively, and the 4-input OR circuits 85 to 88 output the OR data (baseband data) BB1 to BB4 from the output side. The timing control information selection circuit 90 is configured to serially convert the logical sum data BB1 to BB4 and supply the logical sum data BB1 to BB4 to the port selector 89.

  FIG. 5 shows a configuration example of a communication frame (wireless communication frame) 200 that is multiplexed data communicated through each communication channel of the fixed-band communication channel 100A. The content / configuration of the communication frame 200 is basically the same content / configuration as the baseband data BB except that it is modulated to a high frequency.

  The communication frame 200 has a multi-frame MF configuration including four frames F1 to F4, and is repeatedly transmitted and received in units of the multi-frame MF. One frame is composed of 789-bit data each consisting of 98 time slots TS of 8 bits D0 to D7 and 5-bit frame information EF of D0 to D4. Since the time of one frame is 125 [μs], the transmission band is 789 [bit] / 125 [μs] = 6.312 [Mbps]. The time of one multiframe MF is a time 0.5 (= 0.125 × 4) [ms] that is four times the time of one frame.

  The frame timing generator 96 in FIG. 3 generates a timing signal such as a clock CLK (T: T represents transmission), a frame timing FTM (T) for each frame, and a frame timing MFTM (T) for each multiframe MF. Is generated and supplied to the transmission processing units 91 to 94 and the memory read control circuit 95.

  The memory read control circuit 95 supplies the read buffer RD1 to the transmission buffer 74 in accordance with the band allocation data (communication channel allocation data) AL from the setting input unit 97 and the band allocation setting unit 98 and the timing signal. The port select signal PSS1 is supplied to the control terminal of the port selector 102.

  In FIG. 5, in the time slot TS, asynchronous serial data from the L3SW 50 (52) is inserted into the time slots TS1 to TS96 as multiplexed data via the LAN interface 72, the transmission buffer 74, and the port selector 102. In the remaining time slots TS97 and TS98, communication channel automatic selection control information for performing automatic channel selection control based on the allocation setting information AL from the band allocation setting unit 98 is inserted. Further, frame information EF including a game alert signal (S), CRC check information, and frame synchronization information is inserted at the end of each frame.

Each bit D0~D7 time slots TS97, TS98, illustrating by way of example in FIG. 6, bit D0~D7 corresponds to the communication port CHl to CH 8 respectively. A time slot TS97 indicates an initial value of communication band allocation information, and a time slot 98 indicates communication band allocation state information (also referred to as used channel information).

  Specifically, the communication path automatic selection control information inserted in the time slots TS97 and TS98 includes a band allocation setting unit according to a setting input from the setting input unit 97 that can manually change the band allocation setting. The allocation setting information AL is supplied from 98 to the transmission processing units 91 to 94.

  Each of the transmission processing units 91 to 94 determines whether the value of the supplied allocation setting information AL is “1: allocation” or “0: no allocation”, and sets the corresponding bit in the corresponding time slot TS97 to the corresponding bit. Set (insert) this value. In this embodiment, as an initial value, a value 1 is set in bits D0 to D3 to be assigned to communication ports CH1 to CH4 corresponding to four communication paths of fixed band communication path 100, and there is no communication path. A value 0 is set in bits D4 to D7 for communication ports CH5 to CH8.

  That is, the states of the bits D0 to D3 of the time slot TS97 output from the transmission processing units 91 to 94 based on the allocation setting information AL are all TS97 = [000011111], and the four communication paths of the fixed band communication paths 100A and 100B. The four communication ports CH1s to CH4s corresponding to are enabled.

  On the other hand, use channel information (identification code for each communication path) is set in the time slot TS98 by the allocation setting information AL. The bits D0 to D7 correspond to the communication ports CH1 to CH8, and are set to “1: allocation in use” and “0: allocation not in use”. Only the corresponding bit positions are used in each communication port CH1 to CH4.

  That is, the time slots TS98 output from the transmission processing units 91 to 94 to the communication ports CH1s to CH4s are TS98 = [00000001] to the communication port CH1s and TS98 = [00000010] to the communication port CH2s. A bit string of TS98 = [00001000] is set to CH3s, and TS98 = [00001000] is set to communication port CH4s.

  FIG. 7 shows the configuration of the frame information EF of each frame F1, F2, F3, and F4 constituting the multiframe MF.

  In the frame information EF, “D” inserted into the data D0 of the frames F1 and F3 is a data link bit, and “S” inserted into the data D1 of the frame F3 is a game alarm bit {S = 1 ( Alarm time), S = 0 (normal)}, “C” inserted in the frame F3 is a CRC check bit, “1” and “0” inserted in the frames F1 and F2 are synchronization bits [110010100], “1” inserted in the frame F3 is fixed to 1 with an empty bit.

  The communication path automatic selection circuit 80 includes baseband data BB1 and BB2 including a control information separation circuit (not shown) for separating control information such as a synchronization separation circuit (not shown) and an identification code (used channel information) for each communication path. , BB3, BB4, the clock CLK (R: R represents transmission), and the timing signal such as the frame timing FTM (R) for each frame and the frame timing MFTM (R) for each multi-frame MF, The used channel information is read and supplied to the memory write control circuit 99.

  At this time, the memory write control circuit 99 supplies the port select signal PSR1 to the control terminal of the port selector 89 and supplies the write timing WR1 to the reception buffer 76 in accordance with the timing signal.

  Next, the operation of the microwave multiplex radio system 30 basically configured as described above will be described.

  For example, 100BASE-TX asynchronous serial data supplied from the terminal 46 of the station A 42 through the L3SW 50 is converted into parallel data via the LAN interface 72 and temporarily stored in the transmission buffer 74.

  The parallel data stored in the transmission buffer 74 is read 8 bits at a time according to the read timing RD1 from the memory read control circuit 95, and the read 8-bit parallel data is the port select signal from the memory read control circuit 95. Based on the PSS 1, the data is once latched for multiplexing in the port selector 102, and the multiplexed latch data is supplied to the transmission processing units 91 to 94 that are multiplexing units (MUX) via the port selector 102. The output side port of the port selector 102 is sequentially switched by the port select signal PSS1 from the memory read control circuit 95.

  At this time, each of the transmission processing units 91 to 94 performs processing based on the flowchart shown in FIG. 8 based on the setting allocation information AL.

  That is, in step S1, it is determined whether or not it is assigned as a communication path. If it is assigned, the corresponding bits of the time slots TS97 and TSP8 are set to the value 1 in step S2, and if not assigned, the corresponding bits of the time slots TS97 and TS98 are set to the value 0 in step S3 and output to the radio apparatus 10. To do.

  The transmission processing units 91 to 94 convert the parallel data into serial data by using the parallel (serial to serial) conversion function using the clock CLK, and further, the communication path automatic selection control information (see FIG. 6) in the corresponding bits of the time slots TS97 and TS98. Baseband data BB1 to BB4, which are multiframe MF data (transmission signal frames) into which the reference is inserted, are output to the communication ports CH1s to CH4s of the wireless device 10.

  In this case, as described above, the bits of the time slots TS97 and TS98 of the baseband data BB1 to BB4 output to the communication ports CH1s to CH4s of the wireless device 10 are CH1s (TS97 = [000011111], TS98 = [ TS97 = [00001111], 00000001]), CH2s (TS97 = [00001111], TS98 = [00000010]), CH3s (TS97 = [00001111, TS98 = [00000100])), CH4s (TS98 = [00001000]). ing.

  These baseband data BB1 to BB4 are modulated into radio waves by the radio apparatus 10, and demodulated by the relay station 6 via the communication path 100A, thereby reproducing the baseband data BB1 to BB4.

  The reproduced baseband data BB1 to BB4 is supplied to the wireless device 16 through the cables CB1 to CB4.

  At this time, since the cables CB3 and CB4 are crossed, the order of the baseband data supplied to the communication ports CH1, CH2, CH3, and CH4 of the wireless device 16 corresponds to the communication ports CH1 to CH4. The baseband data BB1, BB2, BB3, and BB4 are in this order, and the baseband data BB3 and BB4 are switched.

  Therefore, the baseband data retransmitted from the wireless device 16 and output from the communication path 100B and the communication ports CH1 to CH4 of the wireless device 18 are in the order of the baseband data BB1, BB2, BB4, BB3. 34.

  The reception channel selection circuits 81 to 84 of the communication path automatic selection circuit 80 of the IP converter 34 receive the frame timing FTM (R) and multiframe timing MFTM shown in FIG. 5 from the received baseband data B1, B2, B4, B3. (R) and the clock CLK (R) are reproduced and supplied to the timing control information selection circuit 90 and supplied to the memory write control circuit 99 through the timing control information selection circuit 90.

  The reception channel selection circuits 81 to 84 also receive the supplied baseband data BB1, BB2, BB4, BB3 based on the regenerated frame timing FTM (R), multiframe timing MFTM (R), and clock CLK (R). Each bit information of D0 to D3 of the time slot TS98 is confirmed.

  In this case, as shown in FIG. 4, each of the reception channel selection circuits 81 to 84 includes one frame timing FTM counting counter (FTM counter) 401 and eight port number detection counters (port counters). 402).

  Then, as shown in the flowchart of FIG. 9, each of the reception channel selection circuits 81 to 84 clears all the count values of the FTM counter 401 and the port counter 402 in step S11.

  Next, in step S12, when the FTM counter 401 detects one frame timing FTM, the count is incremented by one.

  Next, in step S13, all bits TS98 [D7, D6, D5, D4, D3, D2, D1, D0] = [D in the time slot TS98 during this frame timing FTM (for example, the frame F1 in FIG. 5). *] Is monitored, and when any bit is 1 (TS98 [D *] = 1, step S13: YES), the port counter 402 of the corresponding bit is counted up in step S14. That is, for example, when the bit D0 is D0 = 1, the port counter 402 of the bit D0 is incremented by 1, and when the bit D2 is D2 = 1, the port counter 402 of the bit D2 is incremented by 1. To do.

  In step S13, the bit TS98 [D *] in the time slot TS98 in the frame timing FTM (for example, the frame F1 in FIG. 5) is monitored, and if any bit is 0, in step S16, the FTM counter It is confirmed whether 401 is fully counted up to a predetermined value (1000 times in this embodiment).

  If the full count is not reached, the process returns to step S12, and the next frame timing FTM is counted up by the FTM counter 401.

  Next, in step S13, all the bits TS98 [D *] in the time slot TS98 are monitored during this frame timing FTM (for example, the frame F2 in FIG. 5), and when any bit is 1 (step S13). (S13: YES), in step S14, the corresponding port counter 402 is incremented by one.

  Next, in step S15, it is determined whether or not the count values of the eight port counters 402 are equal to or greater than a threshold value (800 times in this embodiment).

  If the threshold value has not been reached, the process returns to step S16 to determine whether or not the FTM counter 401 is full, and if not, the processes in and after step S12 are performed again.

  On the other hand, if the count value of the port counter 402 of a certain bit is greater than or equal to the threshold value in the determination process of step S15, the port number for which the counter value of the port counter 402 is greater than or equal to the threshold value is true The reception channel selection circuits 81 to 84 that have determined that there is output the baseband data BB1 to BB4 received from any of the corresponding communication ports CH1 to CH4, and the remaining communication ports CH1 to CH4 that are not applicable. Outputs the value 0.

  In this embodiment, since the baseband data BB1, BB2, BB4, and BB3 are supplied to the reception channel selection circuits 81 to 84, respectively, the port counter 402 of the communication port CH1 is set to the threshold value in the reception channel selection circuit 81. As described above, in the reception channel selection circuit 82, the port counter 402 of the communication port CH2 becomes equal to or greater than the threshold value. In the reception channel selection circuit 83, the port counter 402 of the communication port CH4 becomes equal to or greater than the threshold value. The CH3 port counter 402 is equal to or greater than the threshold value.

  Accordingly, the OR circuits 85 to 88 output the OR signals to the timing control information selection circuit 90 in the order of the baseband data BB1, BB2, BB3, and BB4 that are the OR outputs, that is, eliminate the cross.

  Baseband data BB 1, BB 2, BB 3, and BB 4 input to the timing control information selection circuit 90 are serial-parallel converted and written to the reception buffer 76 via the port selector 89.

  Data written to the reception buffer 76 is read by the write timing signal WR 1 and supplied to the LAN interface 72.

  The LAN interface 72 supplies the data read from the reception buffer 76 to the predetermined terminal 48 through the L3SW 52 as LAN data that is asynchronous serial data.

  As described above, according to the embodiment described above, with reference to FIG. 10, in the IP converter 32 on the transmission side, baseband data BB1 that is a plurality of synchronous data by multiplexing 100BASE-TX asynchronous serial data. When converting to BB4, an identification code (bit of TS98) for each communication path is inserted into each baseband data BB1 to BB4 for conversion. The communication path automatic selection circuit 80 of the IP converter 34 on the receiving side refers to the identification codes (bits of TS98) in the baseband data BB1 to BB4, and demultiplexes the asynchronous serial data in the correct order. Can be restored.

  For this reason, even if the cables CB3 and CB4 between the wireless devices 14 and 16 are erroneously connected to the cross (teleco), the receiving side converts the asynchronous serial data as shown in FIG. Can be restored to the normal order of the same data order as shown in FIG.

  In the process of step S16, if all the port counters 402 do not exceed the threshold before the frame timing counter FTM401 reaches 1000, which is the full count value, it is determined that a correct determination cannot be made due to line degradation or the like. To maintain.

  In addition, since the flowcharts in FIGS. 8 and 9 are detection of a change in the hardware connection state of the communication line, as a general rule, it should be performed only at the start of use of the line, at the time of line restoration, or at the time of testing. However, it is possible to always monitor.

  That is, monitoring the communication channel automatic selection control information of the time slots TS97 and TS98 in the baseband data BB1 to BB4 that is the synchronization data generated in the communication ports CH1 to CH4 of the wireless devices 10, 14, 16, and 18. Thus, the cross of the cable can be accurately determined, and the confirmation time of the correct communication path (communication port) when the microwave multiplex radio system 30 is started up, at the time of system change, at the time of failure recovery, etc. As a result, the construction period can be shortened.

1 is a block diagram showing a configuration of a microwave multiplex radio system to which an embodiment of the present invention is applied. It is a block diagram showing a configuration of a wired multiplex transmission system in which a multiplex communication path is replaced with a wired metallic cable. FIG. 3 is a block diagram illustrating a configuration example of an IP converter in the examples of FIGS. 1 and 2. It is a block diagram which shows the structural example of a communication path automatic selection circuit in IP converter. It is explanatory drawing which shows the structural example of the communication frame of the multi-frame format transmitted / received. It is explanatory drawing of the time slot which instruct | indicates communication path allocation. It is explanatory drawing of the frame information containing a game alert bit. It is a flowchart of an allocation process. It is a flowchart of a communication path automatic selection process. It is explanatory drawing which shows the connection state of the microwave multiplex radio system after a communication channel automatic selection process. It is explanatory drawing when the connection state of a microwave multiplex radio system is normal. It is explanatory drawing when the connection state of a microwave multiplex radio system is an incorrect connection state. FIG. 13A is an explanatory diagram of asynchronous serial data, FIG. 13B is an explanatory diagram when asynchronous serial data is converted into synchronous parallel data, and FIG. 13C is an explanatory diagram of an example in which the order of synchronous parallel data is changed due to miswiring. FIG. 13D is an explanatory diagram of asynchronous serial data whose data content is restored by being broken, and FIG. 13E is an explanatory diagram of asynchronous serial data whose data content is correctly restored.

Explanation of symbols

6 ... Relay station 10, 14, 16, 18, 34 ... Wireless device 30 ... Microwave multiplex radio system 30M ... Wired multiplex transmission system 32, 33, 34 ... IP converter (media converter)
42 ... A station 44 ... B station 50, 52 ... L3SW (layer 3 switch)
72 ... LAN interface 80 ... communication path automatic selection circuit 100, 100A, 100B ... fixed band communication path

Claims (5)

A transmission-side converter that multiplexes asynchronous serial data, converts it into a number of synchronous data corresponding to each fixed-band communication path, and transmits it;
A receiving-side converter that demultiplexes the plurality of received synchronization data and restores the asynchronous serial data;
The transmitter converter converts the asynchronous serial data into the synchronous data by inserting an identification code for each communication path into each of the synchronous data,
The receiving-side converter refers to an identification code for each communication path in each synchronous data, demultiplexes it, and restores the asynchronous serial data .
The data transmission / reception system , wherein the identification code for each communication path inserted into each of the synchronization data is an identification code of a communication path through which the synchronization data itself is transmitted . In claim 1 Symbol placement data transmission and reception system,
The asynchronous serial data is Ethernet (registered trademark) data,
When the synchronization data is the synchronization data in which the Ethernet (registered trademark) data is divided into time slots for each predetermined bit and this time slot is composed of a plurality of frames, the identification code is: The data transmission / reception system is inserted into at least one time slot in the frame. The data transmission / reception system according to claim 2 ,
When starting the demultiplexing, the receiving-side converter identifies a communication path and starts demultiplexing when detecting a number of identical identification codes equal to or greater than a threshold in a predetermined number of frames. A featured data transmission / reception system. The data transmission / reception system according to any one of claims 1 to 3,
The receiving-side converter specifies a communication channel on which the plurality of synchronization data has been transmitted based on the number of received identification codes, and a reception channel selection circuit that outputs only the synchronization data of the corresponding communication channel; And a sequence restoration means for restoring the plurality of synchronization data output by the reception channel selection circuit to the sequence transmitted by the transmitter converter.
A data transmission / reception system characterized by the above. The data transmission / reception system according to claim 4,
The order restoring means is an OR circuit connected to the reception channel selection circuit.
A data transmission / reception system characterized by the above.