JP3845889B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to improvement of a redundant circuit for relieving a defective portion.
[0002]
[Prior art]
Conventionally, in a semiconductor nonvolatile memory device such as an EPROM or a flash memory, when a small number of defective bits (memory transistors) exist in a memory chip, the memory chip is generally repaired in units of bit lines. It is.
That is, the defective chip is relieved by replacing the defective bit line in which the defective memory transistor exists with the redundant bit line.
[0003]
However, a semiconductor nonvolatile memory device having a structure in which a plurality of sub bit lines are connected to the main bit line (for example, DINOR type and AND type) or a semiconductor nonvolatile memory device having a structure in which a plurality of NAND strings are connected to the bit line (for example, In the NAND type), the conventional method of performing redundancy in units of bit lines is not efficient, and a more efficient redundancy method is possible.
[0004]
FIGS. 4A, 4B, and 4C are diagrams showing memory array structures in DINOR type, NAND type, and AND type flash memories, respectively.
[0005]
The DINOR type flash memory of FIG. 4A is a diagram showing a memory array when four memory transistors are connected to one sub bit line connected to one main bit line for convenience.
In FIG. 4A, MBL is a main bit line, SBL is a sub bit line, and the main bit line MBL and the sub bit line SBL are select transistors ST controlled by a select gate line SL. ₁ Are operatively connected via
The sub bit line SBL has four word lines WL. ₁ ~ WL _Four And four memory transistors MT at each intersection ₁ ~ MT _Four Is arranged.
[0006]
The NAND flash memory of FIG. 4B is a diagram showing a memory array when four memory transistors are connected to one NAND type connected to one bit line for convenience.
In FIG. 4B, BL is a bit line, and two select transistors ST are connected to the bit line BL. ₁ , ST ₂ And four memory transistors MT ₁ ~ MT _Four Are connected in series.
Select transistor ST ₁ , ST ₂ Is the select gate line SL ₁ , SL ₂ Controlled by the memory transistor MT ₁ ~ MT _Four Is the word line WL ₁ ~ WL _Four Controlled by
[0007]
The AND type flash memory of FIG. 4C is a diagram showing a memory array when four memory transistors are connected to one sub bit line connected to one main bit line for convenience.
In FIG. 4C, MBL is a main bit line, SBL is a sub bit line, SSL is a sub source line, and the main bit line MBL and the sub bit line SBL are select gate lines SL. ₁ Select transistor ST controlled by ₁ And the sub-source line SSL is connected to the select gate line SL. ₂ Select transistor ST controlled by ₂ Is operatively connected to the ground potential VSS.
Four memory transistors MT sandwiched between the sub-bit line SBL and the sub-source line SSL ₁ ~ MT _Four Are arranged on the respective word lines WL. ₁ ~ WL _Four Controlled by
[0008]
As shown in FIG. 4, a semiconductor nonvolatile memory device having a structure in which a plurality of sub bit lines are connected to the main bit line (for example, DINOR type and AND type), or a semiconductor nonvolatile memory having a structure in which a plurality of NAND columns are connected to the bit lines. In a volatile memory device (for example, NAND type), a conventional method of performing redundancy in units of bit lines (main bit lines) is not efficient.
[0009]
FIG. 5 is a diagram for explaining an example of redundancy efficiency when redundancy is performed in units of main bit lines in the conventional semiconductor nonvolatile memory device having a DINOR type structure, for example.
[0010]
In FIG. 5, reference numeral 1 denotes a memory array, which includes a normal memory array 1a and a redundant memory array 1b.
In FIG. 5, for the sake of convenience, the regular memory array 1a includes three regular main bit lines B. ₁ ~ B _Three However, the redundant memory array 1b has two redundant main bit lines b. ₁ ~ B ₂ An example in which is wired is shown.
Each regular main bit line B ₁ ~ B _Three , And redundant main bit line b ₁ ~ B ₂ Are each connected to three sub-bit lines, and each sub-bit line is composed of a memory column (hereinafter referred to as “□”) and four memory transistors (“〇” in the figure). Sub-bit line block) is connected.
That is, the normal memory array 1a has the normal subbit line block S. ₁₁ ~ S ₃₃ The redundant memory array 1b includes a redundant sub bit line block s. ₁₁ ~ S _{twenty two} Consists of
SL ₁ ~ SL _Three Is a selection gate line for controlling the selection transistor, WL ₁₁ ~ WL ₃₄ Is a word line for controlling the memory transistor.
[0011]
In the example of FIG. 5, the normal subbit line block S ₁₂ , S ₃₂ , S _{twenty three} There is a defect in one of the memory transistors (● in the figure).
In this case, two regular main bit lines B ₂ , B _Three Becomes a defective main bit line, and the defective main bit line is designated as a redundant main bit line b. ₁ , B ₂ Relieve by replacing with.
[0012]
[Problems to be solved by the invention]
By the way, when performing redundancy in units of conventional main bit lines, there are the following problems.
[0013]
For example, in the example of FIG. 5, the defective main bit line B ₂ Is a normal subbit line block connected to S ₁₂ , S ₃₂ Is bad but S _{twenty two} Is normal.
Also, the defective main bit line B _Three Is a normal subbit line block connected to S _{twenty three} Is bad but S ₁₃ , S ₃₃ Is normal.
[0014]
In other words, by performing redundancy in units of main bit lines, even sub-bit line blocks that are normally normal are replaced. As a result, redundancy efficiency deteriorates, and in particular, in a memory chip with many defective memory transistors, redundancy is performed. The deterioration of efficiency becomes remarkable.
[0015]
The present invention has been made in view of such circumstances, and an object thereof is to provide a semiconductor nonvolatile memory device capable of performing efficient redundancy.
[0016]
[Means for Solving the Problems]
To achieve the above object, the present invention has a bit line hierarchical structure in which a main bit line is divided into a plurality of sub bit lines, and memory transistors arranged in a matrix form are connected to the sub bit lines and the word lines. A semiconductor memory device, wherein at least one redundant main bit line selectively connected to a plurality of redundant subbit lines and a defective subbit in which a memory transistor connected to the subbit line has a defect In the case of a line, there is a repair means for replacing the defective sub-bit line with the redundant sub-bit line in the direction in which the same word line extends.
[0017]
In the semiconductor memory device, the relief means selects a defective address recording means for recording an address of a defective subbit line in which a defective memory transistor exists, and a defective subbit line having the same address as the defective address. When the defective main bit line to which the defective sub-bit line is connected is replaced with the redundant main bit line and a sub-bit line having a different address from the defective address connected to the defective main bit line is selected. And a selective main bit line replacement means which does not replace the defective main bit line.
[0018]
According to another aspect of the present invention, there is provided a semiconductor memory device in which a plurality of NAND columns having a NAND structure are connected to bit lines wired in columns, and memory transistors arranged in a matrix are connected to the NAND columns and word lines. And at least one redundant bit line to which a plurality of redundant NAND strings are connected, and a defective NAND string in which a memory transistor connected to the NAND string is defective. Yes, when selecting a non-column NAND string having the same address as the defective address, the defective bit line connected to the defective NAND string is replaced with the redundant bit, and the replacement information and the column selection signal are used. And repairing means for replacing the defective NAND column with the redundant NAND column in the direction in which the same word line extends.
[0019]
In the semiconductor memory device, the relief means selects a defective address recording means for recording an address of a defective NAND string in which a defective memory transistor exists, and a defective NAND string having the same address as the defective address. When a defective bit line connected to a defective NAND string is replaced with the redundant bit line, and a NAND string of another address different from the defective address connected to the defective bit line is selected, the defective bit line is replaced. And selective bit line replacement means that does not perform.
[0020]
Further, each of the defective address recording means in the semiconductor memory device of the present invention is constituted by a nonvolatile memory element.
In addition, the memory array unit and the defective address recording unit are individually integrated.
Further, the recording of the defective address is performed during a shipping test.
Furthermore, the semiconductor memory device can be rewritten repeatedly, and the defective address is recorded every repeated rewrite.
[0021]
According to the semiconductor memory device of the present invention, a memory chip in which a defective memory transistor is present is relieved not in units of main bit lines but in units of sub bit lines. Therefore, an apparatus with high redundancy efficiency can be realized.
[0022]
Specifically, the defective main bit line is replaced by the selective main bit line replacement means only when the address of the defective sub bit line is recorded in the defective address recording means and the defective sub bit line of the same address of the defective address is selected. Replaced with redundant main bit line.
[0023]
In addition, according to the semiconductor memory device of the present invention, a memory chip having a defective memory transistor is relieved not in units of bit lines but in units of NAND columns. Therefore, an apparatus with high redundancy efficiency can be realized.
[0024]
Specifically, the defective main bit line replacement unit replaces the defective bit line with the redundant bit line only when the defective NAND column address is recorded in the defective address recording unit and a defective NAND column having the same address as the defective address is selected. Is replaced by
[0025]
The defective address can be recorded by recording in a register constituted by a non-volatile memory element or another semiconductor memory device separately integrated other than the semiconductor memory device according to the present invention.
[0026]
Further, by recording a defective address in a shipping test of the semiconductor nonvolatile memory device, it is possible to relieve the defective chip when the memory chip is shipped.
[0027]
Further, in a flash memory or the like that can be repeatedly rewritten, it is possible to relieve a defect at each repeated rewrite by recording a defective address for each repeated rewrite.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a first embodiment of a semiconductor nonvolatile memory device according to the present invention, for example, a DINOR type flash memory in which a main bit line is connected to a plurality of sub bit lines via connection means.
[0029]
In FIG. 1, reference numeral 1 denotes a memory array, which includes a normal memory array 1a and a redundant memory array 1b.
The normal memory array 1a has m normal main bit lines B. ₁ ~ B _m However, the redundant memory array 1b includes k redundant main bit lines b. ₁ ~ B _k Are wired.
Each regular main bit line B ₁ ~ B _m , And redundant main bit line b ₁ ~ B _k Are each connected to n sub-bit lines, and each sub-bit line is composed of a memory string (hereinafter referred to as “j”) and one select transistor (□ in the figure) and j memory transistors (〇 in the figure). Sub-bit line block) is connected.
That is, the normal memory array 1a has the normal subbit line block S. ₁₁ ~ S _nm The redundant memory array 1b includes a redundant sub bit line block s. ₁₁ ~ S _nk It is composed of
SL ₁ ~ SL _n Is a selection gate line for controlling the selection transistor, WL ₁₁ ~ WL _nj Is a word line for controlling the memory transistor.
[0030]
2 is a main row decoder, the upper X of the X input ₁ ~ X _a Is decoded and the selection gate line SL is decoded. ₁ ~ SL _n Output voltage and sub-bit line block selection signal x ₁ ~ X _n Is generated.
3 is a sub-row decoder, the lower X of the X input ₁ ~ X _b And the word line voltage V in the selected sub-bit line block ₁ ~ V _j Is generated.
4 is a local decoder, and each word line WL ₁₁ ~ WL _nj Transfer circuit T corresponding to ₁₁ ~ T _nj Sub-bit line block selection signal x ₁ ~ X _n Is selected in block units.
Each transmission circuit T ₁₁ ~ T _nj These transmission circuits T ₁₁ ~ T _nj Is selected by the sub-bit line block selection signal, the word line voltage V ₁ ~ V _j To the corresponding word line, and the transmission circuit T ₁₁ ~ T _nj Is not selected by the sub bit line block selection signal, an appropriate voltage value (for example, ground voltage GND) corresponding to the operation is output to the corresponding word line.
[0031]
5 is a column decoder, Y input Y ₁ ~ Y _c Is decoded and the normal main bit line B is decoded. ₁ ~ B _m Normal column selection signal R corresponding to ₁ ~ R _m Is generated.
Reference numeral 6 denotes a column selector, which includes a normal column selector 6a and a redundant column selector 6b.
The normal column selection unit 6a includes m normal main bit lines B. ₁ ~ B _m Select one of these. The redundant column selection unit 1b includes k redundant main bit lines b. ₁ ~ B _k Select one of these.
[0032]
Reference numeral 7 denotes a defective address recording unit, which is a set of registers composed of nonvolatile storage elements, and includes a normal subbit line block S. ₁₁ ~ S _nm The address of the block where the defective bit (memory transistor) exists is recorded.
The address of the defective sub-bit line block is recorded for each address in the word line direction, and k Y (bit line) addresses are provided for each of i (i ≦ n) X (word line direction) addresses. To be recorded.
That is, the address of the defective subbit line block is recorded in the register corresponding to the redundant subbit line block in the direction in which the same word line extends.
In the figure, X _ar-1 ~ X _ar-i Indicates the defective X address register, Y _ar-11 ~ Y _ar-ik Indicates the defective Y address register.
[0033]
Reference numeral 7a denotes a write circuit which stores an X (word line direction) address X in the defective address recording unit 7. _ar , And Y (bit line) address Y _ar Is recorded as a defective address.
8 ₁ ~ 8 _i Are X address coincidence determination circuits, each of i defective X address registers X _ar-1 ~ X _ar-i , And the recorded defective X address is the currently selected X address X. _ar , The defective Y address read signal φ ₁ ~ Φ _i Is output.
Defective Y address read signal φ ₁ ~ Φ _i Is output, the corresponding defective Y address register Y _ar-11 ~ Y _ar-ik Is checked and the defect Y address is recorded, the defect Y address is output.
[0034]
9 ₁ ~ 9 _k Are Y address coincidence determination circuits each of k defective Y address registers Y _ar-1 ~ Y _ar-i A defective Y address is recorded in a register provided corresponding to X, and the currently selected X address Y _ar Redundant column selection signal r ₁ ~ R _k Is output.
[0035]
NOR1 is a k-input NOR circuit, and each input terminal has a Y-address match determination circuit 9 ₁ ~ 9 _k K redundant column selection signals r respectively connected to the output terminals of ₁ ~ R _k Take the negative conjunction of.
AND1 to ANDm are two-input AND circuits, and one of the input terminals is a normal column selection signal R of the column decoder 5. ₁ ~ R _m The other input terminal is connected in common to the output terminal of the NOR circuit NOR1, and takes the logical product of both signals.
[0036]
Next, the operation according to the above configuration will be described.
Upper X of row address X input ₁ ~ X _a Is input to the main row decoder 2 and decoded, and the main row decoder 2 selects the select gate line SL. ₁ ~ SL _n Output voltage and sub-bit line block selection signal x ₁ ~ X _n The output voltage is supplied to a predetermined selection gate line, and the sub bit line block selection signal x ₁ ~ X _n Is output to the local decoder 4.
The lower X of the row address X input ₁ ~ X _b Is input to the sub-row decoder 3 and decoded, and the word line voltage V in the selected sub-bit line block is ₁ ~ V _j Is generated.
In the local decoder 4, each word line WL ₁₁ ~ WL _nj Transfer circuit T corresponding to ₁₁ ~ T _nj Is the sub-bit line block selection signal x ₁ ~ X _n Is selected in block units. Then, the word line voltage V is passed through the selected transmission circuit. ₁ ~ V _j Is output to the corresponding word line.
On the other hand, the transmission circuit T ₁₁ ~ T _nj Is not selected by the sub bit line block selection signal, for example, ground voltage GND is output to the corresponding word line.
[0037]
In the column decoder 5, the column address Y input Y ₁ ~ Y _c Is decoded and the normal main bit line B ₁ ~ B _m Normal column selection signal R corresponding to ₁ ~ R _m AND circuit AND AND ₁ ~ AND _m Is output.
[0038]
Here, the normal sub-bit line block S ₁₁ ~ S _nm When a defective bit (memory transistor) exists, the write circuit 7a causes the defective address recording unit 7 to store the X (word line direction) address X. _ar , And Y (bit line) address Y _ar Is recorded as a defective address.
Then, the recorded defective X address is changed to the currently selected X address X. _ar X address match determination circuit 8 ₁ ~ 8 _i Defective Y address read signal φ ₁ ~ Φ _i Is output.
Defective Y address read signal φ ₁ ~ Φ _i Is output, the corresponding defective Y address register Y _ar-11 ~ Y _ar-ik Is checked and a defective Y address is recorded, the defective Y address is converted into a Y address match determination circuit 9. ₁ ~ 9 _k And the defective address is recorded in the corresponding register.
[0039]
Y address match determination circuit 9 ₁ ~ 9 _k Then, the defective Y address recorded in the register is the currently selected Y address Y. _ar Redundant column selection signal r ₁ ~ R _k Is output at a high level, and if they do not match, it is output at a low level.
Redundant column selection signal r ₁ ~ R _k Is input to the NOR circuit NOR1, and the redundant column selection signal r ₁ ~ R _k When either one of them is at the high level, the output of the NOR circuit NOR1 becomes the low level, and the redundant column selection signal r ₁ ~ R _k Are all at a low level, the output of the NOR circuit NOR1 is at a high level.
[0040]
When the output of the NOR circuit NOR1 is low level, the AND circuit AND ₁ ~ AND _m Is deactivated and output as a normal column selection signal R ₁ '~ R _m 'Is all low level.
That is, the defective main bit line to which the selected defective sub-bit line block is connected is disconnected and replaced with a redundant main bit line.
When the output of the NOR circuit NOR1 is at a high level, the AND circuit AND ₁ ~ AND _m Is activated and output as a normal column selection signal R ₁ '~ R _m The regular main bit line is selected by '.
[0041]
FIG. 2 is a diagram for explaining an example of redundancy efficiency in the semiconductor nonvolatile memory device according to the present invention shown in FIG.
[0042]
The configuration of the memory array and the number and arrangement of defective memory transistors in the example of FIG. 2 are exactly the same as those in the example of the conventional redundancy efficiency shown in FIG.
That is, also in the example of FIG. 2, the normal subbit line block S ₁₂ , S ₃₂ , S _{twenty three} There is a defect in one of the memory transistors (● in the figure).
In this case, two regular main bit lines B ₂ , B _Three Becomes a defective main bit line, but the defective main bit line is replaced with one redundant main bit line b. ₁ The defect can be remedied by replacing with.
[0043]
This is because, as shown in FIG. 5, in the case where redundancy is performed in units of conventional main bit lines, two defective main bit lines B ₂ , B _Three 2 redundant main bit lines b ₁ , B ₂ Compared with the replacement, the redundancy efficiency is greatly improved.
[0044]
FIG. 3 is a diagram showing a second embodiment of a semiconductor nonvolatile memory device according to the present invention, for example, a DINOR type flash memory in which a main bit line is operatively connected to a plurality of sub bit lines via connection means. It is.
[0045]
The embodiment of FIG. 3 differs from the embodiment of FIG. 1 in that the recording of defective addresses is not a register constituted by a nonvolatile memory element, but is separately integrated other than the semiconductor nonvolatile memory device according to the present invention. It is in the point which is performed to the other semiconductor non-volatile memory device.
[0046]
By recording a defective address in another semiconductor nonvolatile memory device other than the semiconductor nonvolatile memory device according to the present embodiment, even when a large number of defective memory transistors exist in the memory array, the defective sub-bit line Recording of block addresses is easy, which is preferable.
That is, even when a large number of defective addresses need to be recorded, there is an advantage that the area occupied by the defective address recording portion can be reduced.
[0047]
In FIG. 3, reference numeral 10 denotes a memory array of another semiconductor nonvolatile memory device for recording a defective address.
The memory array 10 includes n word lines w wired corresponding to n word line blocks. ₁ ~ W _n And (k · c) bit lines b wired corresponding to k redundant main bit lines and c Y inputs. ₁₁ ~ B _kc Thus, a memory array is configured. In addition, electrically programmable memory cells (（in the figure), for example, an EEPROM or the like are arranged at each lattice position of each word line and bit line.
Each memory cell constitutes a memory column (hereinafter referred to as a Y address column) composed of c memory cells in correspondence with c Y inputs.
That is, the memory array 10 has a Y address string s. ₁₁ ~ S _nk Consists of
Therefore, the address of the defective sub-bit line block is recorded for each address in the word line direction, and k Y (bit line) addresses are recorded for each of the n X (word line direction) addresses. .
That is, the address of the defective sub-bit line block is recorded in the Y address column corresponding to the redundant sub-bit line block in the direction in which the same word line extends.
[0048]
10a is a row decoder A, and the upper X of the X input ₁ ~ X _a Decode the wort line w ₁ ~ W _n In addition, an appropriate voltage value corresponding to the operation is output.
10b is a column decoder A, Y input Y ₁ ~ Y _d To generate a signal for selecting the k Y (bit line) addresses.
10c is a column selection unit, and the currently selected X address X _ar , And Y address Y _ar In addition to the function of the write circuit for recording the selected address represented by (2) as a defective address in the memory array 10, the redundant column selection is performed when a defective address matching the selected address is recorded in the memory array. Signal r ₁ ~ R _k Is output at a high level.
[0049]
The redundant column selection signal r ₁ ~ R _k Is input to the NOR circuit NOR1, and the redundant column selection signal r ₁ ~ R _k When either one of them is at the high level, the output of the NOR circuit NOR1 is set to the low level, and the redundant column selection signal r ₁ ~ R _k Are all at a low level, the output of the NOR circuit NOR1 is set to a high level.
When the output of the NOR circuit NOR1 is low level, the AND circuit AND ₁ ~ AND _m Is deactivated and output as a normal column selection signal R ₁ '~ R _m 'Is all low level.
That is, the defective main bit line to which the selected defective sub-bit line block is connected is disconnected and replaced with a redundant main bit line.
When the output of the NOR circuit NOR1 is at a high level, the AND circuit AND ₁ ~ AND _m Is activated and output as a normal column selection signal R ₁ '~ R _m The regular main bit line is selected by '.
[0050]
As described above, according to the present embodiment, a defective memory transistor exists in a semiconductor nonvolatile memory device (for example, a DINOR type flash memory) having a structure in which a plurality of sub bit lines are connected to a main bit line. It is possible to perform redundancy with high redundancy efficiency by performing redundancy for the memory chip in units of sub-bit lines rather than in units of main bit lines.
[0051]
In the present embodiment, the DINOR type flash memory or the like is specifically described as an example. However, the present invention is not limited to a semiconductor nonvolatile memory device having a structure in which a plurality of NAND columns are connected to a bit line (for example, a NAND). In the case of a type flash memory or the like, the relief of a memory chip in which a defective memory transistor exists can be applied to a method of performing redundancy in units of NAND strings instead of performing redundancy in units of bit lines. It is not.
Furthermore, the present invention is applied not only when a defective chip is relieved at the time of shipment of a memory chip product but also when a defective chip is relieved for a defect at each rewrite in a flash memory that can be rewritten repeatedly. There is nothing you can do or need to explain.
Furthermore, in the present embodiment, the nonvolatile semiconductor memory device has been described as an example. However, it goes without saying that the present invention can be applied to a semiconductor memory device other than the nonvolatile memory device.
[0052]
【The invention's effect】
As described above, according to the present invention, a semiconductor memory device capable of performing efficient redundancy can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a semiconductor nonvolatile memory device according to the present invention.
2 is a diagram for explaining an example of redundancy efficiency in the semiconductor nonvolatile memory device of FIG. 1; FIG.
FIG. 3 is a diagram showing a second embodiment of a semiconductor nonvolatile memory device according to the present invention.
FIG. 4 is a diagram showing a memory array structure in a DINOR type, NAND type, and AND type flash memory;
FIG. 5 is a diagram for explaining an example of redundancy efficiency when redundancy is performed in units of conventional main bit lines in the DINOR type flash memory of FIG. 4;
[Explanation of symbols]
SL ₁ ~ SL _n ... Selected gate line, W ₁₁ ~ W _nj ... Word line, B ₁ ~ B _m ... Regular bit line, b ₁ ~ B _k ... Redundant bit line, X ₁ ~ X _a , X ₁ ~ X _b ... X input, Y ₁ ~ Y _c , Y ₁ ~ Y _d ... Y input, V ₁ ~ V _j ... selected block word line voltage, x ₁ ~ X _n ... Sub-but line block selection signal, T ₁₁ ~ T _nj ... Word line voltage transmission circuit, S ₁₁ ~ S _nm ... Regular secondary line block, s ₁₁ ~ S _nk ... Redundant sub-bit line block, X _ar ... selected X address, Y _ar ... Selected Y address, X _ar-1 ~ X _ar-i ... Defective X address register, Y _ar-11 ~ Y _ar-ik Bad Y address register, φ ₁ ~ Φ _i ... Defective Y address read signal, R ₁ ~ R _m ... Regular column selection signal, r ₁ ~ R _k ... Redundant column selection signal, NOR1 ... NOR circuit, AND ₁ ~ AND _m ... AND circuit, ST ₁ ~ ST ₂ ... Select transistor, MT ₁ ~ MT _Four ... Memory transistor, 1 ... Memory array, 1a ... Regular memory array, 1b ... Redundant memory array, 2 ... Main row decoder, 3 ... Sub-row decoder, 4 ... Local row decoder, 5 ... Column decoder, 6 ... Column selector, 6a ... regular column selection unit, 6b ... redundant column selection unit, 7 ... defective address recording unit (register), 7a ... write circuit, 8 ₁ ~ 8 _i ... X address match determination circuit, 9 ₁ ~ 9 _k ... Y address match determination circuit, 10... Defective address recording section (memory array), 10a... Row decoder A, 10b.

Claims (6)

A plurality of NAND columns having a NAND structure are connected to the bit lines wired in columns, and the memory transistors arranged in a matrix are connected to the NAND columns and word lines,
At least one redundant bit line to which a plurality of redundant NAND strings are connected;
In the case where a defective NAND string having the same address as a defective address is selected, a defective bit line connected to the defective NAND string is connected to the redundant bit. And a repair unit that replaces the defective NAND column with the redundant NAND column in the direction in which the same word line extends in accordance with the replacement information and a column selection signal . The relief means includes a defective address recording means for recording an address of a defective NAND string in which a defective memory transistor exists;
When a defective NAND string having the same address as the defective address is selected, a defective bit line connected to the defective NAND string is replaced with the redundant bit line, and the defective address is different from the defective address connected to the defective bit line. 2. The semiconductor memory device according to claim 1, further comprising: a selective bit line replacement unit that does not replace the defective bit line when selecting a NAND column having a predetermined address. The semiconductor memory device according to claim 2, wherein the defective address recording unit includes a nonvolatile memory element. The semiconductor memory device according to claim 2, wherein a memory array unit and the defective address recording unit are individually integrated. The semiconductor memory device according to claim 2, wherein recording of the defective address is performed at a shipping test. The semiconductor memory device according to claim 2, wherein the semiconductor memory device can be rewritten repeatedly, and the recording of the defective address is performed for each repeated rewriting.

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