JP3845512B2 - Longest match search device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a longest match between a registered address and an address in an input network packet, which is installed in a router that is arranged in an Internet communication line network and mediates transmission of a network packet flowing in the communication line network. The present invention relates to a longest match search device that performs a search.
[0002]
[Prior art]
At present, communication called the Internet has become widespread, and accompanying this, there is a problem of exhaustion of addresses that specify a source and a destination. Currently, in the Internet protocol, a 32-bit IP address is used to address the address exhaustion problem. A technique has been adopted in which a boundary between a network address and a host address constituting an address can be freely set. Here, the length of the network address in the IP address is called the prefix length.
[0003]
An IP address of an Internet protocol employing such a method is searched for by using a method called longest match search.
FIG. 9 is an explanatory diagram of the longest match search.
FIG. 9A shows key data composed of a destination IP address in a network packet that the router intends to mediate transmission. Here, it is assumed that the key data is 186.241.0.6.
[0004]
Assume that two entries shown in FIG. 9B, that is, entry 1: 186.240.0 / 12 and entry 2: 186.192.0.0/10 are registered in the router. Here, / 12 and / 10 indicate the prefix length of each entry. For example, / 12 indicates that the upper 12 bits are a network address.
[0005]
If the key data shown in FIG. 9A is input as a search target (that is, the network packet having the destination IP address shown in FIG. 9A is input), both entries are The key data matches up to the prefix length of each entry. In this case, a path is opened to the network of entry 1 in which the longest bit length part matches from the upper bit side. Searching for an entry that matches the key data from the upper bit side to the longest bit length portion in this way is called longest match search.
[0006]
Consider realizing the longest match search using an associative memory. Here, the associative memory has a plurality of memory areas, stores data of a predetermined bit length in each of the plurality of memory areas, and inputs the key data, and the remaining bits excluding the masked bits This is a kind of memory having a function of searching a memory area in which data matching the input key data is stored. The associative memory itself is a widely known technique, and detailed description of the associative memory itself is omitted here.
[0007]
FIG. 10 is an explanatory diagram of a longest match search method using an associative memory.
Since the IP address is 32 bits, when searching using the associative memory, first, 32 bits are searched without a mask as shown in FIG. That is, it is searched whether there is a matching entry for all 32 bits. Next, as shown in FIG. 10B, a 31-bit search is performed by masking only one least significant bit. Next, a 30-bit search is performed by masking the 2 bits from the least significant bit side, and thereafter, the search is performed while sequentially increasing the mask bit by bit.
[0008]
In this way, if the search is performed 32 times while sequentially increasing the mask length, the longest matching entry can be obtained. According to the above order, the entry having the first hit as a result of the search (the match is detected for the bit portion that cannot be masked) is the longest matching entry.
[0009]
[Problems to be solved by the invention]
FIG. 11 is an explanatory diagram of the problem of the longest match search performed as described above using the associative memory.
Even if the search is performed as described above, the longest match is not accurately obtained in the case described with reference to FIG. That is, when the two entries 1 and 2 are defined as shown in FIGS. 11B and 11C, the search is performed by masking the lower 3 bits using the key data shown in FIG. Entry 1 and entry 2 have different prefix lengths, such as prefix length = 12 for entry 1 and prefix length = 10 for entry 2, but the search results match for both entry 1 and entry 2. Will be detected. According to the rules of the Internet protocol, an entry with a long prefix length, that is, entry 1 should be selected here. In such a case, there is no guarantee that entry 1 is selected.
[0010]
In view of the above circumstances, an object of the present invention is to provide a longest match search apparatus that can detect a correct entry using an associative memory.
[0011]
[Means for Solving the Problems]
In the longest match search device of the present invention that achieves the above object, a network packet including a destination IP address representing a destination address is input, and the input network packet is input from a plurality of registered entries. The address of a plurality of entries is registered in the router that sends to the network of the entry that matches the destination IP address in the registered network packet, and the destination in the input network packet is selected from the plurality of registered entries. In the longest match search device that searches for an entry having an address that matches the longest bit length from the most significant bit to the IP address,
Associative to store data of a predetermined bit length in each of a plurality of memory areas, search for a memory area in which key data is input, and the remaining bits excluding masked bits store data that matches the key data A content addressable memory in which a pair of address data representing the address of each entry and prefix data representing the prefix length of each entry is stored in each of the plurality of memory areas;
A prefix data creation circuit that sequentially creates prefix data for search;
A key data creation circuit that creates key data for search based on the destination IP address in the input network packet and the prefix data created by the prefix data creation circuit;
Based on the key data created by the key data creation circuit, the associative memory has address data that matches the longest bit length from the most significant bit side, and address data that matches the longest bit length from the most significant bit side. When a plurality of address data are stored, the memory area storing the address data paired with the prefix data representing the longest prefix length among the plurality of address data is searched.
[0012]
FIG. 1 is an explanatory diagram of the principle of the present invention.
It is assumed that entry 1 shown in FIG. 1B and entry 2 shown in FIG. 1C are registered in the associative memory. That is, in the example shown here, 32-bit address data and 5-bit prefix data are registered corresponding to each entry.
[0013]
As shown in FIG. 1A, the key data is also a total of 37 bits including 32-bit address data and 5-bit prefix data. In the example shown in FIG. 1, the key data shown in FIG. When the search is performed, the address data matches in both the entry 1 and the entry 2, but the prefix data has the key data of 1C (hex) (meaning prefix = 29), whereas the entry 1 The prefix length of 1C (hex) is the same as the prefix length of key data, and the prefix length of entry 2 is 1A (hex) (which means prefix length = 27) unlike the prefix length of key data. In the example shown, only entry 1 is detected.
[0014]
In this way, the longest match search device of the present invention stores a pair of address data representing the address of each entry and prefix data representing the prefix length (network address length) of each entry in the associative memory, Since the search is made with these pairs, even if the match is detected in multiple entries at the same time only by the address of the entry, the match will be detected only in the entry with a long prefix length. The problem described with reference to FIG. 11 is solved, and a correct entry is detected.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, two types of longest match search methods in the embodiment of the present invention will be described, and then an embodiment of the longest match search device of the present invention will be described.
FIG. 2 is an explanatory diagram of a first longest match search method of two types of longest match search methods.
[0016]
FIG. 2 shows a bit arrangement of key data for each number of searches. In each search, address data consisting of 32 bits is the same, prefix data consisting of 5 bits is 1F (hex) (prefix) for the first search. Starts at length = 32) and is decremented by 1 and becomes 0 (hex) (prefix length = 1) at the 32nd search. Also, the first search does not mask, the second search masks the least significant 1 bit of 32-bit address data, the third search masks the lower 2 bits of 32-bit address data, ... In the 32nd time, the lower 31 bits of the 32-bit address data are masked (only the most significant 1 bit is valid), and the mask is sequentially incremented by 1 bit so as to be searched. Note that the value of the prefix data is rewritten for each search as described above, and always participates in the search as valid data.
[0017]
The search is sequentially performed in accordance with the search order shown in FIG. 2, and the first hit entry is detected as a correct entry including the prefix length.
If the longest match search method shown in FIG. 2 is adopted, it may be considered that 32 types of masks for designating the search target are required. However, the search target portion of the key data is sequentially narrowed bit by bit. One shift register may be prepared as a mask register.
[0018]
FIG. 3 is an explanatory diagram of a second longest match search method of the two longest match search methods.
The address data (32 bits) and prefix data (5 bits) constituting the key data for the first search in FIG. 3 are the same as those for the first search in the search method shown in FIG.
[0019]
The prefix data is sequentially decremented for the second search to the 32nd search, which is the same as the search method shown in FIG.
However, regarding the 32-bit address data, the second search is performed with data in which the least significant bit is replaced with “0”, and the third search is performed with data in which the lower 2 bits are replaced with “0”. ... In the 32nd search, the search is performed with data in which the lower 31 bits are replaced with “0”. That is, '0' is substituted for the bit to be masked in the search method described with reference to FIG. 2 instead of masking.
[0020]
On the other hand, on the associative memory side where the search using the key data shown in FIG. 3 is performed, data valid only for the network address is registered as address data corresponding to each entry, and all the host address portions are registered. Register “0”. Corresponding to each entry, such a pair of address data and prefix data is registered in the content addressable memory.
[0021]
In this way, the search is sequentially performed while sequentially changing the key data as shown in FIG.
Also by this search method, the correct entry including the prefix length can be detected as in the search method described with reference to FIG.
In the search method described with reference to FIG. 3, “0” is substituted on the key data side instead of masking, and “0” is registered in the associative memory side for all host addresses. However, for example, the key data side may substitute “1” in place of the mask, and all “1” may be registered in the host address portion on the associative memory side. The same bit arrangement may be used.
[0022]
FIG. 4 is a block diagram showing an embodiment of the longest match search apparatus of the present invention, and FIG. 5 is a timing chart thereof. Here, the longest match search apparatus shown in FIG. 4 will be described as being searched by the search method described with reference to FIG.
The longest match search device 10 shown in FIG. 4 is provided with a CAM memory block 11, and the CAM memory block 11 includes a CAM data input / output control circuit according to data input via the maintenance port. 12, data corresponding to each entry is registered and added or changed as necessary.
[0023]
FIG. 6 is a diagram showing a data structure corresponding to one entry registered in the CAM memory block 11.
Here, areas of 32-bit IP address data, 5-bit prefix data, and other data are shown. The other data includes, for example, a time stamp indicating the registration time of the entry, although a detailed description is omitted.
[0024]
The longest match search control circuit 13 shown in FIG. 4 includes a longest match search control circuit 13. A clock is input to the longest match search control circuit 13, and the longest match search control circuit 13 receives the input clock. In synchronization with the control, each part is controlled to search for a desired entry from among the entries registered in the CAM memory block 11.
[0025]
The longest match search device 10 shown in FIG. 4 includes a key data generation circuit 14 and a prefix data generation circuit 15. The key data generation circuit 14 receives input data (destination IP address) as a basis of search key data via an input port, and further receives a search start signal instructing the start of the search (FIG. 5). Then, the prefix data generation circuit 15 generates the prefix data that is sequentially decremented as described above and inputs it to the key data generation circuit 14, and the key data generation circuit 14 receives the key data composed of the IP address and the prefix data. It is generated and input to the CAM memory block 11.
[0026]
FIG. 7 is a diagram showing a configuration of key data generated by the key data generation circuit 14.
The key data generation circuit 14 generates key data including 32-bit IP address data, 5-bit prefix data, and other data. Here, the other data plays a role only for matching the data length with the data registered in the CAM memory block (see FIG. 6), and any other data may be used.
[0027]
FIG. 8 is a diagram showing an example of key data used for each search from the first search to the 32nd search.
In each search, the IP address data is the same, and the prefix data is sequentially decremented by one.
In the mask generation circuit 16, mask data for masking the key data is generated and input to the CAM memory block 11. In the first search, only the other data portion is masked. In the second search, the other data portion and the least significant bit of the 32-bit IP address data are masked. Then, different mask data are sequentially generated so as to mask the other data portion and the lower 31 bits of the 32-bit IP address data.
[0028]
Within the CAM memory block 11, among the key data generated by the key data generation circuit 14 and input to the CAM memory block 11, effective portions that are not masked by the mask data generated by the mask generation circuit 16 are sequentially 32. The longest match search result comprising the address of the CAM memory block 11 at the time of the first search and the contents stored at that address is output from the CAM memory block 11 and the longest match search result output circuit. When the 32 searches are completed, a search end signal is sent from the longest match search control circuit 13 to the longest match search result output circuit 17, and the longest match search result output circuit 17 The longest match search result is output from the output port.
[0029]
The longest match search apparatus 10 shown in FIG. 4 is described when the search method described with reference to FIG. 2 is applied. The longest match search shown in FIG. The apparatus 10 can also perform a search using the search method described with reference to FIG. That is, at this time, only the network address of the IP address of each entry is stored in the CAM memory block 11, and “0” is written in the host address portion. In the generation circuit 14, the least significant 1 bit of the 32-bit address data is set to “0” for the second search, and the lower 2 bits of the 32-bit address data is set to “0” for the third search. Generates data in which the lower 31 bits of the 32-bit address data are set to “0”, and the CAM memory block 11 performs a search using the key data thus generated. At this time, the mask data generated by the mask generation circuit 16 generates mask data for masking only the other data portions in all the 32 searches. By performing such a search, the search method described with reference to FIG. 3 using the longest match search apparatus 10 shown in FIG. 4 is realized as it is.
[0030]
【The invention's effect】
As described above, according to the present invention, a correct longest match search is performed.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating the principle of the present invention.
FIG. 2 is an explanatory diagram of a first longest match search method of two types of longest match search methods.
FIG. 3 is an explanatory diagram of a second longest match search method of two types of longest match search methods.
FIG. 4 is a block diagram showing an embodiment of the longest match search device of the present invention.
FIG. 5 is a timing chart thereof.
6 is a diagram showing a data structure corresponding to one entry registered in a CAM memory block 11. FIG.
FIG. 7 is a diagram showing a configuration of key data created by a key data generation circuit 15;
FIG. 8 is a diagram showing an example of key data used for each search from the first search to the 32nd search.
FIG. 9 is an explanatory diagram of a longest match search.
FIG. 10 is an explanatory diagram of a longest match search method using an associative memory.
FIG. 11 is an explanatory diagram of a problem of longest match search using an associative memory.
[Explanation of symbols]
10 longest match search device 11 CAM memory block 12 CAM data input / output control circuit 13 longest match search control circuit 14 key data generation circuit 15 prefix data generation circuit 16 mask generation circuit 17 longest match search result output circuit

Claims (1)

A network packet including a destination IP address that represents a destination address is input, and the input network packet is an entry that matches the destination IP address in the input network packet among a plurality of registered entries. The address of a plurality of entries in the router to be sent to the network is registered, and an address that matches the longest bit length from the most significant bit side to the destination IP address in the input network packet from among the plurality of registered entries In the longest match search device that searches for entries with
Data of a predetermined bit length is stored in each of a plurality of memory areas, key data is input, and a memory area storing data matching the key data is searched for the remaining bits excluding masked bits. An associative memory, wherein each of the plurality of memory areas stores a pair of address data representing the address of each entry and prefix data representing the prefix length of each entry;
A prefix data creation circuit that sequentially creates prefix data for search;
A key data creation circuit that creates key data for search based on the destination IP address in the input network packet and the prefix data created by the prefix data creation circuit;
Based on the key data created by the key data creation circuit, the associative memory is address data that matches the longest bit length from the most significant bit side, and address data that matches the longest bit length from the most significant bit side The longest match search is characterized by searching for the memory area where the address data paired with the prefix data representing the longest prefix length is stored among the multiple address data. apparatus.

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