JP3844013B2 - Display device - Google Patents

Description

The present invention relates to a display device. More particularly, this invention relates to a display device that includes an array of switchable elements, each switchable element being switchable between at least two states, and the type of image displayed by the display device is each switchable. Depends on the state of possible elements.
Such switchable elements may take the form of light modulators that control the passage of light from the light source to the displayed image. Examples of light modulators include, for example, the “deformable reflector spatial light modulator (Hornbeck) published in the August 1989“ the Proceedings of SPIE ”, Volume 1150 (Hornbeck). "Deformable Mirror Spatial Light Modulators") "is included. Such deflectable or “deformable” reflector display devices include an array of deflectable reflector devices, each reflector device being mounted on a torsion element on a control electrode. By applying an electric field between each reflector device and the electrode, the reflector device turns, thereby changing the direction of light reflected from the reflector device.
Another example of the light modulator is a liquid crystal device.
Alternatively, the array of switchable elements may take the form of an array of light sources that can be switched on or off, such as an array of light emitting diodes.
Generally, such display devices are digital devices, that is, each switchable element of the device displays from the element to produce either a “white” or “black” pixel on the displayed image. It is effective to switch the light passing through the image to be “on” or “off”. However, the integrated response of the observer's eyes to control the time each switchable element of the device is in a state where the light from the element reaches the displayed image and to perceive a grayscale image from the element It is also possible to display a grayscale image by using.
An example of such a configuration is described in GB 2014822 which discloses a display device incorporating an XY array of light emitting devices capable of applying a voltage. The display device described in GB 2014822 takes binary digital format data, for example via an 8-bit signal, and the device is in a single line for a number of periods in which the modulator may be “on” or “off”. Is driven. The “on” / “off” state of each pixel during each time period is determined by the state of the corresponding bit of the digital input data.
A display device incorporating a light modulator in the form of a deformable reflector device operates in a similar manner. However, in a deformable reflector device, the entire array of pixels is driven simultaneously to match the longitudinal scan rate of the video source.
The eight time periods within each display frame period have different lengths. The length of the time period corresponding to the least significant bit (LSB) of the input signal for any particular frame is set to a predetermined value, and the duration of the time period corresponding to the next of the least significant bits is the least significant bit. It will be twice as long as that corresponding to. Thus, the length of the time period corresponding to the most significant bit (MSB) for such an 8-bit input signal is 128 times that corresponding to the least significant bit (LSB). If all time periods are contained within a display frame period that is shorter than the duration of about 20 microseconds, the human eye integrates these periods and the brightness level corresponding to the binary signal value. Respond as if to respond in a single period with At the end of each subframe period corresponding to one bit of the input signal, all elements of the array are switched to switch the element to a rest position in some systems or to a state determined by the next bit signal. A reset signal is applied to the element.
Such display systems that use time-division multiple addressing of switching elements to at least partially display grayscale are used in large screen projectors. However, it is recognized that when such a large screen projector is used to display a motion video signal, a band in which pixels glitter is formed at a certain intermediate gray brightness level. In addition, for the same medium gray brightness level, if the observer blinks, moves his head, or flickers his finger in front of the eyes or in front of the projection lens, It can be divided into “now” pixels. These effects are sometimes recognized as “dynamic contouring”.
It is an object of the present invention to provide a display system incorporating an array of switchable elements that alleviates these problems.
According to a first aspect of the invention, a time division modulation process is performed to switch each element between an “on” state where light is directed onto the display and an “off” state where light is not directed onto the display. A display system is provided that includes an array of switchable elements that are used to at least partially display grayscale, wherein each frame period of the display system increases the temporal balance of light from each element. Each element is divided into sufficient time intervals to be switched to the “on” or “off” state.
The present invention has therefore been made with the inventor's admission that the impact defined above as "dynamic contouring" can be reduced by operation of a time division multiple addressing scheme.
Thus, according to a second aspect of the present invention, a display system comprising a switchable array of light-directing elements is provided for each element to reduce the adverse effects caused by the temporary addressing of the switchable elements. Includes means for modifying the time to direct light on the display.
A number of embodiments of a display system according to the invention will now be described by way of example only with reference to the accompanying figures.
FIG. 1 is a schematic overview of a known type of display system.
FIG. 2 is a schematic diagram of a spatial light modulator array incorporated into the system of FIG.
FIG. 3 shows the illuminance of the reflector apparatus in the array of FIG.
FIGS. 4a-4e show five examples of known time division multiple addressing schemes for achieving gray scale in the system of FIG.
FIG. 5 shows an example of a known time division multiple addressing scheme for two adjacent reflector devices in an array incorporated in the display system of FIG.
Figures 6a-6e illustrate five examples of modified time division multiple address schemes used in display systems according to embodiments of the present invention.
FIG. 7 shows a first example of a bit weight distribution scheme for use in a display system according to an embodiment of the present invention.
Figures 8a-8d show an example of a computer simulation of light output from a single pixel resulting from a prior art display system.
Figures 9a-9d show an example of a computer simulation of light output from a single pixel resulting from a modified display system according to an embodiment of the present invention.
FIG. 10 shows a second example of a bit weight distribution scheme for use in a display system according to an embodiment of the present invention.
FIG. 11 shows a third example of a bit weight distribution scheme for use in a display system according to an embodiment of the present invention.
FIG. 12 shows a fourth example of a bit weight distribution scheme for use in a display system according to an embodiment of the present invention.
FIG. 13 shows a modification of the bit weight distribution scheme of FIG.
FIG. 14 shows a portion of a display system designed to implement a modified addressing system according to an embodiment of the present invention.
FIG. 15 shows a sequencer incorporated in the apparatus of FIG.
FIG. 16 shows the contents of the frame storage device incorporated in the device of FIG.
Referring first to FIG. 1, the particular example of a display system described is configured to project a color image on a display screen 101. The display system includes a light source 103 that may be of any suitable form, such as an arc lamp. The light source 103 is arranged so that light rays from the light source are directed onto the three planar deflectable mirror devices 105, 107, 109 described below.
Two dichroic mirrors 111 and 113 are positioned in the light path between the light source 103 and the first deflectable reflector display device 105. The first dichroic mirror 111 is designed and angled to reflect blue light and transmit all other incident light onto the second planar deflectable reflector display device 107. The second dichroic mirror 113 reflects red light on the third planar deflectable reflector device 109 and the remaining green component of light from the light source 103 on the first deflectable reflector display device 105. Designed and angled.
Three deflectable reflector devices 105, 107, 109 reflect the three color components of the light from the light source 103 to direct the spatially modulated light onto the display screen 101 via the projection lens 115. Arranged to be able to.
With further reference now to FIGS. 2 and 3, each deflectable reflector device (DMD) 105, 107, 109 is typically 768 × 576 reflector devices in a low resolution display system, or high resolution. The display system includes an array of m × n deflectable reflector devices, which is 2048 × 1152 reflector devices. Each array 117 together receives an electronic color video signal from a control circuit, indicated at 121, for example, applicant's earlier international patent application PCT / GB92 / 00002 dated January 4, 1992, incorporated herein by reference. Reflector apparatus M described in ₁₁ ~ M _mn Are connected to a driver circuit 119 for addressing each of them. Depending on the applied address signal, each reflector device M corresponds to an “on” state in which reflected light is directed to the first path 123 and an “off” state in which reflected light is directed to the second path 125. It is intended to take one of two different positions. The second path 125 is chosen so that light reflected along this direction deviates from the optical axis of the display system and therefore does not pass through the projection lens 115.
Thus, the reflector device M tilted to the “on” state becomes bright and the reflector device M tilted to the “off” state becomes dark so that each DMD array 117 can represent a two-dimensional image. By changing the ratio of the “on” period to the “off” period, ie by a temporal modulation technique, grayscale can be achieved as will be explained in more detail hereinafter.
Referring now specifically to FIG. 3, the angle at which each mirror apparatus M is deflected between the “on” and “off” states is relatively small. Thus, in order to achieve sufficient discrimination between the “on” and “off” states, the incident light 127 from the light source 103 is measured relative to each spatial light modulator 105, 107, 109 from the normal to each device. And oriented at an angle of about 20 °.
When the individual mirror apparatus M is parallel to the plane of the array 117, the incident ray 127 is reflected at a corresponding 20 ° angle to the normal and a ray dump (not shown) along the “off” path 122. to go into. When the control signal from the driver circuit 119 sets the reflector device M to the first deflection state at a first angle with respect to the surface of the array 117, the incident ray 127 is further along the direction 125 in the "off" path. It is reflected and enters the lamp. When the control signal from the addressing circuit 119 sets the reflector device M to the second deflection state at a second angle with respect to the plane of the array 117, the incident ray 127 is normal to the array along the “on” path 123. Is reflected along.
Reference is now made to FIGS. 4 a-4 e, which illustrate a time division multiple address sequence for each reflector element M of the DMD array 117 that allows grayscale to be displayed on the screen 101. For simplicity, the example illustrated in FIGS. 4a-4e corresponds to a 5-bit input video signal. 4a-4c thus represent a time frame of a particular reflector device M divided into 31 equal time intervals, the horizontal direction thus representing the time axis.
FIG. 4a corresponds to a state in which the reflector device M is configured such that the maximum brightness is displayed on the display screen 101 for the duration of the frame period of the display device. Thus, the reflector device M has a duration of 16 time units (corresponding to MSB), 8 time units, 4 time units, 2 time units, and finally 1 time unit (corresponding to LSB). Is switched to the “on” state during Thus, the integrated brightness level for this particular reflector device M of array 117 is 31 units.
This can be contrasted with the situation illustrated in FIG. 4b, in which the reflector device M is switched to the “on” state only for the duration of the time period corresponding to the MSB during a single frame period of the display device. Therefore, the integrated brightness of the reflector apparatus M for the frame period is 16 units.
Similarly, FIG. 4c shows a state in which the reflector device M is switched to the “off” state for the time interval corresponding to the MSB and to the “on” state for the remaining frame period. Therefore, the integrated brightness of the reflector apparatus M for the frame period is 15 units.
Referring now to FIG. 4d, this figure shows two consecutive frame periods for one reflector device M and is therefore a different time scale than FIGS. 4a-4c. In this particular example, the sequence shown in FIG. 4b is followed by the sequence shown in FIG. 4c. Accordingly, in the example illustrated in FIG. 4d, both the second half of the first frame period and the first half of the second frame period are dark corresponding to the “off” state of the reflector apparatus M. This results in a time interval of one frame period in which no light appears on the display screen 101 for the pixels corresponding to the reflector device M. It is understood by the inventors that this appears as a dark flash on the display screen 101 that can be recognized by the observer.
The state shown in FIG. 4e also illustrates two consecutive frame periods for a single reflector device M, and is therefore shown in the same horizontal time scale as FIG. 4d, but in an inverted frame sequence. In this particular example, when the display screen is illuminated continuously, there is an entire frame period consisting of the second half of the first frame period and the first half of the second frame period. It is understood by the inventors that this appears to the observer as a white flash on the display screen 101.
If the drive signal to the reflector device M fluctuates between the bit sequences of FIG. 4d and FIG. 4e due to, for example, video quantization noise, the pixel appears to match the noise, which is “active contour” This is a phenomenon known as “chemical conversion”. Accordingly, it is understood by the inventors that at certain intermediate gray brightness levels, the type of situation shown in FIGS. 4d and 4e results in sparkling pixels in the projected image on the screen 101. FIG. In addition, this video noise causes quantization time jitter of critical bit transitions in the AD converter used to process the video input signal so that the shimmering pixels are spread over another band.
When the observer blinks, moves his head, or flickers his finger in front of the eyes or in front of the projection lens 105, the state shown in FIGS. 4d and 4e is the apparent “dynamic contour” of the image. It is also understood by the inventor that further “synchronization” can occur. This means that two adjacent reflector devices M ₁₁ And M ₁₂ Referring to FIG. 5 which shows a single frame time period for each of the horizontal scales, the horizontal scale is therefore different from that of FIGS. First reflector device M ₁₁ Is configured such that only the MSB is "on" and all other bits are off. Second reflector device M ₁₂ The MSB is “off” and all other bits are “on”. Therefore, M ₁₁ Image pixels formed from light from ₁₂ It can be seen that the display screen 107 is reached half a frame period before the image pixels formed from the light from.
For example, when the observer's head is moving following a moving object on the displayed image, or when the observer's eyes are scanned on an image projected on the display screen 101, the reflecting mirror device M ₁₁ And M ₁₂ The two pixels corresponding to the light from appear to move relative to the background and hence relative to each other. This makes the reflector device M addressed “later” ₁₂ The pixel corresponding to the light from the eye appears to move in the direction opposite to the scanning direction of the observer's eye, while the reflector device M addressed first ₁₁ The pixels corresponding to the light from appear to move in the same direction as the observer's eye scan direction. Therefore, the movement direction of the observer's eyes is the reflector device M. ₁₁ Reflector device M ₁₂ The two pixels appear to overlap due to the apparent displacement of the two pixels, and the displayed image is apparently brighter at that point on the display screen 101.
Conversely, the direction of movement of the observer's eyes is the opposite direction, that is, the reflector device M ₁₂ Reflector device M ₁₁ The two pixels appear to be separated and the image appears to be dark at corresponding points on the display screen 101. This effect follows the pixels corresponding to the main transitions in the displayed image, much like the contour lines on the map. Since these outlines are not smooth, the apparent relative movement of the pixels gives the impression of a coarse pixel structure at these transition points, which has an effect similar to that of insufficient display resolution.
Thus, when the most significant active bit is “on” or “off”, the bit transition “dynamic contouring” effect experienced by time-division-addressed light modulators is between adjacent display frames or adjacent pixels. It is understood by the inventors that it occurs as a direct result of the temporary displacement of the bit pattern in between. Furthermore, no matter how much filtering is introduced by the observer's eyes, the effect of the temporary shift between adjacent display frames is a unipolar variation in light output, so the overall disturbance energy cannot be reduced, It only spreads over longer time intervals.
The only way that this “dynamic contouring” due to bit transitions can be reduced is to either eliminate or minimize such temporary shifts in the bit pattern at critical bit transitions. This is difficult to achieve completely in the case of time division multiple addressed display systems, since temporary displacements are inherent in their operation. However, if a unipolar disturbance resulting from a temporary shift can be converted into a bipolar disturbance (as described with reference to FIGS. 8 and 9), and (FIGS. 10, 11, 12). The problem can be mitigated by maximizing the frequency of the disturbance and minimizing the amplitude content of the disturbance (as described with reference to FIG. 13).
Next, a modified time-division address used in the display system according to the present invention designed to achieve temporary shift removal or minimization to alleviate display flicker and "dynamic contouring" problems Follow examples of specified schemes.
Turning now to FIGS. 6a-6e, these figures show a modified version of the bit weight sequence shown in the prior art configuration of FIGS. 4a-4d used in a display device according to the present invention.
FIG. 6a shows the situation where only the 16-hour unit MSB is divided into two partial subframes MSB1 and MSB2, and each of the 8-hour unit durations is labeled 16a and 16b. The center of illuminance (COI) can be defined relative to the display frame period, which occurs at the center of the frame period. A qualitative analysis of the benefits of this scheme can then be obtained by considering the moments of the various bit weights about the center of illumination, analogous to the mechanical balance in a mechanical system. Since both MSB1 and MSB2 correspond to a particular reflector device M that is either "on" or "off", it can be seen that the individual moments are equal in magnitude but opposite in sign. Therefore, the contribution from these two partial subframe periods to the moment of illumination is zero. The second longest subframe period, which is 8 units long, is placed as close as possible to and symmetrical about the center of the frame period in order to minimize its contribution to the moment of illumination. The remaining subframes of 4, 2 and 1 are 7 units (4 + 2 + 1), 8 units (single 8 subfields), 15 units (8 + 4 + 2 + 1), 16 units (16a + 16b), 23 units (16a + 16b + 4 + 2 + 1), and 24 units. In order to minimize the change in the moment of illumination of the frame for the various possible combinations of (16a + 16b + 8), it is positioned as symmetrically as possible with respect to the center of illumination.
FIG. 6b shows that 8 units of the second upper bit subframe are further divided into two parts 8a and 8b, each of 4 units duration. Fig. 6a shows a modification of the scheme of Fig. 6a. If the centers of the partial subframes 16a and 16b are separated by a half frame period as shown in FIG. 6b, the flicker fundamental frequency component of the light output at the display frame rate is removed at an intermediate brightness level of 16 units. Therefore, any perceived display flicker is minimized.
Turning now to FIG. 6c, in this bit weight distribution scheme, the three most significant bits are each divided into equal parts. Thus, the 16 unit subframe, the 8 unit subframe, and the 4 unit subframe are all divided into portions 16a and 16b, 8a and 8b, and 4a and 4b, respectively. Since the partial subframes 16a and 16b already have an optimal position as shown in FIG. 6b, 4a and 4b are located near the center of the display frame period adjacent to these partial subframes.
Turning now to the bit weight distribution scheme of FIG. 6d, this scheme illustrates the MSB being divided into four equal partial subframes, each of four unit durations, ie 16a, 16b, 16c and 16d. . The next two most significant bits are each equally divided into two partial subframes 8a and 8b and 4a and 4b, respectively. In this particular scheme, the MSB partial subframes 16a, 16b, 16c and 16d are spaced by a quarter of the frame period. This removes not only the basic 16-unit flicker component but also the second harmonic. The partial subframes 8a and 8b are spaced apart by a half-display frame period so that the basic flicker component at the brightness level of 8 units is further removed. This leaves two gaps at each end of the frame period in which the partial subframes 4a and 4b fit symmetrically.
Turning now to FIG. 6e, this figure shows a bit weight distribution scheme in which unequal bit division is used. In this scheme, the MSB is divided into three partial subframes: 5 unit duration 16a, 2 unit duration 16b and 9 unit duration 16c. The next higher order bits are divided into two partial subframes, 5 unit duration 8a and 3 unit duration 8b. The third upper bit is divided into two equal partial subframes 4a and 4b, each of which is 2 units. This figure therefore shows a bit weight distribution scheme in which a subframe will be divided into an unequal number of partial subframes of unequal duration. However, it can be seen that the address scheme shown in FIG. 6e does not give as much control of the center of illumination as the address scheme shown in FIG. 6d.
Reference is now made to FIG. 7, which shows a bit weight distribution scheme in which the effect of flicker is minimized. As shown in this figure, the MSB is divided into eight equal partial subframes, the next MSB is divided into four equal partial subframes, and the next MSB is divided into two equal partial subframes. Thus, the display frame is 14 equal sub-frames (A to G) of 2 unit duration, 1 sub-frame of 2 unit duration, and 1 sub-frame of 1 unit duration, summing as before The maximum partial frame duration is 2 units here, so that it is divided into 31 units.
The vertical column of the left hand in FIG. 7 represents the increasing level of display brightness in a single frame between a minimum value of 0 units and a maximum value of 31 units. An X in a partial subframe indicates that the corresponding reflector device M is switched to the “on” state at that particular time, and if there is no X, it indicates an “off” state. The timing of the reset pulse for the mirror device of the DMD array 117 is also shown in the figure, and the reset pulse must be given every two units to prepare the mirror device M for their next orientation state. Is apparent from FIG.
The purpose of the scheme shown in FIG. 7 is to extend the period during which the reflector device M is uniformly “on” over the frame period. However, since 31 is a prime number, this spread cannot be perfect. It can be seen that the illuminance levels of 0-3 and 28-31 units do not produce a uniform spread of illuminance over the frame period. However, at these illuminance levels, the disturbance level is small, so the display artifact is much less obvious. It can be seen that for illuminance levels 4 and 5, and 26 and 27, the moment of illuminance is greater, while the fundamental disturbance frequency component doubles to the second harmonic of the display cycle frequency. Similarly, for other illuminance levels, as the illuminance moment increases, the fundamental light output disturbance frequency for each illuminance level also increases, which is indicated by the numbers in the right hand column of FIG.
By using the bit weight distribution scheme shown in FIG. 7, the one-to-one correlation between the video input signal and the address signal to the DMD array 117 has been removed except for the LSB and the next lower bits. Is understood. This can be addressed, for example, by the use of a suitable sequencer that incorporates a ROM to perform the required bit conversion. A preferred apparatus will now be described with reference to FIGS. 14, 15 and 16, and FIG. 7 effectively serves as a truth table for programming the ROM.
It can be seen that the scheme shown in FIG. 7 is designed to reduce the flicker effect caused by the effect of bit weight distribution within a single frame of the display system. Here, since the time division modulation information is received as a continuous stream by the observer, not only the influence of the bit weight distribution within a single display frame but also the movement from one display frame to the next display frame. Impact must also be considered. The effects of transitions between successive frames of the display system can be examined by computer simulation using the opening function of a window that slides in a time-division modulated serial data stream to simulate the integrated effects of the observer's eyes. As the window moves along the bit sequence, changes in the average value within the window are a measure of the light output disturbance perceived by the observer. This includes flicker and other components in addition to disturbances that cause “dynamic contouring”. Choosing a rectangular window opening function with a duration equal to the display frame period does not fully represent the eye movement, but only takes into account the difference between adjacent display cycles, with maximum clarity. Simulate “dynamic contouring” disturbances.
FIGS. 8 and 9 show the result of applying such a sliding window opening function to the MSB and the next higher order bit, the MSB-1 bit transition. FIG. 8 shows the results for the bit sequences of FIGS. 4d and 4e, and FIG. 9 shows the results of the modified bit sequences used in the display device according to the invention. 8 and 9, the MSB is indicated by “M”, the remaining LSBs are indicated by “L”, and the MSB-1 is indicated by “H”.
In the first example, consider a sliding rectangular window that samples from the MSB to the LSB for the first time, as shown in FIG. 8a. If the light output is increased by 1 LSB to turn all LSBs “off” and the MSB “on”, ie, as shown in FIG. 4e, the result at the light output from a given reflector device M It can be seen from FIG. 8a that the typical increase is a monopolar triangle.
Similarly, in the case of the 1LSB reduction shown in FIG. 8b, ie, in the state shown in FIG. 4d, the resulting reduction in light output is also a monopolar triangle.
FIG. 8c shows an equivalent state for the MSB-1 bit transition when an increase of 1 LSB "turns off" all MSBs and "turns on" MSB-1 and the MSB is permanently "off" . The disturbance in light output is also a monopolar triangle that gives an increase in light output relative to the upper transition.
FIG. 8d shows the corresponding state, since FIG. 8d shows the corresponding state for the 1LSB phenomenon indicating a corresponding monopolar triangle reduction in light output.
Thus, from FIGS. 8a-8d, for a given bit transition, the resulting disturbance in the optical output is a unipolar triangle and the amplitude and duration of the disturbance is the most significant bit change transition between each pair of consecutive frames. It can be seen that it increases in proportion to. It can also be seen that the disturbance peak amplitude is equal to the weight of the most significant bit change, and the duration of the disturbance is twice the bit display interval for the same upper bits.
FIGS. 9a to 9d show the effect of bit division on the bit sequence of FIGS. 8a to 8d when the partial sub-frames of the divided bits are positioned symmetrically about the center of the display frame in the display system according to the invention. FIGS. 9a and 9b show that in the MSB split example, the unipolar disturbance of FIGS. 8a and 8b is the state where the disturbance peak amplitude is halved and the phase of the disturbance cycle is reversed between the upper and lower transitions. It shows that it has been converted into a bipolar disturbance. However, the duration of the disturbance has not changed from that of FIG. 8a.
Similarly, FIGS. 9c and 9d show that in the example of the MSB-1 transition, the unipolar disturbance of FIGS. 8c and 8d is a single peak amplitude of half with phase reversal between the upper and lower transitions. It is converted into a bipolar disturbance of the cycle. Again, the duration of the disturbance remains unchanged.
It can be shown that dividing the bit display interval further reduces both the amplitude of the disturbance and the duration of the disturbance. In general, for a given most significant bit change, the disturbance peak amplitude is given by (bit weight) / N, and the disturbance duration is (2 ^* Bit spacing) / N, where N is the bit division factor. In principle, odd values of N can be used, but distributing the resulting partial subframe presents additional problems. Furthermore, although not essential, implementation can be simplified by limiting N to multiples of binary values.
Defining the disturbance energy as the region under the disturbance waveform of FIGS. 8 and 9, by applying the sliding window technique used to produce FIGS. 8 and 9, the bit sequence for the minimum energy is It can be shown that it must have any non-divided bit in the center and the display frame should start and end with a divided MSB interval. Furthermore, the effective part of the divided bits must decrease uniformly towards the center of the display cycle. It can also be shown that placing the most undivided bit in the center of the display cycle results in the bit behaving as if it had been divided at the expense of the second lower bit with higher disturbance energy.
Disturbance energy considerations indicate that only the top 4 or 5 most significant bit weights cause observable bit transition contouring on the displayed image. This is shown in FIG. 10 for a simple bit split with a maximum split factor N of 2, whereas the LSB is the rest of all remaining, where the highest order unsplit bit is located in the center of the display frame. Would be considered as undivided bit weights.
In general, the light output change between adjacent frames for a single reflector device M or the light output change between two adjacent reflector devices can be any value from 0 to peak white. Obviously, a change in zero illumination or maximum peak white illumination is not a problem because no contouring occurs or it is totally masked by a stepped brightness change, but a single effect that causes an MSB change. The LSB step change can have a significant dynamic contouring effect.
Due to the random variation of stepwise brightness changes in the real image, ideally the allocation of individual bit spacing within the display cycle is generated by the change in illumination level between adjacent time frames. Should be performed on a dynamic basis to minimize the amount of "", but this is not necessary. This dynamic allocation needs to take into account factors such as the most significant bit change, the magnitude of the change step, and the acceptable degree of bit splitting.
It has been shown with reference to FIGS. 8 and 9 that the effect of contouring due to step changes in the brightness of a single LSB decreases with decreasing most significant bit changes. However, the level of annoyance of “dynamic contouring” is strongly influenced by the total number of bit changes, the degree of bit splitting, and how these bits are distributed within the display cycle. The element affects both the amplitude and frequency of the disturbance.
Defining the “dynamic contouring annoyance factor” as the product of the peak disturbance amplitude and the disturbance duration, the absolute “dynamic contouring” disturbance changes as the square of the most significant bit weight change. However, because it is represented as part of the average light output, the contouring disturbance changes only in proportion to the most significant bit weight change. Therefore, to reduce the effect of “dynamic contouring”, only the higher order bits should be split.
In the example of a change in light output greater than a 1 LSB step, the masking effect of the change on “dynamic contouring” increases with increasing step size. In general, the peak contouring disturbance amplitude at least up to the magnitude of the changing step is masked by the step change in the light output. This masking effect is further enhanced by the reduction of the “contouring annoyance factor” caused by bit splitting.
As explained above, the peak disturbance amplitude for a sliding window opening equal to the display cycle period is proportional to the bit weight divided by the bit division factor N, and then the effect of “dynamic contouring” is at this level or Masked against stepwise brightness changes of higher levels. The larger the bit splitting factor, the smaller the peak contouring disturbance amplitude, and hence the smaller the step change in light output that masks it.
By way of example, consider FIGS. FIG. 11 shows one possible dynamic bit division sequence where the MSB is divided into four equal partial subframes, and the other divided bits are divided into two equal partial subframes. The position of the partial subframe within the display cycle is dynamically assigned according to the change of the brightness level according to the truth table of FIG. Thus, the disturbance is now equivalent to the disturbance generated by the MSB divided into four, where the peak disturbance amplitude is reduced by a factor of 2 with respect to the peak disturbance amplitude of FIG. Much of the MSB disturbance energy has moved from the fundamental display cycle frequency to the second harmonic of the display frame rate compared to the MSB bit transition of FIG. This results in a disturbance energy reduction factor between 2 and 4, depending on the amount of remaining disturbance energy remaining at the fundamental frequency. For FIG. 10, the MSB-1 transition energy remains.
FIG. 12 shows that the MSB is divided into eight equal partial subframes, the MSB-1 is divided into four equal partial subframes, and the remaining divided bits are divided into two equal partial subframes. A dynamic bit division sequence is shown. These partial subframes are then dynamically positioned within the display cycle according to the truth table of FIG. Thus, the disturbance is now equivalent to the disturbance generated by the MSB divided into eight, where the peak disturbance amplitude is reduced by a factor of 4 relative to that of FIG. Most of the MSB disturbance energy has moved to the fourth high frequency of the display speed as compared to the MSB bit transition of FIG. This results in a disturbance energy reduction between 4 and 16 times the simple bit division of FIG. 10, depending on the amount of residual fundamental frequency. The MSB-1 disturbance energy has an amplitude that is half of the amplitude of FIG. 10, and much of that energy is now in the second harmonic. Therefore, the MSB-1 transition disturbance energy is a factor of 2 to 4 less than that of FIG. 10 depending on the amount of remaining disturbance energy at the fundamental frequency. The remaining bit weight disturbance energy remains unchanged from those in FIG.
The MSB transition fundamental frequency component is due to the dynamic bit-splitting scheme shown in FIG. 13, where dynamic subframe allocation has some further optimization at the expense of a slight increase in disturbance energy for a step change in brightness greater than 1 LSB. It can be virtually eliminated.
12 and 13, the peak disturbance amplitude is equal to the step amplitude for a step change greater than three LSBs. This may be further reduced only by a higher level of bit splitting, but this causes a corresponding increase in the amount of data that must be loaded into the DMD array 117. The schemes of FIGS. 12 and 13 require a total of 14 bit display intervals for the top three MSBs plus a 1 + R interval for the LSB, where R is the number of remaining LSBs. is there.
Therefore, comparing FIG. 7 with FIGS. 10-13, the distribution of partial subframes is relative to the minimum steady state perceived by the display flicker shown in FIG. 7 or the bit transitions shown in FIGS. 10-13. It can be seen that the minimum bit transition “dynamic contouring” due to disturbance can be arranged. Unfortunately, for many bit pattern combinations, the minimum flicker and the minimum “dynamic contouring” are not necessarily concomitant, but the general bit weight distribution that gives the minimum “dynamic contouring” is the flicker operation. Useful improvements are also given, although not optimal. However, experiments have shown that "active contouring" artifacts are generally less preferred than flicker because visible flicker is generally at an extremely low level.
Reference is now made to FIGS. 14, 15 and 16, which illustrate examples of addressing circuits for implementing a modified addressing scheme in accordance with the present invention. Referring specifically to FIG. 14, a video input signal consisting of one of three separate video signals representing the red, green and blue color components of an image to be displayed is converted to an AD converter ( ADC) unit 129. The output of the ADC unit 129 is supplied to a gamma correction unit 131 in order to remove a gamma correction signal normally present in the video signal for display on the cathode ray tube.
The output of the gamma correction unit 131 is provided to the data formatting unit 133 to convert the word serial video input into a format suitable for addressing the DMD array 117. The data formatting unit 133 is configured to alternately address the two frame stores 135, only one of which is shown in FIG. Each frame storage device 135 is configured to store video data for each device M in the DMD array 117 and supply this data to each device M in the DMD array 117 via a driver circuit 119. The format of the frame store 135 will be described in more detail later.
The sequencer 137, whose format will be described in more detail after this, takes the “rest” orientation shown in FIG. 3 before all the reflector devices M are deflected to their next required orientation with respect to the illumination beam. Is configured to provide a reset signal to the reflector device of the DMD array 117 at the end of each bit frame display interval. One frame storage device 135 provides data to the DMD array 117 while the other frame storage device 135 receives fresh video data from the data formatting unit 133.
Referring now specifically to FIG. 15, the sequencer 137 includes a read only memory (ROM) 139 that is programmed with the display time length of each bit field. ROM 139 is addressed by programmable counter 141 clocked by the output of second programmable counter 143, which is clocked by clock pulses from clock 145. The counter 143 is programmed so that the total number of counts occurring within each frame time is determined by a preset value obtained from the ROM 139. The count cycle of counter 143 thus defines the display time duration for the current bit weight, and counter 141 cycles through each bit display interval creating a complete display cycle. The output of counter 141 further defines the next bit weight to be transferred from the associated frame store 135 to DMD array 117.
At the end of each display interval, counter 143 generates an output signal that resets DMD array 117 and forwards new information to reflector device M, presets itself at the next bit frame display time, and finally The counter 141 is incremented to select the bit weight of.
Referring now specifically to FIG. 16, assuming an 8-bit video input signal, each frame store 135 has eight planes P1, P2,. . . Includes P8. Each plane holds data for the DMD array 117 corresponding to one bit weight of the input video signal. Thus, plane P1 corresponds to the MSB, plane P2 corresponds to the next most significant bit, and so on up to P8 corresponding to the LSB. The sequencer 137 provides appropriate control signals to each frame store 135 to write one bit plane of data to the MSB array 117 ready for display during the next bit display interval. The net result is that each mirror device M of the DMD array is reset in a time multiplexed manner.
Implementation of the bit display scheme according to the present invention, as shown in FIGS. 7, 10, 11, 12 and 13, is to properly program the sequencer ROM 139 and set the number of bits to fit the new sequence. To achieve. The distribution of input bit weights between additional display intervals is achieved in the gamma corrector 131 by modifying a look-up table that is typically incorporated in the gamma corrector to increase the output bus width.
While the particular display device that has been described by way of example relates to a display device that includes three deformable reflector devices, the present invention provides other types of light modulators such as liquid crystal devices. It will be appreciated that other types of display devices, including, and display devices that incorporate an array of switchable light sources are equally applicable.
In the particular embodiment described, grayscale is achieved only by time-division modulation of switchable elements, but the invention also applies to display systems in which part of the grayscale is achieved by binary modulation of the light source. It is also understood that it is possible. Such a display system is described, for example, in Applicant's co-pending UK patent application number GB 9231114.1, which is hereby incorporated by reference.
The particular color display system described so far by way of example incorporates three separate light modulators 105, 107, 109, one corresponding to each of the red, blue and green colors that the modulator processes in parallel. It is further understood that is equally applicable to sequential color display systems that use a color wheel or similar device to change the color of light in a controlled manner. In such a sequential color scheme, colors are displayed sequentially from one light modulator so that light from each color is temporarily displaced by one third of the display frame period. Modulation temporary displacement of the light reaching the display screen 101 is added to the delay caused by the sequential color projection. The “dynamic contouring” effect observed in this type of prior art system is similar to that observed in the parallel color scheme, but with color artifacts in addition to brightness artifacts. It can be seen that the addressing scheme described above reduces such artifacts. However, the motion effect observed in such a color sequential method is different from that observed in the parallel color method, and one third of the frame period delay caused by the color sequential method introduces a color fringe to the moving object. To do. The worst case delay is therefore again a half frame period, which has the same effect as seen in the prior art parallel-to-system. Thus, for example, a display system according to the present invention that uses the addressing system described above can be used to alleviate this problem in a sequential color scheme.

Claims (19)

(A) an array (105, 107, 109; 117) of pixels (M _{11 to} M _mn ) each switchable between an “on” state and an “off” state;
(B) means (135) for providing a sequence of image signals each representing successive image frames, each said image signal representing a plurality of numbers each comprising a plurality of bits, The numbers correspond to different pixels (M _{11 to} M _mn ) in each image frame, and each bit of each said number is one of a plurality of different “on” time periods for one of the pixels (M _{11 to} M _mn ). And thus each number represents the total “on” time period for a different one of the pixels (M _{11 to} M _mn ) in each image frame, and
And (c) means (119) for switching each pixel (M ₁₁ ~M _mn) in each image frame relative to the time period corresponding to the "on" time period "on",
The display device further includes
(D) switching at least one of the plurality of different “on” time periods to “on” the one pixel (M _{11 to} M _mn ) during a time interval that is spaced in time from one another; A display device characterized by further comprising means (137) for dividing into effective at least two sub-periods. The display device of claim 1, wherein the one “on” time period corresponds to a maximum time period (MSB) of the “on” time period. Reorder the other “on” time periods in each image frame interval to a number where the “on” time periods for the pixels (M _{11 to} M _mn ) in each image frame correspond to the pixels (M _{11 to} M _mn ). Means (137) for performing a sequence different from the order of a bit, wherein the reordering is a temporal of an “on” time period for each pixel (M _{11 to} M _mn ) in successive frame intervals. The display device of claim 1, wherein any difference in distribution is made to be less than a difference that would occur if the “on” time period is not reordered. The means (137) for reordering said “on” time period each “on” within a display frame period according to a change in the total “on” time for each pixel (M ₁₁ -M _mn ) between successive frame periods. 4. A display device according to claim 3, arranged to position the period. Including a modulated light source arranged to partially display the gray scale by illuminating the array (105, 107, 109; 117) and being switched in synchronism with the switching of the pixels (M _{11 to} M _mn ); The display device according to claim 1. The display device according to claim 1, wherein the different “on” periods are binary sequences. Pixel (M ₁₁ ~M _mn) of the array (105, 107, 109; 117) is a deflectable mirror device, a display device according to any one of claims 1 to 6. The display device according to claim 1, wherein the display device is used in a parallel color display system, and each pixel (M _{11 to} M _mn ) has an effect of emitting light of one color component. 8. The display device according to claim 1, wherein the display device is used in a sequential color display system, and each pixel (M _{11 to} M _mn ) has an effect of emitting light of different color components in a sequence. Display device. A method of addressing a display device comprising an array (105, 107, 109; 117) of pixels (M _{11 to} M _mn ) each switchable between an “on” state and an “off” state,
(A) providing a sequence of image signals each representing a sequence of image frames, each image signal representing a plurality of numbers each including a plurality of bits, each number within each image frame; corresponding to different pixels (M ₁₁ ~M _mn), each bit of each said number defining one of a plurality of different "oN" time period to one of the pixel (M ₁₁ ~M _mn) , And thus each number represents the total “on” time period for a different one of the pixels (M _{11 to} M _mn ) in each image frame,
(B) switching each pixel (M _{11 to} M _mn ) to “on” in each image frame for a time period corresponding to the “on” time period;
The method
(C) switching at least one of the plurality of different “on” time periods to “on” the one pixel (M _{11 to} M _mn ) during a time interval that is temporally spaced from each other; A method of addressing a display device, characterized by further comprising the step of dividing into effective at least two sub-periods. The method of claim 10, wherein the one “on” time period corresponds to a maximum time period (MSB) of the “on” time period. The method further includes reordering another “on” time period in each image frame interval, wherein the reordering step includes an “on” time period for pixels (M _{11 to} M _mn ) in each image frame. Are in a sequence different from the order of the bits in the number corresponding to the pixels (M _{11 to} M _mn ), and the reordering step is a total “on” time for each pixel in successive frame intervals. 12. A method according to claim 10 or 11, wherein any difference in the temporal distribution of periods is performed such that it is less than the difference that would occur if the "on" time period is not reordered. (A) the display device according to any one of claims 1 to 9;
Display system comprising an irradiation means for irradiating; (117 105,107,109) (b) the array of pixels (M ₁₁ ~M _mn). The display system of claim 13, further comprising a display screen having an effect of projecting a representation of successive image frames. The display device according to any one of claims 1 to 6, or when not dependent on claim 7, wherein the array of pixels comprises a liquid crystal array. 13. A method for addressing a display device according to any one of claims 10 to 12, wherein the array of pixels comprises a liquid crystal array. 10. A display according to claim 13 or 14 when dependent on any of claims 1 to 6, or when not dependent on claim 7, wherein the array of pixels comprises a liquid crystal array. system. A series of image signals is derived from an incoming video signal having a gamma correction signal, and the display device or display system includes a degamma configuration (131) for removing gamma correction. 15. The display device according to claim 13 or the display system according to claim 13 or 14. 13. A computer program product with machine readable instructions for causing a processor to perform the method of any one of claims 10-12.

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