JP3839486B2 - Uncooled focal plane array sensor - Google Patents

Description

Background of the Invention
1. Field of Invention
The present invention relates to thermal imaging systems, and more particularly to microcomputer-based microbolometer array uncooled focal plane array sensors.
2. Examination of related technologies
Thermal imaging systems are useful for many low light level applications such as night vision, imaging with reduced visibility, or thermal imaging for process or conditional monitoring in industrial or residential environments. is there. These imaging devices generally perform two-dimensional real-time display for an operator to observe. The real-time image allows the user to observe the object and / or landscape, and to see the thermal characteristics of the object, with the human eye not functioning properly.
Some focal plane array sensors operate using image intensifier tubes or sensors cooled at cryogenic temperatures. The image intensifier tube amplifies visible light and near visible light having a wavelength of 0.4 to 1.0 micron in its place. Such an image multiplication sensor has some limitations. The image intensifier sensor amplifies the light at that location and cannot operate in total darkness. It also does not work if there is a sudden flash or if there is bright lighting around. Such sensors cannot detect signals through obstacles such as camouflage or smoke. Furthermore, the image intensifier does not perform hot spot detection, which is an important function for certain imaging applications.
Some conventional imaging systems generate images by amplifying near-infrared radiation visible at night. This type of radiation amplification is generally performed using a photomultiplier tube. The photomultiplier tube amplifies light having a wavelength of, for example, 0.4 to 1.0 microns using a microchannel device. The available microchannel device itself has a photosensitive input surface on one side and an output display surface on the other side. No cooling is necessary.
Some thermal vision apparatuses utilize a two-dimensional infrared focal plane array such as PtSi, Ins, and HgCdTe that operates at extremely low temperatures. Unfortunately, such focal planes require complex cooling systems.
Other focal plane arrays such as pyroelectric arrays and ferroelectric arrays are also used as night vision devices. These devices utilize an AC coupled focal plane array and require a mechanical scanner or chopper to generate an infrared image. Such focal plane arrangements are generally referred to as “uncooled” focal plane arrangements because they do not require complex cooling systems. However, they are heavier, less sensitive and consume an undesirable amount of power compared to other sensors and the uncooled sensor of the present invention.
To overcome the shortcomings of conventional devices, an independent low cost, low power consumption, lightweight portable that collects radiation at that location in the visible to infrared range, outputs digital image data, and produces a real-time visual display. It is desirable to provide a thermal sensor for the vehicle. It would also be desirable to have a sensor that produces an image using a microbolometer focal plane array with digital image data output integrated into a single chip, processing electronics, power supply and display.
Summary of invention
The present invention provides a staring focal plane array sensor with an optical system provided along an optical path for transporting radiation. Focal plane arrays and integrated circuits provided along the optical path to receive the transported radiation sensitively generate image signals from the transported radiation. The integrated circuit includes means for converting the image signal into digital image data at the digital image data output.
One aspect of the present invention comprises a microbolometer focal plane array integrated in a single semiconductor circuit having a digital image output in a modular structure package that is smaller, lighter and consumes less power than conventional devices. An uncooled focal plane array sensor is provided. The uncooled focal plane array may be formed to operate in the wavelength region from 8 microns to 14 microns, which is the wavelength region of the naturally occurring radiation at that location. Since no visible light is required, it is possible to operate in the darkness where the image intensifier cannot operate. In addition, it can operate without trouble during the day. The focal plane arrangement of the present invention does not require continuous mechanical chopper cooling.
Other objects, features, and advantages of the present invention will become apparent to those skilled in the art through the description of the preferred embodiments, claims, and drawings, wherein like reference numerals represent like elements. It will be.
[Brief description of the drawings]
FIG. 1A is a schematic block diagram of one embodiment of an uncooled focal plane array sensor of the present invention.
FIG. 1B is a schematic block diagram of a focal plane alignment apparatus utilized in one embodiment of the present invention.
FIG. 2 is a schematic diagram of a detector array of one embodiment of the present invention.
FIG. 3A is a circuit schematic diagram of a portion of the microbolometer arrangement of the present invention showing four exemplary detectors and detector electronics.
FIG. 3B is a schematic circuit diagram of another embodiment of a portion of the microbolometer arrangement of the present invention showing a plurality of detectors and detector electronics.
FIG. 4 is a circuit schematic diagram of the microbolometer focal plane array processing circuit of the present invention.
5 and 6 show another embodiment of the microbolometer focal plane array processing circuit in the integrated circuit of the present invention utilizing, for example, a bolometer offset compensator.
FIG. 7 shows another embodiment of a bolometer offset compensator circuit contemplated by a modified embodiment of the present invention.
FIG. 8 schematically illustrates an example of a non-linear compensation voltage source contemplated by a modified embodiment of the present invention.
FIG. 9 shows an example of a 1-bit latch used in a 6-bit data latch utilized in a modified embodiment of the present invention.
FIG. 10 shows an example of a buffer direct injection (BDI) preamplifier using a horizontal bipolar transistor.
FIG. 11 schematically shows a block diagram of one embodiment of a temperature stabilizer for a microbolometer focal plane arrangement implemented in accordance with the present invention.
FIG. 12 is a schematic block diagram of an analog / digital converter according to the present invention.
FIG. 13 is a schematic block diagram of the metastable decomposition circuit illustrated in FIG.
FIG. 14 is a schematic block diagram of the analog waveform generator illustrated in FIG.
FIG. 15 is a schematic block diagram of an array of analog / digital converters according to the present invention.
FIG. 16 is a schematic block diagram of the clock multiplication phase locked loop illustrated in FIG.
FIG. 17 is a schematic block diagram of the 90 ° phaser illustrated in FIG.
FIG. 18 is a schematic block diagram of a modified embodiment of the circuit illustrated in FIG.
FIG. 19 is a schematic block diagram of a two-phase voltage controlled oscillator and a square circuit used in the circuit of FIG.
FIG. 20 is a detailed schematic circuit diagram of the voltage controlled oscillator illustrated in FIG.
FIG. 21 is a detailed schematic circuit diagram of the squaring circuit illustrated in FIG.
FIG. 22 is a timing diagram illustrating the temporal relationship between the least significant bits of the gray code signal.
Detailed description
FIG. 1A shows a schematic block diagram of one embodiment of the uncooled focal plane array sensor of the present invention. The focal plane array FPA 100 is accommodated in a sealed vacuum package 103 having an infrared transmission window 105. The focal plane array FPA 100 advantageously comprises a two-dimensional focal plane array composed of a plurality of microbolometers formed on an integrated circuit. The radiation 13 from that place passes through the window 105 and is collected in the FPA 100 by the optical system 101. The FPA 100 receives radiation that generates an image on a focal plane array, and a microbolometer element including the FPA 100 generates a plurality of electronic image signals representing the image with sensitivity. The two-dimensional microbolometer array FPA 100 is read out by an analog / digital circuit integrated on an integrated circuit chip, and converts radiation into digitized electronic signals. Similarly, the integrated circuit chip includes the FPA 100. In this way, digital image data is sent from the sealed vacuum package 103 to the processing electronics 30. Integrated circuits and processing are described in further detail below. As further described herein, it is advantageous to stabilize the temperature of the FPA 100 during operation.
The signal processing electronics 30 is advantageously provided outside the sealed vacuum package 103 and is connected to compensate for the image generated on the FPA 100 and to regenerate digital image data. The digital image data may be displayed on a television monitor or equivalent display, for example.
The digital image data is sent to processing electronics 30 for non-uniformity compensation. The non-uniformity compensation circuit 143 includes level adjustment, gain correction, defective pixel removal, brightness, and contrast adjustment. One embodiment of gain correction is described in Butler's US patent application Ser. No. 08 / 521,266, entitled “Bolometer Focal Plane Array,” filed Aug. 30, 1995, co-pending, This patent is assigned to the same assignee as the present invention, in which the present invention is incorporated by reference. In one embodiment of the invention, an offset correction circuit may be integrated on the FPA chip, as described below with reference to FIG. After processing, the data is regenerated and sent to the display processor 34.
A control panel 90 may be provided to control the imaging apparatus. The control panel 90 includes means for adjusting the brightness, contrast, symbol display, on / off and other functions necessary to control the operation of the imaging system of the present invention.
The system receives power from the power source 92. As an example, the power source 92 may comprise a battery mounted in a suitable housing having a sensor package, or a suitable external power source or equivalent power source. An auxiliary port 98 is provided for control signals and video signals. The first auxiliary input video port 98A may be connected to an external power source, and other images from such an external power source can be displayed in the present invention. The second auxiliary video output port 98B provides a means for viewing and recording which images are being collected and displayed in accordance with the present invention. A test interface 94 may be provided to access the diagnosis, initial test and / or calibration of the present invention.
In one embodiment of the invention, the optical system 101 is advantageously a refractive optical system for wide field applications and a reflective optical system for narrow field applications. It is. The optical system 101 may be selected according to conventional design techniques to operate from the visible spectrum to the infrared spectrum. The FPA 100 is provided in a vacuum package 103 that includes a thermoelectric ballast 326 and a temperature sensing element 325. In one example embodiment, the temperature sensing element 325 may be integrated on a semiconductor chip having an FPA or may comprise the FPA itself. The cover of the package 103 includes a window 105 having an anti-reflective coating.
A switch on the control panel 90 provides an input to the microprocessor microcontroller 318. Microprocessor microcontroller 318 analyzes the position of the switch on control panel 90 and sends out an appropriate command signal. The microprocessor provides programmability. In one embodiment of the invention, a cathode ray tube (CRT) or flat panel display may be used.
FIG. 1B shows a schematic block diagram of a system utilizing the focal plane arrangement and integrated signal processor of the present invention. The digital offset correction device includes a shutter / chopper controller 328 coupled to control the shutter 330. It will be appreciated that a germanium or opaque chopper or other equivalent optical element may be used in place of the shutter 330, depending on the particular application. Shutter 330 controls the radiant energy entering the system. When the shutter is open, the radiant energy strikes the focal plane array (FPA) 100. The chopper 330 may be synchronized with the FPA frame rate. The FPA 100 is advantageously composed of an integrated microbolometer focal plane array with associated control electronics. The integrated microbolometer focal plane array may further comprise pixel elements, where each pixel element provides a signal that represents the amount of radiant energy absorbed by the pixel element. The FPA 100 is operated in a shutterless or vidicon mode where the FPA 100 is not obstructed by an obstacle. In vidicon mode, images are obtained continuously.
The timing generator 310 provides two timing signals 348 and receives two clock signals 350 from the focal plane array 100. The timing generator 310 generates an FPA 100 clock, a system clock, and necessary timing signals. Timing generator 310 also provides a timing signal to video timing bad pixel replacement controller 312. The gain controller 304 provides a gain adjustment signal 333. Global image correction controller 306 provides an 8-bit signal to video interface 308.
Video generator 316 is supplied with the video timing and output of controller 318. The video generator 316 advantageously includes a known digital / analog converter. The controller 318 advantageously includes a microprocessor such as, for example, a commercially available model 80C186EC type microprocessor or equivalent. The background processor interface 324 includes a program memory 322 and a data memory 320. In one embodiment of the present invention, program memory 322 may comprise 256K × 16 flash memory and data memory 320 may comprise 128K × 16 RAM. The controller 318 is advantageously connected through a background processor interface 324 to read and write data from each memory, including gain memory 338 and video memory 314. Serial communication line 340 may be coupled to provide an external interface to controller 318. Video output data is obtained from a video digital / analog converter (DAC) 316 and the frame data is available to an external frame grabber on line 342. Symbol information such as alphanumeric information is also incorporated into the video stream by the symbol generator 125. The display driver electronic circuit 123 converts the electronic signal into a visible image. A useful display driver advantageously comprises, for example, an RS170 standard driver.
The controller 318 interfaces the imaging system to an external system via the host microcomputer. The controller 318 also generates histograms, generates luminance and equivalent curves, controls choppers or shutters, generates reference image frame timing, performs memory diagnostics and system diagnostics, monitors manual controls and switches, Control the TE ballast 326.
FIG. 2 is a schematic view of the array sensor of the present invention. The microbolometer array 102 comprises the radiation sensitive portion of the focal plane array 100. In one embodiment, the array 102 may comprise more than 80,000 individual microbolometers. The electronic circuit associated with each microbolometer is shown in more detail in FIG. 3A. The detector grounds 126 are evenly distributed on the array 102. The array is arranged in a regular grid of microbolometers by column lines 114 that are individually addressed using dynamic row selection register 104 and column circuit 110. The array 102 and the array's electronic circuitry may be tested during array production. Test clock 122, test data 124, test mode enable 116, global test enable 128 and detector test force 118 signals provide control signals used to test the array. The column processing circuit 200 is supplied to each column line 114 in the array. The column processing circuit 110 is shown in further detail below.
Array 102 is addressed using dynamic row selection register 104 and dynamic column selection test register 108. During operation, the column circuit 200 addresses any particular column. A control 112 controls the operation of the column circuit. As will be appreciated by those skilled in the art, the microbolometer element may be swept with a bias current for a short time to generate an output signal from a particular row and column address selected by a row and column select line.
FIG. 3A is a schematic circuit diagram of a portion of the microbolometer arrangement of the present invention showing an example of four detectors and associated detector electronics. The microbolometer array comprises a plurality of basic unit cells that contain multiplexer test transistors. In one embodiment, the microbolometer focal plane array may comprise a 328 × 246 matrix of unit cells with 328 column circuits. In particular, the detector common ground 126 is connected to one side of each of the bolometers 218A, 218B, 218C and 218D and the unit cells 212A, 212B, 212C and 212D. The bolometer is connected in parallel to the test transistors 220A, 220B, 220C and 220D. The “on” resistance of transistors 220A, 220B, 220C, and 220D approximates the on resistance of bolometers 218A, 218B, 218C, and 218D. In this way, the test transistor can be used to provide a signal that emulates a bolometer signal. The emulated signal may be used to test the multiplexer circuit before the bolometer is created. Such tests can result in even cheaper manufacturing, as defective chips are thus identified prior to final manufacturing. Switches 222A, 222B, 222C and 222D switch the bolometer or test transistor signal in response to row select lines 216A and 216B. In the test mode, the test transistors are activated by the global test enable 128, and each individual row may be selected using one of the row select lines. Outputs 114A and 114B can be used in each column circuit 200A and 200B. In test mode, column circuits 200A and 200B are bypassed and addressed by a column multiplexer.
Referring now to FIG. 3B, there is shown a schematic circuit diagram of a modified embodiment of a portion of the microbolometer arrangement of the present invention that conceptually illustrates a plurality of detectors 3218 and detector electronics. Each of the plurality of detectors 3218 is advantageously formed on an upper level 3219 of a microbolometer focal plane array 3221 comprising an integrated circuit fabricated on a semiconductor chip 3223. A series of switches 3214 are formed on the second level 3227 of the semiconductor chip 3223. The switch 3214 advantageously comprises a CMOS switch. The switches 3214 are connected so as to be activated in a pair. That is, the switch is connected to the common bus 3210 at the first terminal and to one end of the detector at the second terminal 3225. The row selection line 3233 operates to activate a pair of switches to select one of the detectors. The output of the selected detector may then be detected on the column bus 3212. For example, during operation, row select 2 activates a pair of switches consisting of switch 3235 and switch 3237 in response to a control signal, so that a signal from detector 3218A can be sent to column bus 3212. An advantage of this configuration is that the number of connection lines required to connect the detector column to the switching level may be reduced to one more than the number of detectors. I want.
The structure unique to the uncooled focal plane array sensor of the present invention provides high thermal separation between the detectors, thereby producing a high contrast image. The uncooled focal plane array generates a high contrast image compared to other thermal imaging elements. These high-contrast images allow the user to observe more detailed parts and produce a clearer image. Referring now to FIG. 4, an example of a microbolometer array processing circuit used in accordance with the present invention is shown. Advantageously, the processing circuit may be integrated with the focal plane arrangement into a single integrated circuit, for example using MOS technology. The bidirectional vertical shift register 104 functions as array row selection. Row select line 216 activates switch 222 to select a signal from bolometer 218 or test transistor 220. Global test enable 128 activates all engaged test transistors. The column line 114 is biased by the power supply 703. Column line 114 is sensed by a buffer direct injection (BDI) circuit 1704 with a preamplifier stage and an output transistor stage. The integrating capacitor 180 integrates the signal on the column sensing line 181. In one embodiment of the invention, integrating capacitor 180 may have an integration time of about 29 microseconds. Comparator 20 compares analog ramp signal 18 with the integrated signal on column sense line 181.
A ramp generator 33, described in detail below, provides an analog ramp signal 18 to the comparator. In one example, the ramp signal may be a 34 As lamp that nominally falls within the range of between about 5 volts and 10 volts. Comparator 20 provides a binary signal to analog / digital latch 150. The digital ramp signal 151 is obtained from a 13-bit gray code counter / encoder 146. The 13-bit gray code counter / encoder 146 may operate with a frequency equal to 12 times the pixel clock using four phases of 13x resolution 12x-clock. The digital ramp signal and the analog ramp signal are adjusted so that they start and end simultaneously.
Column select line 113 provides output latch and driver 140 addressing. Depending on the column selected, the output latch and driver provide a count of the analog / digital converter latch 150 enabled by the comparator 20. Output driver 148 provides digital data 495 to the off-focal plane circuit. Digital data 495 may be clocked with a pixel clock.
In that example embodiment, the bolometer offset compensator 701 is connected in parallel with the detector elements. It will be appreciated that the bolometer offset compensator and its control circuitry are replicated for each column of detectors in the array. The embodiment shown in FIG. 4 optionally includes a non-linear compensation voltage source 703 coupled to load resistor 115. The load resistor 115 is connected to the bolometer / offset compensator 701. One embodiment of the bolometer offset compensator 701 is described in further detail below with reference to FIG. The bolometer offset compensator 701 is coupled to the load resistor 115 at a first terminal and to the data latch 744 at a control input. Data latch 744 is described in further detail below with reference to FIG. Digital offset data 745 is provided to data latch 744. The digital offset data represents the offset applied to each row and column bolometer signal on the column line 114. The BDI preamplifier 1704 amplifies the offset bolometer signal for further processing.
Reference is now made to FIG. 5 showing another variation of the microbolometer array compensation circuit of the present invention that utilizes a bolometer offset compensator 701 connected in series with a load resistor 115 and a detector element. . A low noise bias power supply 117 provides a voltage bias to the bolometer offset compensator 701. It will be appreciated that the bolometer offset compensator and its control circuit are replicated for each column of detectors in the array. 5 may optionally include a non-linear compensation voltage source 703 coupled to one input of the BDI preamplifier 1704. The other elements are connected in a similar manner as described above.
Reference is now made to FIG. 6, which shows another variation of the microbolometer array compensation circuit of the present invention that utilizes a non-linear compensation voltage source 703 coupled to a load resistor 115. The other elements are connected in a manner similar to that described above with reference to FIG. The operation of the non-linear compensation voltage source is described in further detail below.
Reference is now made to FIG. 7 which shows a modified embodiment of the bolometer-offset-compensation circuit contemplated by the present invention. As described above, each column of the focal plane array is coupled to a bolometer offset compensator 701. Thus, the bolometer offset compensator 701 and the associated circuit indicated by arrow 707 are replicated on the FPA integrated circuit chip for each M column. Here, M represents the number of column circuits. The bolometer signal on the column line 114 is selected by the row selection line 216 and connected to the BDI preamplifier 1704. The signal from the bolometer on the column line 114 is a signal that is compensated by the bolometer offset compensator 701. In the illustrated example, the bolometer offset compensator 701 is shown for illustrative purposes as compensation resistors 702, 704, and 708, each individually associated with a plurality of switches 710A, 710B, and 710D. A first compensation resistor to a sixth compensation resistor are coupled. The plurality of switches are coupled and controlled by the output of a 6-bit data latch 744, for example. The 6-bit data latch 744 is enabled by the horizontal shift register 106. Digital offset data 745 selects a particular resistor combination through data latch 744. In one embodiment of the present invention, the first compensation resistor to the sixth compensation resistor are set to values in the nominal range of 1200 ohms to 8200 ohms, and are coupled to a load resistor 115 of, for example, about 145 kiloohms. . The embodiments shown herein are illustrated rather than limiting, and other equivalent values and combinations of compensating resistors or equivalent circuits may be used without departing from the spirit and scope of the present invention. May be. In one embodiment, a non-linear compensation voltage source 703 provides a voltage to the bolometer offset compensator 701.
Here, with reference to FIG. 8, an example of a non-linear compensation voltage source 703 intended by a modified embodiment of the present invention is shown schematically. The non-linear compensation voltage source includes a switch 750 connected to a capacitor 752 connected in parallel to a resistor 754. When closed, switch 750 applies voltage VNC to amplifier 756. Amplifier 756 preferably comprises a uniform gain amplifier with output 762 through output capacitor 758 connected in series with output resistor 760. Referring again to FIG. 4, output 762 may be connected to node V1 or, in a modified embodiment, to node V3 to control the BDI preamplifier. Switch 750 is advantageously activated in synchronism with detector row selection. As will be appreciated by those skilled in the art having the benefit of this disclosure, amplifier 756 may include a uniform gain inverting operational amplifier or a uniform gain non-inverting operational amplifier, depending on the integrated circuit technology.
Reference is now made to FIG. 9 which shows an example of a 1-bit latch 744A used in a 6-bit data latch 744. Bit latch 744A may be coupled to level shifter circuit 725 to change the voltage level from input to output. Level shifter 725 is advantageously configured to reduce the n-channel on resistance. The circuit of FIG. 9 is advantageously replicated multiple times for each compensation resistor. In an example where the bolometer offset compensator 701 utilizes six compensation resistors, the same data latch circuit is advantageously fabricated six times for each of the M columns on the FPA chip. In the preferred embodiment, data latch 744 comprises a complementary metal oxide semiconductor (CMOS) transistor.
At the input, each bit latch 744A includes a row select transistor 714, 712 configured to dynamically latch and select the Nth offset bit. The transistor 714 is controlled by a row selection output from the horizontal shift register 106. The transistor 716 is controlled by a NOT row selection output from the horizontal shift register 106. Transistors 716 and 722 operate as a second dynamic latch. Transistors 718 and 720 drive transistor 726 in response to control signals T and NOT T that, when activated, transfer the state of the n offset bit to transistor 726. The NOT HV reset signal resets the outputs of transistors 726 through 724 while transfer signal T and NOT T are not activated. After reset, the activated transfer signal and transistors 718 and 720 drive transistor 726. Transistors 728 and 730 operate to drive transistor 710 in response to the output of transistor 726. At the output, switching transistor 710 controls compensation resistor selection by shorting from load tap N to load tap N + 1. The plurality of switches 710A to 710D includes the switching transistor 710 of the above example. The first latch may be biased with a first voltage Vdd for operating the transistors in the region in a 3 × 2 micron range, while a second voltage Vda substantially higher than Vdd is It may be selected to operate 710. Transistor 710 may include a semiconductor material having an area of about 40 × 2 microns.
Now that the elements of the bolometer offset compensator circuit have been described, it will now be useful to the present invention to describe the operation of the bolometer offset compensator circuit. Due to the additional background, microbolometer focal plane arrays usually require a very large dynamic range of electronics to handle both detector non-uniformities and very low signal levels simultaneously. A dynamic range of over 1 million to 1 is typical. Electronic circuit switches can meet this difficult requirement, especially when applicable to large focal plane arrays, resulting in significant advantages and practical applications of microbolometer technology. In the embodiment illustrated in FIG. 7, the non-linear compensation voltage source, if utilized, is an off-focal plane nonlinearity connected to a focal plane circuit comprising a bolometer detector, a load resistor, a preamplifier and a compensation resistor. A compensation voltage source is preferred. When voltage V1 is applied, current is selected by detector column line 114, load resistor 115, and at least one, as selected by opening one or more of the plurality of switches 710A-710D. Flows through the compensation resistor. In some embodiments, load resistor 115 is not required. The voltage V1 is set by the BDI preamplifier 1704 and is nominally the same voltage for each of the M detector circuits. The current flowing into the preamplifier represents the signal current. Compensation resistors may be utilized to compensate for differences in detector resistance that can vary greatly from detector to detector. If such a compensation resistor is not utilized, the preamplifier circuit requires a significantly increased dynamic range to handle not only the effective signal current but also the large additional current resulting from detector resistance variations.
When current is applied to the bolometer detectors, J2 R heating (ie, heating proportional to the square of the current flowing through the resistor) raises the temperature of each detector. As a result of the temperature increase, the detector resistance changes, thereby increasing the input dynamic range requirement of the BDI preamplifier 1704. An external nonlinear compensation voltage source 703 senses a change in current at node Vi and provides a nonlinear voltage that accurately compensates for the change in preamplifier current induced by J2R heating. In this way, the non-linear voltage also reduces the dynamic range requirements of the preamplifier circuit to a level that can be easily achieved in an electronic circuit integrated on the focal plane.
Referring now to FIG. 10, an example of a BDI preamplifier using a horizontal bipolar transistor is shown. The BDI preamplifier includes, for example, a PNP horizontal bipolar input stage 802, a current source load 806, a P-MOS pass transistor 804, an integrating capacitor 810, and a reset switch 808. The column line 114 may be connected to the PNP horizontal bipolar input stage by a gate 801. Gate 801 may also be coupled to a suitable voltage VPA, which may be about 10 volts. The emitter of input stage 802 may be coupled to a second voltage VB of about 8 volts. A current source load 806 may be coupled to the collector of the input stage 802. Next, the column sense line 181 may be coupled to an integration capacitor 810, which may be reset by a reset switch 808. The reset switch 808 may also be implemented as a horizontal bipolar transistor. The horizontal bipolar transistor is a paper by Holman and Connery entitled “Small and Low-Noise Operational Amplifier for 1.2 μm Digital CMOS Technology” (June 1995, IEEE Solid Circuit Journal Vol. 30, No. 6) In more detail.
Referring now to FIG. 11, there is shown a block diagram of one particular example of a temperature stabilizer for a microbolometer focal plane arrangement implemented in accordance with the present invention. The apparatus comprises a microbolometer focal plane array 100 for supplying temperature data from each of a plurality of microbolometers. As described above, data from FPA 100 may have been processed to create gain corrected signal 621 from gain / image correction controller 304. The TE ballast loop adjustment 548 may include means for determining an average signal 912 that is coupled to the gain corrected signal from the gain / image correction controller 304. The average signal determining unit 912 includes a feedback signal output 906. An average signal indicative of the average temperature of the microbolometer array is calculated from the gain corrected signal to generate a feedback signal on the feedback signal output 906. The feedback signal is advantageously proportional to the average signal. The TE ballast control 546 may include means for generating a temperature control signal 902 that includes an input for accepting a feedback signal output 906. The temperature control signal means 902 includes a temperature control output 904 for carrying a temperature control signal proportional to the feedback signal. The temperature stabilizer 326 is in contact with the microbolometer focal plane array. The temperature stabilizer 326 has an input coupled to the temperature control output and adjusts the average temperature of the microbolometer focal plane array 100 in response to the temperature control signal, as shown at coupling 910.
In one embodiment of the apparatus of the present invention, thermoelectric stabilizer 326 advantageously includes a thermoelectric cooler. The means 912 for determining the average signal may advantageously be implemented as a computer program comprising a microprocessor or running in the controller 318. The temperature control signal generating means 902 may include a conventional power amplifier.
In a useful embodiment of the apparatus of the present invention, the mean signal determining means is coupled to receive data from each microbolometer in the FPA or from a selected portion of the microbolometer in the array. preferable. In this way, the method and apparatus of the present invention initially utilizes the temperature sensitivity of the FPA bolometer elements to stabilize the array itself at the average temperature of the bolometer elements in the array.
During operation, the method of the present invention provides temperature stabilization of the microbolometer focal plane array in a computer controlled manner, where each process step is implemented in response to a computer generated command. The computer controlled method includes the following steps:
A. Reading temperature data from each of a plurality of microbolometers in the microbolometer focal plane array;
B. Determining an average signal from the temperature data;
C. Generating a feedback signal in which the feedback signal is proportional to the average signal;
D. Generating a temperature control signal proportional to the feedback signal; and
E. Stabilizing the temperature of the microbolometer focal plane array by adjusting the average temperature of the microbolometer focal plane array in response to a temperature control signal.
In one embodiment, stabilizing the temperature includes adjusting the temperature of a thermoelectric ballast coupled to the microbolometer focal plane array.
In one alternative embodiment of the invention using a separate temperature sensor on the array substrate, the TE ballast may keep the FPA temperature stable within 100 microdegree Kelvin for the following parameters:
Sensor resistance: 5KΩ ≦ R ≦ 20KΩ
Temperature coefficient: -2% / degree Kelvin
A separate temperature sensor circuit may be realized by placing the sensor in one leg of the differential bridge. The two power leads to the bridge are automatically switched so that differential measurements can be taken, and the bridge is supplied with power in both directions to offset the drift in the dc drive power supply. The bridge resistor is set to a value R equal to the sensor resistance. In order to obtain an accurate absolute temperature within the 1 degree Kelvin range, for a temperature coefficient of -2% / degree K, the value of R must be accurate to within 2%. In the case of a specified range of sensor resistance, there may be N total difference values in the bridge.
1.02N = (20K / 5K)
N = log (4) / log (1.02)
N = 70
Thus, each sensor must be measured to select a suitable resistor for assembly. The voltage difference across the bridge for the drive voltage, which is 12 volts, is about 6 μV for a change in temperature of 100 μ °. This voltage is then amplified by approximately 100,000 and sampled by an analog / digital converter for input to the background processor. The processor may be used to control a power drive circuit for the TE ballast.
The present invention is described below with reference to specific embodiments and operating parameters only for purposes of illustration and not limitation of generality. However, those skilled in the art will appreciate that the invention is not limited to the specific operating parameters described.
Reference is now made to FIG. 12, which is a general schematic block diagram of the analog / digital converter of the present invention. An analog input signal 1015 that is an analog signal to be converted is connected to one input of an analog comparator 1020 that is not clocked. The other input of the comparator 1020 is connected to the analog ramp signal 1018. Analog waveform generator 1030 generates an analog ramp signal 1018. If the analog ramp signal 1018 is substantially equal to the analog input signal 1015, the comparator generates an output signal 1021. Comparator output signal 1021 is connected to the control input of metastable decomposition circuit 1035. Synchronized to the analog waveform generator 1030 is a gray code generator 1045 that generates a digital gray code on the digital gray code bus 1062. Digital gray code bus 1062 is connected to the data input of metastable decomposition circuit 1035. The metastable decomposition circuit 1035 stores the state of the digital gray code on the bus 1062 according to the activation state of the comparator output signal 1021. As a result, the digital output signal 1047 of the metastable decomposition circuit 1035 is a digital representation of the magnitude of the analog input signal 1015 when the magnitude of the analog ramp signal 1018 is equal to the magnitude of the analog input signal 1015.
Reference is now made to FIG. 13, which shows the metastable decomposition circuit 1035 in more detail. Comparator output signal 1021 is connected to the control input of N-bit data latch 1011. N is the number of bits of resolution at which the analog signal 1015 is digitized (converted) by the analog-to-digital converter. N is an arbitrary number and is typically between 8 and 16 for most applications. The data input of the N-bit data latch 11 is connected from the gray code generator 1045 to the digital gray code bus 1062. Data latched by N-bit data latch 1011 (which is the code generated by gray code generator 1045) is provided on line 1017 to N-bit flip-flop 1019. N-bit flip-flop 1019 stores the data on line 1017 for a predetermined period after N-bit data latch 1011 stores the state of gray code generator 1045, thereby making the system metastable. Decompose sex. Digital output 1047 is provided as described above.
Reference is now made to FIG. 14 which shows a schematic block diagram of the analog waveform generator 1030 illustrated in FIG. The operational amplifier 1032 supplies the analog ramp signal 1018 by supplying the output signal to the integrating capacitor 1028. The RESET signal 1034 is generated by timing circuit 1033 and activates switch 1028A to discharge capacitor 1028 when a new conversion must be initiated. One input 1039 of the operational amplifier 1032 is connected to the RAMP_BIAS signal, and the second input 1023 is connected to the output of the programmable current source 1031. Programmable current source 1031 is controlled by operational transconductance amplifier 1027. Amplifier 1027 has a first input connected to analog ramp signal 1018. The second input of the amplifier 1027 is connected to the ramp reference voltage RAMP_REF. The third input of the amplifier 1027 is connected to the output of the lamp adjustment circuit 1029. The starting voltage of the analog ramp can be adjusted by changing the RAMP_BIAS voltage. The slope of the analog ramp signal 1018 is controlled by the amplifier 1027. By changing the output of programmable current source 1031 in response to current signal 1027A from transconductance amplifier 1027, the slope of analog ramp signal 1018 can be changed. In response to the control signal 1033A from the timing circuit 1033 sent just before the ramp signal 1018 must end, the ramp adjustment circuit 1029 turns on the amplifier 1027 via the control signal 1029A to turn on the RAMP_REF voltage and the analog ramp. The difference between the voltages of signal 1018 is sampled. The transconductance amplifier 1027 converts this voltage difference into a current 1027A used for controlling the programmable current source 1031. After the programmable current source 1031 has been adjusted, the timing circuit 1033 turns off the amplifier 1027, opens the feedback loop, sends out the RESET signal 1034, and outputs the RESET signal 1034 via the control signal 1033A, using the switch 1028A. After discharging 1028, switch 1028A is opened and another integration cycle begins.
Reference is now made to FIG. 15, which is a schematic block diagram of parallel analog / digital converters 1010A and 1010B. For clarity, only two converters are shown and there may be m converters in the array. In one preferred embodiment, there are 328 converters in the array. Each analog / digital converter is connected to a digital gray code bus 1062 and an output bus 1057. A digital gray code bus 1062 is connected to each data input of the m data latches. For clarity, only the connections to data latches 1024A and 1024B are shown. The data input of each data latch is driven by a gray code generator 1045. N-bit output bus 1057 is connected to the data output of each transfer latch (latch 1026A and 1026B shown) and is read by multiplexer read circuit 1059.
The analog signal on line 1015A, which is the signal to be converted, is stored in capacitor 1023A until sampling switch 1012A is closed, thereby transferring charge to capacitor 1016A. Capacitor 1016A integrates analog signal 1015A until switch 1012A is opened. When the predetermined time interval elapses, switch 1012A is opened and switch 1025A is closed, thus resetting capacitor 1023A at the beginning of each conversion period. One skilled in the art will recognize that any charge transfer element or circuit can be used to transfer the signal to be compared. During the readout phase, the sampled signal 1014A is compared with the analog ramp signal 1018 by the comparator 1020A. If the sampled signal 1014A is equal to or at some predetermined potential relative to the analog ramp signal 1018, the output 1022A of the comparator 1020A activates the latch 1024A. The output of comparator 1020A is connected to the enable input of latch 1024A. A latch 1024A connected to the digital gray code bus 1062 stores the state of the gray code count when the analog ramp signal 1018 is equal to the signal 1014A sampled in response to the comparator output signal 1022A. The output of the latch 1024A is supplied to the transfer latch 1026A. An output control shift register 1054 connected to transfer latches 1026A and 1026B selects the output of a particular analog / digital converter from the array of converters. The output of each transfer latch is connected to a sense amplifier 1053 via an N-bit output bus 1057, which is part of the multiplexer read circuit 1059. At any one time, only one transfer latch is active, providing an output to bus 1057. The output control register 1054 is synchronized with the input clock 1068.
Here, the multiplexer read circuit 1059 is described. Those skilled in the art will appreciate that each of the circuit blocks in multiplexer read circuit 1059 is N bits wide to handle the number of bits from each transfer latch. The output of sense amplifier 1053 is connected to the input of input register 1055 which is clocked by input clock 1068. Input register 1055 latches data on N-bit output bus 1057, where the transfer latch is enabled by output control shift register 1054 from either N-bit. The output of register 1055 is connected to the input of metastable decomposition register 1036, also clocked by input clock 1068. The metastable decomposition register 1036 receives data from the input register 1055 that is one complete clock cycle after the state of the N-bit output bus 1057 is latched into the input register 1055. Clocked to be supplied to the input. Register 1036 resolves the metastability of the conversion that may have occurred when the digital signal on bus 1062 was latched by the output signal 1022A from analog comparator 1020A. As a result of the circuit analysis of the latch array, the metastability of the system is at least 2 by adding the metastable decomposition register 1036. ³⁰ It was shown that it was improved by a factor of. The output of metastable decomposition register 1036 is connected to a gray code decoder 1038 that converts the gray code signal to a standard binary signal. The gray code decoder 1038 is an exclusive OR in which the output of each latch in the metastable decomposition register 1036 is exclusively ORed (XOR) with adjacent bits that are sequentially exclusive ORed with another bit or the like. The process of taking (XORing) may be used. The standard binary N-bit code output by the gray code decoder 1038 is provided to the data input of an N-bit output register 1071 that latches the output value in response to the input clock 1068. The output of the output register 1071 is supplied to an N output driver 1073 that supplies an N-bit converted binary output signal 1047.
The input clock 1068 is also supplied to a clock multiplication phase locked loop circuit 1050 that generates a high-speed clock 1064. In one embodiment of the invention, the clock multiplier is a 12x clock multiplier. In one embodiment of the present invention, for example, the input clock 1068 is a 7 MHz nominal clock, and the clock multiplier 1050 increases this to 12 times 84 MHz.
Here, a gray code generator 1045 is described. In one embodiment of the present invention, the digital gray code on bus 1062, which is an N-bit binary gray code, comprises the least significant bit 1060, the least significant next bit 1058, and the N-2 bit code. It is generated by a chain of three bit streams, Gray Code Word 1056. A high speed clock 1064 clocks the N-2 bit synchronous binary counter 1048. The N-2 bit sync counter 1048 provides the output signal to the N-2 bit gray code encoder 1046. The gray code encoder provides the N-2 most significant bit 1056 of the digital gray code on bus 1062. Gray code encoder 1046 provides a gray code by XOR (exclusive OR) each bit output by counter 1048 with the adjacent output bit.
The fast clock 1064 and the least significant bit 1049 of the N-2 bit sync counter are connected to the negative edge trigger flip-flop 1044. Negative edge triggered flip-flop 1044 provides the least significant next bit signal, LSB + 1 1058, as part of the digital gray code on bus 1062.
High speed clock 1064 is also connected to 90 ° analog phaser 1042. The 90 ° phase shifter 1042 generates the least significant bit signal LSB 1060 as part of the digital gray code on the bus 1062 by shifting the high speed clock 1064 by 90 °.
In one implementation, N is equal to 13 bits, and sync counter 1048 and gray code encoder 1046 supply the 11 most significant bits on gray code bus 1062. The twelfth bit (LSB + 1) is provided by dividing the (about) 75 MHz clock by 2 and then latching it on the falling edge of the 75 MHz clock of flip-flop 1044. The thirteenth bit (LSB) is generated by delaying the 75 MHz clock by an exact 90 ° that is 1/4 of one complete clock cycle in the closed loop phaser 1042. This type of phaser is also called a delay locked loop.
Reference is now made to FIG. 16, which illustrates in further detail the clock multiplication phase locked loop 1050 of FIG. The clock multiplier 1050 includes a phase detector 10100 that detects the phase difference between the input clock 1068 and the frequency divided version of the high speed clock 1064 on the line 102. The output 10104 of the phase detector 10100 is used to control a frequency multiplied voltage controlled oscillator (VCO) 10106. The VCO 10106 increases the frequency of the input clock 1068 by a predetermined coefficient. In one example, the VCO 10106 increases the frequency of the input clock 1068 by a factor of 12 and generates a high speed clock 1064. The output 10108 of the VCO 10106 is supplied to a “square” circuit 10110. The function of the squaring circuit 10110 is to shape the output signal 10112 so that the high-speed clock 1064 has a 50% impact coefficient, or “squared” output. The high-speed clock 1064 is supplied to an n-dividing circuit 10114 that divides the frequency by a coefficient n so that the frequency of the clock signal transmitted on the line 10102 is equal to the frequency of the input clock 1068. As described above, in one embodiment, if the VCO 10106 increases the clock frequency by a factor of 12, the frequency of the high speed clock 1064 is reduced by division in the n divider circuit 10114 before supplying the signal to the phase detector 10100. N will be 12 as reduced by a factor of 12. In one embodiment, VCO 10106 may include a ring oscillator.
Reference is now made to FIG. 17, which is a schematic block diagram of the 90 ° analog phaser 1042 illustrated in FIG. High-speed clock 1064 and its complement from clock multiplier 1050 are connected to a first clock input and a second clock input of a four-input exclusive OR (XOR) gate 1080. XOR gate 1080 includes an output that is coupled to the inverting input of high gain integrating amplifier 1082. Amplifier 1082 outputs a control signal 1083 that is coupled to the control input of voltage controlled delay circuit 1078. The voltage control delay circuit 1078 receives a clock drive signal from the high-speed clock 1064. The high gain of amplifier 1082 ensures that the delay is always 90 °, even when there are variations in component values and clock frequency. The voltage control delay circuit 1078 outputs a delay signal to the “square” circuit 1077 in response to the control signal 1083 and the clock 1064. The squaring circuit 1077 shapes the delayed signal so that the delayed signal is symmetric and has a 50% impact coefficient (ie, “squared” output) and outputs the signal to the input of the line driver inverter 1075. The squaring circuit 1077 is similar to the squaring circuit 10110 described above. The line driver inverter 1075 outputs the first line driver inverter signal 1075A and the second line driver inverter signal 1075B to the third input and the fourth input of the 4-input exclusive OR gate 1080. The first line driver inverter signal and the second line driver inverter signal are also coupled to a first input and a second input of delay matching circuit 1081. Signals 1075A and 1075B include complementary delayed clocks. The delay matching circuit 1081 ensures that the delay experienced by each signal 1075A and 1075B is the same so that the signals remain in proper phase relationship with each other. The delay matching circuit 1081 outputs the LSB 1060.
Reference is now made to FIG. 18, which is a schematic block diagram of a modified embodiment of the circuit of FIG. In the circuit of FIG. 18, the 90 ° phase shifter 1042 of FIG. 15 is omitted. Further, the clock multiplier 1050 has been modified to provide the LSB 1060 directly. In all other respects, the operation of FIG. 18 is the same as described above in connection with FIG.
Reference is now made to FIG. 19, which is a schematic block diagram of the clock multiplier 1050 of FIG. In FIG. 19, as in FIG. 16, the input clock 1068 is provided to a phase detector 10100 that provides a voltage controlled oscillator 10120 control signal 10104 in response to the input clock 1068 and the signal 10102. The VCO 10120 multiplies the output frequency supplied to the squaring circuit 10110 on the line 10108 to generate the high speed clock 1064 on the line 10112. The output of the squaring circuit 10110 is further provided on line 10112 to an n-dividing circuit 10114 that sends a control signal 10102 in a manner similar to that described with respect to FIG.
The VCO 10120 is 90 ° out of phase with the output 10108 and then provides a second output 10122 that is fed to another squaring circuit 10110. Square circuit 10110 operates as described above with respect to FIG. 16 and provides a “square” output for LSB 1060 on line 10124.
Here, reference is made to FIG. 20, which is a schematic diagram of the VCO 10120. VCO 10120 provides two outputs 10108, 10122 that are 90 degrees out of phase with each other. VCO 10120 is a ring oscillator formed from an odd number of inverter stages connected in a loop. More specifically, VCO 10120 includes inverters 10126, 10128, 10130, 10132 and 10134. The output of inverter 10134 is connected to the input of inverter 10126 via line 10136 to form a ring. When t is a time delay in one inverter and p is the number of stages in the oscillator, the oscillation frequency f is as follows.
(1) f = 1 / (2pt)
The change of frequency is achieved by changing the power supply voltage of the inverter chain and changing the time t. In the case of a CMOS inverter, the transport delay increases as the power supply voltage decreases.
The phase deviation for each stage in the ring oscillator is as follows.
(2) Phase / stage = 180 / p
For example, in the 5-stage oscillator illustrated in FIG. 20, the phase deviation for each stage is 36 °. Therefore, a tap that is two steps away from the main output has a phase deviation of 72 °, while a phase deviation of a tap that is three steps away from the main output is 108 °. If all of the inverters are the same, a 90 ° phase excursion is not possible.
However, if the various inverters in the ring oscillator are not configured identically, a 90 ° phase shift between the inverters in the ring oscillator is obtained. In the case of a CMOS inverter, the delay through the inverter depends on many factors, including the size and shape of the component transistors and the amount of capacitive load on the output. Any of these factors can be adjusted to take advantage of increasing the carrier delay of one of the inverters relative to the remaining inverters in the ring to achieve the required 90 ° phase excursion.
In the case of the VCO 120 shown in FIG. 20, the carrier delay of the inverter 10130 is adjusted by adding two transistors 10138 and 10140 that are biased to always be on. This increases the transport delay through inverter 10130, so the total delay through inverters 10134, 10126, and 10128 is approximately the same as the delay through modified inverter 10130 and inverter 10132. If the delay through inverters 10134, 10136 and 10128 is the same as the delay through modified inverters 10130 and 10132, the phase excursion between outputs 10108 and 10122 will be exactly 90 °.
Reference is now made to FIG. 21 which is a schematic circuit diagram of the squaring circuit 10110 illustrated in FIGS. The square circuit 1077 in FIG. 17 operates in the same manner as the square circuit 10110.
As shown in FIG. 21, the output of the VCO 10120 is supplied to the squaring circuit 10110. Obviously, the circuit shown in FIG. 19 has two square circuits, one for each output of the VCO 10120.
In general, the VCO 10120 operates at a reduced voltage compared to the rest of the circuit, so the outputs 10108 and 10122 need to be translated to a higher voltage level of the rest of the circuit. In addition, the carrier delay is generally not the same at the rising and falling edges of the output signal, so even if the signal in the ring oscillator is symmetric, the output of the level translation circuit is not symmetric, ie, a “square” output Or having an impact coefficient of 50%. In this way, circuit 10110 incorporates a level converter in a closed loop feedback circuit that adjusts the input threshold required to maintain the symmetry of the output signal.
The level shifter includes transistors 10150 and 10152 and inverters 10154 and 10156. Two current source transistors 10158 and 10160 are controlled by voltages VMINUS and VPLUS. Voltages VMINUS and VPLUS are supplied by current mirror 10162 and control the amount of current delivered by transistors 10158 and 10160. The feedback loop of signal 10112 or 10124 is provided to level shift transistors 10150 and 10152 through transistors 10158, 10160, 10164. When the waveform of the output signal 10112 or 10124 becomes asymmetric, i.e., not "square", the transistors 10158, 10160 change the gate voltage on the input stage current source transistor 10150 in a direction to reset the output symmetry. To respond. In addition, transistor 10164 used as a capacitor filters out any ripple voltage and sets the response time of the feedback loop.
Here, reference is made to FIG. 22 which is a timing diagram of LSB 1060 and LSB + 1 1058. The timing chart of FIG. 22 shows the operation of the circuit of FIG. 15 or the circuit of FIG. The high speed clock 1064 transitions from low to high at time 3. The least significant bit 1049 on the N-2 bit binary counter 1048 transitions during the transition of the high speed clock 1064 from low to high. LSB 1060 derived from high speed clock 1064 transitions to a high level at time 5 and to a low level at time 9. Derived from the least significant bit 1049 of the counter. LSB + 1058 transitions to a high level at time 7 and transitions to a low level at time 2. The N-2 most significant bit 1056 of the gray coded signal transitions only at time 3, while the LSB 1060 and LSB + 1058 signals do not change at time 3. At times 2, 5, 7 and 9, only one of these signals changes at a time, thus meeting the gray code requirement of only a single bit change when there is a change in count.
One skilled in the art will be able to control counter 1048, flip-flop 1044, and 90 ° phase shifter 1042 using an external high-speed clock rather than using an input clock signal having a frequency that is multiplied to provide a high-speed clock. Let's understand.
One advantage of the present invention is that the gray code least significant bit frequency is equal to the frequency of the clock used to control the circuit. That is, the frequency of the least significant bit is equal to the maximum toggle frequency of the flip-flop. Traditionally, in a typical gray code, the master clock frequency is four times the least significant bit of the gray code. In the present invention, in contrast, the frequency of the least significant bit of the Gray code can be equal to the clock frequency. Thus, the clock frequency is limited only by the inherent frequency limitation of the clock counter circuit itself. As a result, a higher conversion speed than that which can be achieved in the past can be realized.
For a normal 2 micron CMOS process at room temperature, this frequency limit is about 150 MHz and about 500 MHz at 80 ° K. For a 1 micron CMOS process, this frequency limit is approximately 500 MHz at room temperature and may exceed 1 GHz at 80 ° K. In one embodiment of the present invention, a 72 MHz master clock generates a 3.5 ns resolution gray code that allows 13-bit conversion in 30 μs. The 500 MHz master clock generates 500 ps resolution gray code and allows 16-bit conversion at 33 μs or 12-bit conversion at 2 μs. Using several hundred of these converters on one chip, the total conversion rate may be about 100 MHz. The estimated power is below 50 μw per channel. As a result, such an array of converters can be used on a single chip, resulting in a relatively fast conversion speed, but if the power consumption is low, the present invention provides a relatively slow analog / digital conversion. It is possible to use a single tilt method. Furthermore, the simple design of single slope analog / digital converters saves power and allows integration of the majority of these converters on a single integrated circuit, especially when using CMOS technology. .
The gray code count is used as a digital signal that is stored when the comparator is activated because, by definition, only one bit changes for each code increment. When the latch is enabled, only one of the gray coded bits can enter the process of change, so only one of the sampled bits can exhibit metastability. Instead, the resulting code is unstable by one least significant bit. This is in contrast to the case where standard binary codes are used as stored digital signals. Since multiple bits can change for each increment of code, many sampled bits can exhibit metastability.
Using gray code count allows the metastable decomposition to be advantageously determined at a point in the circuit when there is more time to complete it, thus reducing the need for circuit power and speed. Reduced. As a result, in the present invention, metastable decomposition can be postponed until after data multiplexing when the data rate is much lower than the rate at which the data is supplied by each analog / digital converter. Particularly in conventional circuits, metastability decomposition could usually be provided when the binary code from the counter is clocked by the N-bit data latch. To that end, it may be necessary to perform metastable decomposition at very high clock rates and at very short intervals. As previously noted, in contrast to this, the present invention can achieve this function using a very slow clock speed that reduces the power and speed requirements of the circuit.
For example, a gray code may be generated using a (about) 75 MHz clock. This 75 MHz clock is generated from a (approximately) 6 MHz input clock. The 75 MHz clock is used for analog / digital conversion only. The 6 MHz clock is used for all other functions of the integrated circuit.
By using an array of 328 converters, the conversion is completed in about 30 microseconds with 13-bit resolution. Conventional methods require, for example, a master clock frequency of about 300 MHz, which is higher than the capabilities of a conventional 2 micron CMOS process. The use of gray code allows metastable decomposition to be performed at a rate of 6 MHz with 13 bits instead of 300 MHz on 328 comparators.
The present invention further provides a method for converting an analog signal from an array of analog / digital converters with a high effective clock speed and increased resolution. A number of input signals, one for each converter, are sampled and held. The signal is formed by integrating the current from the analog source. This signal is kept constant on the capacitor during the conversion process. The analog ramp and digital counter are then started simultaneously. The comparator circuit compares the lamp voltage with the sampled and held voltage. If they are equal, the output of the comparator changes state and the value of the digital counter is stored in an N-bit latch. Values stored in an array of latches, which are digital representations of various input voltages, are transferred in parallel to another array of latches. A new group of transformations is then performed, while the results of the previous transformations are multiplexed to form a digital output signal.
In the case of an array of converters, the digital counter and ramp generator are common to all converters. Each converter itself requires only an array of sampling and holding, comparators and digital latches.
The circuit of the present invention may be monolithically integrated in semiconductor form using conventional CMOS technology.
While at least one exemplary embodiment of the present invention has been described above, various changes, modifications and improvements will occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended as limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.

Claims (3)

In a plurality of sensor unit cells arranged as a two-dimensional grid for detecting radiation, each unit cell emulates an image signal connected in parallel with the sensor that outputs an image signal based on the detected radiation. A plurality of sensor unit cells, including test transistors that output test signals to be
A processing circuit that processes the image signals from the plurality of sensor unit cells and outputs processed image data based on the image signals,
The plurality of sensor unit cells and the processing circuit are formed monolithically on a semiconductor substrate in one integrated circuit chip,
The processing circuit includes a test circuit that operates the test transistor of each unit cell to output the test signal;
The processing circuit outputs the processed image data based on the test signal from each unit cell when the test transistor is activated.
The apparatus, wherein the sensor is a bolometer. The device according to claim 1,
The sensor has a sensor resistance;
The activated test transistor has an on-time resistance equal to the sensor resistance. The device according to claim 1,
The two-dimensional grid includes a column of unit cells, each column having a column output for supplying the image signal and the test signal from the unit cell;
Each unit cell further includes a switch connecting the sensor and the test transistor between a common supply bus and the column output.

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