JP3839021B2 - Power system - Google Patents

Description

  The present invention relates to a power supply system including a plurality of power supply devices that perform a parallel operation.

Conventionally, many power supply systems in which a plurality of power supply devices perform a parallel operation have been disclosed (for example, see Patent Documents 1 and 2). Among them, when a plurality of power supply devices are started simultaneously, a synchronization signal is input / output between the plurality of power supply devices, and the process of setting the output voltage to a predetermined value is performed synchronously based on the synchronization signal. There is a power system.
Japanese Patent Laid-Open No. 01-209925 Japanese Patent Laid-Open No. 04-0669016

  However, in the conventional power supply system, if a new power supply device is additionally connected during parallel operation of a plurality of power supply devices, a synchronization signal is output from the added power supply device to the already operating power supply device. The output voltage setting process is performed again up to the operating power supply device in synchronization with the operated power supply device, thereby causing an output voltage abnormality in the operating power supply device.

  Accordingly, an object of the present invention is to provide a power supply system that can prevent an output voltage abnormality from occurring in a power supply device that is already operating when a new power supply device is additionally connected during the parallel operation of a plurality of power supply devices. Is to provide.

  In order to achieve the above object, according to the power supply system of the present invention, each of a plurality of power supply devices that perform parallel operation detects the output voltage of the constant voltage circuit when the power supply device of the power supply device starts up, and the output voltage reaches a predetermined value. A synchronization signal connection circuit that disconnects the synchronization signal input / output terminal for inputting / outputting the synchronization signal to / from another power supply device from the output voltage synchronization activation circuit. There is.

  Therefore, even if a new power supply device is additionally connected to a plurality of power supply devices operating in parallel, the synchronization signal output from the added power supply device is not input to the operating power supply device. In the power supply device, the output voltage is kept constant, thereby preventing the occurrence of an output voltage abnormality.

  As described above, according to the present invention, even when another power supply device is additionally connected to a plurality of power supply devices operating in parallel, the output voltage is maintained constant in the operating power supply device. It is possible to prevent the occurrence of an abnormality, and it is possible to perform the output voltage setting process normally even in the added power supply apparatus, thereby enabling stable parallel operation.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
The configuration of the power supply system of the present invention will be described with reference to FIG.

  Referring to FIG. 1, the power supply system of the present invention has two power supply devices A and B that perform parallel operations. When the power supply devices A and B are simultaneously activated, the power supply devices A and B mutually input and output synchronization signals in order to synchronize the process of setting the output voltage to a predetermined value. In FIG. 1, only two power supply devices A and B are shown, but there is no particular limitation as long as the number of power supply devices is two or more.

  The power supply devices A and B have an output voltage synchronous start circuit 20 having a constant voltage output circuit 10 and a synchronization signal input / output terminal P2 for inputting / outputting a synchronous signal between the power supply device and another power supply device when the power supply device is started. And an output voltage control unit 30 that performs control to set the output voltage of the constant voltage circuit 10 to a predetermined value using a synchronization signal input / output to / from the synchronization signal input / output terminal P2 as necessary when the power supply device is started. And have. Further, the output voltage synchronous start circuit 20 detects the output voltage of the constant voltage circuit 10 when starting its own power supply device, and synchronizes with the output voltage synchronous start circuit 20 when determining that the output voltage has reached a predetermined value. A synchronization signal connection circuit 40 is provided to bring the signal input / output terminal P2 into a disconnected state.

  Since the power supply devices A and B have the same function and the same internal circuit, only the configuration of the power supply device A is shown in detail in FIG. 1, and the configuration of the power supply device B is partially omitted. Are shown. Therefore, hereinafter, only the connection state of each component of the power supply device A will be described in detail, and the connection state of each component of the power supply device B will be omitted.

  In the power supply device A, an external ON signal 100A is input to the base of the transistor Q1 in the output voltage synchronous start circuit 20, the control power supply Vcc is connected to the emitter of the transistor Q1, and the resistor R1 is connected in series to the collector of the transistor Q1. One end is connected, and the resistor R2 and the capacitor C1 connected in parallel are connected in series to the other end of the resistor R1. The anodes of the diode D1 are connected to the contacts of the resistors R1, R2 and the capacitor C1, the anode of the diode D2 is connected to the cathode side of the diode D1, and the output voltage control unit 30 is connected to the cathode side of the diode D2. One input terminal of the comparator Z1 is connected. A synchronization signal connection circuit 40 is also connected to the cathode side of the diode D1, and the synchronization signal connection circuit 40 is input from the other power supply device B at the output end of the synchronization signal 200A output to the other power supply device B. There is a synchronization signal input / output terminal P2 which is also an input terminal of the synchronization signal 200B. In addition, a diode D3 is inserted in a subsequent stage (plus output side) of the constant voltage output circuit 10 serving as an output terminal of the output voltage of the power supply device A, and on the anode side of the diode D3, a synchronization signal connection circuit 40, One input terminal of the comparator Z1 in the output voltage control unit 30 is connected. The reference voltage Vref1 is input to the other input terminal of the comparator Z1. Although not shown, the output terminal of the comparator Z1 is connected to the constant voltage output circuit 10.

  Next, the configuration of the synchronization signal connection circuit 40 according to the first embodiment of the present invention will be described with reference to FIG.

  Referring to FIG. 2, the synchronization signal connection circuit 40 has an output voltage detection terminal P1 serving as a detection terminal for the output voltage of the constant voltage output circuit 10 as a signal input / output terminal with respect to an external circuit, and each of the power supply devices A and B. A synchronization signal input / output terminal P2 serving as an input / output terminal for the synchronization signals 200A and 200B and an output voltage control section terminal P3 serving as an output terminal for the synchronization signals 200A and 200B to the output voltage control section 30 are provided.

Further, the synchronization signal connection circuit 40 has the output voltage detection terminal P1 connected to the negative input side, and the reference voltage Vref2 is input to the positive input side, and the output voltage based on the comparison result between the output voltage and the reference voltage Vref2. Is connected to the output terminal of the comparator Z1, the drain is connected to the sync signal input / output terminal P2, and the source is connected to the output voltage control unit terminal P3. When it is determined that the output voltage has reached a predetermined value according to the output value of the comparator Z1, the FET Q2 that controls the output signal synchronous start circuit 20 to disconnect the synchronization signal input / output terminal P2 and the gate of the FET Q2 are controlled. And a resistor R3 that is pulled up to the power source Vcc.

  In FIG. 1, when the power supply devices A and B perform parallel operation, the connection between the cathodes of the diodes D3 at the output terminals (plus output side) of the power supply devices A and B, and the negative output side of the power supply devices A and B. And the output terminals of the synchronization signals 200A and 200B of the synchronization signal connection circuit 40 of the power supply devices A and B are connected by connectors P +, P− and Ps, respectively.

  Hereinafter, in the power supply system according to the present embodiment, the operation when starting the power supply apparatuses A and B will be described with reference to FIGS. 1 and 2.

  First, the operation when the power supply device A is activated alone will be described.

  First, in the output voltage synchronous activation circuit 20 of the power supply device A, the level of the ON signal 100A changes from low level to high, and the high level ON signal 100A is applied to the base of the transistor Q1. Then, the transistor Q1 is turned off, and the voltage applied to the output voltage control unit 30 from the control power supply Vcc via the resistor R1 and the diodes D1 and D2 is turned off. Instead, the voltage Vc1 of the capacitor C1 charged by the control power supply Vcc when the transistor Q1 is in the ON state is discharged to the output voltage control unit 30.

  At this time, in the synchronization signal connection circuit 40 of the power supply device A, the voltage level of the output voltage detection terminal P1 that is the negative input of the comparator Z2 is during a period that is equal to or lower than the reference voltage value Vref2 that is the positive input of the comparator Z2. The output of the comparator Z2 becomes the control voltage level of the control power supply Vcc via the resistor R3, and the FET Q2 is turned on. When the FET Q2 is in the ON state, the capacitor voltage Vc1 that is the voltage level of the output voltage control unit terminal P3 is output to the power supply device B as the synchronization signal 200A. On the other hand, since the power supply apparatus B is not activated, the synchronization signal 200B of the power supply apparatus B is not input to the synchronization signal connection circuit 40 of the power supply apparatus A. Therefore, the synchronization signals 200A and 200B are output from the output voltage control unit 30. Is not entered.

  Next, in the output voltage control unit 30 of the power supply device A, the total value of the capacitor voltage Vc1 from the output voltage synchronous start circuit 20 and the output voltage of the constant voltage output circuit 10 is compared with the reference voltage Vref1 by the comparator Z1. Control is performed to set the output voltage of the constant voltage output circuit 10 to a predetermined value so that the value becomes equal to the reference voltage Vref1. Thereby, a voltage having a predetermined value set by the output voltage control unit 30 is output from the constant voltage output circuit 10.

  After that, when the output voltage of the constant voltage output circuit 10 reaches a predetermined value set by the output voltage control unit 30 in the synchronization signal connection circuit 40 of the power supply device A, the output terminal of the comparator Z2 in FIG. It will be in the OFF state. As a result, the synchronization signal input / output terminal P2 is disconnected from the output voltage synchronization activation circuit 20.

  Next, the operation when the power supply devices A and B are activated simultaneously will be described.

  First, when the high-level ON signals 100A and 100B are respectively applied to the output voltage synchronous starting circuits 20 of the power supply devices A and B, the capacitor voltages Vc1 are supplied to the output voltage control unit 30 in the same manner as described above. And discharge.

  At this time, in each of the synchronization signal connection circuits 40 of the power supply devices A and B, as described above, during the period in which the voltage level of each output voltage detection terminal P1 is equal to or lower than the reference voltage value Vref2, The output becomes the control voltage level of the control power supply Vcc via the resistor R3, and each FET Q2 is turned on.

  In each synchronization signal connection circuit 40 of the power supply devices A and B, when each FET Q2 is ON and the synchronization signals 200A and 200B are output, the cathode side of each diode D1 of the synchronization signals 200A and 200B. The synchronization signal of the power supply device having the higher potential is applied to each output voltage control unit 30 via each diode D2.

  That is, in the output voltage control unit 30 of each of the power supply devices A and B, since the applied voltage is at the same potential level, the above-described output voltage setting process is performed with the voltage at the same potential level, The output voltage setting process is synchronized between the power supplies A and B.

  Thereafter, when the output voltage of each constant voltage output circuit 10 reaches a predetermined value set by the output voltage control unit 30 in each of the synchronization signal connection circuits 40 of the power supply devices A and B, the output terminal of each comparator Z2 is Each of the FETs Q2 is turned off, and each of the synchronization signal input / output terminals P2 is disconnected from the output voltage synchronous activation circuit 20. However, since the power supply devices A and B have already been started, no problem occurs.

  Next, an operation when the power supply device B is additionally connected to the power supply device A during the operation of the power supply device A will be described.

  In this case, in the synchronization signal connection circuit 40 of the power supply device A, since the power supply device A has already been activated and the FET Q2 is in the OFF state, the synchronization signal input / output terminal P2 in FIG. It is in a disconnected state.

  For this reason, when the power supply apparatus B is additionally connected, the synchronization signal 200B output from the synchronization signal connection circuit 40 of the power supply apparatus B does not affect the power supply apparatus A. Therefore, even when the output voltage setting process is performed on the power supply apparatus B side as described above, the output voltage setting process is not performed again on the power supply apparatus A side in synchronization therewith.

  Thereafter, when the output voltage of the constant voltage output circuit 10 of the power supply apparatus B also becomes a predetermined value, the FET Q2 is turned off in the synchronization signal connection circuit 40 of the power supply apparatus B, and the synchronization signal input / output terminal P2 is connected to the output voltage synchronous start circuit 20. It will be in the state disconnected from. Therefore, even if another power supply is additionally connected, the synchronization signal output from the added power supply does not affect the power supplies A and B that are already operating.

(Second Embodiment)
The configuration of the synchronization signal connection circuit 40 according to the second embodiment of the present invention will be described with reference to FIG. In the present embodiment, the time until the FET Q2 is turned off is delayed according to the comparison result of the comparator Z2. The present embodiment has the same configuration as that of FIG. 1 except for the configuration of the synchronization signal connection circuit 40.

Referring to FIG. 3, in the synchronization signal connection circuit 40 according to the present embodiment, the output voltage detection terminal P1 is connected to the negative input side, the reference voltage Vref2 is input to the positive input side, and the output voltage and the reference voltage Vref2 are input. Based on the comparison result, the comparator Z2 detects that the output voltage has reached a predetermined value, the resistor R4 has one end connected to the output end of the comparator Z2, and the output end of the comparator Z2 has the resistor R4 at the gate. Is connected to the drain, the sync signal input / output terminal P2 is connected to the drain, the output voltage control unit terminal P3 is connected to the source, and the output voltage becomes a predetermined value according to the output value of the comparator Z2 via the resistor R4. If it is determined that reaches the, the FETQ2 to a state of being cut sync signal input and output terminals P2 from the output voltage synchronous start circuit 40, controls the gate of the FETQ2 supply Vc To a resistor R3 to pull up connection, one end is connected to the gate of the FET Q2, the other end and a capacitor C2 is grounded. In FIG. 3, the output voltage detection terminal P1, the synchronization signal input / output terminal P2, and the output voltage control unit terminal P3 are connected in the same manner as in FIG.

  The comparator Z2 sets the output to a low level when detecting that the output voltage of the constant voltage output circuit 10 has reached a predetermined value, but when the output level of the comparator Z2 is at a high level, the control power supply Vcc passes through the resistor R3. Since the charging voltage Vc2 is charged in the capacitor C2, the time until the gate voltage of the FET Q2 decreases according to the discharge time constant by the capacitor C2, the resistor R3, and the resistor R4 is delayed, so that the FET Q2 is turned off. Time to be delayed. The purpose of this delay is to prevent the synchronization signal input / output terminal P2 from being disconnected when the power supply device is not sufficiently activated.

(Third embodiment)
The configuration of the synchronization signal connection circuit 40 according to the third embodiment of the present invention will be described with reference to FIG. The present embodiment delays the time until the FET Q2 is turned off according to the comparison result of the comparator Z2, and the purpose thereof is also the same. The present embodiment has the same configuration as that of FIG. 1 except for the configuration of the synchronization signal connection circuit 40.

Referring to FIG. 4, in the synchronization signal connection circuit 40 according to the present embodiment, the output voltage detection terminal P1 is connected to the positive input side, the reference voltage Vref2 is input to the negative input side, and the output voltage and the reference voltage Vref2 are input. Based on the comparison result, the comparator Z2 detects that the output voltage has reached a predetermined value, the FET Q3 whose gate is connected to the output terminal of the comparator Z2, the source is grounded, and the drain of the FET Q3 is the gate. The sync signal input / output terminal P2 is connected to the drain, the output voltage control unit terminal P3 is connected to the source, and the output voltage reaches a predetermined value according to the output value of the comparator Z2 via the FET Q3. If it is determined, the FETQ2 to a state of being cut sync signal input and output terminals P2 from the output voltage synchronous start circuit 40, controls the gate of FETQ3 A resistor R5 to pull-up connected to a source Vcc, a resistor R3 to pull up connected to the control power supply Vcc to the gate of the FET Q2, one end is connected to the gate of FET Q3, is grounded and the other end, are connected in parallel to each other A resistor R4 and a capacitor C2 are included. In FIG. 4, the output voltage detection terminal P1, the synchronization signal input / output terminal P2, and the output voltage control unit terminal P3 are connected in the same manner as in FIG.

  The comparator Z2 sets the output to a high level when the output voltage of the constant voltage output circuit 10 reaches a predetermined value. When the output of the comparator Z2 is set to a high level, the voltage Vc2 of the capacitor C2, which is the gate voltage of the FET Q3, is charged according to the charging time constant by the resistor R3, the resistor R4, and the capacitor C2, and the FET Q3 is turned on. . Then, since the FET Q3 is in the ON state, the gate voltage level of the FET Q2 becomes low, and until then, the FET Q2 that has been in the ON state by applying the control power source Vcc to the gate by the resistor R5 is in the OFF state.

It is a figure which shows the structure of the power supply system of this invention. It is a figure which shows the structure of the synchronous signal connection circuit which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the synchronizing signal connection circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the synchronizing signal connection circuit which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Constant voltage output circuit 20 Output voltage synchronous starting circuit 30 Output voltage control part 40 Synchronization signal connection circuit A, B Power supply device C1, C2 Capacitor D1-D3 Diode P1 Output voltage detection terminal P2 Synchronization signal input / output terminal P3 Output voltage control part End Q1 Transistor Q2, Q3 FET
R1-R5 Resistor Vcc Control power supply Vref1, Vref2 Reference voltage Z1, Z2 Comparator

Claims (4)

When having a plurality of power supply devices that perform parallel operation and simultaneously starting the plurality of power supply devices, the plurality of power supply devices input and output a synchronization signal to each other, and an output voltage is set to a predetermined value based on the synchronization signal. In the power supply system that synchronizes the processing set to
Each of the plurality of power supplies is
A constant voltage circuit;
An output voltage synchronous start circuit comprising a synchronous signal input / output terminal for mutually inputting and outputting the synchronous signal to and from another power supply device at the time of starting its own power supply device;
An output voltage control unit for performing control to set the output voltage of the constant voltage circuit to a predetermined value by using the synchronization signal input / output to / from the synchronization signal input / output terminal as necessary when starting up its own power supply device; Have
The output voltage synchronous start circuit detects the output voltage of the constant voltage circuit when starting its own power supply device, and determines that the output voltage has reached a predetermined value. A power supply system having a synchronizing signal connection circuit in which a signal input / output terminal is disconnected. The synchronization signal connection circuit includes:
An output voltage detection terminal, which is an output voltage detection terminal of the constant voltage output circuit, is connected to the negative input side, a reference voltage is input to the positive input side, and a comparison result between the output voltage and the reference voltage is used as a source. A comparator that detects that the output voltage has reached a predetermined value;
The output terminal of the comparator is connected to the gate, the synchronization signal input / output terminal is connected to the drain, and the output voltage control unit terminal that is the output terminal of the synchronization signal to the output voltage control unit is connected to the source. When the output voltage reaches a predetermined value in accordance with the output value of the comparator, the FET that makes the synchronous signal input / output terminal disconnected from the output voltage synchronous activation circuit,
The power supply system according to claim 1, further comprising a resistor that pulls up the gate of the FET to a control power supply. The synchronization signal connection circuit includes:
An output voltage detection terminal, which is an output voltage detection terminal of the constant voltage output circuit, is connected to the negative input side, a reference voltage is input to the positive input side, and a comparison result between the output voltage and the reference voltage is used as a source. A comparator that detects that the output voltage has reached a predetermined value;
A first resistor having one end connected to the output end of the comparator;
The output terminal of the comparator is connected to the gate via the first resistor, the synchronization signal input / output terminal is connected to the drain, and the output voltage is the output terminal of the synchronization signal to the output voltage control unit to the source When the control unit terminal is connected and the output voltage reaches a predetermined value according to the output value of the comparator via the first resistor, the synchronization signal input / output terminal is connected to the output voltage synchronization terminal. FET that is in a state disconnected from the startup circuit,
A second resistor that pulls up the FET gate to a control power supply;
The power supply system according to claim 1, further comprising: a capacitor having one end connected to the gate of the FET and the other end grounded. The synchronization signal connection circuit includes:
An output voltage detection terminal serving as a detection terminal for the output voltage of the constant voltage output circuit is connected to the positive input side, a reference voltage is input to the negative input side, and the comparison result between the output voltage and the reference voltage is used as a source. A comparator that detects that the output voltage has reached a predetermined value;
A first FET having a gate connected to the output terminal of the comparator and a source grounded;
The drain of the first FET is connected to the gate, the synchronization signal input / output terminal is connected to the drain, and the output voltage control unit terminal serving as the output terminal of the synchronization signal to the output voltage control unit is connected to the source. When the output voltage has reached a predetermined value according to the output value of the comparator via the first FET, the synchronization signal input / output terminal is disconnected from the output voltage synchronization start circuit. A second FET,
A first resistor that pulls up the gate of the first FET to a control power supply;
A second resistor that pulls up the gate of the second FET to a control power supply;
The power supply system according to claim 1, wherein one end is connected to the gate of the first FET, the other end is grounded, and the capacitor and the third resistor are connected in parallel to each other.

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