JP3838753B2 - Element isolation region structure and element isolation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an element isolation region structure and an element isolation method.
[0002]
[Prior art]
In recent years, MOSFETs including an SOI (Silicon on Insulator) structure have attracted attention as MOSFETs. The SOI MOSFET itself has the characteristics of improving the subthreshold (S) value, reducing the parasitic capacitance, reducing soft errors (malfunction caused by the incidence of α rays), preventing latch-up, and the like. This SOI MOSFET can realize a high-speed device and a low power consumption device.
[0003]
As an element isolation method of the SOI structure, there is an example using a PELOX (Polysilicon Encapsulated Local Oxidation) method (Reference: 1995, Symposium on VLSI Technology of Technical Papers, p. 38).
[0004]
According to this conventional PELOX method, element isolation is performed by the following steps. A SIMOX (Separation by Implanted Oxygen) substrate is used as the substrate. This substrate is a substrate obtained by forming a buried oxide film in a silicon substrate and separating the silicon layer into two. A pad oxide film and a nitride film pattern are sequentially formed on the substrate.
[0005]
Next, using a wet etching method, the pad oxide film existing in the region of the lower surface of the nitride film pattern is left, and the other pad oxide films are removed by etching.
[0006]
Next, a thin oxide film is again formed on the exposed silicon layer using any suitable method.
[0007]
Next, the nitride film pattern and the oxide film are covered with a polysilicon layer. Subsequently, the entire polysilicon layer is changed to an oxide film by thermal oxidation, and a part of the silicon layer on the buried oxide film is changed to a field oxide film, so that the first silicon layer region is only in the lower region of the nitride film pattern. To remain.
[0008]
Thereafter, the field oxide film on the nitride film pattern, the nitride film pattern, and the pad oxide film existing on the lower surface of the nitride film pattern are sequentially removed by etching.
[0009]
The element separation is performed through the above-described steps.
[0010]
[Problems to be solved by the invention]
However, according to the element isolation method using the conventional PELOX method described above, the number of steps is significantly increased as compared with the conventional LOCOS method, which causes an increase in cost.
[0011]
Further, when element isolation is performed by the PELOX method, when the cross section of the first silicon layer region embedded in the field oxide film is viewed, the first silicon layer region is not rectangular, and the first silicon layer region The lower region extends to the bottom of the field oxide film. For example, when a MOSFET is formed in such a skirt-like first silicon layer region, it is known that a hump occurs in the Id-Vg characteristic (Document II: IEICE Technical Report, TECHNICICAL REPORT OF IEICE. SDM 95-263, 1996-03, pp. 1-6).
[0012]
When such a hump occurs, the transistor operates at a voltage lower than the normal transistor characteristics, which is not preferable.
[0013]
Therefore, it has been desired to develop an element isolation region structure capable of preventing the occurrence of humps and an element isolation method capable of reducing the number of processes.
[0014]
[Means for Solving the Problems]
Therefore, according to the element isolation region structure of the present invention, the insulating film, the field oxide film provided on the insulating film, and the field oxide film on the insulating film surrounded by the field oxide film are not in contact with each other. A first silicon layer region provided in a state; and a second silicon layer region that covers the exposed surface of the first silicon layer region and is formed by epitaxial growth. In the present invention, an SOI (Silicon on Insulator) layer is constituted by the first silicon layer region and the second silicon layer region.
[0015]
In the present invention, since the SOI layer is constituted by the first silicon layer region and the second silicon layer region covering the exposed surface of the first silicon layer region, when the cross-sectional shape of the SOI layer is viewed, compared to the conventional case. The film thickness of the bottom portion of the first silicon layer region can be increased. For this reason, when, for example, a MOSFET is formed using this SOI layer, humping of the Id-Vg characteristic can be prevented.
[0016]
In practicing the present invention, it is preferable that the substrate be a film constituting an SOI structure or a SIMOX structure. By using a substrate having such an SOI structure or SIMOX structure, the first silicon layer region is surrounded by the insulating film and the field oxide film, so that the element isolation is better than that of the conventional silicon substrate. .
[0017]
According to the element isolation method of the present invention, a step of sequentially forming a pad oxide film and a nitride film pattern on a substrate having a silicon layer on an insulating film, and a silicon layer by thermal oxidation A region of the substrate is oxidized into a field oxide film, and a first silicon layer region for forming a semiconductor element is left below the nitride film pattern, and the nitride film pattern and the nitride film pattern are etched. A part of the pad oxide film and the field oxide film remaining on the lower surface is sequentially removed to project the first silicon layer region on the insulating film, and the entire surface of the first silicon layer region is selected using a selective epitaxial technique. And a step of forming a second silicon layer region by epitaxial growth.
[0018]
According to the element isolation method of the present invention, the step of sequentially forming the pad oxide film and the nitride film pattern on the substrate using the substrate having the silicon layer on the insulating film, and the thermal oxidation of the silicon layer A part of the region is changed to a field oxide film, and a step of leaving the first silicon layer region for forming a semiconductor element under the nitride film pattern is left, and the field oxide film and the pad oxide film are simultaneously etched using wet etching. A step of leaving a part of the pad oxide film on the lower surface of the nitride film pattern and projecting the first silicon layer region on the insulating film; and a surface of the first silicon layer region using a selective epitaxial technique. Forming a second silicon layer region by epitaxial growth, and then remaining on the lower surface of the nitride film pattern and the nitride film pattern by etching; Characterized in that it comprises the step of sequentially removing the pad oxide film that.
[0019]
By such a process, since the second silicon layer region is formed over the entire surface of the first silicon layer region or on the exposed surface of the first silicon layer region, the film thickness of the bottom portion of the first silicon layer region is reduced. It can be made thicker than before.
[0020]
For this reason, when a MOSFET is formed on the SOI layer constituted by the first silicon layer region and the second silicon layer region, it is possible to prevent occurrence of a hump of Id-Vg characteristics.
[0021]
Further, in the process of the present invention, element isolation is performed using the LOCOS method, so that the number of processes can be reduced by 3 to 4 processes compared to the number of processes of the conventional PELOX method.
[0022]
In practicing the present invention, preferably, a pad oxide film and a nitride film pattern are sequentially formed on the substrate, and a partial region of the silicon layer is changed to a field oxide film by thermal oxidation. It is preferable to include a step of removing the pad oxide film exposed other than the nitride film pattern by etching between the step of leaving the first silicon layer region on the lower side.
[0023]
Thus, the exposed pad oxide film on the insulating substrate exposed by etching away the pad oxide film other than the nitride film pattern is thermally oxidized, for example, pad oxide film damaged by ion implantation into the field oxide film, for example. Can be removed.
[0024]
In carrying out the present invention, it is preferable to use a hydrofluoric acid solution as an etching solution for the pad oxide film and the field oxide film.
[0025]
By using such a hydrofluoric acid solution, the pad oxide film and the field oxide film can be etched simultaneously. In addition, the first silicon layer region can be projected on the insulating film using such an etching solution.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of an element isolation region structure and an element isolation method according to the present invention will be described with reference to the drawings. 1 to 4 schematically show the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood.
[0027]
With reference to FIG. 1D and FIG. 4C, the element isolation region structures of the first and second embodiments of the present invention will be described. FIG. 1D and FIG. 4C are cross-sectional views showing a part of a plurality of SOI layer portions surrounded by a field oxide film.
[0028]
[Element Isolation Region Structure of First Embodiment]
The element isolation region structure according to the first embodiment of the present invention includes a silicon layer 102, an insulating film (here, a buried oxide film) 104, a field oxide film 16, and an SOI layer 20.
[0029]
In the first embodiment, the insulating film 104 is a buried oxide film formed on the SIMOX substrate 10. The substrate 10 having a SIMOX structure is configured by laminating a lower silicon layer 102, a buried oxide film 104, and an upper silicon layer 106.
[0030]
The field oxide film 16 is an oxide film for separating elements and is provided on the buried oxide film 104. Here, the field oxide film 16 is an SiO ₂ film, and the maximum film thickness is about 400 nm.
[0031]
The first silicon layer region 106 a is provided on the buried oxide film 104 surrounded by the field oxide film 16. The first silicon layer region 106 a is provided in a substantially non-contact state with the field oxide film 16. That is, in this embodiment, the skirt 30 of the first silicon layer region 106a and the lower portion of the field oxide film 16 are provided so as to be in contact with each other in a slight region (enclosed by the dotted line in FIG. 1D). However, this contact is a contact that can be said to be substantially non-contact. In this embodiment, the example in which the skirt 30 of the first silicon layer region 106a and the lower portion of the field oxide film 16 are in contact with each other has been described. However, they may be configured to be separated from each other. .
[0032]
The second silicon layer region 18 covers the first silicon layer region 106a and is formed by epitaxial growth. Here, the second silicon layer region 18 is provided over the entire surface of the first silicon layer region 106a. Therefore, in this embodiment, an SOI (Silicon on Insulator) layer 20 is constituted by the first silicon layer region 106 a and the second silicon layer region 18 on the buried oxide film 104.
[0033]
[Element Isolation Method of First Embodiment]
Next, the element isolation method according to the first embodiment will be described with reference to FIGS. 1A to 1D are cross-sectional views for explaining a process for forming the element isolation region structure of the first embodiment. In addition, each figure has shown the cross section cut of the structure obtained in the main structure stage.
[0034]
In this embodiment, a substrate 10 having a silicon layer 106 on an insulating film 104 is used. Here, the above-described SIMOX substrate is used as the substrate 10. The film thicknesses of the buried oxide film 104 and the upper silicon layer 106 of the SIMOX substrate 10 are about 100 nm and about 140 nm, respectively.
[0035]
A pad oxide film 12 and a nitride film pattern 14 are sequentially formed on the silicon layer 106 of the substrate 10 to obtain a structure shown in FIG. Note that the pad oxide film 12 is formed of a SiO ₂ film, and its thickness is about 30 nm. The steps so far are performed in the same manner as in the conventional PELOX method.
[0036]
In the present invention, a partial region of the silicon layer 106 of the structure shown in FIG. 1A is oxidized by thermal oxidation to be changed to the field oxide film 16, and the first silicon layer region 106 a is formed below the nitride film pattern 14. (B in FIG. 1). That is, when the silicon layer 106 is oxidized by thermal oxidation, the oxidation does not proceed because the nitride film pattern 14 is present above the silicon layer 106, and the first silicon layer region 106a remains. A region without the nitride film pattern 14 is changed to a field oxide film 16. In this step, since the pad oxide film 12 is formed of a SiO ₂ film, the pad oxide film 12 is substantially the same as the field oxide film 16. The film thickness of the field oxide film 16 is about 400 nm.
[0037]
In this process, when the silicon layer 106 is changed to the field oxide film 16 by thermal oxidation, the oxidation proceeds not only in the vertical direction of the silicon layer 106 but also in the horizontal direction. Also penetrates and grows. At this time, the end portion of the nitride film pattern is lifted by the volume increase of the grown field oxide film. Further, when the silicon layer 106 is changed to the field oxide film 16 by thermal oxidation, a bird's beak 15 is formed at the end of the first silicon layer region 106a. In FIG. 1B, the bird's beak 15 is shown only at both ends of the first silicon layer region 106a. However, in reality, the bird's beak 15 is formed at the peripheral edge of the first silicon layer region 106a. Yes.
[0038]
Next, a part of the nitride film pattern 14, the pad oxide film 12 and the field oxide film 16 remaining on the lower surface of the nitride film pattern 14 are sequentially removed by etching, and the first silicon layer is formed on the buried oxide film 104. The region 106a is protruded (FIG. 1C). Thus, by projecting the first silicon layer region 106 a onto the buried oxide film 104, the skirt portion of the first silicon layer region 106 a and the lower portion of the field oxide film 16 are brought into a non-contact state. Here, as described above, the skirt portion 30 of the first silicon layer region and the lower portion of the field oxide film are disposed in contact with each other.
[0039]
In this embodiment, for example, a hot phosphoric acid solution is used as an etchant for the nitride film pattern 14. As an etchant for the pad oxide film 12 and the field oxide film 16, a 5 wt% hydrofluoric acid solution is used.
[0040]
Next, the results of simulating the etching time dependency when the pad oxide film 12 and the field oxide film 16 were etched using a hydrofluoric acid solution using the structure after removing the nitride film pattern 14 are shown in FIG. As shown in FIG. FIGS. 5A to 5B and FIGS. 6A to 6B are diagrams for explaining changes in the bird's beak length with respect to the etching time. In the figure, the vertical axis represents the depth (μm) from the upper surface of the nitride film pattern 14 and the horizontal axis represents the distance (μm) from the channel center.
[0041]
As an etchant used for this simulation, a 5 wt% HF solution is used.
[0042]
As can be understood from FIGS. 5 and 6, when the etching time is 1 minute, the bird's beak length (L ₀ ) is about 0.5 μm or more (FIG. 5A), and the etching time is 2 minutes. When the bird's beak length (L ₁ ) is about 0.3 μm (FIG. 5B), and when the etching time is 3 minutes, the bird's beak length (L ₂ ) is about 0.15 μm (FIG. 6). (A)) When the etching time is 4 minutes, the bird's beak length (L ₃ ) is about 0.05 μm (FIG. 6B). Therefore, if the etching time is set to about 4 minutes, the bird's beak can be substantially removed.
[0043]
Returning to the step of FIG. 1C, the second silicon layer region 18 is formed by epitaxial growth over the entire surface of the first silicon layer 106a using a selective epitaxial technique (FIG. 1D). At this time, the CVD method is used to form the second silicon layer region 18. As film formation conditions for the CVD method, silane (SiH ₄ ) gas is used, and the substrate temperature during epitaxial growth is set to a temperature range of 550 to 600 ° C., for example. Here, the film thickness of the second silicon layer region 18 is about 100 nm.
[0044]
In this embodiment, the SOI layer 20 is constituted by the first silicon layer region 106 a and the second silicon layer region 18.
[0045]
In this way, by epitaxially growing the second silicon layer region 18 on the surface of the first silicon layer region 106a, the film thickness of the bottom portion of the first silicon layer region 106a can be increased.
[0046]
Thereafter, using a known technique, a gate oxide film 24, a gate electrode 26, a source 22a and a drain 22b are formed on the SOI layer 20 to form an SOI MOSFET (FIG. 2).
[0047]
[Element Isolation Region Structure of Second Embodiment]
Next, with reference to FIG. 4C, an element isolation region structure according to the second embodiment of the present invention will be described.
[0048]
In the second embodiment, the second silicon layer region 18 is partially provided on the surface of the first silicon layer region 106a. That is, the recess 32 is provided in the center of the first silicon layer region 106a, and the surface of the other first silicon layer region 106a is covered with the second silicon layer region 18 (FIG. 4C). Other configurations are the same as those of the first embodiment described above. Therefore, detailed description is omitted here.
[0049]
[Element Isolation Method of Second Embodiment]
Next, an element isolation method according to the second embodiment will be described with reference to FIGS. FIGS. 3A to 3B and FIGS. 4A to 4C are cross-sectional views for explaining a method of forming an element isolation region structure according to the second embodiment.
[0050]
A pad oxide film 12 and a nitride film pattern 14 are sequentially formed on the substrate 10, and then thermally oxidized to form a first silicon layer region 106 a below the nitride film pattern 14. The steps so far are the same as those in the first embodiment described above.
[0051]
Next, the pad oxide film 12 and the field oxide film 16 of the structure shown in FIG. 3B are simultaneously etched by wet etching. By performing such etching, a part of the pad oxide film 12 remains on the lower surface of the nitride film pattern 14 and the first silicon layer region 106a protrudes on the buried oxide film 104 (FIG. 4A). .
[0052]
At this time, the etchant is 5 wt% HF, and the etching time is about 5 minutes. By performing such etching, bird's beaks are eliminated.
[0053]
Next, the second silicon layer region 18 is formed on the exposed surface of the first silicon layer region 106a by selective epitaxial growth using the CVD method (FIG. 4B)).
[0054]
Next, the nitride film pattern 14 is etched using, for example, a hot phosphoric acid solution, and then the pad oxide film 12 is sequentially removed using a hydrofluoric acid solution (FIG. 4C).
[0055]
In the second embodiment, the second silicon layer region 18 is selectively grown only on the periphery of the bottom of the first silicon layer region 106a, not on the entire surface of the first silicon layer region. Compared with this embodiment, the consumption of source gas such as silane can be reduced.
[0056]
In the above-described embodiment, the SIMOX substrate is used as the substrate. However, the substrate is not limited to this substrate, and an SOI structure substrate such as a bonded SOI substrate may be used instead of the SIMOX substrate. .
[0057]
【The invention's effect】
As is apparent from the above description, according to the element isolation region structure and element isolation method of the present invention, the surface of the first silicon layer region is covered with the second silicon layer region. The film thickness of the ground part becomes thick. For this reason, when an SOI MOSFET is manufactured using this SOI layer composed of the first and second silicon layer regions, it is possible to prevent the Id-Vg characteristic hump.
[0058]
Further, in the element isolation method of the present invention, the element isolation region structure is formed using the LOCOS method, so that the number of steps can be reduced by 4 to 5 steps as compared with the conventional PELOX method. Therefore, the cost of the product can be reduced as compared with the conventional case.
[Brief description of the drawings]
FIGS. 1A to 1D are cross-sectional views for explaining a method for forming an element isolation region structure according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view for explaining an SOI MOSFET structure manufactured through a final process of the present invention.
FIGS. 3A to 3B are cross-sectional views for explaining a method for forming an element isolation region structure according to a second embodiment of the present invention. FIGS.
4A to 4C are cross-sectional views provided to explain a method for forming an element isolation region structure subsequent to FIG.
FIG. 5 is an explanatory diagram for explaining the relationship between etching time and bird's beak length;
FIG. 6 is an explanatory diagram for explaining a relationship between etching time and bird's beak length.
[Explanation of symbols]
10: SIMOX substrate 12: pad oxide film 14: nitride film pattern 16: field oxide film 18: second silicon layer region 20: SOI layer 22a: source 22b: drain 24: gate oxide film 26: gate electrode 30: first silicon Bottom of layer region 32: recess 102: silicon layer 104: buried oxide film 106: silicon layer 106a: first silicon layer region

Claims (8)

An insulating film, a field oxide film provided on the insulating film, and a first silicon layer region provided on the insulating film surrounded by the field oxide film in a non- contact state with the field oxide film And a second silicon layer region that covers the exposed surface of the first silicon layer region and is formed by epitaxial growth.   2. The element isolation region structure according to claim 1, wherein the insulating film is a film constituting an SOI (Silicon on Insulator) structure or a SIMOX (Separation by Implanted Oxygen) structure.   2. The element isolation region structure according to claim 1, wherein the first silicon layer region and the second silicon layer region form an SOI (Silicon on Insulator) layer. (A) using a substrate having a silicon layer on an insulating film, and sequentially forming a pad oxide film and a nitride film pattern on the substrate;
(B) changing a partial region of the silicon layer into a field oxide film by thermal oxidation, and leaving a first silicon layer region for forming a semiconductor element under the nitride film pattern;
(C) The nitride film pattern, the pad oxide film remaining on the lower surface of the nitride film pattern, and a part of the field oxide film are sequentially removed by etching, and the first silicon layer region protrudes on the insulating film. A step of bringing the skirt portion of the first silicon layer region and the lower portion of the field oxide film into a non-contact state ,
(D) forming a second silicon layer region by epitaxial growth over the entire surface of the first silicon layer region using a selective epitaxial technique. (A) using a substrate having a silicon layer on an insulating film, and sequentially forming a pad oxide film and a nitride film pattern on the substrate;
(B) changing a partial region of the silicon layer into a field oxide film by thermal oxidation, and leaving a first silicon layer region for forming a semiconductor element under the nitride film pattern;
(C) The field oxide film and the pad oxide film are simultaneously etched using wet etching so that a part of the pad oxide film remains on the lower surface of the nitride film pattern and the first silicon is formed on the insulating film. Projecting the layer region to bring the bottom of the first silicon layer region and the lower part of the field oxide film into a non-contact state ;
(D) forming a second silicon layer region by epitaxial growth on the surface of the first silicon layer region using a selective epitaxial technique;
And (e) subsequently removing the nitride film pattern and the pad oxide film remaining on the lower surface of the nitride film pattern by etching in sequence.   6. The element isolation method according to claim 4, further comprising a step of removing the pad oxide film exposed other than the nitride film pattern by etching between the steps (a) and (b). An element isolation method characterized by the above. In isolation method according to claim 4 or 5, isolation method characterized by Ru with hydrofluoric acid solution as an etchant of the pad oxide film and the field oxide film.   6. The element isolation method according to claim 4, wherein a substrate having an SOI structure or a substrate having a SIMOX structure is used as the substrate.

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