JP3838358B2 - Information processing apparatus and apparatus abnormality detection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus capable of communicating with each other via a line, and an apparatus abnormality detection method.
[0002]
[Prior art]
Conventionally, when a communication frame, which is a signal transmission unit, is transmitted and received between information processing apparatuses via a network, each apparatus stores a transmission source address and a transmission destination address of the communication frame as history information when the communication frame is received. (For example, refer to Patent Document 1). By storing history information, when an abnormality occurs in communication, the operator of the information processing device displays a log (Log) that is a record indicating the device status at the time of the failure on the screen with reference to the history information. I was investigating the cause of the communication error.
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-272508
[0004]
[Problems to be solved by the invention]
In the conventional technology described above, even if a delay occurs in transmission / reception of a communication frame due to a minor failure, communication is continued as long as there is no problem in communication. After that, when a minor failure develops into a major communication failure and communication between devices becomes impossible, even if an operator tries to investigate the cause of the failure by operating the device, the history of the location where the delay occurred first Not only is it time-consuming to identify from the information, but it is difficult to identify the cause of the delay from the many logs accumulated.
[0005]
The present invention has been made to solve the above-described problems of the prior art, and provides an information processing apparatus and an apparatus abnormality detection method for early detection of the occurrence of a minor failure. Objective.
[0006]
[Means for Solving the Problems]
An information processing apparatus of the present invention for achieving the above object includes a counter circuit that outputs a counter signal every time a signal generated from a clock is received a predetermined number of times,
A memory for storing a counter value corresponding to the counter signal number;
When the counter signal is received from the counter circuit, the self-counter value stored in the memory is incremented by 1. When an interrupt signal due to a hardware failure is received, the device status is recorded in the memory, and the counter during recording A processing unit that rejects the signal and transmits the own counter value read from the memory to the counterpart device of the communication destination, and a counter value that is the counter value of the counterpart device and the counter value in a normal communication state. When a reference value that is a ratio is stored in the memory and the counterpart counter value is received from the counterpart device, the counterpart counter value and a counter ratio of the counter value stored in the memory when the counterpart counter value is received are obtained. A check circuit for determining whether or not the counter ratio matches the reference value;
It is the structure which has.
[0007]
In the information processing apparatus of the present invention, the check circuit includes:
When it is determined that the counter ratio does not match the reference value, a signal that the counter ratio does not match the reference value is sent to the processing unit,
The processor is
When a signal indicating that the counter ratio does not match the reference value is received from the check circuit, the failure information including a record indicating a device status at the time of the failure is requested to the partner device, and the failure received from the partner device Information may be displayed.
[0008]
Furthermore, in the information processing apparatus according to the present invention, the processing unit includes:
The self-counter value may be added to a communication frame, which is a signal transmission unit, and transmitted to the partner apparatus.
[0009]
On the other hand, the apparatus abnormality detection method of the present invention for achieving the above object is an apparatus abnormality detection method for detecting the occurrence of a failure of a partner apparatus that is a communication destination between information processing apparatuses that are communicably connected. And
Each time a signal generated from a clock provided in the own device is received a predetermined number of times, a counter signal is output to the processing unit of the own device,
Holds a self-counter value corresponding to the counter signal number, and a reference value that is a ratio of the counter value that is the counter value of the counterpart device and the counter value in a normal communication state,
When the counter signal is received from the counter circuit, the self-counter value is incremented by 1, and when an interrupt signal due to a hardware failure is received, the device status is recorded, and reception of the counter signal during recording is rejected.
Send the counter value read from the memory to the counterpart device,
When receiving the counterpart counter value from the counterpart device, obtain a counter ratio between the counterpart counter value and the counter value stored in the memory when the counterpart counter value is received,
It is determined whether or not the counter ratio matches the reference value.
[0010]
Further, when the apparatus abnormality detection method of the present invention determines that the counter ratio does not match the reference value, it requests the partner apparatus for failure information including a record indicating a device status at the time of failure occurrence,
When the failure information is received from the counterpart device, the failure information may be displayed.
[0011]
Furthermore, the apparatus abnormality detection method of the present invention may add the self-counter value to a communication frame that is a signal transmission unit and transmit it to the partner apparatus.
[0012]
(Function)
In the present invention, when a hardware failure occurs, the processing based on the interrupt signal is given priority, and the counter value is shifted to a smaller value than when the counter value is normal. Therefore, when the own counter value is transmitted to the counterpart device, the check circuit of the counterpart device determines whether or not the counter ratio matches the reference value. As a result, the counter ratio and the reference value do not match, so the communication destination It is detected that an injury has occurred in the device. In addition, since the counter ratio is monitored between apparatuses having clocks of different frequencies, the counter ratio changes when a failure occurs in the counterpart apparatus, and an apparatus abnormality can be detected.
[0013]
Further, in the present invention, when it is detected that a failure has occurred in the device, the failure information can be received from the counterpart device, the failure information can be displayed and notified to the operator. Therefore, a minor failure occurring in the apparatus can be detected at an early stage, and the operator can easily identify the cause of the failure.
[0014]
Further, according to the present invention, when the communication frame is transmitted to the partner apparatus, the counter value can be transmitted to the partner apparatus together with the communication frame by adding the counter value to the communication frame.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
The information processing apparatus according to the present invention measures the counter value according to the number of output signals from the clock for each apparatus, even between apparatuses having clocks of different frequencies, and in the case of normal communication between the apparatuses. The ratio between the counter value and the counter value of the partner device is stored as a reference value, and each time the counter value of the partner device is received, the ratio between the counter value of the own device and the counter value of the partner device is obtained. It is possible to detect an abnormality of the counterpart device by determining whether or not it matches the value.
[0016]
An apparatus abnormality detection system using the information processing apparatus of the present invention will be described.
[0017]
FIG. 1 is a block diagram showing a configuration example of an apparatus abnormality detection system having an information processing apparatus according to the present invention.
[0018]
As shown in FIG. 1, the device abnormality detection system includes a peripheral device 2 such as an information processing terminal, a display, and a printer, and a peripheral control device 1 that transfers data received from a host 3 that is a general-purpose computer to the peripheral device 2. It is a configuration. The peripheral control device 1 is connected to the host 3 serving as the host device through the dedicated interface 4 and is connected to the peripheral device 2 serving as the lower device via the network 20.
[0019]
Next, the configuration of the peripheral control device 1 and the peripheral device 2 which are information processing devices of the present invention will be described in detail.
[0020]
FIG. 2 is a block diagram showing a configuration example of the peripheral control device and the peripheral device according to the present invention.
[0021]
The peripheral control device 1 receives a signal generated from a host interface (I / F) control unit 13 that transmits and receives a communication frame with the host 3 and a clock (not shown) provided in the own device a predetermined number of times. A counter circuit 18 for outputting the counter value, a memory 15 for storing the counter value, and a microprocessor section 11 serving as a processing section for incrementing the counter value stored in the memory 15 by 1 each time a counter signal is received from the counter circuit 18; The check circuit 19 calculates the ratio of the two counter values, and the lower I / F control unit 12 transmits and receives the communication frame to and from the peripheral device 2.
[0022]
The memory 15 includes a trace area 16 for storing trace information including a communication frame type, and a counter area 17 for storing a counter value and the like.
[0023]
The trace area 16 stores a control table for recording the address and device status of the peripheral device 2 capable of communication, an input / output buffer for temporarily storing communication frames to be transmitted and received, and trace information. When the transfer data is included in the communication frame, the trace information includes information that simply indicates the content of the transfer data.
[0024]
In addition to the counter value, the counter area 17 stores a counter ratio between the own counter value that is the counter value of the own device and the counter value that is the counter value of the communication destination device. A counter ratio when communication between the peripheral control device 1 and the peripheral device 2 is normal is referred to as a reference value.
[0025]
When receiving a communication frame from the peripheral device 2, the check circuit 19 stores the counterpart counter value from the received communication frame, and reads and stores the own counter value stored in the counter area 17. Subsequently, a counter ratio is calculated from these two counter values and compared with a reference value stored in the memory 15. If the counter ratio does not match the reference value as a result of the comparison, a signal indicating that the counter ratio does not match the reference value is sent to the microprocessor unit 11, and the stored self counter value and counter counter value are stored in the counter area 17. Delete the reference value. On the other hand, if the counter ratio matches the reference value as a result of the comparison, the newly obtained counter ratio is stored in the counter area 17 as the reference value.
[0026]
When the reference value is not stored in the counter area 17 in the memory 15, the counter ratio is calculated from the two stored counter values, and the obtained counter ratio is written in the counter area 17 as the reference value.
[0027]
The microprocessor unit 11 stores firmware (FW) serving as a program, and executes predetermined processing under program control.
[0028]
When the microprocessor unit 11 receives the transfer data from the host 3 through the host I / F control unit 13, the microprocessor unit 11 temporarily stores the transfer data in the input / output buffer. Subsequently, the address and device status of the peripheral device 2 as the transmission destination are confirmed in the control table, and a communication frame for sending transfer data is created. Thereafter, the created communication frame is transmitted to the peripheral device 2 via the lower I / F control unit 12. At this time, the own counter value stored in the counter area 17 and the counter counter value stored in the check circuit 19 are added to the communication frame to be transmitted. When a communication frame for connection establishment request from the peripheral device 2 is received, similarly, a response communication frame with the two counter values added is transmitted to the peripheral device 2.
[0029]
When transmitting a communication frame to the peripheral device 2 and receiving a communication frame from the peripheral device 2, the communication frame trace information, the counter value included in the communication frame, and the counter area 17 are stored. History information including its own counter value is stored in the trace area 16.
[0030]
When an interrupt signal due to a hardware failure is received, a log is recorded and the counter signal from the counter circuit 18 is rejected during recording.
[0031]
Further, when information indicating that the counter ratio does not match the reference value is received from the check circuit 19, it is determined that a failure has occurred in the peripheral device 2, and a failure information request frame for requesting failure information including a log is Transmit to device 2. When a failure information frame for returning failure information is received from the peripheral device 2, a signal indicating that a failure has occurred in the peripheral device 2 and the failure information are transmitted to the host 3.
[0032]
Next, the peripheral device 2 will be described. In the following, the configuration and operation related to detection of an apparatus abnormality according to the present invention will be described, and description of general functions provided in the peripheral device 2 will be omitted.
[0033]
The peripheral device 2 includes an I / F control unit 22 that transmits and receives data to and from the peripheral control device 1 via the network 20, a check circuit 29, a memory 25, a counter circuit 28, and a microprocessor unit 21. is there. Note that the check circuit 29, the memory 25, the counter circuit 28, and the microprocessor unit 21 have the same configurations as the check circuit 19, the memory 15, the counter circuit 18, and the microprocessor 11 of the peripheral control device 1, and therefore their details. The detailed explanation is omitted.
[0034]
Further, when a failure occurs in the peripheral device 2, the microprocessor unit 21 stores a log at the time of occurrence in the trace area 26. When a failure information request frame is received from the peripheral control device 1, the log is read from the trace area 26, and a failure information frame for sending the log is created and transmitted to the peripheral control device 1.
[0035]
Next, a configuration example of a communication frame transmitted / received between the peripheral control device 1 and the peripheral device 2 will be described.
[0036]
FIG. 3 is a diagram illustrating a configuration example of a communication frame transmitted and received between the peripheral control device and the peripheral device. Note that (5) in FIG. 3 indicates the format of history information to be stored in the trace areas 16 and 26.
[0037]
(1) shown in FIG. 3 indicates the format of a communication frame to be transmitted when one apparatus requests the other apparatus to establish a connection. Information on the own counter value and the counter value of the other party is added after the header part including the address of the other party that is the transmission destination, the address of the own apparatus that is the transmission source, and the type of packet to be transmitted. In the other formats (2) to (7), two counter values are added after the header portion as in the case (1).
[0038]
(2) shown in FIG. 3 shows the format of an establishment response frame for responding to the partner apparatus when the own apparatus receives the communication frame (1) from the partner apparatus. Also, (3) shows the format of the transfer data communication frame for transmitting the transfer data attached, and (4) shows the format of the communication response frame as a response. Further, (6) in FIG. 3 indicates the format of the failure information request frame, and (7) indicates the format of the failure information frame.
[0039]
Next, an operation procedure of the apparatus abnormality detection system configured as described above will be described.
[0040]
FIG. 4 is a flowchart showing the operation procedure of the apparatus abnormality detection system described above. “H” shown in FIG. 4 indicates a header portion. FIG. 5 is a table showing a main part of history information when a communication frame is received in the operation of the apparatus abnormality detection system of the present invention. The left column of the table shown in FIG. 5 is the history information of the peripheral control device, and the right column is the history information of the peripheral device.
[0041]
In the following, the counter value of the peripheral control device 1 is indicated by “′” at the upper right of the number. A detailed description of the operation of the counter circuits 18 and 28 is omitted.
[0042]
As shown in FIG. 4, when the operator turns on the power supply of the peripheral control device 1, the microprocessor unit 11 transmits a communication frame for connection establishment request to which the self-counter value “2 ′” is added to the peripheral device 2. The history information of the communication frame is stored in the trace area 16.
[0043]
When the I / F control unit 22 of the peripheral device 2 receives the communication frame of the connection establishment request from the peripheral control device 1, the check circuit 29 receives the counter value “1” at the time of reception and the partner read from the received communication frame. The counter value “2 ′” is stored. Further, the microprocessor unit 21 stores the history information of the communication frame of the connection establishment request in the trace area 26. Subsequently, when transmitting the communication frame of the establishment response to the peripheral control device 1 in order to respond, the own counter value “2” at the time of transmission and the counter counter value “2 ′” stored in the check circuit 29 are transmitted. Is transmitted to the peripheral control device 1, and the history information of the transmitted communication frame is stored in the trace area 26.
[0044]
When the lower I / F control unit 12 of the peripheral control device 1 receives the communication frame of the establishment response from the peripheral device 2, the microprocessor unit 11 stores the history information of the received communication frame in the trace area 16. In addition, the check circuit 19 stores the counter value “2” read from the communication frame of the establishment response and the counter value “6 ′” at the time of reception.
[0045]
On the other hand, after transmitting the establishment response communication frame, the microprocessor unit 21 of the peripheral device 2 establishes a connection with its own counter value “3” and the counter counter value “2 ′” stored in the check circuit 29. "Is added to the peripheral control device 1, and history information of the transmitted communication frame is stored in the trace area 26.
[0046]
When the lower I / F control unit 12 of the peripheral control device 1 receives the communication frame for the connection establishment request from the peripheral device 2, the check circuit 19 reads the counter counter value “3” read from the received communication frame and the reception time The own counter value “8 ′” is stored. Subsequently, a counter ratio is calculated from the two stored counter values, and the result is stored in the counter area 17 of the memory 15 as a reference value. Further, the microprocessor unit 11 stores the history information of the communication frame of the connection establishment request in the trace area 16. Subsequently, when transmitting the communication frame of the establishment response to the peripheral device 2 in order to respond to the connection establishment request, the own counter value “10 ′” at the time of transmission and the counter counter value “10” stored in the check circuit 19 are transmitted. 3 ”is added and transmitted to the peripheral device 2, and the history information of the transmitted communication frame is stored in the trace area 16.
[0047]
When the I / F control unit 22 of the peripheral device 2 receives the communication frame of the establishment response from the peripheral control device 1, the microprocessor unit 21 stores the history information of the received communication frame in the trace area 26. The check circuit 29 stores the counter value “10 ′” read from the received communication frame and the self counter value “5” at the time of reception. Subsequently, the counter ratio is calculated from the two stored counter values, and the result is stored in the counter area 27 in the memory 25 as a reference value.
[0048]
Next, when the host I / F control unit 13 of the peripheral control device 1 receives the transfer data a to the peripheral device 2 from the host 3, the microprocessor unit 11 transmits the transfer data a to the peripheral device 2. A transfer data communication frame to which the own counter value “16 ′” at the time of transmission and the counterpart counter value “3” stored in the check circuit 19 are added is created, and history information of the created transfer data communication frame is stored in the trace area 16. In addition to storing, the transfer data communication frame is transmitted to the peripheral device 2.
[0049]
When the I / F control unit 22 of the peripheral device 2 receives the transfer data communication frame from the peripheral control device 1, the microprocessor unit 21 executes predetermined processing on the transfer data a, and the received transfer data communication frame The history information is stored in the trace area 26. The check circuit 29 stores the counter value “16 ′” read from the transfer data communication frame and the self counter value “8” when the transfer data communication frame is received. Subsequently, the counter ratio is calculated from the two stored counter values, and the result is compared with the reference value stored in the counter area 27.
[0050]
As shown in FIG. 5, since the counter ratio at the time of receiving the transfer data “a” matches the reference value stored in the counter area 27, the check circuit 29 uses the counter ratio newly obtained in the counter area 27 as a reference. Update as a value.
[0051]
Thereafter, in order to notify that the processing of the transfer data a has been completed, the microprocessor unit 21 adds the own counter value “9” and the counter counter value “16 ′” stored in the check circuit 29. A response frame is created and transmitted to the peripheral control device 1, and history information of the transmitted communication response frame is stored in the trace area 26.
[0052]
When the lower I / F control unit 12 of the peripheral control device 1 receives the communication response frame from the peripheral device 2, the microprocessor unit 11 stores the history information of the communication response frame in the trace area 16. Further, the check circuit 19 stores the counter value “9” read from the communication response frame and the own counter value “20 ′” when the communication response frame is received. Subsequently, the counter ratio is calculated from the two stored counter values, and the result is compared with the reference value stored in the counter area 17.
[0053]
As shown in FIG. 5, since the counter ratio at the time of receiving a response to the transfer data “a” matches the reference value stored in the counter area 17, the check circuit 19 newly calculates the counter ratio calculated in the counter area 17. Is updated as a reference value.
[0054]
Next, when the host I / F control unit 13 of the peripheral control device 1 receives the transfer data b to the peripheral device 2 from the host 3, the microprocessor unit 11 transmits the transfer data b to the peripheral device 2. Similarly to the case of the transfer data a, a transfer data communication frame to which the own counter value “22 ′” at the time of transmission and the counter counter value “9” stored in the check circuit 19 are added is created. The communication frame history information is stored in the trace area 16 and the transfer data communication frame is transmitted to the peripheral device 2.
[0055]
When the I / F control unit 22 of the peripheral device 2 receives the transfer data communication frame from the peripheral control device 1, the microprocessor unit 21 executes predetermined processing on the transfer data b, and the received transfer data communication frame The history information is stored in the trace area 26. The check circuit 29 stores the counter value “22 ′” read from the transfer data communication frame and the self counter value “11” when the transfer data communication frame is received. Subsequently, the counter ratio is calculated from the two stored counter values, and the result is compared with the reference value stored in the counter area 27.
[0056]
As shown in FIG. 5, since the counter ratio at the time of receiving the transfer data b matches the reference value stored in the counter area 27, the check circuit 29 uses the newly calculated counter ratio in the counter area 27 as a reference. Update as a value.
[0057]
Here, as shown in FIG. 4, when the microprocessor unit 21 receives a hardware (HW) interrupt signal due to a minor failure occurring in the peripheral device 2 when creating a communication response frame, the log is displayed. Store in the trace area 26. For this reason, even if there is a counter signal from the counter circuit 28 while the log is stored, the processing by the HW interrupt signal is prioritized. Is reduced by the amount that cannot be received.
[0058]
Then, a communication response frame to which the own counter value “12” and the counterpart counter value “22 ′” stored in the check circuit 29 are added is created, but the time lag until the communication response frame is created by the HW interrupt. Will have occurred. Subsequently, the communication response frame is transmitted to the peripheral control device 1 and the history information of the communication response frame is stored in the trace area 26.
[0059]
When the lower I / F control unit 12 of the peripheral control device 1 receives the communication response frame from the peripheral device 2, the microprocessor unit 11 stores the history information of the communication response frame in the trace area 16. Further, the check circuit 19 stores the counter value “12” read from the communication response frame and the self counter value “28 ′” when the communication response frame is received. Subsequently, the counter ratio is calculated from the two stored counter values, and the result is compared with the reference value stored in the counter area 17.
[0060]
As shown in FIG. 5, the counter ratio at the time of receiving a response to the transfer data b is “8: 3”, whereas the reference value stored in the counter area 17 is “2: 1”. The ratio does not match the reference value. Therefore, the check circuit 19 transmits a signal indicating that the counter ratio does not match the reference value to the microprocessor unit 11 and erases the stored counter value and the reference value in the counter area 17.
[0061]
When the microprocessor unit 11 receives information indicating that the counter ratios do not match from the check circuit 19, the microprocessor unit 11 determines that a failure has occurred in the peripheral device 2, and sets its own counter value “30” in the communication frame for requesting the failure information. “′” Is added and transmitted to the peripheral device 2, and the history information of the transmitted failure information request frame is stored in the trace area 16.
[0062]
When the I / F control unit 22 of the peripheral device 2 receives the failure information request frame from the peripheral control device 1, the check circuit 29 deletes the stored two counter values and the reference value in the counter area 27, and the failure information The other party counter value “30 ′” read from the request frame and the own counter value “14” when the failure information request frame is received are stored. Further, the microprocessor unit 21 stores the history information of the received failure information request frame in the trace area 26. Subsequently, the log is read from the trace area 26, and a failure information frame for sending the log is created. Thereafter, when transmitting the failure information frame to the peripheral control device 1, the self-counter value “15” at the time of transmission and the counterpart counter value “30 ′” stored in the check circuit 29 are added and transmitted to the peripheral control device 1. Then, the history information of the transmitted failure information frame is stored in the trace area 26.
[0063]
When the lower I / F control unit 12 of the peripheral control device 1 receives the failure information frame from the peripheral device 2, the check circuit 19 and the counter counter value “15” read from the failure information frame and the own counter value “at reception” “ 34 '"is stored. Further, the microprocessor unit 11 stores the history information of the received failure information frame in the trace area 16, and transmits a signal indicating that a failure has occurred in the peripheral device 2 and the failure information to the host 3.
[0064]
When the host 3 receives a signal indicating that a failure has occurred in the peripheral device 2 and the failure information, the host 3 displays on the display that the failure has occurred in the peripheral device 2 and the failure information.
[0065]
In the present invention, as described above, the reference value of the counter ratio for normal communication between devices is stored, and when a communication frame is transmitted to a partner device, the communication frame is transmitted with its own counter value added. When a communication frame is received from a partner device, the ratio between the own counter at the time of reception and the partner counter value added to the communication frame is obtained and compared with a reference value. If the obtained counter ratio does not match the reference value It is determined that there is an abnormality in the counterpart device. Therefore, a minor failure occurring on the counterpart device side can be detected at an early stage, and the operator of the host 3 can easily identify the cause of the failure.
[0066]
In addition, as described above, the counter ratio is monitored even between devices having clocks of different frequencies, so that when the failure occurs in the counterpart device, the counter ratio changes and an abnormality can be detected.
[0067]
If there is an abnormality in the peripheral control device 1, the peripheral device 2 detects the abnormality as described above, and notifies the operator of information indicating that the peripheral control device 1 is abnormal. For example, the peripheral device 2 is provided with a display, and information indicating that there is an abnormality in the peripheral control device 1 is displayed on the display. Further, a warning lamp indicating that there is an abnormality in the peripheral control device 1 may be provided in the peripheral device 2 so that the warning lamp is turned on.
[0068]
Further, the present invention is not limited to the case where the own counter value is added to the communication frame and transmitted to the partner apparatus, but the own counter value alone may be transmitted to the partner apparatus.
[0069]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0070]
In the present invention, the counter ratio when normally communicating between devices is stored as a reference value, and every time a counter value is received from the counterpart device, the counter ratio obtained from the counter value of the counterpart device and the counter value of the own device The reference value is compared, and if the counter ratio does not match the reference value, it is determined that there is an abnormality in the counterpart device. Therefore, a minor failure occurring on the counterpart device side can be detected at an early stage, and the operator can easily identify the cause of the failure.
[0071]
Further, upon receiving the counter value of the counterpart device, a step of obtaining a ratio between the counter value of the counterpart device and the counter value of the subject device, a step of comparing the obtained counter ratio with a reference value stored in a memory, and a comparison result counter It is possible to perform sequence control that sequentially advances the step of determining whether or not the rate matches the reference value.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of an apparatus abnormality detection system having an information processing apparatus of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a peripheral control device and a peripheral device according to the present invention.
FIG. 3 is a diagram illustrating a configuration example of a communication frame transmitted and received between the peripheral control device and the peripheral device according to the present invention.
4 is a flowchart showing an operation procedure of the apparatus abnormality detection system shown in FIG. 1. FIG.
FIG. 5 is a table showing a main part of history information when a communication frame is received in the operation shown in FIG. 4;
[Explanation of symbols]
1 Peripheral control device
2 Peripheral devices
3 Host
4 Dedicated interface
11, 21 Microprocessor part
12 Lower I / F control part
13 Host I / F control unit
15, 25 memory
16, 26 Trace area
17, 27 Counter area
18, 28 Counter circuit
19, 29 Check circuit
20 network
22 I / F control unit

Claims (6)

A counter circuit that outputs a counter signal each time a signal generated from a clock is received a predetermined number of times;
A memory for storing a counter value corresponding to the counter signal number;
When the counter signal is received from the counter circuit, the self-counter value stored in the memory is incremented by 1. When an interrupt signal due to a hardware failure is received, the device status is recorded in the memory, and the counter during recording A processing unit that rejects the signal and transmits the own counter value read from the memory to the counterpart device of the communication destination, and a counter value that is the counter value of the counterpart device and the counter value in a normal communication state. When a reference value that is a ratio is stored in the memory and the counterpart counter value is received from the counterpart device, the counterpart counter value and a counter ratio of the counter value stored in the memory when the counterpart counter value is received are obtained. A check circuit for determining whether or not the counter ratio matches the reference value;
An information processing apparatus. The check circuit is
When it is determined that the counter ratio does not match the reference value, a signal that the counter ratio does not match the reference value is sent to the processing unit,
The processor is
When a signal indicating that the counter ratio does not match the reference value is received from the check circuit, the failure information including a record indicating a device status at the time of the failure is requested to the partner device, and the failure received from the partner device The information processing apparatus according to claim 1, wherein information is displayed. The processor is
The information processing apparatus according to claim 1, wherein the self-counter value is added to a communication frame that is a signal transmission unit and transmitted to the counterpart apparatus. A device abnormality detection method for detecting a failure of a partner device that is a communication destination between information processing devices that are communicably connected,
Each time a signal generated from a clock provided in the own device is received a predetermined number of times, a counter signal is output to the processing unit of the own device,
Holds a self-counter value corresponding to the counter signal number, and a reference value that is a ratio of the counter value that is the counter value of the counterpart device and the counter value in a normal communication state,
When the counter signal is received from the counter circuit, the self-counter value is incremented by 1, and when an interrupt signal due to a hardware failure is received, the device status is recorded, and reception of the counter signal during recording is rejected.
Send the counter value read from the memory to the counterpart device,
When receiving the counterpart counter value from the counterpart device, obtain a counter ratio between the counterpart counter value and the counter value stored in the memory when the counterpart counter value is received,
An apparatus abnormality detection method for determining whether or not the counter ratio matches the reference value. If it is determined that the counter ratio does not match the reference value, request the failure information including a record indicating the device status at the time of failure occurrence to the counterpart device,
5. The apparatus abnormality detection method according to claim 4, wherein when the failure information is received from the counterpart device, the failure information is displayed. 6. The apparatus abnormality detection method according to claim 4, wherein the own counter value is added to a communication frame which is a signal transmission unit and transmitted to the counterpart apparatus.

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