JP3822687B2 - Data processing system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock-synchronous semiconductor memory device, and further to a function expansion in the clock-synchronous semiconductor memory device, and more particularly to a semiconductor memory device that can handle both a data memory portion of a set-associative cache memory and normal random access.
[0002]
[Prior art]
A set associative cache memory has a plurality of ways for a direct map. Therefore, the data memory unit must receive the way selection signal related to the hit from the cache memory unit and select data from the cache entry of the way related to the hit. Such a selection function is not considered in a general-purpose single memory. When the data memory unit of the secondary cache memory arranged outside the microprocessor is configured using a general-purpose SRAM chip, the data memory unit is configured by assigning a separate SRAM chip for each way. The data input / output terminals of these SRAM chips can be wired or connected, and the way selection signal from the address memory unit can be made to correspond to the output enable signal of the SRAM chip to select the way. However, in the configuration using a plurality of SRAM chips, if there is no SAM chip having the optimum storage capacity for each way in relation to the storage capacity required for the cache memory, a part of the storage area of the plurality of SRAM chips is not stored. There is a problem that it is not used at all and consumes a mounting area and the cost increases.
[0003]
[Problems to be solved by the invention]
In view of this, the present inventor studied to incorporate a selector applicable to way selection into the SRAM chip. However, the way selection signal is a signal obtained as a result of the associative search in the address memory unit of the cache memory, and is delayed compared to the supply timing of the index address signal to the address memory unit and the data memory unit. Therefore, it is not necessary to simply incorporate the selector in the existing SRAM chip.
[0004]
Here, since the secondary cache memory needs to have a larger storage capacity than the primary cache memory, the high speed of the circuit operation must be sacrificed to some extent. In addition, the primary cache memory is usually formed on the same semiconductor chip as the CPU (Central Processing Unit), whereas the secondary cache memory is often formed on a separate chip from the CPU. In this respect, the secondary cache memory is disadvantageous compared to the primary cache memory in terms of its high-speed operation. For this reason, various technical devices have been devised in the secondary cache memory in order to improve the data transfer rate with the CPU. For example, a synchronous SRAM or pipeline burst SRAM in which a well-known pipeline process used in a RISC architecture microprocessor or the like is applied to an SRAM is provided with a plurality of pipeline latch circuits for engraving a pipeline inside a memory chip. And the throughput of data transfer with the CPU is improved. For example, assuming an address input latch to the address buffer, an address input latch to the address decoder, and a data output latch to the data output buffer, each pipeline latch circuit performs a latch operation every clock signal cycle and synchronizes with this. When a read operation is performed, a period of two cycles of the clock signal must be waited after the address is given to the memory until the data at that address is output. In addition, read data can be obtained every clock cycle.
[0005]
Such a clock synchronous SRAM is usually used for the secondary cache memory, and is operated in synchronization with the operation reference clock signal of the microprocessor. Under these circumstances, when the supply timings of the two types of address signals, the index address signal and the way selection signal, supplied to the data memory unit of the secondary cache memory are different as described above, the way selection is simply performed. It has been clarified that it is not sufficient to mount this selector on a general-purpose SRAM chip. If a new SRAM dedicated to the cache data memory unit considering such a difference in address supply timing from the beginning is newly designed, man-hours, personnel, and costs for new development will be forced, the number of SRAM types will increase, and inventory will increase. It is not desirable for management.
[0006]
An object of the present invention is to provide a clock synchronous semiconductor memory device that can be used for both general-purpose random access and cache data memory units.
[0007]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0008]
[Means for Solving the Problems]
The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.
[0009]
That is, in a clock synchronous semiconductor memory device in which pipeline latch means operated synchronously with a clock signal is arranged in an address signal transmission path to a first address decoder for selecting a memory cell from a memory array, A selector for further selecting a memory cell selected in the memory array is provided, and a pipeline latch means with a bypass function is arranged in a path for supplying an address signal to the second address decoder for controlling the selection operation of the selector, A control terminal is provided for instructing whether to perform the latch operation or the signal through operation for the pipeline latch means with the bypass function.
[0010]
When this semiconductor memory device is used as a normal random access memory, an address signal is supplied to the first and second address decoders in parallel in synchronization with a synchronous clock signal. The selector selecting operation by the second address decoder is performed in synchronization with the memory cell selecting operation from the memory array by the first address decoder. Both pipeline latch means have the number of serial latch stages necessary to realize such timing synchronization.
[0011]
When this semiconductor memory device is applied to a data memory unit of a set associative cache memory, an index address is supplied to the first address decoder, and a way selection signal is supplied from the cache address memory unit to the second address decoder. Supplied. Since the way selection signal is a signal obtained as a result of the associative search in the cache address memory unit, it is delayed by one or more cycles of the synchronous clock signal with respect to the supply timing of the index address signal. The pipeline latch means with a bypass function selects the signal through operation instead of the latch operation only for a period necessary to recover the delay. The selection is instructed by the state of the control terminal. As a result, even if the way selection signal is supplied later than the index address signal, the data can be output to the outside at the required timing to recover the delay.
[0012]
Thereby, it can respond to the use of both a general purpose random access memory and a cache data memory part.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a block diagram of an SRAM 1 which is an example of a semiconductor integrated circuit according to the present invention. In the figure, reference numeral 2 denotes a memory array. Although not shown in detail, the memory array 2 includes known static memory cells arranged in a matrix, the selection terminals of the memory cells are connected to the corresponding word lines for each row, and the data input / output terminals of the memory cells are Each column is coupled to a corresponding bit line, and the bit line is connected to a common data line via a column switch circuit. Data read from the memory cell to the common data line is amplified by a sense amplifier and supplied to the selector 3. The data selected by the selector 3 is latched by the latch circuit 4. The latched data is output from the data input / output terminal 5 through a data output buffer (not shown). Write data applied to the data input / output terminal 5 from the outside is taken into a data input buffer and latch circuits 7 and 8 (not shown), and the memory array is connected to the memory array 2 via a column switch circuit (not shown). 2 common data lines.
[0014]
The memory array 2 has a storage capacity of 256K × 18 bits, although not particularly limited. The memory array 2 is divided into 18 memory mats MAT0 to MAT17 corresponding to the respective bits 0 to 17, and the storage areas of the respective mats MAT0 to MAT17 are divided into four units UNT0 to UNT3, respectively. In each of the memory mats MAT0 to MAT17, the read operation is performed in units of 4 bits, and the write operation is performed in units of 1 bit. That is, for the read operation, one bit is selected from each unit UNT0 to UNT3 of each memory mat MAT0 to MAT17. Selection of bit lines and word lines by a column switch circuit (not shown) is performed by the address decoder 8. According to this example, the address decoder 8 is supplied with an 18-bit address signal, and in a read operation, a 1-bit memory cell is selected from each of the units UNT0 to UNT3 of the respective memory mats MAT0 to MAT17. The selector 3 selects a 1-bit memory cell of one unit from 4 bits for each of the memory mats MAT0 to MAT17. The selection operation is performed by an address decoder 11 that decodes a 2-bit address signal. In the write operation, the address decoder 8 selects a 1-bit memory cell from each of the memory mats MAT0 to MAT17. Switching of such a selection operation by the address decoder 8 is instructed by a control signal 16.
[0015]
FIG. 2 schematically shows selection logic relating to the memory units UNT0 to UNT3 of one memory mat as an example of a logical configuration for switching the selection operation of the address decoder 8. In FIG. 2, reference numerals 23A to 23D denote one bit line representatively shown in each of the memory units UNT0 to UNT3. Each bit line is connected to the read common data lines 22A to 22D via the read column switches 21A to 21D. The One end of the read common data lines 22 </ b> A to 22 </ b> D reaches the selector 3. The bit lines 23A to 23D are connected to the write common data line 25 via the write column switches 24A to 24D. The write common data line 25 reaches the latch circuit 8.
[0016]
The AND gates 27A to 27D constitute a read driver connected to the other ends of the read column switches 21A to 21D, and the read common data lines 22A to 22D can be driven on condition that the signal 16 is set to the high level. The The AND gates 26A to 26D are connected to selection terminals of the write column switches 24A to 24D so that any of the bit lines 23A to 23D can be connected to the write common data line 25 on condition that the signal 16 is set to the low level. Is done.
[0017]
The AND gates 20A to 20D output selection signals for the AND gates 26A to 26D and 27A to 27D. One of the decoding result signals of the address signals a0 to a15 is supplied to one input of the AND gates 20A to 20D. As is apparent from this description, the bit lines 23A to 23D are bit lines selected by one decode signal 18 of 16-bit address signals a0 to a15. Outputs of the OR gates 19A to 19D are given to the other inputs of the AND gates 20A to 20D. Decoding result signals 17A to 17D of 2-bit address signals a16 and a17 are supplied to one input of the OR gates 19A to 19D. The decode result signals 17A to 17D are regarded as signals for selecting one of the four bit lines 23A to 23D selected by the decode result signal 18. Therefore, although not particularly shown, the decode result signals 17A to 17D are used in common for all the decode result signals of the address signals a0 to a15. The signal 16 is given to the other inputs of the OR gates 19A to 19D. When the signal 16 is at a high level (read operation), the decoding result signals of the 2-bit address signals a16 and a17 are substantially ignored, and a 1-bit memory cell is selected from each of the memory units UNT0 to UNT3 and the common data line 22A to 22D. The signal 16 is set to a high level in response to a read operation. The decoding result signals 17A to 17D of the 2-bit address signals a16 and a17 have a substantial meaning when the signal 16 is at a low level, so that one memory unit of the memory units UNT0 to UNT3 is stored in each memory mat. A 1-bit memory cell is selected and connected to the common data line 25. The signal 16 is set to a low level in response to a write operation.
[0018]
In FIG. 1, 18-bit latch circuits 9 and 10 are arranged in series before the address decoder 8, and a 2-bit latch circuit 12 with a bypass function is arranged before the address decoder 11. The input of the latch circuit 12 is connected to the upper 2 bits of the latch circuit 10. The latch circuit 10 is supplied with 18-bit address signals a0 to a17 from an address input terminal 13 through an address buffer (not shown).
[0019]
The latch circuits 4, 7, 8, 9, 10, and 12 function as pipeline latch circuits and perform a latch operation in synchronization with the clock signals ckw and ck. These latch circuits are not particularly limited, and are configured to include a master / slave latch stage.
[0020]
1 is a timing timing controller which receives external control signals such as a chip select signal CS, a write enable signal WE, and an output enable signal OE, and an external clock signal CLK, and thereby operates in the SRAM. Control mode and operation timing.
[0021]
When the SRAM is brought into the chip selection state by the chip selection signal CS, the memory cell selection system from the address input terminal 13 to the memory array 2 and the selector selection system from the address decoder 11 are activated. The latch timing of the latch circuits 9, 10, and 12 at this time is controlled by the internal clock signal ck synchronized with the external clock signal CLK. When a read operation is instructed by the output enable signal in the chip selection state, the operation of the latch circuit 4 is selected. The latch operation of the latch circuit 4 is controlled by the internal clock signal ckr, and the clock cycle of the clock signal ckr is the same as the internal clock signal ck. In the read operation, the signal 16 is set to a high level. On the other hand, when a write operation is instructed by the write enable signal WE in the SRAM chip selection state, the operation of the latch circuits 7 and 8 is selected. The latch operations of the latch circuits 7 and 8 are controlled by an internal clock signal ckw, and the internal clock signal ckw is changed in synchronization with the internal clock signal ck when the write enable signal WE is activated. In the write operation, the signal 16 is set to a low level.
[0022]
The bypass function-equipped latch circuit 12 can select a signal latch operation and a signal through operation, and the selection is controlled by a way mode signal WMD applied to the external terminal 14. The bypass function-equipped latch circuit 12 performs a signal through operation according to the high level of the way mode signal WMD, and performs a latch operation in synchronization with the clock signal ck when the way mode signal WMD is at the low level.
[0023]
An example of the latch circuit 12 with the bypass function is shown in FIG. The master stage of the latch circuit 12 with the bypass function is configured by clocked inverters 120M and 121M, inverters 122M and 123M, and a NOR gate 124M. Similarly, the slave stage is configured by clocked inverters 120S and 121S, inverters 122S and 123S, and a NOR gate 124S. The The clocked inverters 120M and 120S perform an inverted output operation when the control terminal is set to a low level (logic value “0”), and a high output impedance when the control terminal is set to a high level (logic value “1”). Put into a state. Contrary to the above, the clocked inverters 121M and 121S perform an inverting output operation when the control terminal is set to the high level, and are set to the high output impedance state when the control terminal is set to the low level. A way mode signal WMD is supplied to one input terminal of the NOR gates 124M and 124S. Further, the inverted signal of the clock signal ck is supplied to the other input terminal of the NOR gate 124M included in the master stage, and the clock signal ck is supplied to the other input terminal of the NOR gate 124S included in the slave stage.
[0024]
In the bypass latch circuit 12 shown in FIG. 3, when the way mode signal WDM is at a high level, the outputs of both NAND gates 124M and 124S are fixed at a low level. As a result, the clocked inverters 120M and 120S perform an inverting output operation, and the clocked inverters 121M and 121S are brought into a high output impedance state. As a result, the latch circuit 12 with a bypass function outputs an input regardless of the clock signal ck. A through operation is performed in which the signal is transmitted through.
[0025]
On the other hand, in the bypass latch circuit 12 shown in FIG. 3, when the way mode signal WDM is at a low level, the clocked inverters 120M and 121M are controlled by applying an inverted signal of the clock signal ck to their control terminals. 120S and 121S are controlled by applying a clock signal ck to their control terminals. As a result, the master stage performs a latch operation and the slave stage performs a through operation in synchronization with the high level of the clock signal ck. In synchronization with the low level of ck, the master stage performs a latch operation, the slave stage performs a through operation, and the latch circuit 12 with a bypass function as a whole performs a latch operation in synchronization with the clock signal ck.
[0026]
When the SRAM 1 is used as a normal random access memory, the way mode signal WMD is set to a low level, whereby the latch circuit 12 performs a latch operation in synchronization with the clock signal ck. FIG. 4 shows an example of the read operation timing when the SRAM 1 is used as a normal random access memory. In normal random access, address signals a0 to a17 to be supplied to the address decoders 8 and 11 are supplied to the address input terminal 13 in parallel. The timing at which the address signals a0 to a15 supplied to the address input terminal 13 are output from the slave stage of the latch circuit 9, and the address signals a16 and a17 supplied to the address input terminal 13 are output from the slave stage of the latch circuit 12. The memory cell selection in the memory array 2 and the selection by the selector 3 for the selected memory cell are performed synchronously, and the 18 bits selected by the selector 3 are latched by the latch circuit 4. . If the read operation is continued, read data is obtained for each cycle of the clock signal ck, as exemplified by D0 and D1. In this random access operation, all of the latches 4, 9, 10, and 12 function as pipeline latches.
[0027]
When the SRAM is applied to the data memory unit of the set associative cache memory, the address signals a0 to a15 are index access for the cache memory and are supplied to the address decoder 8. At this time, the address signals a16 to a17 are used as way selection signals from the cache address memory unit and are supplied to the address decoder 11. FIG. 5 shows an example of the read operation timing when the SRAM 1 is applied to the data memory unit of the set associative cache memory. The way selection signal is a signal obtained as a result of the associative search in the cache address memory unit, and is delayed by, for example, one cycle of the clock signal CLK with respect to the supply timing of the index address signal. At this time, in order to recover the delay, the latch circuit 12 with a bypass function may be operated through. As described above, when the SRAM is applied to the data memory portion of the set associative cache memory, the way mode signal WMD is set to the high level, thereby causing the latch circuit 12 to pass through the clock signal ck regardless of the state. Perform the action. As a result, the timing at which the address signals a0 to a15 (index address) supplied to the address input terminal 13 are output from the slave stage of the latch circuit 9, and the address signals a16 and a17 (way selection) supplied to the address input terminal 13 are obtained. Signal) is outputted from the slave stage of the latch circuit 12, and the selection of the memory cell in the memory array 2 and the selection by the selector 3 for the selected memory cell are performed synchronously, and the selection is made by the selector 3. The 18 bits thus read are read out as data of the way related to the cache hit.
[0028]
FIG. 6 shows an example timing chart of the write operation of the SRAM 1. As can be seen from the figure, the selector 3 is not used in the write operation. The write operation is completed in the second cycle of the clock signal. Writing is performed at a timing one cycle earlier than the read operation. Therefore, when the SRAM 1 is used as a cache memory, if a cache hit occurs in a write access, the supply timing of the index address signal to the SRAM 1 as the data memory unit is delayed by one clock using an appropriate external circuit. Please understand.
[0029]
FIG. 7 shows a data processing system to which the SRAM is applied. What is indicated by 100 is a microprocessor, and a secondary cache memory 102 is connected to the microprocessor 100 via an external bus 101.
[0030]
Although not particularly limited, the microprocessor 100 has a 32-bit RISC (Reduced Instruction Set Computer) architecture. The microprocessor 100 has a floating point unit 103. Further, the microprocessor 100 has a central processing unit (CPU) 104, which is an integer unit capable of processing integers. The CPU 104 is coupled to the floating point unit 103 via an internal bus 105. The CPU 104 and the floating point unit 103 fetch instructions and data from the primary cache memory 106. The primary cache memory 106 is connected to the bus controller 108 via the cache bus 107. An instruction address and data address for external access caused by a cache miss or the like in the primary cache memory 106 are given to the bus controller 108. The bus controller 108 starts an external bus cycle in order to access an external memory or the like according to the instruction address or data address.
[0031]
When the external bus cycle is activated, the secondary cache memory 102 is searched, and in the case of a hit, data is read from the secondary cache memory 102 or data is written to the secondary cache memory 102. In the case of a cache miss, there is no particular limitation, but the cache fill is performed from the main memory or the like to the secondary cache memory, the necessary data is given to the data processor, or the write data is stored in the cache filled cache entry. The
[0032]
Although not particularly limited, what is indicated by 109 in FIG. 7 is a main memory, which is connected to the external bus 101 at the subsequent stage of the secondary cache memory 102. As the main memory 109, for example, the SRAM 1 can be used. In this case, since the main memory 109 is used as a normal random access memory, the way mode signal WDM is fixed to a low level by a process such as pull-down on the mounting circuit board.
[0033]
FIG. 8 shows the data memory unit 110 and the address memory unit 111 of the secondary cache memory 102. The secondary cache memory 102 is not particularly limited, but has a configuration as a known set associative cache memory having a plurality of ways. The SRAM 1 described with reference to FIG. 1 is used to configure the data memory unit 110 of the secondary cache memory 102. The address memory unit 111 has a field for storing a cache tag, a valid bit, and the like, and the data memory unit 110 has a field for holding a cache entry correspondingly. An address signal for external bus access by the bus controller 108 includes a tag address 112, an index address 113, and an offset 114. An index for the address memory unit 111 and the data memory unit 110 is performed by an index address 113. In the address memory unit 111, the indexed cache tag and the address tag 112 are compared. The comparison operation is performed for each way. The data memory unit 110 is accessed by a way selection signal 115, an index address 113, and an offset 114 in the case of a cache hit. The way selection signal 115, the index address 113, and the offset 114 correspond to the address signals a0 to a17 in FIG. The data memory unit 110 is accessed by the address signal. The way mode signal WMD is not particularly limited, but is fixed at a high level by pull-up processing on the mounting circuit board. In FIG. 8, an access path for cache fill operation and tag address writing is not shown.
[0034]
The SRAM 1 described above can be used for both general-purpose random access and the cache data memory unit. That is, it is not necessary to newly develop an SRAM dedicated to the cache data memory unit.
[0035]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, the pipeline latch means with a bypass function is not limited to a one-stage bypass latch circuit. When the supply timing of the way selection signal is expected to be delayed by two clock cycles or more, two or more bypass latch circuits may be provided, and a control terminal for selecting a latch operation and a signal through operation may be provided for each stage. . Further, the configurations of the memory array and the address decoder can be variously changed in addition to the above examples.
[0036]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0037]
That is, a selector for further selecting a memory cell selected in the memory array is provided, and a pipeline latch means with a bypass function is arranged in the address signal supply path to the address decoder for controlling the selection operation of the selector. When the semiconductor memory device is applied to the data memory unit of the set associative cache memory because a control terminal is provided for instructing whether to perform the latch operation or the signal through operation for the pipeline latch means with a function. Even if the way selection signal is delayed with respect to the supply timing of the index address signal, the pipeline latch means with bypass function is operated as a signal through operation instead of the latch operation only for a period necessary to recover the delay, At the required timing to recover the delay It can be output over data to the outside. Thereby, it can respond to the use of both a general purpose random access memory and a cache data memory part.
[Brief description of the drawings]
FIG. 1 is a block diagram of an SRAM as an example of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a logic circuit diagram showing an example of a logic configuration for column selection by an address decoder.
FIG. 3 is a logic circuit diagram of an example of a latch circuit with a bypass function.
4 is a timing chart showing an example of a read operation timing when the SRAM of FIG. 1 is used as a normal random access memory. FIG.
FIG. 5 is a timing chart showing an example of read operation timing when the SRAM of FIG. 1 is applied to a data memory unit of a set associative cache memory;
6 is a timing chart illustrating an example of a write operation of the SRAM in FIG. 1;
7 is a block diagram showing an example of a data processing system to which the SRAM of FIG. 1 is applied.
8 is a block diagram schematically showing a configuration of a data memory unit and an address memory unit of the secondary cache memory of FIG. 7;
[Explanation of symbols]
1 SRAM
2 Memory array
3 Selector
8,11 Address decoder
12 Latch circuit with bypass function
4, 9, 10 Latch circuit
WMD Way mode signal
14-way mode signal input terminal

Claims (1)

A microprocessor, which is connected via a bus to a microprocessor and a cache memory of the set associative type with m-way, the cache memory, the data processing system to have the address memory section and a data memory section There,
The part of the access address of the microprocessor is supplied in common to the data memory unit and the address memory section as an index address, the address memory section performs an associative search using the index address, the way selection signal according to the search hit Is provided to the data memory unit ,
Before Symbol data memory unit, the first address signal transmission path to the address decoder for selecting the m × n bits of the memory cell from the memory array in a data read operation, the pipeline latches operated in sync with the external clock signal And a selector that further selects an n-bit memory cell from among m × n-bit memory cells selected by the memory array, and an address signal is sent to a second address decoder that controls the selection operation of the selector. In the supply path, a pipeline latch means with a bypass function is arranged, and a control terminal for instructing whether to perform a latch operation or a signal through operation for the pipeline latch means with a bypass function is provided.
Wherein said external clock signal supplied to the data memory unit is a clock signal synchronized with the operation reference clock signal of the microprocessor, the index address is supplied to the first address decoder, the way selection signal the first The data processing system is characterized in that the control terminal is fixed to a level which is supplied to the address decoder of No. 2 and causes the pipeline latch means with bypass function to select a signal through operation.

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