JP3821834B2 - Parallel efficiency calculation method - Google Patents

Description

  The present invention relates to a performance evaluation technique for a parallel computer system and a technique for using a result of the performance evaluation. The technology of the present invention can be applied to fields (structural analysis, fluid analysis, computational chemistry, etc.) handled by conventional high performance computing (HPC), biosimulation developed on a grid or cluster, web ( Web) service (for example, MtoM (Machine to Machine)) is applicable to all fields that perform parallel processing.

  The performance of the parallel computer system varies greatly depending on the application. Therefore, its performance evaluation is important. There are two methods for evaluating the performance of parallel computer systems: (1) a specific process performed by various computers for comparison, and (2) how much performance a computer exhibits against its own potential. There are two types of self-contained types. The former is mainly used as a benchmark test for performance comparison between computers. The latter needs to be implemented in actual operation after introduction. Although this self-contained performance evaluation can be performed using an index called parallel efficiency, it has not been actually implemented. In addition, parallel performance evaluation (so-called scalability evaluation) is possible by measuring time while changing the number of processors p instead of parallel efficiency and comparing with the ideal degree of decrease 1 / p, but several time measurements are required. Therefore, it is not usually implemented. Scalability evaluation is qualitative, and strict parallel performance evaluation cannot be performed. Therefore, currently, it is not possible to detect processes with poor parallel efficiency, and they are in an open state.

例えば式（１）は、柄谷，中村，奥田，矢川；並列有限要素法コードのGeoFEMの性能評価，Transactions of JSCES, No.20000022 (2000)という文献に開示されている。
”ＵＸＰ／Ｖ アナライザ使用手引書 Ｖ２０用”，富士通株式会社，１９９９年９月３０日，第２版，ｐｐ．１３−３１（マニュアル2004-00476-001） 特開２０００−２９８５９３号公報 特開平０９−２６５４５９号公報 The performance evaluation of the parallel processing based on the parallel efficiency is performed by obtaining the parallel efficiency E _p (p) determined by the following equations (1) and (2). Here, p is the number of processors, τ (1) is the processing time when executed by one processor, τ (p) is the processing time when the same processing is executed by p processors, and τ _i (p) is 1 ≦ The processing time of the i-th processor with i ≦ p.

For example, the equation (1) is disclosed in the literature: Karaya, Nakamura, Okuda, Yagawa; GeoFEM performance evaluation of parallel finite element method code, Transactions of JSCES, No. 20000022 (2000).
"UXP / V Analyzer User's Manual for V20", Fujitsu Limited, September 30, 1999, 2nd edition, pp. 13-31 (Manual 2004-00476-001) JP 2000-298593 A Japanese Patent Application Laid-Open No. 09-265459

However, even if the parallel efficiency was determined by the conventional method, the quantitative relationship with the parallel performance impediment factors was not clear, so it was not possible to know which impediment factor worked for the parallel efficiency. Further, some parallel performance evaluation techniques (for example, Japanese Patent Application No. 2001-241121, US Patent Application No. 09/998160) include “the load balance is maintained and each processing time γ _i ( Parallel part), χ _{i, 1} (redundant processing part), χ _{i, 2} (communication part), χ _{i, others} (other parallel performance impediment factors) are required. There was a problem that it could only be applied.

  In addition, it is difficult to apply the conventional method to parallel processing using a grid or cluster. This is because when resources such as memory, data, and CPU, which are distributed on a grid or cluster, are collected in one processor, the processing is often so large that it cannot be realized by one processor. That is, it is difficult to measure τ (1) itself. In formula (1), to obtain τ (1) and τ (p) by actual measurement is based on the premise that the performance of the processors is the same, but the performance of individual processors on the grid or cluster is usually different. There is also a problem that the correct parallel efficiency cannot be determined even if the actually measured τ (1) and τ (p) are substituted into the equation (1).

  Therefore, the object of the present invention is to remove the condition that “the load balance is maintained”, and can be applied to various kinds of parallel processing including a heterogeneous processor environment, and between the parallel efficiency, the parallel performance evaluation index, and the parallel performance impediment factor. It is to provide a parallel processing performance evaluation technology that performs quantitative association.

  Another object of the present invention is to provide a technique for enabling an appropriate operation of a parallel computer system using parallel efficiency or the like.

  Furthermore, another object of the present invention is to provide a technique for enabling appropriate judgment on capacity enhancement, update, etc. of a parallel computer system using parallel efficiency or the like.

  Still another object of the present invention is to provide a technique for appropriately executing tuning of a program executed in a parallel computer system and selection of an algorithm using parallel efficiency or the like.

により計算し、記憶装置に格納するステップとを含む。なお、並列効率Ｅ_p(p)は、ｐ個のプロセッサによって並列処理を行った場合における最長の処理時間がｐ個のプロセッサの各処理時間τ_i(p)に等しいと仮定した場合の総処理時間に対する、並列処理を行わない場合における処理時間の割合である。 The parallel efficiency calculation method for calculating the parallel efficiency E _p (p) of the parallel computer system according to the first aspect of the present invention is the parallel computer system processing time γ _i (p) (i Indicates the processor number), and the processing time χ _{i, j} (p) of each parallel performance impediment factor j is measured and stored in the storage unit of the parallel computer system, and the data acquisition unit and load balance contribution rate calculation A parallel computing rate calculation unit, a parallel performance impediment factor contribution rate calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device. The step of acquiring the processing time γ _i (p) of the portion and the processing time χ _{i, j} (p) of each parallel performance impediment factor j and storing them in the log data storage unit, and the log data by the load balance contribution rate calculation unit Case in storage A load balance contribution ratio Rb (p) representing a degree of load balance between processors included in the parallel computer system using the data obtained, and storing the load balance contribution ratio Rb (p) in a storage device; By using the data stored in the log data storage unit by the conversion rate calculation unit, the virtual parallelization rate Rp ( all processors included in the parallel computer system using the data stored in the log data storage unit by the virtual parallelization rate calculation step of calculating p) and storing it in the storage device, and the parallel performance impediment factor contribution rate calculation unit All processing parallel performance impediment factor contribution ratio Rj representing the percentage of processing time chi _{i, j} of each parallel performance impediment factor portion j (p) (p) calculated for time storage of The parallel performance impediment factor contribution rate calculation step to be stored and the parallel efficiency calculation unit store the load balance contribution rate Rb (p), virtual parallelization rate Rp (p), and parallel performance impediment factor contribution rate Rj stored in the storage device. (p) and the parallel efficiency E _p (p)

And calculating and storing in a storage device. Note that the parallel efficiency E _p (p) is the total processing when it is assumed that the longest processing time is equal to each processing time τ _i (p) of p processors when parallel processing is performed by p processors. This is the ratio of processing time to time when parallel processing is not performed.

により計算し、前記記憶装置に格納するステップとを含む。 The parallel efficiency calculation method according to the second aspect of the present invention is a parallel computer system in which processing time γ _i (p) (i indicates a processor number) of a parallel calculation part in processing and each parallel performance impediment factor j A step of measuring the processing time χ _{i, j} (p) and storing it in the storage unit of the parallel computer system, a data acquisition unit, a load balance contribution rate calculation unit, an auxiliary index calculation unit, and a parallel performance impediment factor contribution rate calculation unit A parallel efficiency calculation unit, a log data storage unit, and a storage device, a computer data acquisition unit, from the storage unit of the parallel computer system, the processing time γ _i (p) of the parallel calculation unit and each parallel performance impediment factor j It acquires processing time χ _{i, j (p),} and storing the log data storage unit, the load balance contribution ratio calculation unit, by using the data stored in the log data storage, is included in the parallel computer system The load balance contribution ratio Rb (p) representing the degree of load balance between the processors is calculated, and the data stored in the log data storage section by the load balance contribution ratio calculation step stored in the storage device and the auxiliary index calculation section Is used to calculate the acceleration rate A _p (p) that represents the limit of improvement in the degree of reduction in processing time by parallelizing the processing executed in the parallel computer system, and to store the acceleration rate in the storage device, and the parallel performance Using the data stored in the log data storage unit by the inhibition factor contribution rate calculation unit, the processing time χ _{i, j} (p of each parallel performance inhibition factor part j with respect to the total processing time of all processors included in the parallel computer system ), The parallel performance impediment factor contribution ratio Rj (p) is calculated and stored in the storage device. Been, by using the load balance contribution ratio Rb (p) and the acceleration rate A _p (p) and the parallel performance impediment factor contribution ratio Rj (p), parallel efficiency E _p a (p)

And storing in the storage device.

により計算し、前記記憶装置に格納するステップとを含む。 The parallel efficiency calculation method according to the third aspect of the present invention is a parallel computer system in which processing time γ _i (p) (i indicates a processor number) of a parallel calculation part in processing and each parallel performance impediment factor j Measuring the processing time χ _{i, j} (p) and storing it in the storage unit of the parallel computer system; a data acquisition unit, a load balance contribution rate calculation unit, a parallel performance impediment factor contribution rate calculation unit, and a parallel efficiency calculation unit A data acquisition unit of a computer having a log data storage unit and a storage device, from the storage unit of the parallel computer system, the processing time γ _i (p) of the parallel calculation part and the processing time χ _{i of} each parallel performance impediment factor j _, get the _j (p), and storing the log data storage unit, the load balance contribution ratio calculation unit, by using the data stored in the log data storage, among the processors included in the parallel computer system The load balance contribution ratio Rb (p) representing the degree of load balance is calculated and stored in the log data storage section by the load balance contribution ratio calculation step stored in the storage device and the parallel performance impediment factor contribution ratio calculation section. Is used to calculate the parallel performance impediment factor contribution ratio Rj (p) that represents the ratio of the processing time χ _{i, j} (p) of each parallel performance impediment factor part j to the total processing time of all processors included in the parallel computer system. The parallel performance impediment factor contribution rate calculation step stored in the storage device and the load efficiency contribution ratio Rb (p) and the parallel performance impediment factor contribution rate Rj (p) stored in the storage device by the parallel efficiency calculation unit To calculate parallel efficiency E _p (p)

And storing in the storage device.

により計算し、記憶装置に格納するステップとを含む。 In the parallel efficiency calculation method according to the fourth aspect of the present invention, in a parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and each parallel performance impediment factor j processing time chi _{i, j} and (p) were measured, and storing in the storage unit of the parallel computer system, a data acquisition unit and the load balance contribution ratio calculating unit and the virtual parallelization ratio calculator and the parallel efficiency calculation unit aid A computer data acquisition unit having an index calculation unit, a log data storage unit, and a storage device allows the parallel computer part processing time γ _i (p) and the processing time of each parallel performance impediment factor j from the storage unit of the parallel computer system. get the χ _{i, j (p),} and storing the log data storage unit, the load balance contribution ratio calculation unit, by using the data stored in the log data storing unit, each process included in the parallel computer system The load balance contribution ratio Rb (p) representing the degree of load balance between the servers is calculated and stored in the log data storage section by the load balance contribution ratio calculation step stored in the storage device and the virtual parallelization ratio calculation section. Virtual parallelization that calculates a virtual parallelization rate Rp (p) that represents a proportion of time of a part that is calculated in parallel by each processor among processes executed in a parallel computer system using data, and stores it in a storage device The processing time γ _i (p) of the parallel calculation portion of the processing performed in each processor included in the parallel computer system using the data stored in the log data storage unit by the rate calculation step and the auxiliary index calculation unit Is calculated by an auxiliary index calculating step for storing the sum α of the processing times and the sum β of the processing time of the processing executed in each processor and storing it in the storage device, and the parallel efficiency calculating unit. Using the α, β, load balance contribution rate Rb (p), and virtual parallelization rate Rp (p) stored in the storage device, the parallel efficiency E _p (p) is calculated.

And calculating and storing in a storage device.

により計算し、前記記憶装置に格納するステップとを含む。 In the parallel efficiency calculation method according to the fifth aspect of the present invention, in a parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and each parallel performance impediment factor j If there is a parallel performance impediment other than the processing time χ _{i, j} (p) and redundant processing, the processing time X _{i, j} (p ) And storing in the storage unit of the parallel computer system, the data acquisition unit of the computer having the data acquisition unit, the auxiliary index calculation unit, the parallel efficiency calculation unit, the log data storage unit and the storage device, in parallel When there are parallel performance impediments other than the processing time γ _i (p) of the parallel computation part, the processing time χ _{i, j} (p) of each parallel performance impediment factor j, and redundant processing from the storage unit of the computer system Acquire processing time X _{i, j} (p) and store log data When the processing is performed by one processor using the data stored in the log data storage unit by the step stored in the unit and the data stored in the log data storage unit, this corresponds to the total processing time of the parallel performance impeding part of the processing. The first processing time ρ was calculated and stored in the storage device, and the auxiliary index calculation unit was implemented in each processor included in the parallel computer system using the data stored in the log data storage unit The second processing time α, which is the sum of the processing times γ _i (p) of the parallel calculation part of the processing, is stored in the storage device, and the parallel efficiency calculation unit determines the processor used in the parallel computer system. P, the longest processing time τ (p) when parallel processing is performed by p processors, the first processing time ρ and the second processing time stored in the storage device The parallel efficiency E _p (p) is calculated using the processing time α of

And storing in the storage device.

  According to a sixth aspect of the present invention, a parallel efficiency calculation method for calculating parallel efficiency of a parallel computer system has a load balance contribution ratio Rb (p) representing a degree of load balance between processors included in the parallel computer system. A load balance contribution ratio calculating step for calculating and storing in a storage device, and a virtual parallelization ratio Rp (p) representing a time ratio of a part of the processing executed in the parallel computer system that is calculated in parallel by each processor A virtual parallelization rate calculating step for calculating and storing in the storage device, and a parallel performance impediment factor contribution ratio Rj (representing the ratio of processing time of each parallel performance impediment factor portion to the total processing time of all processors included in the parallel computer system) p) is calculated and stored in the storage device in parallel performance impediment factor contribution rate calculation step, load balance contribution rate Rb (p) and virtual parallelization rate Rp (p) in parallel Calculate the parallel efficiency by using the ability inhibitory factor contribution ratio Rj (p) (Equation (4-4) in the example embodiment), and storing in the storage device.

  Thereby, the parallel efficiency is quantitatively related to parallel performance evaluation indexes such as a load balance contribution rate, a virtual parallelization rate, and a parallel performance impediment factor contribution rate.

According to a seventh aspect of the present invention, there is provided a parallel efficiency calculation method for calculating parallel efficiency of a parallel computer system, wherein a load balance contribution ratio Rb (p) representing a degree of load balance among processors included in the parallel computer system is calculated. Calculate and store the load balance contribution ratio calculation step to be calculated and stored in the storage device, and the acceleration rate A _p (p) representing the limit of improvement in the degree of reduction in processing time by parallelizing the processing executed in the parallel computer system. Acceleration rate calculation step to be stored in the apparatus and parallel performance impediment factor contribution ratio Rj (p) representing the ratio of the processing time of each parallel performance impediment factor part to the total processing time of all processors included in the parallel computer system, The parallel performance impediment factor contribution ratio calculation step stored in the storage device, the load balance contribution ratio Rb (p), the acceleration rate A _p (p), and the parallel performance impediment contribution ratio Rj (p) are used in parallel. Calculating column efficiency (for example, equation (4-5) in the embodiment), and storing it in the storage device.

  Thereby, the parallel efficiency is quantitatively related to a parallel performance evaluation index such as a load balance contribution ratio and a parallel performance impediment factor contribution ratio and an auxiliary index such as an acceleration rate.

  A parallel efficiency calculation method for calculating the parallel efficiency of a parallel computer system according to an eighth aspect of the present invention provides a load balance contribution ratio Rb (p) representing a degree of load balance between processors included in the parallel computer system. A load balance contribution ratio calculation step for calculating and storing in the storage device, and a parallel performance impediment factor contribution ratio Rj () representing the ratio of the processing time of each parallel performance impediment factor part to the total processing time of all processors included in the parallel computer system p) is calculated and the parallel efficiency is calculated using the parallel performance impediment factor contribution ratio calculation step stored in the storage device, the load balance contribution ratio Rb (p) and the parallel performance impediment contribution ratio Rj (p) ( For example, the step (8-2) in the embodiment and the step of storing in the storage device are included.

  For example, if the sum of the processing times of the parallel computing portion of the processing executed in each processor included in the parallel computer system is substantially the same as the processing time when the same processing is performed by one processor, that is, almost parallel calculation can be performed. In the case of such processing contents, it can be calculated in this way.

  A parallel efficiency calculation method for calculating the parallel efficiency of a parallel computer system according to a ninth aspect of the present invention provides a load balance contribution ratio Rb (p) representing a degree of load balance between processors included in the parallel computer system. A load balance contribution ratio calculating step for calculating and storing in a storage device, and a virtual parallelization rate Rp (p) representing a time ratio of a part of the processing executed in the parallel computer system that is calculated in parallel by each processor The virtual parallelization rate calculation step for calculating and storing in the storage device, the sum of the processing time of the parallel calculation portion of the processing executed in each processor included in the parallel computer system, and the processing of the processing executed in each processor The parallel efficiency is calculated using the sum of time, the load balance contribution ratio Rb (p), and the virtual parallelization ratio Rp (p) (for example, in the embodiment) (Equation (9-1)) and storing in the storage device. It is a modification of the 1st mode of the present invention.

  The parallel efficiency calculation method for calculating the parallel efficiency of the parallel computer system according to the tenth aspect of the present invention corresponds to the total processing time of the parallel performance impeding part of the processing when the processing is performed by one processor. Calculating a processing time of 1 and storing the processing time in a storage device; and calculating a second processing time that is a sum of processing times of a parallel computing portion of processing executed in each processor included in the parallel computer system; A step of storing in the storage device; the number of processors used in the parallel computer system; the longest processing time of the processing times executed in each processor included in the parallel computer system; and the first processing time; Calculating parallel efficiency using the second processing time (for example, equation (9-2) in the embodiment), and storing in the storage device; Including.

  The parallel efficiency can be calculated with only a processing time obtained by one measurement based on a predetermined modeling.

  Further, in the load balance contribution ratio calculation step described above, the load balance contribution ratio Rb (p) is included in the parallel computer system, and the total processing time of the processes executed in all the processors included in the parallel computer system is included in the parallel computer system. A calculation may be made by dividing by the longest processing time of processing times executed in each processor and the number of processors used in the parallel computer system (for example, equation (5) in the embodiment). Is possible.

  Furthermore, in the virtual parallelization rate calculation step described above, the virtual parallelization rate Rp (p) is set to the sum of the processing time of the parallel calculation portion among the processing executed in each processor included in the parallel computer system. It is also possible to adopt a configuration such that calculation is performed by dividing by the processing time corresponding to the third processing time when the same processing is performed by the processor (for example, Expression (6-1) in the embodiment).

Also, in the parallel performance impediment factor contribution rate calculation step described above, the parallel performance impediment factor contribution ratio R _j (p) for the specific parallel performance impediment factor is determined as the specific parallel performance in each processor included in the parallel computer system. It is also possible to calculate by dividing the sum of the processing times of the obstruction factor part by the sum of the processing times of the processors included in the parallel computer system (for example, equation (7) in the embodiment). It is.

  Further, in the acceleration rate calculation step described above, when the same processing is performed by one processor, the above acceleration rate is the sum of the processing times of the parallel calculation portion of the processing executed in each processor included in the parallel computer system. The virtual parallelization rate calculated by dividing by the processing time corresponding to the third processing time is calculated as the reciprocal of the value subtracted from 1 (for example, the expression (6-2) in the embodiment) A configuration is also possible.

  Furthermore, the processing time described above may be represented by the number of confirmations of the corresponding event in addition to the actual processing time.

  Moreover, the structure which further includes the step which calculates the auxiliary | assistant parameter | index by multiplying the calculated parallel efficiency by the number of processors used in the parallel computer system, and stores it in a memory | storage device may be sufficient. As a result, it is possible to present how many processors have been processed in the parallel computer system.

  Furthermore, when the third processing time described above is performed by one processor, each of the processing included in the parallel computer system and the first processing time corresponding to the total processing time of the parallel performance impeding portion of the processing. The configuration may be such that the calculation is performed by the sum of the second processing time that is the sum of the processing times of the parallel calculation portion of the processing performed in the processor (for example, Expression (15) in the embodiment). Calculation of parallel efficiency and the like becomes possible by measuring the processing time once by the predetermined modeling.

  Furthermore, the first processing time described above is calculated by the sum of processing times of redundant processing or communication processing among the processing executed in each processor included in the parallel computer system (for example, the expression ( 12-1) etc.) is also possible.

  Further, in the sixth to tenth aspects of the present invention, the step of setting the target parallel efficiency, and the optimum processor number is calculated by dividing the product of the calculated parallel efficiency and the number of processors by the target parallel efficiency, and stored. A configuration that further includes a step of storing in the apparatus is also possible. Even if a large number of processors are input, the processing time is not necessarily shortened. If the optimal number of processors can be calculated in this way, it is possible to prevent unnecessary resources from being input.

  Further, in the sixth to tenth aspects of the present invention, a step of setting an increased operating time and predicted parallel efficiency at the time of system enhancement, and processing of processing executed in each processor currently included in the parallel computer system The sum of the sum of time and the calculated parallel efficiency for all processes, and the product of the increased operating time and predicted parallel efficiency is the sum of the operating time of each processor currently included in the parallel computer system. In other words, the system may further include a step of calculating the acceleration rate at the time of system enhancement (for example, the equation (18) in the embodiment) and storing it in the storage device. Appropriate quantitative guidelines can be given to system operators during system enhancement.

  Further, in the sixth to tenth aspects of the present invention, a step of setting a performance factor of a new parallel computer system with respect to the parallel computer system, and calculating an estimated parallel efficiency using the performance factor of the new parallel computer system, And a step of storing in the storage device. Quantitative guidelines can be given at the time of system replacement.

  Furthermore, in the sixth to tenth aspects of the present invention, the sum of products for all the processes of the sum of the processing times of the processes executed in each processor currently included in the parallel computer system and the calculated parallel efficiency is calculated in parallel. The system further includes a step of calculating the system operation efficiency by dividing by the sum of the operating time of each processor currently included in the computer system (for example, the equation (17) in the embodiment) and storing it in the storage device It may be. Using the system operation efficiency considering the parallel efficiency as in the present invention as compared with the conventional concept of operating rate enables the system operation status to be evaluated in a more realistic manner.

  Further, in the sixth to tenth aspects of the present invention, the step of setting the target processing time, the step of calculating the target parallel efficiency using the target processing time and storing it in the storage device, and the validity of the target parallel efficiency It may be configured to further include a step of confirming. For example, the target parallel efficiency can be calculated by linear extrapolation.

  Further, when the validity of the target parallel efficiency is confirmed, the step of calculating the parallel efficiency after the tuning is performed and storing it in the storage device, and the step of comparing the parallel efficiency after the tuning is performed with the target parallel efficiency; May be included. Tuning of applications and the like can be performed from a more quantitative viewpoint.

  In addition, in the sixth to tenth aspects of the present invention, the step of setting the target processing time and the estimated value of the number of processors required using the parallel efficiency of the algorithm for each different algorithm are calculated and stored in the storage device. The number of processors calculated for different algorithms is smaller than the acceleration rate that represents the limit of improvement in the degree of reduction in processing time due to parallelization of processing by the algorithm executed in the parallel computer system, and the estimated value of the number of processors. The configuration may further include a step of extracting an algorithm having a minimum value from the estimated values. An algorithm that can further improve parallel efficiency can be quantitatively selected.

  The parallel efficiency calculation method according to the present invention can be implemented by a program and a computer, and when the program is executed by a computer, the computer becomes a parallel efficiency calculation device. Such a program is stored in a storage medium or storage device such as a flexible disk, a CD-ROM, a magneto-optical disk, a semiconductor memory, or a hard disk. Also, it may be distributed via a network or the like. The intermediate processing result is temporarily stored in the memory.

  As described above, according to the present invention, the condition that “the load balance is maintained” is removed, and the present invention can be applied to various kinds of parallel processing including a heterogeneous processor environment including grid computing. A quantitative relationship between the performance evaluation index and the parallel performance impediment factor can be made.

  Further, according to another aspect, the parallel computer system can be appropriately operated using parallel efficiency or the like.

  Furthermore, according to another aspect, it is possible to make an appropriate determination on the capacity enhancement, update, etc. of the parallel computer system using parallel efficiency or the like.

  Furthermore, according to another aspect, it becomes possible to appropriately execute tuning of a program executed in a parallel computer system and selection of an algorithm using parallel efficiency or the like.

[Principle of the present invention]
In the present invention, the parallel by describing in parallel performance metrics efficiency E _p a (p), linking the parallel efficiency E _p a (p) in parallel performance impediment factor quantitatively. As shown in FIG. 2, the parallel processing time tau _i (p) is the processing time of parallel computing section gamma _i (p), wherein the sum of the processing time chi _{i, j} of each parallel performance impediment factor j (p) It can be expressed as (3). Here, 1 ≦ j ≦ j _Others . In FIG. 2, i is a processor number and p is the number of processors. In FIG. 2, only the processor i and the processor i + 1 are shown.

Then, formula (1) is modified as follows, and load performance contribution index Rb (p), virtual parallelization ratio Rp (p), and parallel performance impediment factor contribution ratio Rj (p) are introduced. And describe the parallel efficiency E _p (p).

The transformation from the formula (1) to the formula (4-1) is performed by multiplying the numerator and denominator of the formula (1) by the sum of τ _i (p) for i. Further, the transformation to the equation (4-2) changes the position of each element in the equation (4-1), and adds the numerator and denominator of the equation (4-1) to the sum of i of γ _i (p). This is done by multiplying Further, the following expression is derived from Expression (3). This represents the sum of τ _i (p) for i.

また加速率Ａ_p(p)を用いると以下のようにも表される。

Then, the following equation is derived from the load balance contribution rate Rb (p), the virtual parallelization rate Rp (p), and the parallel performance impediment factor contribution rate Rj (p).

When the acceleration rate A _p (p) is used, it is also expressed as follows.

なお、並列性能阻害要因はｊで番号付けされる。 The load balance contribution rate Rb (p), the virtual parallelization rate Rp (p), the parallel performance impediment factor contribution rate Rj (p), and the acceleration rate A _p (p) are expressed as follows.

The parallel performance impediment factors are numbered with j.

The state where the load balance is maintained is a state where the processing time τ _i (p) of the processor is equal as shown in FIG. Equation (5) represents this state as Rb (p) = 1, and further represents a state that cannot be maintained as 1 / p ≦ Rb (p) ≦ 1. As shown in FIG. 3, when only one processor is used for parallel processing, the numerator of equation (5) becomes τ (p), so the load balance contribution ratio Rb (p) is a lower limit of 1 / p. Become. Further, according to the equation (5), the load balance contribution ratio Rb (p) is a ratio of the parallel efficiency E _p (p), which makes it easy to intuitively understand the parallel performance.

The virtual parallelization rate Rp (p) is the ratio of the sum of the processing times γ _i of the parallel computing units to τ ₁ (1). When this is smaller than 1, it indicates that the process includes a process that cannot be processed in parallel. By this ratio, the upper limit of the parallel performance can be expressed as the acceleration rate A _p (p). A _p (p) is an ideal upper limit A _p (p) = τ (1) / Σ _j χ _{1, j} (1) = 1 / (1- (Σ _i γ _i (p) / τ (1))). Normal τ (1) / τ (p) is smaller than A _p (p) due to parallel performance impediment factors.

The parallel performance impediment factor contribution ratio Rj (p) is standardized by the sum of i of τ _i (p) as shown in Equation (7). The contribution can be grasped as a percentage of processing time. In addition, since this ratio becomes the ratio of parallel efficiency, it is possible to quantitatively grasp the inhibition of parallel performance.

すなわち、並列効率Ｅ_p(p)はτ(1)という推定値を用いずに済むので、正確に決定することができる。一方、条件式（８−１）に関係なく、式（８−２）を、式（４−４），（４−５）の代替値として並列性能評価において用いることも可能である。この場合、式（８−２）の値はＲp(p)≦１ゆえ、式（４−４）、（４−５）の値に等しいか小さい値となる。 All of the variables in equations (2), (5), (6-1), and (7) can be measured during parallel execution except for τ (1). When equation (8-1) holds, the virtual parallelization rate Rp (p) is approximately 1 from equation (6-1), and equation (4-4) is equivalent to equation (8-2).

That is, the parallel efficiency E _p (p) can be determined accurately because it is not necessary to use the estimated value τ (1). On the other hand, irrespective of the conditional expression (8-1), the expression (8-2) can be used in the parallel performance evaluation as an alternative value of the expressions (4-4) and (4-5). In this case, since the value of the equation (8-2) is Rp (p) ≦ 1, the value is equal to or smaller than the values of the equations (4-4) and (4-5).

式（９−１）は、式（４−３）からロードバランス寄与率Ｒb(p)及び仮想並列化率Ｒp(p)のみを用いて変形した結果である。 The parallel efficiency E _p (p) can also be calculated by the equations (4-4), (4-5), (8-2) and the following equation (9-1) described above.

Expression (9-1) is a result of transformation from Expression (4-3) using only the load balance contribution ratio Rb (p) and the virtual parallelization ratio Rp (p).

ここでγ₁(1)とχ_1,j(1)を、γ_i(p)とχ_i,j(p)を用いてモデル化する。グリッドやクラスタのように異なったＣＰＵ性能を有する計算機による並列処理でのτ₁(1)の実測は不可能であるため、このモデル化によりτ(1)が決定でき、式（６−１）の仮想並列化率Ｒp(p)を計算することが可能となる。 Also, from equation (3), τ (1) becomes equation (10).

Here, γ ₁ (1) and χ _{1, j} (1) are modeled using γ _i (p) and χ _{i, j} (p). Since it is impossible to actually measure τ ₁ (1) in parallel processing by computers having different CPU performances such as grids and clusters, τ (1) can be determined by this modeling, and Equation (6-1) It is possible to calculate the virtual parallelization rate Rp (p).

この式（１１）の概念図を図４に示す。式（１１）のモデル化により、個々のプロセッサの性能が異なっている場合でも、仮想的に１プロセッサのγ₁(1)の時間を決めることができる。 When the processor performance is the same and ideal, when the parallel computing unit is processed by p processors, the processing time is 1 / p compared to p = 1. In this case, a _{τ i (p) = γ i} (p), can be obtained when any processor gamma _i a (p) p multiplies γ _{1 (1).} On the other hand, computers having different CPU performances usually exist on a grid or cluster. Based on γ _i (p) measured in p processors, γ ₁ (1 ) Is estimated as shown in Equation (11).

A conceptual diagram of this equation (11) is shown in FIG. By modeling the equation (11), the time of γ ₁ (1) of one processor can be virtually determined even if the performance of each processor is different.

In addition, χ _{1, j} (1) is modeled by dividing it into two processes, that is, redundant processing and others. All processing times not belonging to γ ₁ (1) are included in χ _{1, j} (1).

ここでiiは以下の式におけるiiである。

(1) Modeling of redundant processing time When each processor performs exactly the same processing, it is called redundant processing here. This processing is not parallel processing, and the processing time does not decrease even if the number of processors increases. Therefore, j = 1 is set as a redundancy process, and the time χ _1,1 (1) is modeled as shown in equations (12-1) to (12-4).

Here, ii is ii in the following formula.

  Redundant processing is processing that is the same procedure (processing content) but processing different data in parallel, so-called data parallel processing. In the case of data parallel, to maintain load balance, it is assumed that the CPU performance is parallel processing by the same processor. Therefore, it can be considered that the difference in the redundant processing time for each processor is due to the variation caused by the time measurement of each processor. In this case, it is appropriate to apply Expression (12-1) obtained by averaging the measurement values of the processors.

On the other hand, it is assumed that processors having different performances are mixed in the grid and cluster. In order to accurately grasp the influence of the processors having different performances, the equations (12-2) and (12-3) are used. If Expression (12-2) is used, the virtual parallelization rate Rp (p) of Expression (6-1) is estimated to be the minimum, and the parallel efficiency E _p (p) is maximized. If Expression (12-3) is used, the virtual parallelization rate Rp (p) is estimated to the maximum, and the parallel efficiency E _p (p) is minimized. By comparing these two parallel efficiencies E _p (p), it is possible to detect that data parallel processing is being performed by processors having different CPU performances.

τ (p) is determined by equation (2), and the redundant processing time of the processor i is the value of equation (12-4). Therefore, if it is considered that the data for which the parallel efficiency E _p (p) is determined is analyzed, the use of Expression (12-4) is appropriate. On the other hand, this equation means that χ _1,1 (1) is determined only from the information of the processor ii, and has a drawback that it cannot detect a case that is significantly different from the values of other processors. As an example of this, FIG. 5 shows a case where the processor whose CPU performance is 1/5 is the processor 1 (i = 1). In the equation (12-4), the redundant processing time is evaluated only by the value of the processor 1. In the expression (12-1), evaluation is performed by averaging the values of the four processors. In the expression (12-2), the evaluation is performed using the value of the processor 1, and in the expression (12-3), the evaluation is performed using the values of the processors with i = 2, 3, and 4. Therefore, it is appropriate to use other definitions as necessary based on the formula (12-1).

(2) Modeling χ _{1, j} (1) (2 ≦ j ≦ j _Others ) When the processing time due to the parallel performance impediment factor is actually measured, there is a case where χ _{1, j} (1) ≠ 0. Since this processing time is not decrease after parallel processing, are reflected in the virtual parallelization ratio Rp (p) of the formula (6-1), the acceleration rate A _p of formula (6-2) becomes a finite value, the processing To determine the upper limit of the number of processors that are meaningful. Therefore the processing time by the parallel performance impediment factors other than the redundant processing _{χ 1, j (1) (} 2 ≦ j ≦ j Others), a p = 1 the processing time chi _{1, j} and (1) p> 1 the processing time The expression (13-2) is modeled as in Expression (13-1), and the processing time Χ _{i, j} due to the parallel performance impediment that occurs when χ _{i, j} (p) and p> 1 and depends on p Measure (p) to obtain χ _{1, j} (1). That is, χ _{1, j} (1) = χ _{i, j} (p) −Χ _{i, j} (p), and the two terms on the right side are both obtained by measurement.

As an example, in the case of χ _{1, j} (1) ≠ 0, the processing time of p = 1 is shown in FIG. 6A, and the processing time of p = 4 is shown in FIG. 6B. As shown in FIG. 6B, χ _{i, 2} (p) at the time of parallel processing is an expression obtained by adding Χ _{i, 2} (p) to the processing time χ _1,2 (1) of p = 1 -1). Such a phenomenon is observed when the preprocessing until the communication hardware is activated by communication or the like is executed even when p = 1.

例えば図６（ｂ）ではχ_i,2(p)＝χ_1,2(1)＋Χ_i,2(p)と実測されるので、Χ_i,2(p)＝５，６，７，８を実測して式（１３−３），（１３−４），（１３−５）からχ_1,2(1)＝５を算出できる。この値は図６（ａ）のχ_1,2(1)と一致する。 From the equations (13-1) and (13-2), χ _{1, j} (1) (2 ≦ j ≦ j _Others ) is represented by the equations (13-3), (13-4), (13- 5).

For example, in FIG. 6B, since it is actually measured as χ _{i, 2} (p) = χ _1,2 (1) + Χ _{i, 2} (p), Χ _{i, 2} (p) = 5, 6, 7, 8 Χ _1,2 (1) = 5 can be calculated from the equations (13-3), (13-4), and (13-5). This value coincides with χ _1,2 (1) in FIG.

₍₃₎ χ _i, jothers not be measured by classifying the determination method parallelism impediment _{(p) χ i, jothers (} p) is found from Equation (13-6).

また、式（８−１）は、以下のように変形される。

この式が成り立つためには式（１４）の条件を満たす必要がある。この条件式は測定値より求めた値の大小関係の比較であるため、具体的に判定を行うことができる。

Next, Formula (10) is rewritten by the following formula by Formula (11) obtained by modeling.

Moreover, Formula (8-1) is deform | transformed as follows.

In order for this equation to hold, the condition of equation (14) must be satisfied. Since this conditional expression is a comparison of the magnitude relationship of the values obtained from the measured values, it can be specifically determined.

Γ _i (p) in the equation (14) is obtained by actual measurement. The sum of χ _{1, j} (1) with respect to j is expressed by modeling equations (12-1), (12-2), (12-3), (12-4) and equations (13-1), ( 13-2), (13-3), (13-4), and (13-5). As a result, it is possible for the first time to specifically determine the equation (8-1) using the equation (14). For example, in the following case, the condition of Expression (14) is satisfied, the virtual parallelization rate Rp (p) of Expression (6-1) is almost 1, and Expressions (4-4) and (4-5) are Equivalent to the equation (8-2), an accurate parallel efficiency E _p (p) can be obtained in the sense that the influence of the estimated value τ (1) becomes almost zero.

以上説明した式（１），（２），（１５）より以下に示す式（９−２）を得る。

Moreover, Formula (10), (11), (12-1), (12-2), (12-3), (12-4), (13-1), (13-2), (13-3) ), (13-4), (13-5), and (13-6), τ (1) can be specifically calculated as Equation (15). Equation (15) represents τ (1) as the sum of the parallel processing time γ _i (p) of each processor and the processing time χ _{1, j} (1) due to the parallel efficiency impediment factor when p = 1. Is.

From the expressions (1), (2), and (15) described above, the following expression (9-2) is obtained.

Expressions (9-1) and (9-2) use the sum of i of the time γ _i (p) of the parallel calculation unit, and compared with Expressions (4-4) and (4-5), χ There is an advantage that the parallel efficiency E _p (p) can be obtained without the data of _{i, j} (p). However, the data of χ _{1, j} (1) is necessary.

As indicated by the equations (4-4), (4-5), and (7), in the present invention, an arbitrary number of parallel performance impediment factors j can be added. Examples of additional parallel performance impediment factors are shown in FIGS. 7 (a) and 7 (b). FIG. 7B shows the processing time when the time is measured in consideration of the rise time χ _TC , and FIG. 7A shows the processing time when the time is not measured in the same processing. In the case of FIG. 7A, the following calculation is performed.
τ ₁ = 10 + 5 + 90 + 20 + 20 = 145
τ ₂ = 10 + 80 + 10 = 100
τ ₃ = 15 + 80 + 10 = 105
τ ₄ = 10 + 90 + 10 = 110
Rb (4) = (145 + 100 + 105 + 110) / (145 × 4) = 0.7931
R _C (4) = (25 + 20 + 25 + 20) /460=0.1957
Rp (4) = 1 (assumed)
E _p (4) = 0.7931 × 1 × (1-0.1957) = 0.6379

In the case of FIG. 7B, the following calculation is performed.
τ ₁ = 10 + 5 + 90 + 20 + 20 = 145
τ ₂ = 5 + 10 + 80 + 10 = 105
τ ₃ = 10 + 15 + 80 + 10 = 115
τ ₄ = 15 + 10 + 90 + 10 = 125
Rb (4) = (145 + 105 + 115 + 125) / (145 × 4) = 0.8448
R _C (4) = (25 + 20 + 25 + 20) /490=0.1837
R _TC (4) = (0 + 5 + 10 + 15) /490=0.0612
Rp (4) = 1 (assumed)
E _p (4) = 0.8448 × 1 × (1-0.1837-0.0612) = 0.6379

The values of these parallel performance evaluation indexes are collectively shown in FIG. Compared with the value obtained from FIG. 7A (Case 1), the value obtained from FIG. 7B (Case 2) decreases R _C by adding R _TC for the rise time, and R b It can be seen that E _p is the same. In this case, E _p is not changed by adding a parallel performance impediment factor, but the breakdown becomes clearer.

By expressing the load balance contribution ratio Rb (p) as shown in the equation (5), the load balance and the parallel efficiency E _p (p) can be related. The reason for defining the load balance contribution ratio Rb (p) as shown in equation (5) is that it can be considered that the load balance is established in a state where the contribution of the parallel performance impediment factor is different in each processor as shown in FIG. It is. In FIG. 9, for example, the number of parallel processing portions of the processor 1 is very small compared to the others, and the redundant processing is very large. However, since the processing times of all the processors are the same, the load balance is maintained. That is, γ _i (p) and χ _{i, j} (p) are not individually balanced but are balanced in total. Note that χ _{i, jothers} (p) (= τ _i −γ _i −χ _{i, 1} −χ _{i, 2} ) is, for example, processing time by I / O.

In the case of FIG. 9, the load balance contribution ratio Rb (p) is 1. When processing is performed by only one processor in parallel processing as shown in FIG. 10, Rb (p) is the lower limit 1 / p. In addition, as shown in FIG. 11, the processing times of the processor 1 and the processor 2 are the same, but the processing times of the processors 3 and 4 are not the same, and the load balance is not achieved. In this case, Rb (p) is as follows.

Furthermore, parallel processing impediment factors that did not become apparent in the case of low parallelism may become apparent in high parallelism. Parallelization rate (= (processing time of parallel processing unit with p = 1)) / ((processing time of parallel processing unit with p = 1) + (p = 1 parallel processing is not possible) In part processing time))), this phenomenon could not be fully captured. For example, in the example of FIG. 12, the parallelization rate at p = 1 is 0.99 (= 198 / (198 + 2)), and the remaining 0.01 is the ratio of processing time that cannot be processed in parallel. However, this value is 2 hours even in high parallelism as in the case of p = 100 in the figure, and does not reflect the fact that the portion that cannot be processed in parallel accounts for 50% (≈2 / (1.98 + 2)). In the present invention, as shown in the equation (7), the parallel performance impediment factor R _j (p) is standardized by the sum of i of χ _{i, j} (p) with respect to _i of τ _i (p). It is expressed as a digitized value. As a result of this standardization, even when τ (p) becomes small in high parallelism, the upper limit of R _j (p) is 1, and the influence of each parallel performance impediment factor can be expressed as a percentage during parallel processing. it can.

As described above, the parallel efficiency E _p (p) is calculated and the parallel performance evaluation indexes Rb (p), Rp (p), R _j (p) (R _RED (4), R _C (4), R _Others (4)) and auxiliary indices A _p (p), E _p (p) · p can also be calculated. An example of the calculation result is shown in FIG. The parallel performance can be quantitatively expressed by the eight items shown in FIG.

As shown in FIG. 13, since E _p (p) · p = 1.777, it is understood that the parallel computer system has a 4-processor configuration, but is processing with the performance of the 1.777 processor. The parallel efficiency decreases to 94% (Rb (4) = 0.9392) as a load balance contribution ratio. The effects of parallel performance impediments are 22% for redundant processing (R _RED (4) = 0.2230), 33% for communication (R _C (4) = 0.3309), and 3% for other (R _Others (4) = 0.0288) It is. Therefore, 55% parallel performance is reduced by communication and redundant processing. In FIG. 13, since R _p (4) = 0.8821, the maximum parallel performance when an infinite number of processors are added is 8.482 (= A _p (4) = 1 / (1−0.8821)) times that of one processor. Can be estimated. Therefore, it can be seen that this processing should be performed by 8 processors or less.

For example, when the set target value (E _p ) _T of parallel efficiency is set to 0.8, assuming the processing group as shown in FIG. 13, the optimum number of processors is calculated by the following equation.
(P) _OPT = E _p (4) / (E _p ) _T · p
= 0.4443 / 0.8 × 4 = 2.215
Therefore, the estimated value of the optimal processor is (p) _OPT = 2.

  The processing group refers to a plurality of processes in which only the input data is changed using the same function in the same application program, and is a process frequently performed in a parametric study of scientific and technical calculation.

稼働時間と処理時間の総和（以下の式）の例を図１４に示す。

図１４では、稼働時間Ｔiに対して処理時間の総和は少なくなっている。この減少の度合いはプロセッサによって異なる。 Conventionally, evaluation of a parallel computer system has been performed by a working rate (Net Working Rate) NWR _system represented by the following equation (16). However, since processing with low parallel efficiency may be included, just because the operation rate is good, the system operation efficiency is not always high.

An example of the sum of operating time and processing time (the following formula) is shown in FIG.

In FIG. 14, the total processing time is less than the operating time Ti. The degree of this reduction varies depending on the processor.

According to the present invention, it is possible to create an index called system operation efficiency E _system based on the equation (16) and evaluate the operation efficiency of the system. It is possible to give specific guidelines for improving operational efficiency, such as how much the parallel efficiency of which processing needs to be improved in order to improve this index.

なお、従来の稼働率ＮＷＲ_system＝（１０＋９）／４０＝０．４８３８となる。並列効率を考慮することにより、並列処理により各処理において無駄にしている時間を考慮したシステムの運用効率を評価することができる。 For example, if P _system = 4, Ti = 10, k _max = 2 and the following condition is satisfied, E _system = (5 + 9) / (10 + 10 + 10 + 10) = 0.35.

The conventional operation rate NWR _system = (10 + 9) /40=0.4838. By considering the parallel efficiency, it is possible to evaluate the operational efficiency of the system in consideration of the time wasted in each process by the parallel processing.

Uptime described above, the sum of tau _i (p) in the process 1 is a parallel processing, the product of the parallel efficiency and tau _i (p) in the process 1, tau in non-parallel processing is processing 2 (processor 4 only) _i FIG. 15 shows the sum of (p) and the product of τ _i (p) and parallel efficiency in process 2. In FIG. 15, in the case of parallel processing, τ _i (p) is shorter than the operating time Ti, and further considering the parallel efficiency, it is further shortened because unnecessary processing time is eliminated. Meanwhile, since the parallel efficiency becomes 1 in the case of non-parallel processing, even to the same value for the product of the parallel efficiency in the processing 2 τ _i (p) is also τ _i (p).

Conventionally, system availability has been used as the basis data for adding processors in parallel computer systems. However, since it is not based on the resources of a system that has been used effectively, there is a possibility of adding or replacing resources for processing with low parallel efficiency. According to the present invention, it is possible to give a quantitative guideline for the addition of processors in a parallel computer system. If the total number of processors in the system is P _System , Ti is the operating time of each processor, P _Add is the number of processors after augmentation, k _max is the total number of processes, and α is the expected parallel efficiency, for example, The acceleration rate A _system when the operating time (Equation 28) is increased is as shown in Expression (18).

Ａ_system＝（３９＋１×１０）／４０＝１．２３
このように約２３％のシステム増強となる。この値は従来の処理の並列効率を考慮しているという点で、増設に対して従来の稼働率より説得力がある値となる。システム増強に予測並列効率α（＜１）をかけて加速率を算出すれば、より現実的な値となる。また、増強したプロセッサのＣＰＵ能力を１０倍とするならば、α＝１０としてＡ_systemを求めることもできる。上記の例に当てはめると、Ａ_system＝（３９＋１０×１０）／４０＝３．４８となる。これにより異なるＣＰＵ性能のプロセッサの増設に対しても稼働率を基にした以上に根拠がある予測データを作成することが可能となる。 For example, assuming that α = 1 under the following conditions, the acceleration rate A _system is calculated as follows.

A _system = (39 + 1 × 10) /40=1.23
Thus, the system is increased by about 23%. This value is more persuasive than the conventional operation rate for expansion in that the parallel efficiency of the conventional processing is taken into consideration. If the acceleration rate is calculated by multiplying the system enhancement by the predicted parallel efficiency α (<1), it becomes a more realistic value. If the CPU capacity of the increased processor is 10 times, A _system can be obtained with α = 10. Applying the above example, A _system = (39 + 10 × 10) /40=3.48. As a result, it is possible to create prediction data that is based on the operation rate based on the addition of processors having different CPU performances.

Further, according to the present invention, it is possible to give a quantitative guideline for replacement of parallel computer systems. Indicators calculated for each process (parallel efficiency, load balance contribution rate, virtual parallelization rate, parallel performance impediment factor contribution rate, τ _i (p), γ _i (p), χ _{i, j} (p), The processor operating time Ti) makes it possible to estimate the parallel efficiency as shown in the following example for each process, and to estimate the performance of the system after system replacement.

For example, when introducing a system in which the CPU performance of the system whose elapsed time is measured as shown in FIG. 16 is increased by five times, γ _i (p), χ _{i, RED} (p), χ _{i, Other} ( p) becomes 1/5. On the other hand, χ _{i, C} (p) depends on the network performance. If the performance is the same this time, the parallel efficiency of the new system can be estimated as follows.

When χ _{i, C} (1) = 0 and χ _{i, Others} (1) = 0, the performance evaluation index when the CPU performance is five times can be calculated as follows. Further, χ _{1, RED} (1) is expressed as follows by the equation (12-1) described above. Also, the load balance contribution rate is calculated according to equation (5), the virtual parallel rate is calculated according to equation (6-1), the parallel performance impediment factor contribution rate (redundancy processing, communication, etc.) is calculated according to equation (7), and the parallel efficiency is calculated according to equation (7). According to (4-4) and (9-1), it is calculated as follows.

FIG. 17 shows a summary of the calculation results shown above and performance indexes based on actual measurements. As shown in the table of FIG. 17, the system operation efficiency E _system of a new system can be estimated by predicting the parallel performance when the system is replaced. Therefore, using the log data of the system so far, all performance indices are calculated for the processing so far as in FIG.

A trial calculation for obtaining the system operation efficiency E _system when the CPU performance is increased by 5 times is as follows. By comparing this E _system obtained based on the estimated value with the E _system obtained from the actual measured values so far, it is possible to obtain data that is more grounded than the operating rate for system replacement.

As shown in FIG. 18, E _system can be calculated according to the sum of E _p (4) and τ _i (p) for each process and the number of processors when the CPU performance becomes five times. The following conditions were used as a premise.

[Description of Embodiment]
FIG. 19 shows a system outline diagram according to one embodiment of the present invention. The parallel performance analysis apparatus 100 is a single processor computer that analyzes the parallel performance of the parallel computer system 200, and is connected to an output device 110 such as a printing device or a display device. However, the parallel performance analysis apparatus 100 may be a parallel computer. The parallel performance analyzer 100 includes a data acquisition unit 10, a load balance contribution rate calculation unit 11, a virtual parallelization rate calculation unit 12, a parallel performance impediment factor contribution rate calculation unit 13, a parallel efficiency calculation unit 14, and an auxiliary Index calculation unit 15, processor number optimization processing unit 21, processor expansion estimation processing unit 22, system replacement data processing unit 23, operational efficiency data processing unit 24, tuning processing unit 25, and algorithm selection processing unit 26 And a parallel performance evaluation processing unit 27. The parallel performance analysis apparatus 100 is connected to the log data storage unit 30. The parallel computer system 200 includes a measurement unit 201. For example, the parallel performance analysis apparatus 100 is connected to the parallel computer system 200 via a network.

The measuring unit 201 of the parallel computer system 200 measures each processing time γ _i (p), χ _{i, j} (p), τ _i (p) while executing parallel processing according to a program. For example, the time from the start to the end of each process is measured by a timer, the start time and the end time of each process are recorded, and the process time is calculated after the process ends. The time measurement may be performed by software including an operating system (OS) or hardware. The measured processing time data is temporarily stored in the memory of the parallel computer system 200, and in some cases, stored in another storage device.

  Further, instead of measuring the processing time, there may be a case where the events of the program being executed are confirmed at regular time intervals and the events are counted. Such measurement is called measurement by sampling. In such measurement by sampling, equations (4-4), (9-1), (9-2) and Rb (p), Rp (p), Rj (p) are in the form of time ratios. Therefore, it can be adopted. Although there are differences depending on the measurement accuracy, the results are the same between the time measurement method and the sampling method.

FIG. 20 shows a conceptual diagram of measurement by sampling. FIG. 20 shows how time elapses from left to right. In FIG. 20, a downward arrow indicates a sampling timing, and sampling is performed at a constant time interval as indicated by an interval of the downward arrow. In FIG. 20, after redundant processing is first performed for χ _{i, RED} (p), parallel computation is performed for γ _i (p). As a whole, the processing is performed only for τ _i (p). The number of samplings is 7 in the event of redundant processing that lasts for χ _{i, RED} (p) and 9 in the event of parallel computation that lasts for γ _i (p). During the entire processing time τ _i (p), the number of samplings is 22 times. Of the parallel performance impediments, events other than the intentionally measured χ _{i, RED} (p) are collectively expressed as χ _{i, others} (p), and the intentionally measured τ _i (p), χ _{i, RED} ( Calculate from equation (13-6) using p) and γ _i (p). In the example of FIG. 20, it can be seen that the number of samplings during χ _{i, others} (p) is 6 (= 22-9-7).

The outline of how the measurement by sampling is actually performed will be described below.
(1) Part of τ _i (p) (a) The flag for the event τ _i (p) is turned on at the beginning of the process, and turned off at the end of the process. It is assumed that on / off of the flag for the event τ _i (p) is identified at a constant time interval at the time of execution, and the number of sampling is obtained by counting the number of times identified as on.
The description and processing of any of the following methods are combined and measured as necessary.
The programmer detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
When a parallel language extension or compiler directive is used, the tool interprets the parallel language extension or compiler directive, and makes a description for turning the flag on / off.
If a parallel language extension or compiler directive is used, the compiler interprets the parallel language extension or compiler directive, and makes a description for turning the flag on / off.
The compiler detects the beginning and end of the processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
The OS detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
The runtime library detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
The hardware detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
A description for processing for identifying that the flag is on and counting the number of times is given at the compiler level.
A description for processing for identifying that the flag is on and counting the number of times is given at the OS level.
A description for processing for identifying that the flag is on and counting the number of times is given at the runtime library level.
A description for processing for identifying that the flag is on and counting the number of times is given at the hardware level.
A description for the process of identifying that the flag is on and counting the number of times is given at the tool level.
A description for the process of identifying that the flag is on and counting the number of times is given at the program level.
A process of identifying that the flag is on and counting the number of times is performed at the hardware level.

(B) An event is identified by a program name or an execution module name that substitutes for it, and the program name or execution module name is identified at a certain time interval at the time of execution, and the number of times of identification of the identified name is counted and the number of sampling times Shall be obtained.
The name generation method of any of the following methods, the identification process, and the count process are combined and measured as necessary.
-The compiler generates the program name or the execution module name.
The OS generates the program name or execution module name.
The runtime library generates the program name or execution module name.
The hardware generates the program name or execution module name.
-The above program name or execution module name is generated based on the description of parallel language extensions, compiler directives, etc.
-The above program name or execution module name is generated by the programmer's description.
A description for identification processing and count processing such as the generated program name or execution module name is performed at the compiler level.
A description for identification processing and count processing such as the generated program name or execution module name is performed at the OS level.
A description for identification processing and count processing such as the generated program name or execution module name is performed at the runtime library level.
A description for identification processing and count processing such as a generated program name or execution module name is performed at the hardware level.
A description for identification processing and count processing such as the generated program name or execution module name is performed at the tool level.
A description for identification processing and count processing such as the generated program name or execution module name is performed at the program level.
The identification process of the generated program name or execution module name and the count process are performed at the hardware level.

(2) Parts of χ _{i, j} (p) and γ _i (p) (a) Each time an event χ _{i, j} (p), γ _i (p) appears, the flag for that is turned on at the beginning of the processing And set the flag for that to off at the end of the process.
It is assumed that the flag on / off for each event is identified at a certain time interval at the time of execution, and the number of times of being identified as on is counted to obtain the number of times of sampling. Since there is a case where it cannot be detected by one method, measurement is performed by combining any of the following methods and processes as necessary.
The programmer detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
When a parallel language extension or compiler directive is used, the tool interprets the parallel language extension or compiler directive, and makes a description for turning the flag on / off.
If a parallel language extension or compiler directive is used, the compiler interprets the parallel language extension or compiler directive, and makes a description for turning the flag on / off.
The compiler detects the beginning and end of the processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
The OS detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
The runtime library detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
The hardware detects the beginning and end of processing in the program, that is, the position where the flag should be turned on / off, and makes a description for turning the flag on / off.
A description for processing for identifying that the flag is on and counting the number of times is given at the compiler level.
A description for processing for identifying that the flag is on and counting the number of times is given at the OS level.
A description for processing for identifying that the flag is on and counting the number of times is given at the runtime library level.
A description for processing for identifying that the flag is on and counting the number of times is given at the hardware level.
A description for the process of identifying that the flag is on and counting the number of times is given at the tool level.
A description for the process of identifying that the flag is on and counting the number of times is given at the application program level.
A process of identifying that the flag is on and counting the number of times is performed at the hardware level.

(B) A known module name is classified in advance into a parallel processing unit or a processing unit related to a parallel performance impediment factor, the module name is identified at the time of execution, and the number of sampling is obtained by counting for each module name. The classification method shown below, the identification process, and the count process are combined and measured as necessary.
・ Classify module names at the compiler level.
-Module names are classified at the OS level.
・ Classify module names at runtime library level.
・ Classify module names at the hardware level.
-Classify module names at the parallel language extension or compiler directive level.
・ Classify module names at the user level.
-Description for the module name identification processing and count processing is performed at the compiler level.
A description for the module name identification processing and count processing is performed at the OS level.
-Description for the module name identification processing and count processing is performed at the runtime library level.
A description for the module name identification process and count process is performed at the hardware level.
-The description for the module name identification process and the count process is performed at the tool level.
-The description for the module name identification process and the count process is given at the program level.
-The module name identification process and the count process are performed at the hardware level.

As an example, the following is a sampling method for χ _{i, j} (p) using a program that describes the process of adding each element of F (Imax) in all processors in Fortran and a parallel library MPI (Message Passing Interface). Table 1 shows. For example, an on flag is represented by “* sampon” that instructs the compiler, and an off flag is represented by “* sampoff”. Further, RED is assumed to be redundant processing, C is assumed to be communication, and the numbers after RED and C represent the appearance order. Since the summation process is a redundant process in which each processor performs the same calculation, "* sampon (RED), 2" and "* sampoff (RED), 2" are placed at the start and end points, and the flag is set to on / Turn off. Since the calculation of the variable nLOCAL is also a redundant process, “* sampon (RED), 1” and “* sampoff (RED), 1” are arranged at the start point and end point, and the flag is turned on / off. Furthermore, MPI_ALLTOALL is a communication library. Here, "* sampon (C), 1", "* sampoff (C), 1", "* sampon (C), 2" and "* sampoff (C), 2" Place and turn flag on / off. In the case of MPI_ALLTOALL, the tool, compiler, or OS can identify the event and set a flag.

(Table 1)
subroutine GSUM (Imax, F, FW, NP)
real * 8 F (Imax), FW (Imax)
include 'mpif.h'

sampon (RED), 1
nLOCAL = (Imax + NP-1) / NP
sampoff (RED), 1

sampon (C), 1
call MPI_ALLTOALL (F, nLOCAL, MPI_DOUBLE_PRECISION,
& FW, nLOCAL, MPI_DOUBLE_PRECISION,
& MPI_COMM_WORLD, IERR)
sampoff (C), 1

sampon (RED), 2
do j = 2, NP
k = (j-1) * nLOCAL
do i = 1, nLOCAL
FW (i) = FW (i) + FW (i + k)
end do
end do

do j = 2, NP
k = (j-1) * nLOCAL
do i = 1, nLOCAL
FW (i + k) = FW (i)
end do
end do
sampoff (RED), 2

sampon (C), 2
call MPI_ALLTOALL (FW, nLOCAL, MPI_DOUBLE_PRECISION,
& F, nLOCAL, MPI_DOUBLE_PRECISION,
& MPI_COMM_WORLD, IERR)
sampoff (C), 2
return
end

  An example of sampling when the program of Table 1 is executed is shown in FIG. In FIG. 21, the event [(RED), 1], [(RED), 2], [(C), 1], [(C), 2] is counted. However, when calculating parallel efficiency etc., it treats as the whole redundant process [(RED), 1+ (RED), 2] and the whole communication process [(C), 1 + (C), 2].

Returning to the description of FIG. 19, the data acquisition unit 10 of the parallel performance analysis apparatus 100 performs processing times γ _i (p), χ _i measured by the measurement unit 201 as processing times or sampling numbers as described above. _{, j} (p), τ _i (p) are acquired from the parallel computer system 200 and stored in the log data storage unit 30 connected to the parallel performance analyzer 100. The log data storage unit 30 also stores data such as parallel performance evaluation indexes including parallel efficiency calculated in addition to each processing time. As described above, the load balance contribution ratio calculation unit 11 calculates the load balance contribution ratio Rb (p) according to the equation (5) and stores it in the storage device. Note that τ (p) is calculated according to equation (2). The virtual parallelization rate calculation unit 12 calculates the virtual parallelization rate Rp (p) according to Equation (6-1) and stores it in the storage device. Note that τ (1) in the denominator of equation (6-1) may be approximated as shown in equation (8-1). In addition, Expression (10) and Expression (11) to Expression (15) may be used. For the second term (χ _{1, j} (1), j = 1) in equation (15), equations (12-1), (12-2), (12-3) or (12-4) ) In some cases. Further, χ _{1, j} (1), j> 1 may be calculated by any one of formulas (13-3) to (13-5). j = 1 of χ _{1, j} (p) is a redundant process. However, the processing time for other parallel performance impediment factors may be used.

The parallel performance impediment factor contribution rate calculation unit 13 calculates the parallel performance impediment factor contribution rate Rj (p) for each parallel performance impediment factor according to Equation (7) and stores it in the storage device. The parallel efficiency calculation unit 14 calculates the expression (8-2), the expression (9-1), or the expression when the conditions of the expressions (4-4), (4-5), and (8-1) are satisfied. The parallel efficiency E _p (p) is calculated according to any of (9-2) and stored in the storage device. When the formula (9-2) is used, the first term of the molecule is expressed by the formulas (12-1), (12-2), (12-3), (12-4), (13-3), (13 -4) or (13-5). Expressions (12-1) to (12-4) are redundant processes of χ _{1, j} (p), j = 1. The auxiliary index calculation unit 15 calculates the acceleration rate A _p according to, for example, the equation (6-2), and E _p (p) · p from the parallel efficiency E _p (p) and the number of processors p, and stores them in the storage device. .

  The processor number optimization processing unit 21 performs processing for instructing an end user of the parallel computer system 200 about the optimum number of processors to be input for processing. The processor expansion estimation processing unit 22 performs processing for presenting a numerical value serving as a guideline when adding a processor to the operation manager of the parallel computer system 200. The system replacement data processing unit 23 performs processing for presenting numerical values that serve as guidelines for system replacement to the operation manager of the parallel computer system 200. The operational efficiency data processing unit 24 performs processing for presenting data related to system operational efficiency to the operation manager of the parallel computer system 200. The tuning processing unit 25 performs processing for enabling a programmer to perform efficient tuning of a program or the like by appropriate target setting or the like for a program for performing parallel processing. The algorithm selection processing unit 26 performs processing for allowing a programmer to select an algorithm that can further improve parallel efficiency as a program for performing parallel processing when different algorithms exist for the same processing. carry out. The parallel performance evaluation processing unit 27 performs processing for allowing a parallel computer system developer or researcher to easily evaluate parallel performance. Detailed processing contents of these processing units will be described below.

  Next, a processing flow of the system shown in FIG. 19 will be described with reference to FIG. First, in order to turn on / off the flag for counting the sampling number corresponding to each processing time by the description for direct measurement of the processing time, compiler, OS, tool, programmer, runtime library, hardware, etc. Preprocessing including classification of module names and the like for counting the number of samplings corresponding to each processing time is performed by a description of the above, compiler, OS, tool, programmer, runtime library, hardware, etc. (step S1). This processing may be performed by the parallel computer system 200 or may be performed by another computer system. Furthermore, it may be performed by a person such as a programmer. Note that step S1 is not a process executed by the parallel performance analysis apparatus 100 but may be a process executed by the parallel computer system 200, and is therefore represented by a dotted line block.

Next, the measurement unit 201 of the parallel computer system 200 performs a measurement process that measures the processing time and counts the number of samplings based on the preprocessing (step S3). Each processing time γ _i (p), χ _{i, j} (p), τ _i (p), which is a measurement result, or a sampling count value corresponding to each processing time is stored in the storage device of the parallel computer system 200. The data acquisition unit 10 of the parallel performance analyzer 100 reads the data. When the data acquisition unit 10 acquires each processing time γ _i (p), χ _{i, j} (p), τ _i (p) or the count value of sampling corresponding to each processing time, the data acquisition unit 10 logs Store in the data storage unit 30.

The load balance contribution rate calculation unit 11, virtual parallelization rate calculation unit 12, parallel performance impediment factor contribution rate calculation unit 13, parallel efficiency calculation unit 14, and auxiliary index calculation unit 15 are stored in the log data storage unit 30. Using each processing time γ _i (p), χ _{i, j} (p), τ _i (p) or the count value of sampling corresponding to each processing time, the load balance contribution ratio Rb (p), virtual parallelization The rate Rp (p), each parallel performance impediment factor contribution rate Rj (p), the parallel efficiency E _p (p), the acceleration rate A _{p and} other auxiliary indicators are calculated and stored in the log data storage unit 30 (step S5). .

As for the parallel efficiency E _p (p), as described above, when the conditions of the equations (4-4), (4-5), and (8-1) are satisfied, the equation (8-2) , And calculated according to either equation (9-1) or equation (9-2). Therefore, the parallel efficiency calculation unit 14 includes the load balance contribution rate Rb (p) calculated by the load balance contribution rate calculation unit 11, the virtual parallelization rate Rp (p) calculated by the virtual parallelization rate calculation unit 12, About other necessary data, using each parallel performance impediment factor contribution rate Rj (p) calculated by the performance impediment factor contribution rate calculation unit 13 and the acceleration A _p (p) calculated by the auxiliary index calculation unit 15 The parallel efficiency E _p (p) is calculated using the processing time and the like stored in the log data storage unit 30.

For example, a calculation example when the measurement result of the processing time as shown in FIG. 23 is stored in the log data storage unit 30 by the data acquisition unit 10 is shown below. More specifically, τ ₁ (p) = 34, τ ₂ (p) = 35, τ ₃ (p) = 33, τ ₄ (p) = 37, γ ₁ (p) = 15, γ ₂ (p ) = 14, γ ₃ (p) = 13, γ ₄ (p) = 16, χ _{1, RED} (p) = 8, χ _{2, RED} (p) = 9, χ _{3, RED} (p) = 7, χ _{4, RED} (p) = 7, χ _{1, C} (p) = 10, χ _{2, C} (p) = 11, χ _{3, C} (p) = 12, χ _{4, C} (p) = 13 It is assumed that the measurement result is obtained. Therefore, χ _{1, others} (p) = 1 (= 34-15-8-10), χ _{2, others} (p) = 1 (= 35-14-9-11), χ _{3, others} (p) = 1 (= 33-13-7-12), χ _{4, others} (p) = 1 (= 37-16-7-13). Although it is necessary for the following calculation, it is assumed that both χ _{1, C} (1) and χ _{1, others} (1) which have not been measured are 0.

（２）仮想並列化率（式（６−１），（１２−１），（１５））

（３）加速率（式（６−２））

（４）並列性能阻害要因寄与率（式（７））
（４−１）冗長処理の並列性能阻害要因寄与率

（４−２）通信処理の並列性能阻害要因寄与率

（４−３）その他の並列性能阻害要因寄与率

(1) Load balance contribution ratio (Formula (5))

(2) Virtual parallelization rate (formulas (6-1), (12-1), (15))

(3) Acceleration rate (Formula (6-2))

(4) Parallel performance impediment factor contribution ratio (Formula (7))
(4-1) Redundant processing parallel performance impediment factor contribution rate

(4-2) Parallel processing impediment contribution rate of communication processing

(4-3) Contribution rate of other parallel performance impediment factors

（５−２）並列効率（式（９−１））

（５−３）並列効率（式（９−２））

(5-1) Parallel efficiency (Formula (4-4))

(5-2) Parallel efficiency (Formula (9-1))

(5-3) Parallel efficiency (Formula (9-2))

The above results are summarized as shown in FIG. The auxiliary index E _p (p) · p is also calculated. E _p (4) · p = 1.777, it can be seen that processing is performed in parallel with four processors with the performance of 1.777 processors. The parallel efficiency is reduced to about 94% (= Rb (4) = 0.9392) in load balance. The effects of parallel performance impediments are about 22% for redundant processing (= R _RED (4) = 0.2230), about 33% for communication (= R _C (4) = 0.3309), and 3% for _others (= R _others ( 4) = 0.0288). Therefore, the parallel efficiency is lowered by about 55% mainly by communication and redundant processing execution. In FIG. 13, since Rp (4) = 0.8221, the maximum parallel performance when an infinite number of processors are inserted is 8.482 times (= A _p (4) = 1 / (1-0.8821)) times that of one processor. It can be estimated that there is. Therefore, it can be seen that this processing should be performed by eight processors or less. If this processing is performed under the condition of E _p (x) ≧ 0.8, E _p (x) · p = 0.4443 × 4 = 1.777 = E _p (x) · x = 0.8 * x , X = 2.22. Therefore, it can be expected that the optimum number of processors for a given condition of p ≧ 2.22 = 2.

Further, for example, a calculation example in the case where the count number by sampling as shown in FIG. 24 is stored in the log data storage unit 30 by the data acquisition unit 10 is shown below. More specifically, τ ₁ (p) = 3488, τ ₂ (p) = 3561, τ ₃ (p) = 3372, τ ₄ (p) = 3756, γ ₁ (p) = 1521, γ ₂ (p ) = 1411, γ ₃ (p) = 1322, γ ₄ (p) = 1601, χ _{1, RED} (p) = 823, χ _{2, RED} (p) = 945, χ _{3, RED} (p) = 711, χ _{4, RED} (p) = 703, χ _{1, C} (p) = 1105, χ _{2, C} (p) = 1111, χ _{3, C} (p) = 1230, χ _{4, C} (p) = 1341 It is assumed that the measurement result is obtained. Therefore, χ _{1, others} (p) = 88 (= 3488-1521-823-1056), χ _{2, others} (p) = 94 (= 3561-1141-11545-1111), χ _{3, others} (p) = 109 (= 3372-1322-711-1230) and χ _{4, others} (p) = 111 (= 3756-1601-703-1341). Although it is necessary for the following calculation, it is assumed that both χ _{1, C} (1) and χ _{1, others} (1) which have not been measured are 0.

（２）仮想並列化率（式（６−１），（１２−１），（１５））

（３）加速率（式（６−２））

（４）並列性能阻害要因寄与率（式（７））
（４−１）冗長処理の並列性能阻害要因寄与率

（４−２）通信処理の並列性能阻害要因寄与率

（４−３）その他の並列性能阻害要因寄与率

(1) Load balance contribution ratio (Formula (5))

(2) Virtual parallelization rate (formulas (6-1), (12-1), (15))

(3) Acceleration rate (Formula (6-2))

(4) Parallel performance impediment factor contribution ratio (Formula (7))
(4-1) Redundant processing parallel performance impediment factor contribution rate

(4-2) Parallel processing impediment contribution rate of communication processing

(4-3) Contribution rate of other parallel performance impediment factors

（５−２）並列効率（式（９−１））

（５−３）並列効率（式（９−２））

以上の結果をまとめると処理時間の計測の場合と同じ図１３のようになる。 (5-1) Parallel efficiency (Formula (4-4))

(5-2) Parallel efficiency (Formula (9-1))

(5-3) Parallel efficiency (Formula (9-2))

The above results are summarized as shown in FIG. 13 which is the same as the case of measuring the processing time.

  Returning to the description of FIG. 22, the log data storage unit 30 stores a measurement result such as a processing time, a parallel performance evaluation index and an auxiliary index as shown in FIG. 13 as a set for each process. Then, the parallel performance analysis apparatus 100 outputs the processing result as shown in FIG. 13 to the output device 110 such as a display device or a printing device in response to a user request or automatically (step S7).

  The user can analyze the parallel performance by using only the data as shown in FIG. 13, estimate the optimum number of processors, estimate the effect when adding a processor or replacing a system, tune a program, select an algorithm, etc. good. However, the processor number optimization processing unit 21, the processor expansion estimation processing unit 22, the system replacement data processing unit 23, the operational efficiency data processing unit 24, the tuning processing unit 25, the algorithm selection processing unit 26, and the parallel performance evaluation processing unit 27 Various consulting support processes as described below are performed in accordance with user instructions (step S9). Thereby, more specific data can be obtained.

A. Processor Number Optimization Processing Processing performed by the processor number optimization processing unit 21 will be described with reference to FIGS. 25 and 26. The processor number optimization processing unit 21 receives a setting input of a target parallel efficiency (E _p ) _T value by the user (step S11). Then, the optimal number of processors is calculated according to the following formula and stored in the storage device (step S13).
(p) _OPT = E _p (p) / (E _p ) _T · p
Then, the calculated optimum number of processors is output to the output device 110 (step S15). As a result, the user can minimize the number of processors used when the next process belonging to the same process group is performed. For example, as described above, the calculation result as shown in FIG. 13 is obtained, and when the target parallel efficiency (E _p ) _T = 0.8, p = 2.22. Therefore, the optimum number of processors is 2.

  In addition, when processing of the same processing group is continuously performed, it is possible to perform processing more efficiently while adjusting the optimum number of processors. That is, processing as shown in FIG. 26 is performed. First, provisional setting of the number of processors p is performed (step S21). The temporarily set processor number p is used for the first process in the same process group. Further, the setting of the target parallel efficiency is received from the user (step S23). Then, according to the setting of the number of processors p, parallel processing is performed by the parallel computer system 200, the processing time is measured by the measuring unit 201, and the measurement result is stored in the storage device (step S25). The data acquisition unit 10 stores data such as processing time measured by the measurement unit 201 in the log data storage unit 30. Then, a parallel performance evaluation index including parallel efficiency is calculated by the parallel efficiency calculation unit 14 and the like, and stored in the log data storage unit 30 (step S27).

Then, the processor number optimization processing unit 21 calculates the optimum processor number (p) _OPT in accordance with the above-described formula and stores it in the storage device (step S29). The calculated optimum processor number (p) _OPT is set to p as the number of processors to be used in the next process of the same process group (step S31). And it is judged whether all the processes of the same process group were implemented (step S33). If not all the processes have been performed, the next process in the same process group is selected (step S35), the process returns to step S25, and the parallel process is performed with the number of processors set in step S31.

  By performing such processing, the optimal number of processors for the previous processing belonging to the same processing group can be set as the number of processors for the next processing, so that processing of the processing group can be performed more efficiently. become able to.

B. Processor Expansion Estimation Processing The processor expansion estimation processing unit 22 performs processing for giving an acceleration rate A _system at the time of system enhancement as a quantitative guideline for processor expansion of the parallel computer system 200. FIG. 27 shows a processing flow. First, the processor expansion estimation processing unit 22 accepts setting input of data on the operating time for the increase in system expansion and data on the predicted parallel efficiency (step S41). Then, the acceleration rate A _system at the time of system expansion is calculated according to equation (18) and stored in the storage device (step S43). Note that data such as the operating time of each processor currently in use is calculated using past processing log data stored in the log data storage unit 30. Then, the calculated acceleration rate A _system at the time of system expansion is output to the output device 110 such as a display device (step S45).

Based on the set up operating time and the estimated parallel efficiency, the acceleration rate A _system at the time of system expansion can be used to determine how much time is required to perform meaningful processing. .

C. System replacement data processing Processing for presenting quantitative guidelines for determining the performance of new parallel computer systems when parallel computer systems are replaced. FIG. 28 shows a processing flow for this purpose. The system replace data processing unit 23 receives setting inputs of the target parallel efficiency (E _p ) _T and the number of repetitions icmax (step S51). Also, the setting input of the performance factor A for the current parallel computer system is accepted as the performance of the new parallel computer system (step S53). As for the performance magnification, setting inputs such as the CPU performance magnification A _CPU , the communication performance magnification A _C , and the I / O performance magnification A _{I / O} are accepted. Quantitative guidance is obtained with this magnification value. In most computer system replacements, in order to improve the system performance by improving the CPU performance, for example, A _CPU is first set, and E _p is calculated with another performance magnification of 1. Then, processing may be performed in such a manner that values such as A _C and A _{I / O} are repeatedly calculated so as to approach (E _p ) _T and a guideline for determining the performance of a new parallel computer system is obtained.

More specifically, the system replace data processing unit 23 performs a calculation for shortening each processing time and the like stored in the log data storage unit 30 in accordance with each set performance magnification (step S55). For example, when the CPU performance is set to 5 times (A _CPU = 5), the calculation is performed such that the processing time γ _i (p) of parallel processing is reduced to 1/5. Then, based on each processing time shortened according to each set performance magnification, an estimated value of a parallel performance evaluation index including parallel efficiency (for example, the estimated value of parallel efficiency is (E _p ) _E ) is stored in the storage device. Store (step S57).

The system replacement data processing unit 23 determines whether the estimated value (E _p ) _E of the parallel efficiency matches the target parallel efficiency (E _p ) _T (step S59). It does not have to be a perfect match, and it is determined whether the estimated value (E _p ) _E is within a predetermined range of the target parallel efficiency (E _p ) _T. If it is determined that the estimated parallel efficiency (E _p ) _E is substantially equal to the target parallel efficiency (E _p ) _T , a message indicating the achievement of the target parallel efficiency and each parallel performance calculated in step S57. The estimated value of the evaluation index is output to the output device 110 such as a display device (step S61). On the other hand, if it cannot be said that the estimated parallel efficiency (E _p ) _E is substantially equal to the target parallel efficiency (E _p ) _T, it is determined whether the counter ic is equal to or greater than the number of repetitions icmax (step) S63). If the counter ic exceeds the number of repetitions icmax, the message indicating that the target parallel efficiency has not been achieved and the estimated value of each parallel ability evaluation index calculated in step S57 are output from the display device or the like. It outputs to the apparatus 110 (step S65).

  On the other hand, if ic is less than the number of repetitions icmax, a change in performance magnification such as a CPU performance magnification, a communication performance magnification, and an I / O performance magnification is performed (step S67). About this step, you may make it change automatically and may accept the setting by a user. Then, the counter ic is incremented by 1 (step S69), and the process returns to step S55.

In the above process, the parallel efficiency is estimated by changing the performance factor up to the maximum number of repetitions icmax so as to achieve the target parallel efficiency (E _p ) _T. It is also possible to select a new parallel computer system having a performance satisfying (E _p ) _T for a specific process whose processing time is stored in the log data storage unit 30 for some types of processes. On the other hand, it becomes possible to select a new parallel computer system having a performance satisfying (E _p ) _T.

An application example of the processing flow of FIG. 28 will be described specifically in a case where the processing time is measured as shown in FIG. Here, assuming that the target parallel efficiency (E _p ) _T = 0.6 and introducing a new system with CPU performance five times, that is, A _CPU = 5, γ _i (p), χ _{i, RED} (p) is 1 / A _CPU . It is assumed that χ _{i, others} (p) whose properties are unknown is also 1 / A _CPU . On the other hand, χ _{i, C} (p) depends on network performance. Here, first, the feasibility is examined with A _C = ∞. Note that χ _{1, C} (1) and χ _{1, others} (1) that have not been measured are both set to 0.

［Ａ_CPU＝５，Ａ_C＝∞の場合の(Ｅ_p)_E］

The following calculation is performed from the equation (12-1).

[(E _p ) _E when A _CPU = 5 and A _C = ∞]

The above calculation results are summarized in FIG. When A _C = ∞, the term of χ _{i, C} (p) becomes 0 and E _p = 0.6850, which is larger than the target value 0.6. Thus it can be seen that the target parallel efficiency may be achieved depending on the performance improvement of the A _C. Accordingly, the parallel efficiency is repeatedly calculated while changing A _C in step S67 (step S57), and A _C that satisfies E _p (p) ˜0.6 is searched. Although the calculation in the middle is omitted, the calculation result in the case of E _p (p) to 0.6 is shown in the second row of FIG. In this case, A _C = 19.2. From this, when (E _p ) _T = 0.6 and the CPU performance is set to A _CPU = 5, a guideline is obtained that a parallel computer system having a performance of A _C = 19.2 or more may be searched and replaced.

If the number A _C = 19.2 is too high and no such system exists, consider reducing other parallel performance impediment factors. According to the estimation result in the second row in FIG. 29, it can be seen that the redundancy processing R _RED (4) = 0.2953 should be improved. To reduce redundant processing, program tuning is necessary. Run the tuned program performs the process of FIG. 28 again, it Estimate the A _C again.

Also, as shown in FIG. 29, it is possible to estimate the system operation efficiency E _system of a newly introduced parallel computer system by predicting the parallel performance at the time of system replacement. For example, in a new system that clears the target parallel efficiency (E _p ) _T = 0.6 in a certain process, A _CPU = 5, A _C = 19.2, the processes 1 to 4 shown in FIG. It can be seen that E _system = 0.6534. This and predicted E _system, by comparing the E _system obtained from the previous processing log, we are possible to indicate quantitatively with the data is more evidence to improve the operating rate due to replacement of the system .

D. System Operation Efficiency Improvement Process For example, the system operation efficiency is evaluated based on the index of the system operation efficiency E _system expressed by the equation (17). In order to improve this index, specific guidelines are given for improving operational efficiency, such as how much parallel efficiency of which processing needs to be improved. Specifically, the process of FIG. 30 is performed.

The operational efficiency data processing unit 24 accepts the setting input of the system operational efficiency target value (E _system ) _T and the number of repetitions icmax by the operational manager (step S71). Then, data such as processing time and parallel efficiency stored in the log data storage unit 30 is read, and the system operation efficiency E _system is calculated according to the equation (17) and stored in the storage device (step S73). If the parallel performance evaluation index including the parallel efficiency is not calculated, the load balance contribution rate calculation unit 11, the virtual parallelization rate calculation unit 12, the parallel performance impediment factor contribution rate calculation unit 13, A parallel performance evaluation index including parallel efficiency is calculated by the parallel efficiency calculation unit 14 and the like. Then, it is determined whether the system operation efficiency E _system calculated in step S73 exceeds the target value (E _system ) _T of the system operation efficiency (step S75). If it is determined that E _system > (E _system ) _T , the message indicating the achievement of the target and the system operation efficiency E _system calculated in step S73 are output to the output device 110 such as a display device (step). S77). On the other hand, if E _system ≦ (E _system ) _T , it is determined whether the counter value ic is equal to or greater than the number of repetitions icmax (step S79). If the counter value ic is equal to or greater than the number of repetitions icmax, a message indicating that the target has not been achieved and the system operation efficiency E calculated in the immediately preceding step S73 are used to notify that the system operation efficiency improvement process is not functioning well. _{The system} is output to the output device 110 such as a display device (step S81).

  On the other hand, if the counter value ic is less than the number of repetitions icmax, the operational efficiency data processing unit 24 performs an improvement procedure for the end user for the end user and an improvement procedure for the system administrator for the system administrator. Recommends that the parallel computer system developer or researcher implement the improvement measures for the parallel computer system developer or researcher. Implement (step S83). Examples of measures to be implemented include optimizing the number of processors, adding processors, replacing systems, tuning programs, and the like. After the system operation efficiency improvement measures are implemented, parallel processing is again performed by the parallel computer system 200, and simultaneously measurement processing such as processing time by the measurement unit 201 is performed (step S85). Then, the counter value ic is incremented by 1 (step S87), and the process returns to step S73. Since step S83 may be a process performed by an end user or the like, it is a dotted line block, and step S85 is not a process of the parallel performance analysis apparatus 100, and is therefore indicated by a chain line.

By carrying out such processing, it is possible to improve the system operation efficiency reflecting the parallel efficiency that is not taken into consideration in the conventional operation rate NWR _system , that is, taking the effective processing time into consideration. Become.

E. Tuning process Conventionally, performance improvement work by tuning parallel application programs has been difficult to estimate because the goal has not been clear. In some cases, the target processing time is not reachable by tuning, and there are many cases where a great amount of work time is spent continuing the tuning work. Therefore, processing as shown in FIG. 31 is performed.

First, the tuning processing unit 25 receives setting input of the target processing time (τ) _T , the number of repetitions icmax and the limited parallel efficiency (E _p ) _max by the programmer (step S91). Next, using the parallel efficiency and processing time data stored in the log data storage unit 30 (for example, the parallel efficiency and processing time included in the processing log of the program to be tuned), the target processing time (τ) _T The target parallel efficiency (E _p ) _T corresponding to is calculated and stored in the storage device (step S93). The target parallel efficiency (E _p ) _T is calculated by the following formula. This equation represents linear extrapolation.
(E _p ) _T = max (τ _i ) × E _p (p) / (τ) _T

Then, it is determined whether the target parallel efficiency (E _p ) _T is equal to or less than the limited parallel efficiency (E _p ) _max (step S95). If the target processing time (τ) _T is set without any limitation, an unrealizable target parallel efficiency (E _p ) _T may be set, so the target processing time (τ) _T is appropriate in this step. It is a judgment whether it is. If the target parallel efficiency (E _{p) T} exceeds the limit parallel efficiency (E _{p) max} is, the target processing time (tau) _T or limit parallel efficiency (E _p) resets the _max is needed Return to step S91.

On the other hand, when the target parallel efficiency (E _p ) _T is equal to or less than the limited parallel efficiency (E _p ) _max , it is determined whether the processing time τ (p) of the current measurement is equal to or less than the target processing time (τ) _T. (Step S97). Note that the first process in step S97 is always determined as No. If the processing time of the current measurement is less than or equal to the target processing time (τ) _T , a message indicating that the target has been achieved, the parallel efficiency achieved, data such as the processing time τ (p), etc. are displayed on the display device. To the output device 110 (step S99). On the other hand, if the processing time of the current measurement exceeds the target processing time (τ) _T , it is determined whether the counter value ic is equal to or greater than the number of repetitions icmax (step S101). If the counter value ic is equal to or greater than the number of repetitions icmax, a message indicating that the target cannot be achieved, the parallel efficiency achieved, the data such as the processing time τ (p), and the like are output to the output device 110 such as a display device. (Step S103).

  If the counter value ic is less than the number of repetitions icmax, the counter value ic is incremented by 1 (step S105). Then, tuning is performed for parallel performance impediment factors such as redundancy processing, load balance, communication processing, and I / O (step S107). Tuning may be performed by tools, compilers, runtime libraries, etc. instead of rewriting programs. Since it may be an operation performed by a programmer, it is indicated by a dotted line block here. After tuning, the parallel computer system 200 processes the program again in parallel, and at the same time, the measurement unit 201 performs measurement processing such as processing time and stores it in the storage device (step S109). Since step S109 is not a process of the parallel performance analysis apparatus 100, it is represented by a block with a one-dot chain line. Thereafter, the data acquisition unit 10 acquires data such as processing time from the parallel computer system 200 and stores the data in the log data storage unit 30. Then, a parallel performance evaluation index including parallel efficiency is calculated by the load balance contribution rate calculation unit 11, virtual parallelization rate calculation unit 12, parallel performance impediment factor contribution rate calculation unit 13, parallel efficiency calculation unit 14, and the like, and log data Store in the storage unit 30 (step S111). Then, the process returns to step S97.

Thus, the tuning operation is performed so as to achieve the target processing time (τ) _T by a predetermined number of tunings, so that the programmer can also perform the efficient operation.

For example, a specific example is shown based on the processing time as shown in FIG. At this time, since τ (p) = 37 and E _p (4) = 0.4443, assuming that (E _p ) _max = 0.6 and (τ) _T = 28, (E _p ) _T = 0.5871 Become. Therefore, the process proceeds from step S95 to step S97. Since this is the first process, the process proceeds from step S97 to step S107 via steps S101 and S105. Therefore, it is assumed that the communication time χ _C is reduced to ½ as the first tuning. Using the result, a parallel performance evaluation index including parallel efficiency is calculated in step S111. Then, a result as shown in FIG. 32 is obtained. FIG. 32 shows a comparison with the processing time max (τ _i ) added.

（１）ロードバランス寄与率（式（５））

（２）仮想並列化率（式（６−１））

（３）並列性能阻害要因寄与率（式（７））

（４−１）並列効率（式（４−４））

（４−２）並列効率（式（９−１））

As a tuning, the calculation method when the communication time χ _C is reduced to ½ is as follows. Note that χ _{1, C} (4) = 10/2 = 5, χ _{2, C} (4) = 11/2 = 5.5, χ _{3, C} (4) = 12/2 = 6, χ _{4, C} (4) = 13/2 = 6.5. Moreover, it calculates as follows from Formula (12-1).

(1) Load balance contribution ratio (Formula (5))

(2) Virtual parallelization rate (Formula (6-1))

(3) Parallel performance impediment factor contribution ratio (Formula (7))

(4-1) Parallel efficiency (Formula (4-4))

(4-2) Parallel efficiency (Formula (9-1))

In one tuning, the processing time max (τi) (= τ (p)) is 30.5 and the target processing time (τ) _T has not been achieved. Therefore, some tuning needs to be performed again.

  Conventionally, evaluation of parallel performance has been performed on the basis of processing time comparison such as time change with the number of processors, processing time comparison with other systems, and comparison of the number of operations performed within the time. This required more than two time measurements, which increased the program development time. Further, in this relative parallel performance evaluation called comparison, when the processing data changes, it is necessary to measure the comparison criterion again. As a result of the time taken for parallel performance evaluation in this way, an application program that produces parallel performance only under certain conditions may be developed. By performing the processing described above, parallel performance evaluation based on parallel efficiency can be performed in a single measurement, and the performance evaluation time in the development time of parallel application programs can be significantly reduced. It becomes possible. As a result, it becomes possible to practically develop a parallel application program that fully considers parallel performance.

  In the past, performance improvement work by tuning application programs was not easy to estimate, because the goal was unclear. Further, it is not clear when the work is finished, and as a result, a large amount of work time may be spent. In some cases, redevelopment is required instead of tuning application programs. By performing the processing as described above, it becomes possible to clearly set a target for improving the parallel efficiency by tuning the application program and to predict the working time based on the number of times of tuning.

  Furthermore, in the past, tuning of an application program is to find a procedure (part of the application program) with a long processing time in the application program by measuring time, etc., and process the parallel performance impediment factors that are problematic in the procedure. The search was made by comparing the time, and the processing time was reduced. With the processing described above, it has become possible for the first time to evaluate the performance of the load balance against the tuning of a part of the application program.

F. Algorithm selection processing Traditionally, processing time was used to compare the performance of algorithms that were used as part of a parallel application program. It was not possible to determine whether it was an effect (for example, a decrease in the number of operations). As a result, we missed the waste of resources that put a lot of processors into algorithms with short processing time but poor scalability. In this embodiment, an algorithm with better parallel efficiency is selected to improve the operational efficiency of the entire system. Here, an example in which an algorithm that is not suitable for parallel processing is compared with an algorithm that is suitable for parallel processing will be described.

（１）ロードバランス寄与率（式（５））

（２）仮想並列化率（式（６−１））

（３）加速率（式（６−２））

（４）並列性能阻害要因寄与率（式（７））

（４−１）並列効率（式（４−４））

（４−２）並列効率（式（９−１））

[Algorithms not suitable for parallel processing]
For example, the case where the processing time is measured as shown in FIG. 33 will be described as an example. Note that χ _{1, C} (1) = 0. Moreover, it calculates as follows from Formula (12-1).

(1) Load balance contribution ratio (Formula (5))

(2) Virtual parallelization rate (Formula (6-1))

(3) Acceleration rate (Formula (6-2))

(4) Parallel performance impediment factor contribution ratio (Formula (7))

(4-1) Parallel efficiency (Formula (4-4))

(4-2) Parallel efficiency (Formula (9-1))

（１）ロードバランス寄与率（式（５））

（２）仮想並列化率（式（６−１））

（３）加速率（式（６−２））

（４）並列性能阻害要因寄与率（式（７））

（４−１）並列効率（式（４−４））

（４−２）並列効率（式（９−１））

[Algorithm for parallel processing]
An example when the processing time as shown in FIG. 34 is measured will be described. Note that χ _{1, C} (1) = 0. Moreover, it calculates as follows from Formula (12-1).

(1) Load balance contribution ratio (Formula (5))

(2) Virtual parallelization rate (Formula (6-1))

(3) Acceleration rate (Formula (6-2))

(4) Parallel performance impediment factor contribution ratio (Formula (7))

(4-1) Parallel efficiency (Formula (4-4))

(4-2) Parallel efficiency (Formula (9-1))

The above processing results are summarized as shown in FIG. Assuming that the number of the algorithm not suitable for parallel processing is j = 1 and the number of the algorithm suitable for parallel processing is j = 2, the acceleration rate A _p = 5.000 is finite at j = 1, and even if the number of processors is increased. It can be seen that the limit of 5 is effectively the limit. On the other hand, when j = 2, the acceleration rate A _p = ∞, and the processing time may be shortened as the processor is inserted. Since the processing time τ is 110 when j = 1 and shorter than 120 when j = 2, j = 1 may be selected, which is an algorithm that is not suitable for parallel processing.

Therefore, in the present embodiment, it is assumed that the processing shown in FIG. First, the setting input of the target processing time (τ) _T is received by the programmer (step S121). Then, as an initial setting, the algorithm number j to 1, set to 1 the optimal algorithm number j _T (step S123). When j = 1, the number of processors (p) ₁ necessary to achieve the target processing time (τ) _T is calculated by linear extrapolation (step S125). That is, (p) ₁ = (τ) ₁ / (τ) _T / (E _p ) ₁ + (p) ₁ using the processing time of the algorithm number j = 1 stored in the log data storage unit 30 Calculate and store in the storage device (step S125). Further, the number of processors required for the optimum algorithm is set as (p) _T = INT ((p) ₁ +0.99). Further, p _min = p ₁ is set.

Next, j is incremented by 1 (step S127). Then, the number of processors (p) j in the case of _j is calculated by the following formula and stored in the storage device (step S129).
(p) _j = (τ) _j / (τ) _T / (E _p ) _j + (p) _j
Then, it is confirmed whether (p) _j <(p) _min and (A _p ) _j > (p) _j (step S131). That is, it is confirmed whether (p) _j is minimum and the optimal number of processors is smaller than the acceleration rate (A _p ) _{j of the} algorithm, that is, it is feasible. In steps S125 and S129, since (p) _j is simply calculated by linear extrapolation, whether or not it can be realized is guaranteed here. If (p) _j <(p) _min and (A _p ) _j > (p) _j , the algorithm number j is set to j _T. That is, j _T = j. Further, (p) _T = INT ((p) _j +0.99) is set (step S133).

After step S131 or step S133, it is confirmed whether j is equal to or greater than the algorithm number j _max (step S135). That is, it is determined whether all algorithms have been processed. If j ≧ j _max , the algorithm number finally specified by j _T and the number of processors (p) _{T in} that case and other processing results (j, (p) _j , (A _p ) _j , (τ) _{j and the} like) are output to the output device 110 such as a display device (step S137). On the other hand, if j < _jmax , the process returns to step S127.

  In this way, it is possible to specify an algorithm that can achieve the target processing time with a small number of processors within a feasible range. It is also possible to select not only the algorithm optimized in this processing flow but also an algorithm that does not differ much in number of processors and that can be easily tuned.

This will be specifically described with an example of two algorithms shown in FIG. First, the target processing time (τ) _T = 50 is set. Next, the required number of processors (p) _j is calculated by linear extrapolation using (E _p ) _j and (τ) _j of those algorithms. In the processing flow shown in FIG. 36, since (p) _{j is obtained} by linear extrapolation, A _p (4) considering only redundant processing is introduced as the upper limit of the number of processors, and A _p (4)> (p) _{If j} , (p) _j can be applied. As a result, the limit performance of an algorithm that is not suitable for parallel processing is 5.000, whereas (p) _j is 7.872, and (p) _j cannot be applied to an algorithm that is not suitable for parallel processing. On the other hand, since the limit performance of an algorithm suitable for parallel processing is ∞, there is a possibility that (τ) _T = 50 can be achieved with a 6.618 processor. Therefore, an algorithm j _T = 1 suitable for parallel processing can be selected. The initial guide in that case is (p) _T = 7 obtained by rounding up 6.618. Up to now, in many cases, an algorithm that has a shorter processing time than τ of 110 and 120 but is not suitable for parallel processing has been adopted. However, according to the processing flow of FIG. The algorithm can be selected.

G. Parallel Performance Evaluation Processing In this embodiment, it is possible to create log data of parallel performance evaluation indexes for all processes in actual operation. If a specific process in the log data is targeted, it becomes possible to obtain specifications (CPU performance, communication performance, I / O performance, runtime library performance, etc.) necessary for the dedicated parallel computer system. If processing by all applications is targeted, it is possible to create specifications necessary for a general-purpose parallel computer system for the logs.

  For example, in order to improve the processing performance of processing numbers 1 to 4 shown in FIG. 37, it is only necessary to improve the communication performance or to improve the performance of both in a form that maintains the ratio between the CPU performance and the communication performance. I understand. For example, the parallel performance evaluation processing unit 27 forms a table as shown in FIG. 37 from the data stored in the log data storage unit 30 and outputs the table to the output device 110 such as a display device. Moreover, you may perform the process which highlights what shows a relatively high value in any process among parallel performance obstruction | occlusion factors. Further, it can be seen that in order to improve the performance of the process 5, it is necessary to tune the application program, etc., not to improve the performance by replacing the system. This is because the parallel performance impediment factor contribution rate due to the redundant processing is large only for the processing 5, and the parallel performance evaluation processing unit 27 also extracts characteristic processing, for example, highlighting it. There is also.

As a method for determining the communication performance, for example, the processing described in the system replacement data processing may be performed. That is, it is fixed to 1 except for the magnification of the communication performance, and is performed until the target E _p (4) is cleared.

  If the communication performance is improved by paying attention to the processing of patterns with process numbers 1 to 4 having a large number of processes, this system becomes a general-purpose parallel computer system. On the other hand, if a mechanism for reducing the redundant processing is introduced into the computer system by paying attention to the processing of the pattern with the processing number 5 having a small number of processing, a dedicated parallel computer system is obtained. Further, if the application program of process number 5 is tuned to reduce redundant processing, it becomes a general-purpose parallel computer system of 1 to 5 only by improving communication performance.

  Conventionally, since the parallel performance of a parallel computer system varies greatly depending on the parallel processing characteristics of application programs, it has been difficult to develop a parallel computer system. As a method for overcoming this problem, a method of identifying an application program, analyzing parallel performance, and developing a parallel computer system suitable for it has been used. However, with this method, if the application program changes, there is a risk of developing a system that cannot exhibit parallel performance at all. According to the present embodiment, it is possible to create log data of parallel performance evaluation indexes for all processes in actual operation. Therefore, if a specific process is targeted based on this log data, dedicated parallel It is possible to create specifications (CPU performance, communication performance, I / O performance, runtime library performance, etc.) necessary for the computer system. In addition, if all processes are targeted, it is possible to create specifications necessary for a general-purpose parallel computer system for the log.

  Conventionally, whether or not a means for quantitatively grasping the parallel performance impediment factor of the parallel computer system varies greatly depending on the system, and there is no means for quantitatively grasping the parallel performance impediment factor. There is also a system. In this embodiment, as shown in Equation (7), since there is a function that can arbitrarily add a factor from the state where there is no parallel performance impediment factor, evaluation is performed by adding a factor measurement function after system upgrade. Accuracy can be increased.

  Furthermore, conventional performance evaluation indexes such as flop / s, Mop / s, and tpmC may be applicable or not applicable depending on the type of application program. In this embodiment, since the index is represented by a time ratio, it is effective for all application programs, and performance evaluation can be appropriately performed. Furthermore, some conventional parallel performance evaluation methods can be applied only to special parallel processing, but according to the present embodiment, they can be applied to all parallel processing.

  Although the embodiment of the present invention has been described above, the ratio of reducing the parallel efficiency representing the performance of parallel processing by the parallel performance evaluation index, that is, the load balance contribution ratio, the virtual parallelization ratio, and the parallel performance. It becomes possible to show by the obstruction factor. The load balance contribution ratio is added to the parallel performance evaluation index, and parallel performance evaluation of all parallel processing becomes possible.

Further, if the equation (8-2) is used, when R _p (p) is approximately 1, the estimated value τ (1) is not required for the calculation of the parallel efficiency, and therefore τ (1) cannot be measured. Accurate parallel performance evaluation (in the sense of not including the estimated value τ (1)) of all parallel processing including parallel processing by grids and clusters becomes possible.

Furthermore, using Equations (9-1) and (9-2), even when R _p (p) <1, by estimating τ (1) for the calculation of parallel efficiency, τ (1) Parallel performance evaluation of all parallel processing is possible, including parallel processing by grids and clusters that cannot measure

  The form of the expression (7) makes it possible to introduce a parallel processing impediment factor specific to the target parallel computer system as needed, and a detailed performance evaluation can be easily performed. Furthermore, the contribution rate of the parallel performance impediment factor can be grasped as a percentage of the parallel efficiency, and an intuitive parallel performance evaluation becomes possible.

  In addition, since the contribution of load balance is clarified by the numerical value of the ratio to the parallel efficiency, the contribution of the load balance to the parallel performance that could not be evaluated so far can be specifically shown.

  In addition to calculating and presenting a parallel performance index, the number of processors that perform efficient processing can be determined using the parallel efficiency determined by processing time measurement. Furthermore, the increase or decrease of the processor can be considered in consideration of the efficiency of parallel processing.

  Furthermore, the introduction of a new parallel computer system with different performance specifications can be examined on the desk. In addition, the use efficiency management in system operation can be performed using the parallel performance evaluation index.

  Although the embodiment of the present invention has been described above, the present invention is not limited to this. For example, the functional block diagram of FIG. 19 is an example and does not necessarily correspond to a program module. Further, the processor number optimization processing unit 21, the processor expansion estimation processing unit 22, the system replacement data processing unit 23, the operation efficiency data processing unit 24, the tuning processing unit 25, the algorithm selection processing unit 26, and the parallel performance evaluation processing unit 27 are all included. It does not have to be provided, and all may be provided or may not be provided at all. Furthermore, it may be provided in any combination.

[Example]
The above-described embodiments are all parallel processing (memory, network, grid with the same or different hetero configuration with the same CPU performance, cluster or distributed memory, or SMP (Symmetric MultiProcessing), SMP + distributed memory. NUMA (Non Uniform Memory Access) and the like. Below, the example of a calculation is shown about a typical mode.

(1) Grid etc. in homo structure (χ _{1, j} (1) = 0)
When processing is performed in a grid or cluster, communication occurs because a network is used for allocation of processing to each processor and collection of processing results, but this does not occur when processing is performed by one processor. Such a process is a process of χ _{1, j} (1) = 0. Here, the parallel performance impediment factor is only communication, and the parallel performance of the processing in which χ _{1, C} (1) = 0 is evaluated. For example, a case where a measurement result of elapsed time as shown in FIG. 38 is obtained will be described.

式（５）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（８−２）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from the equations (5), (6-1), (6-2), and (7), respectively.

For the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (8-2), (9-1), and (9-2), respectively. The

The calculated parallel performance evaluation indexes are summarized as shown in FIG. Since A _p (p) = ∞, the possibility of performance improvement when parallel processing is performed with p = ∞ is infinite, but the actual performance improvement E _p (4) · p is 1.929 with the number of processors p = 4 is there. The reason is that the parallel efficiency E _p (4) is 93% (Rb (4) = 0.9286) as a load balance contribution ratio, and is further reduced by 48% (Rc (4) = 0.4808) due to communication.

(2) Grids in homo structure (χ _{1, RED} (1) ≠ 0)
In numerical calculations, application programs are often copied to all processors, loop processing indexes and the like are identified, and processing is shared by each processor, so-called data parallel processing is often performed. In data parallel, for example, processing that cannot be performed in parallel remains between loops. When this processing is performed by all the processors, the content is the same processing, so this is called redundancy processing. The feature of the redundant processing is that χ _{1, RED} (1) ≠ 0 because it is necessary processing even when it is not parallel processing. Here, the parallel performance impediment factor is only redundant processing, and the parallel performance of processing in which χ _{1, RED} (1) ≠ 0 is evaluated. For example, a case where a measurement result of elapsed time as shown in FIG. 40 is obtained will be described.

式（５）、式（１２−１）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

Regarding the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (9-1), and (9-2).

The calculated parallel performance evaluation indexes are summarized as shown in FIG. Here, since A _p (p) = 9.737, parallel processing of p> 9 is meaningless. The actual performance improvement E _p · p with the number of processors p = 4 is 2.874. The reason is that the parallel efficiency E _p is 94% (Rb (4) = 0.9398) as a load balance contribution ratio, and is further reduced by 31% (R _RED (4) = 0.3141) by the redundancy processing.

(3) Grid in homo structure (χ _{1, j} (1) ≠ 0: except for redundant processing)
For example, the processing time of the communication library is composed of network communication and calculation. This calculation time is treated as χ _{1, C} (1). Here, the parallel performance impediment factor is only communication, and the parallel performance of the processing in which χ _{1, C} (1) ≠ 0 is evaluated. For example, a case where a measurement result of elapsed time as shown in FIG. 42 is obtained will be described.

式（５）、式（１２−１）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

Regarding the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (9-1), and (9-2).

The calculated parallel performance evaluation indexes are summarized as shown in FIG. Here, since A _p (p) = 22.57, it should be processed with p <22. The actual performance improvement E _p · p with the number of processors p = 4 is 1.859. This is because the parallel efficiency E _p is reduced by 53% (R _C = 0.5263) due to communication. The load balance contribution ratio is 94% (Rb (4) = 0.9375), and the load balance is not the main factor that hinders the parallel performance in this case. The difference from the embodiment (1) is that A _p (p) becomes a finite value because χ _{1, C} (1) ≠ 0.

The calculations included in the communication process may change as the number of processors increases. By considering this as Χ _{i, C} (p) and incorporating it into the parallel performance evaluation, it becomes possible to incorporate different numbers of operations into the evaluation depending on the number of processors.

(4) Grid etc. in a homo structure (when there is a wait (also called idling: wait))
When a specific processor processes and the result is used by another processor, the other processor cannot start the next processing until the processing is completed. For example, this is the case when only a specific processor can access the database (DB). In FIG. 44, this processing (γ ′) is performed by the processor # 1. Other processors are in a waiting state during DB processing. In this way, the parallel performance can be evaluated when there is an idling process that keeps the CPU waiting. Assume that a measurement result of elapsed time as shown in FIG. 44 is obtained.

式（５）、式（１２−１）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（８−２）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

For the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (8-2), (9-1), and (9-2), respectively. The

The above calculated parallel performance evaluation indices are summarized as shown in FIG. Since A _p (4) = ∞, the possibility of performance improvement when parallel processing is performed at p = ∞ is infinite, but the actual performance improvement E _p · p when p = 4 is input is 2.226. This is because the parallel efficiency E _p is reduced by 32% (R _C (4) = 0.3158) due to communication and 11% (R _W (4) = 0.1108) due to idling. The load balance contribution ratio is 97% (Rb (4) = 0.9704). In this case, the load balance is not a main factor that hinders parallel performance.

(5) Grid in homo structure (when there is a wait due to other processing)
When processing is performed in a grid or cluster, it is rare to use each processor only for its own processing, and in general, it coexists in a plurality of processing. In that case, a wait is caused by another process interrupting. This is shown in FIG. In this way, the parallel performance when there is waiting due to other processing is evaluated. Assume that a measurement result of elapsed time as shown in FIG. 46 is obtained.

式（５）、式（１２−１）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（８−２）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

For the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (8-2), (9-1), and (9-2), respectively. The

The calculated parallel performance evaluation index is summarized as shown in FIG. Since A _p (4) = ∞, the possibility of performance improvement when parallel processing is performed at p = ∞ is infinite, but the actual performance improvement E _p · p when p = 4 is input is 1.808. The reason for this is that the parallel efficiency E _p is 79% (Rb (4) = 0.7875) in the load balance contribution ratio, 28% (R _W (4) = 0.2778) due to waiting for time sharing, and further due to communication This is because it decreases by 14% (R _C = 0.1418). Since R _W (4) is generated by other processing, Rb (4) is a load balance contribution ratio considering the entire system. When there are other processes, it is necessary to pay attention to Rb (4) and R _W (4). Even if Rb (4) = 1, if R _W (4) is large, it means that a crowded system is used, and E _p has a low value. When deploying grid or clustering, particularly Rb (4) is by selecting the system to be and R _W is 0 to approach 1, it is possible to perform parallel processing efficiently. This is the first time that this is understood.

  Note that there is a method of measuring CPU time and elapsed time as a method for distinguishing between own processing (target processing) and other processing (non-target processing). In general, the CPU time is the time of only the own process, and the elapsed time is the time including other processes. Therefore, there may be a case where waiting time for time sharing = elapsed time−CPU time.

(6) Grid etc. in homo configuration (in case of data parallel processing)
The data parallel processing is parallel processing in which, for example, 1000 pieces of data are divided into 250 pieces by 4 processors for processing, and the procedures of each processor are the same and the data are different. Processing that cannot be performed in parallel may be the case where data of all processors is made the same, that is, when redundant processing is performed, or processing is performed by a certain processor and broadcasted to all processors. Here, the parallel performance of both is evaluated.

[Data parallel processing using redundant processing]
Assume that a measurement result of elapsed time as shown in FIG. 48 is obtained. In addition, χ _{1, C} = 0.

並列効率については、順番に式（４−４）、式（４−５）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculations are performed from Expression (3), Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

Regarding the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (9-1), and (9-2).

The calculated parallel performance evaluation indexes are summarized as shown in FIG. Since A _p (4) = 21.01, the number of processors should be selected with p ≦ 21. The actual performance improvement E _p · p when the number of processors p = 4 is input is 2.800. The reason is that the parallel efficiency E _p (4) is reduced by 20% (R _C = 0.2000) in communication and 13% (R _RED (4) = 0.133) in redundant processing.

[Data parallel processing where a specific processor processes parts that cannot be processed in parallel]
Instead of performing redundant processing on parts that cannot be processed in parallel, processing may be performed by a specific processor. FIG. 50 shows a case where only the processor # 1 performs processing (γ ′ portion) instead of the redundant processing of FIG. 48, and the result is broadcast to each processor. Of course, the other processors wait for the result of processor # 1. Here, γ ′ is handled as parallel processing, but if it is added to parallel processing impediment factors as sequential processing, more detailed parallel performance evaluation can be performed. However, for that purpose, it is necessary to determine whether the processing of γ ′ is sequential processing or parallel processing. Assume that a measurement result of elapsed time as shown in FIG. 50 is obtained. In addition, χ _{1, C} = 0.

並列効率については、順番に式（４−４）、式（４−５）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculations are performed from Expression (3), Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

Regarding the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (9-1), and (9-2).

The calculated parallel performance evaluation index is summarized as shown in FIG. The performance improvement when parallel processing is performed with A _p (4) = ∞ is infinite, but the actual performance improvement E _p · p when p = 4 is input is 2.800. The reason is that the parallel efficiency E _p (4) decreases by 20% (R _C (4) = 0.000) in communication and decreases by 10% (R _W (4) = 0.000) in waiting. 49 and 51 are different in values of R _p (4), A _p (4), R _RED (4), and R _W. On the other hand, Rb (4) and E _p (4) have the same value. In FIG. 51, since the portion γ ′ that cannot be processed in parallel is evaluated as parallel processing, R _p (4) = 1. In addition, the redundant processing of the processors # 2, 3, and 4 is changed to waiting, and is replaced with the parallel performance impediment factor R _W (4).

(7) Grid in homo configuration (in case of control parallel processing)
In the control parallel processing, the procedure of each processor is usually different. For this reason, there are many cases in which parallel processing with different procedure times of each processor is performed. Here, the parallel performance of the control parallel is evaluated. Assume that a measurement result of elapsed time as shown in FIG. 52 is obtained. In addition, χ _{1, C} = 0.

式（５）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（８−２）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from the equations (5), (6-1), (6-2), and (7), respectively.

For the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (8-2), (9-1), and (9-2), respectively. The

The calculated parallel performance evaluation index is summarized as shown in FIG. The performance improvement when parallel processing is performed with A _p (4) = ∞ is infinite, but the actual performance improvement E _p · p when p = 4 is input is 2.528. The reason for this is that the parallel efficiency E _p is 82% (Rb (4) = 0.8231) in terms of load balance contribution, and 23% (R _TC (4) + R _C (4) + R _W ) including task generation, communication, and waiting. (4) = 0.0344 + 0.1089 + 0.0888).

In order to improve parallel performance, we compare parallel performance indexes and examine room for improvement in descending order of influence on parallel performance degradation. In the case of FIG. 53, this is the order of Rb (4), R _C (4), R _W (4), and R _TC (4). When Rb (4) = 1, E _p (4) · p = 3.071 (= 2.528 / 0.8231). Therefore, for example, an attempt is made to change the processing schedule so that the processing time of the processor # 1 is the same as that of the other processors. The next room for improvement is the reduction of R _C (4). As a reduction method, for example, it is conceivable to replace with hardware that doubles the communication performance. In that case, the following calculation is performed.

式（５）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、式（４−４）以下のような計算がなされる。

さらに、以下のような計算もなされる。

もし、通信の性能を上記のように向上させ、さらにＲb(4)＝１にロードバランスを変更できれば、以下のような計算がなされる。

First, the following calculation is performed from Equation (3).

The following calculations are performed from the equations (5), (6-1), (6-2), and (7), respectively.

For the parallel efficiency, the following equation (4-4) is calculated.

Further, the following calculation is performed.

If the communication performance is improved as described above and the load balance can be changed to Rb (4) = 1, the following calculation is performed.

E. As shown in the tuning process, in this embodiment, the parallel performance when each parallel performance impediment factor is tuned and improved can be estimated. In the conventional tuning it had a target value in the processing time, but impossible target value had to be set, in this embodiment it is possible to reasonable goal set by using the E _p. Furthermore, in the present embodiment, since the parallel efficiency and the like can be calculated from a single measurement result, the performance evaluation time during tuning can be shortened. Furthermore, in the conventional tuning, when the input data or the processing function is changed, the processing time for each parallel performance impediment factor measured so far cannot be used for performance evaluation. Therefore, independent parallel performance evaluation has been performed for each input data and processing function. In this embodiment, all the performance evaluation indexes are in the form of ratios, and the parallel performance of different input data and processing functions can be compared.

(8) Grid, etc. in a homo configuration (when master / slave processing is performed in control parallel)
In the control parallel processing, the procedure of each processor is usually different. In the case of the master / slave process, one processor serves as a master that manages other processors, and a plurality of processors execute processes according to the instruction. Here, the parallel performance when the processor # 1 is a master processor is evaluated. Assume that a measurement result of elapsed time as shown in FIG. 54 is obtained. In addition, χ _{1, C} = 0.

式（５）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（８−２）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from the equations (5), (6-1), (6-2), and (7), respectively.

For the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (8-2), (9-1), and (9-2), respectively. The

The calculated parallel performance evaluation index is summarized as shown in FIG. Since A _p (4) = ∞, the performance improvement when parallel processing is performed at p = ∞ is infinite, but the actual performance improvement E _p · p when p = 4 is input is 2.055. The reason is that the parallel efficiency E _p is 86% (Rb (4) = 0.8571) in the load balance contribution ratio, 23% in the waiting state (R _W (4) = 0.2340), 17% in total for task generation and communication ( This is because R _TC (4) + R _C (4) = 0.0385 + 0.1282). When performing master slave processing, it is known that the waiting time of the master processor has an important effect on the performance of the entire processing. It can be determined whether the process is being performed effectively.

(9) Grid, etc. in homo configuration (when data parallel and control parallel are mixed)
A process in which data parallel and control parallel are mixed is not used in normal business because it is difficult to maintain load balance. In this embodiment, parallel performance evaluation in such a case is also possible. Since this embodiment provides a performance evaluation index for control of processing, it provides a practical evaluation method for such processing. Here, the parallel performance when the processors # 1 to # 4 are control parallel, the processors # 5 to # 8 are data parallel, and the processor # 1 is a master processor is evaluated. Assume that a measurement result of elapsed time as shown in FIG. 56 is obtained. In addition, χ _{1, C} = 0.

式（５）、式（１２−１）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（８−２）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

For the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (8-2), (9-1), and (9-2), respectively. The

The calculated parallel performance evaluation index is summarized as shown in FIG. Since A _p (8) = 47.62, parallel processing should be performed with p <47. The actual performance improvement E _p · p when the number of processors p = 8 is 5.42 is 5.242. The reason is that the parallel efficiency E _p is 93% (Rb (8) = 0.9286) in the load balance contribution ratio, 11% in the waiting state (R _W (8) = 0.080), and 11% in the communication (R _C (8)) This is because the redundancy processing and task generation are reduced by 9% (R _RED (8) + R _TC (8) = 0.0592 + 0.0296). As described above, the present embodiment can be applied to a parallel processing system in which data parallel and control parallel are mixed.

(10) When there is redundant processing in a hetero configuration such as a grid (χ _{1, RED} ≠ 0)
Processors connected by a grid or cluster often have different CPU capabilities. This is called a hetero configuration. This embodiment can also be applied to a hetero configuration. Here, in the embodiment (2), the parallel performance when the processor # 1 has a half performance is evaluated. Assume that a measurement result of elapsed time as shown in FIG. 58 is obtained.

式（５）、式（１２−１）、式（６−１）、式（６−２）及び式（７）からそれぞれ以下のような計算がなされる。

並列効率については、順番に式（４−４）、式（４−５）、式（９−１）、式（９−２）からそれぞれ以下のような計算がなされる。

The following calculation is performed from Equation (3).

The following calculations are performed from Expression (5), Expression (12-1), Expression (6-1), Expression (6-2), and Expression (7), respectively.

Regarding the parallel efficiency, the following calculations are performed in order from the equations (4-4), (4-5), (9-1), and (9-2).

The calculated parallel performance evaluation indexes are summarized as shown in FIG. Since A _p (4) = 9.881, parallel processing with p> 9 is meaningless. The actual performance improvement E _p · p with the processor of p = 4 is 1.918. The reason is that the parallel efficiency E _p is 63% (Rb (4) = 0.6250) as a load balance contribution ratio, and is further reduced by 31% (R _RED (4) = 0.3103) by the redundancy processing. Compared with FIG. 41, it can be seen that the load balance contribution ratio Rb (4) decreases from 0.9398 to 0.6250. This is a result of the difference in processor # 1 being reflected in the performance evaluation index Rb (4) as shown in FIG. 41 and FIG. In general, when an equally divided task is processed by a processor having a different CPU capability, the load balance is lost. In the present embodiment, this can be detected by Rb (4).

(Appendix 1)
A parallel efficiency calculation method for calculating parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating step of calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system, and storing the load balance contribution ratio in a storage device; and
A virtual parallelization rate calculating step of calculating a virtual parallelization rate representing a ratio with respect to time of a portion calculated in parallel by each processor in the processing performed in the parallel computer system, and storing the virtual parallelization rate in a storage device;
A parallel performance inhibition factor contribution ratio calculating step of calculating a parallel performance inhibition factor contribution ratio representing a ratio of processing time of each parallel performance inhibition factor portion to the total processing time of all processors included in the parallel computer system, and storing the calculation result in a storage device When,
Calculating a parallel efficiency using the load balance contribution rate, the virtual parallelization rate, and the parallel performance impediment factor contribution rate, and storing in a storage device;
Parallel efficiency calculation method including

(Appendix 2)
A parallel efficiency calculation method for calculating parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating step of calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system, and storing the load balance contribution ratio in a storage device; and
An acceleration rate calculating step for calculating an acceleration rate representing a limit of improvement in a reduction degree of processing time by parallelization of processing performed in the parallel computer system, and storing the acceleration rate in a storage device;
A parallel performance inhibition factor contribution ratio calculating step of calculating a parallel performance inhibition factor contribution ratio representing a ratio of processing time of each parallel performance inhibition factor portion to the total processing time of all processors included in the parallel computer system, and storing the calculation result in a storage device When,
Calculating parallel efficiency using the load balance contribution rate, the acceleration rate, and the parallel performance impediment factor contribution rate, and storing in a storage device;
Parallel efficiency calculation method including

(Appendix 3)
A parallel efficiency calculation method for calculating parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating step of calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system, and storing the load balance contribution ratio in a storage device; and
A parallel performance inhibition factor contribution ratio calculating step of calculating a parallel performance inhibition factor contribution ratio representing a ratio of processing time of each parallel performance inhibition factor portion to the total processing time of all processors included in the parallel computer system, and storing the calculation result in a storage device When,
Calculating parallel efficiency using the load balance contribution rate and the parallel performance impediment factor contribution rate, and storing the storage efficiency in a storage device;
Parallel efficiency calculation method including

(Appendix 4)
A parallel efficiency calculation method for calculating parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating step of calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system, and storing the load balance contribution ratio in a storage device; and
A virtual parallelization rate calculating step of calculating a virtual parallelization rate representing a ratio of time of a part to be calculated in parallel by each processor among processes executed in the parallel computer system, and storing the virtual parallelization rate in a storage device;
Of the processes executed in each processor included in the parallel computer system, the sum of the processing times of the parallel calculation part, the sum of the processing times of the processes executed in the processors, the load balance contribution ratio, and the virtual Calculating the parallel efficiency using the parallelization rate and storing it in a storage device;
Parallel efficiency calculation method including

(Appendix 5)
A parallel efficiency calculation method for calculating parallel efficiency of a parallel computer system,
A step of calculating a first processing time corresponding to the total processing time of the parallel performance impeding portion of the processing in a case where the processing is performed by one processor, and storing the first processing time in a storage device;
Calculating a second processing time that is the sum of the processing times of the parallel computing portions of the processing performed in each processor included in the parallel computer system, and storing the second processing time in a storage device;
The number of processors used in the parallel computer system, the longest processing time of the processing times executed in each processor included in the parallel computer system, the first processing time, and the second processing Calculating parallel efficiency using time and storing in a storage device;
Parallel efficiency calculation method including

(Appendix 6)
In the load balance contribution ratio calculating step,
The load balance contribution ratio is
The total processing time of the processes executed in all the processors included in the parallel computer system is used in the longest processing time and the parallel computer system among the processing times of the processes executed in the processors included in the parallel computer system. The parallel efficiency calculation method according to any one of appendices 1 to 4, wherein the calculation is performed by dividing by the number of processors processed.

(Appendix 7)
In the virtual parallelization rate calculation step,
The virtual parallelization rate is
Dividing the sum of the processing times of the parallel computing portion of the processing executed in each processor included in the parallel computer system by the processing time corresponding to the third processing time when the same processing is executed by one processor. The parallel efficiency calculation method according to appendix 1 or 4, wherein the parallel efficiency calculation method is performed by the following.

(Appendix 8)
In the parallel performance impediment factor contribution rate calculation step,
The parallel performance impediment factor contribution ratio for a specific parallel performance impediment factor
Calculating the sum of the processing times of the specific parallel performance impediment factors in each processor included in the parallel computer system by dividing the sum of the processing times of the processors included in the parallel computer system. The parallel efficiency calculation method according to any one of supplementary notes 1 to 3.

(Appendix 9)
In the acceleration rate calculating step,
The acceleration rate,
By dividing the sum of the processing times of the parallel computing portion of the processing executed in each processor included in the parallel computer system by the processing time corresponding to the third processing time when the same processing is executed by one processor. The parallel efficiency calculation method according to appendix 2, wherein the calculated virtual parallelization rate is calculated as an inverse of a value obtained by subtracting from 1.

(Appendix 10)
The parallel efficiency calculation method according to any one of appendices 1 to 9, wherein the processing time is represented by the number of confirmations of the corresponding event.

(Appendix 11)
Multiplying the calculated parallel efficiency by the number of processors used in the parallel computer system to calculate an auxiliary index and storing it in a storage device;
The parallel efficiency calculation method according to any one of appendices 1 to 10, further including:

(Appendix 12)
The third processing time is
In the case where the processing is performed by one processor, the first processing time corresponding to the total processing time of the parallel performance impeding portion of the processing and the parallel computing portion of the processing executed in each processor included in the parallel computer system. The parallel efficiency calculation method according to any one of appendices 7 and 9, wherein calculation is performed based on a sum of the second processing time which is a sum of processing times.

(Appendix 13)
The first processing time is a value obtained by dividing the sum of the processing times of redundant processing by the number of processors among the processing executed in each processor included in the parallel computer system, and is executed in each processor included in the parallel computer system. Among the processed processing, the maximum value of the processing time of the redundant processing, the minimum value of the processing time of the redundant processing among the processing performed in each processor included in the parallel computer system, and implemented in each processor included in the parallel computer system The parallel processing according to appendix 5 or 12, wherein the processing time of the parallel processing and the processing time of the parallel performance impediment factor among the processed processing is one of the values of the processing time of the redundant processing in the processor Efficiency calculation method.

(Appendix 14)
The first processing time is generated in the number of processors of two or more from the processing time due to the parallel performance impediment factor other than the redundant processing among the processing executed in each processor included in the parallel computer system, and depends on the number of processors. A value obtained by dividing the value obtained by adding the fourth processing time obtained by reducing the processing time due to the parallelization inhibiting factor for all processors by the number of processors, the maximum value of the fourth processing time in all processors, and the fourth value in all processors. The parallel efficiency calculation method according to appendix 5 or 12, characterized in that it is one of the minimum values of the processing time.

(Appendix 15)
Setting a target parallel efficiency; and
Calculating the optimum number of processors by dividing the calculated product of the parallel efficiency and the number of processors by the target parallel efficiency, and storing it in a storage device;
The parallel efficiency calculation method according to any one of appendices 1 to 14, further including:

(Appendix 16)
A step of setting an increased operation time and predicted parallel efficiency at the time of system enhancement;
The product sum of the total processing time of the processing time performed by each processor currently included in the parallel computer system and the calculated parallel efficiency, the product of the increased operating time and the predicted parallel efficiency And calculating the acceleration rate at the time of system augmentation by dividing by the sum of the operating time of each processor currently included in the parallel computer system, and storing in the storage device,
The parallel efficiency calculation method according to any one of appendices 1 to 14, further including:

(Appendix 17)
Setting a performance factor of a new parallel computer system with respect to the parallel computer system;
Calculating an estimated parallel efficiency using the performance factor of the new parallel computer system and storing it in a storage device;
The parallel efficiency calculation method according to any one of appendices 1 to 14, further including:

(Appendix 18)
The sum of the processing times of the processes performed in each processor currently included in the parallel computer system and the product sum of all the processes of the calculated parallel efficiency are calculated as the total operation of each processor currently included in the parallel computer system. Calculating the system operating efficiency by dividing by time and storing it in a storage device;
The parallel efficiency calculation method according to any one of appendices 1 to 14, further including:

(Appendix 19)
Setting a target processing time;
Calculating a target parallel efficiency using the target processing time and storing it in a storage device;
Checking the validity of the target parallel efficiency;
The parallel efficiency calculation method according to any one of appendices 1 to 14, further including:

(Appendix 20)
When the validity of the target parallel efficiency is confirmed, the parallel efficiency after tuning is calculated and stored in a storage device;
Comparing the parallel efficiency after performing the tuning with the target parallel efficiency;
The parallel efficiency calculation method according to appendix 19, further including:

(Appendix 21)
Setting a target processing time;
Calculating an estimate of the required number of processors using the parallel efficiency in the algorithm for each different algorithm and storing it in a storage device;
The estimated number of processors calculated for an algorithm whose estimated value for the number of processors is smaller than an acceleration rate that represents the limit of improvement in the degree of reduction in processing time due to parallelization of processing by the algorithm executed in the parallel computer system Extracting an algorithm having a minimum value among
The parallel efficiency calculation method according to any one of appendices 1 to 14, further including:

(Appendix 22)
A program for causing a computer to execute the parallel efficiency calculation method according to any one of appendices 1 to 21.

(Appendix 23)
A parallel efficiency computing device for computing the parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating means for calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system and storing the load balance contribution ratio in a storage device;
A virtual parallelization rate calculating means for calculating a virtual parallelization rate representing a ratio of time of a part of the processing executed in the parallel computer system, which is calculated in parallel by each processor, and storing the virtual parallelization rate in a storage device;
Parallel performance inhibition factor contribution ratio calculating means for calculating a parallel performance inhibition factor contribution ratio representing a ratio of processing time of each parallel performance inhibition factor portion to the total processing time of all processors included in the parallel computer system, and storing it in a storage device When,
Means for calculating parallel efficiency using the load balance contribution rate, the virtual parallelization rate, and the parallel performance impediment factor contribution rate, and storing the storage efficiency in a storage device;
A parallel efficiency computing device having:

(Appendix 24)
A parallel efficiency computing device for computing the parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating means for calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system and storing the load balance contribution ratio in a storage device;
Acceleration rate calculation means for calculating an acceleration rate representing the limit of improvement in the degree of reduction in processing time by parallelization of processing performed in the parallel computer system, and storing the acceleration rate in a storage device;
Parallel performance inhibition factor contribution ratio calculating means for calculating a parallel performance inhibition factor contribution ratio representing a ratio of processing time of each parallel performance inhibition factor portion to the total processing time of all processors included in the parallel computer system, and storing it in a storage device When,
Means for calculating parallel efficiency using the load balance contribution rate, the acceleration rate, and the parallel performance impediment factor contribution rate, and storing the storage efficiency in a storage device;
A parallel efficiency computing device having:

(Appendix 25)
A parallel efficiency computing device for computing the parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating means for calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system and storing the load balance contribution ratio in a storage device;
Parallel performance inhibition factor contribution ratio calculating means for calculating a parallel performance inhibition factor contribution ratio representing a ratio of processing time of each parallel performance inhibition factor portion to the total processing time of all processors included in the parallel computer system, and storing it in a storage device When,
Means for calculating parallel efficiency using the load balance contribution rate and the parallel performance impediment factor contribution rate, and storing the storage efficiency in a storage device;
A parallel efficiency computing device having:

(Appendix 26)
A parallel efficiency computing device for computing the parallel efficiency of a parallel computer system,
A load balance contribution ratio calculating means for calculating a load balance contribution ratio representing a degree of load balance between processors included in the parallel computer system and storing the load balance contribution ratio in a storage device;
A virtual parallelization rate calculating means for calculating a virtual parallelization rate representing a ratio of time of a part of the processing executed in the parallel computer system, which is calculated in parallel by each processor, and storing the virtual parallelization rate in a storage device;
Of the processes executed in each processor included in the parallel computer system, the sum of the processing times of the parallel calculation part, the sum of the processing times of the processes executed in the processors, the load balance contribution ratio, and the virtual Means for calculating the parallel efficiency using the parallelization rate and storing it in a storage device;
A parallel efficiency computing device having:

(Appendix 27)
A parallel efficiency computing device for computing the parallel efficiency of a parallel computer system,
Means for calculating a first processing time corresponding to the total processing time of the parallel performance impeding portion of the processing in a case where the processing is performed by one processor and storing it in a storage device;
Means for calculating a second processing time that is the sum of the processing times of the parallel calculation portion of the processing performed in each processor included in the parallel computer system, and storing the second processing time in a storage device;
The number of processors used in the parallel computer system, the longest processing time of the processing times executed in each processor included in the parallel computer system, the first processing time, and the second processing Means for calculating parallel efficiency using time and storing in a storage device;
A parallel efficiency computing device having:

により計算し、前記記憶装置に格納するステップと、
を含む並列効率計算方法。 (Appendix 28)
A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the total processing when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to the processing times τ _i (p) of the p processors. The ratio of processing time to the time when parallel processing is not performed,
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
By the data acquisition unit of the computer having a data acquisition unit, a load balance contribution rate calculation unit, a virtual parallelization rate calculation unit, a parallel performance impediment factor contribution rate calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device, From the storage unit of the parallel computer system, the processing time γ _i (p) of the parallel calculation part and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are obtained and stored in the log data storage unit Storing, and
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
A virtual representing a ratio of time of a part calculated in parallel by each processor in processing executed in the parallel computer system by using the data stored in the log data storage unit by the virtual parallelization rate calculation unit A virtual parallelization rate calculating step of calculating a parallelization rate Rp (p) and storing it in the storage device;
Using the data stored in the log data storage unit by the parallel performance inhibition factor contribution rate calculation unit, the processing time χ of each parallel performance inhibition factor part j relative to the total processing time of all processors included in the parallel computer system calculating a parallel performance impediment factor contribution ratio Rj (p) representing a ratio of _{i, j} (p) and storing it in the storage device;
Using the load balance contribution rate Rb (p), the virtual parallelization rate Rp (p), and the parallel performance impediment factor contribution rate Rj (p) stored in the storage device by the parallel efficiency calculation unit. , Parallel efficiency E _p (p)

And calculating and storing in the storage device;
Parallel efficiency calculation method including

により計算し、前記記憶装置に格納するステップと、
を含む並列効率計算方法。 (Appendix 29)
A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the parallel processing with respect to the total processing time when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to each processing time of the p processors. Is the ratio of the processing time when not performing
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
The data acquisition unit of the computer having a data acquisition unit, a load balance contribution rate calculation unit, an auxiliary index calculation unit, a parallel performance impediment factor contribution rate calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device allows the parallel The processing time γ _i (p) of the parallel computing portion and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are acquired from the storage unit of the computer system and stored in the log data storage unit Steps,
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
The auxiliary index calculation unit uses the data stored in the log data storage unit, and uses the data stored in the log data storage unit to express the acceleration rate A _p (p ) And calculating an acceleration rate to be stored in the storage device,
Using the data stored in the log data storage unit by the parallel performance inhibition factor contribution rate calculation unit, the processing time χ of each parallel performance inhibition factor part j relative to the total processing time of all processors included in the parallel computer system calculating a parallel performance impediment factor contribution ratio Rj (p) representing a ratio of _{i, j} (p) and storing it in the storage device;
Using the load balance contribution rate Rb (p), the acceleration rate A _p (p), and the parallel performance impediment factor contribution rate Rj (p) stored in the storage device by the parallel efficiency calculation unit, Parallel efficiency E _p (p)

And calculating and storing in the storage device;
Parallel efficiency calculation method including

により計算し、前記記憶装置に格納するステップと、
を含む並列効率計算方法。 (Appendix 30)
A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the total processing when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to the processing times τ _i (p) of the p processors. The ratio of processing time to the time when parallel processing is not performed,
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
The data acquisition unit of the computer having a data acquisition unit, a load balance contribution rate calculation unit, a parallel performance impediment factor contribution rate calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device allows the storage of the parallel computer system Obtaining the processing time γ _i (p) of the parallel computing portion and the processing time χ _{i, j} (p) of each parallel performance impediment factor j from the unit, and storing the log data in the log data storage unit;
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
Using the data stored in the log data storage unit by the parallel performance inhibition factor contribution rate calculation unit, the processing time χ of each parallel performance inhibition factor part j relative to the total processing time of all processors included in the parallel computer system calculating a parallel performance impediment factor contribution ratio Rj (p) representing a ratio of _{i, j} (p) and storing it in the storage device;
The parallel efficiency calculation unit calculates the parallel efficiency E _p (p) using the load balance contribution rate Rb (p) and the parallel performance impediment factor contribution rate Rj (p) stored in the storage device.

And calculating and storing in the storage device;
Parallel efficiency calculation method including

により計算し、前記記憶装置に格納するステップと、
を含む並列効率計算方法。 (Appendix 31)
A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the total processing when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to the processing times τ _i (p) of the p processors. The ratio of processing time to the time when parallel processing is not performed,
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
The parallel computer system includes the data acquisition unit, the load balance contribution rate calculation unit, the virtual parallelization rate calculation unit, the parallel efficiency calculation unit, the auxiliary index calculation unit, the log data storage unit, and the storage device. Obtaining the processing time γ _i (p) of the parallel computing portion and the processing time χ _{i, j} (p) of each parallel performance impediment factor j from the storage unit of the storage unit, and storing in the log data storage unit; ,
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
A virtual representing a ratio of time of a part calculated in parallel by each processor in processing executed in the parallel computer system by using the data stored in the log data storage unit by the virtual parallelization rate calculation unit A virtual parallelization rate calculating step of calculating a parallelization rate Rp (p) and storing it in the storage device;
Using the data stored in the log data storage unit by the auxiliary index calculation unit, the sum of the processing times γ _i (p) of the parallel calculation part of the processes executed in each processor included in the parallel computer system an auxiliary index calculating step of calculating α and a sum β of processing times of processing performed in each of the processors, and storing in the storage device;
Using the α, β, the load balance contribution rate Rb (p), and the virtual parallelization rate Rp (p) stored in the storage device by the parallel efficiency calculation unit, a parallel efficiency E _p ( p)

And calculating and storing in the storage device;
Parallel efficiency calculation method including

により計算し、前記記憶装置に格納するステップと、
を含む並列効率計算方法。 (Appendix 32)
A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is assumed that the longest processing time τ (p) when parallel processing is performed by p processors is equal to each processing time τ _i (p) of the p processors. Is the ratio of the processing time when parallel processing is not performed to the total processing time of the case,
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing, the processing time χ _{i, j} (p) of each parallel performance impediment factor j, and other than redundant processing When a parallel performance impediment factor exists in p, the processing time X _{i, j} (p) generated by p> 1 and depending on the parallel performance impediment factor j depending on p is measured and stored in the storage unit of the parallel computer system Storing, and
The data acquisition unit of the computer having a data acquisition unit, an auxiliary index calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device causes the processing time γ of the parallel calculation part from the storage unit of the parallel computer system. _i (p), the processing time χ _{i, j} (p) of each parallel performance impediment factor j and the processing time X _{i, j} (p) when there are parallel performance impediment factors other than the redundant processing. Obtaining and storing in the log data storage unit;
A first processing time corresponding to the total processing time of the parallel performance impeding portion of the processing when the processing is performed by one processor using the data stored in the log data storage unit by the auxiliary index calculation unit calculating ρ and storing it in the storage device;
Using the data stored in the log data storage unit by the auxiliary index calculation unit, the processing time γ _i (p) of the parallel calculation part of the processing performed in each processor included in the parallel computer system Calculating a second processing time α which is a sum and storing it in the storage device;
The parallel efficiency calculation unit stores the number p of processors used in the parallel computer system, the longest processing time τ (p) when parallel processing is performed by the p processors, and the storage device. , Using the first processing time ρ and the second processing time α, the parallel efficiency E _p (p) is

And calculating and storing in the storage device;
Parallel efficiency calculation method including

(Appendix 33)
The load balance contribution ratio calculating step includes:
A step of calculating a sum β of processing times of processes executed in each processor by using the data stored in the log data storage unit by the load balance contribution rate calculation unit, and storing the sum β in the storage device;
Using the data stored in the storage device and the log data storage unit by the load balance contribution rate calculation unit, the load balance contribution rate Rb (p) is calculated as the processing time of processing performed in each processor. Dividing the sum β by the longest processing time τ (p) when processing is performed by the p processors and the number p of processors used in the parallel computer system;
32. The parallel efficiency calculation method according to any one of appendices 28 to 31, including:

(Appendix 34)
The virtual parallelization rate calculation step includes:
The virtual parallelization rate calculation unit calculates the sum of the processing times γ _i (p) of the parallel calculation part using the data stored in the log data storage unit, and stores it in the storage device;
By the virtual parallelization rate calculation unit, the virtual parallelization rate is calculated using the data stored in the log data storage unit and the storage device, and the sum of the processing times γ _i (p) of the parallel calculation part is obtained, Calculating by dividing by a third processing time τ (1) corresponding to the processing time when the same processing is performed by one processor;
32. A parallel efficiency calculation method according to appendix 28 or 31.

(Appendix 35)
The parallel performance impediment factor contribution rate calculating step includes:
The parallel performance impediment factor contribution rate calculation unit calculates the sum of the processing times χ _{i, j} (p) of a specific parallel performance impediment factor part j and the processing time β of the processing performed in each processor. Storing in the storage device;
Using the data stored in the log data storage unit and the storage device, the parallel performance inhibition factor contribution rate calculation unit calculates the parallel performance inhibition factor contribution rate Rj (p) for the specific parallel performance inhibition factor, Calculating by dividing the sum of the processing times χ _{i, j} (p) of the specific parallel performance impediment factor part j by the sum of processing times β of the processing performed in each of the processors;
The parallel efficiency calculation method according to any one of appendices 28 to 30, including:

(Appendix 36)
In the acceleration rate calculating step,
Using the data stored in the log data storage unit by the acceleration rate calculation unit, calculating the sum of the processing times γ _i (p) of the parallel calculation part, and storing in the storage device;
By the acceleration rate calculation unit, by using the data stored in the log data storage unit and the storage device, the acceleration rate A _p, the parallel calculation portion gamma _i processing time (p) γ _i (p) Is calculated as a reciprocal of the value obtained by subtracting 1 from the virtual parallelization rate calculated by dividing the sum of the two by the third processing time τ (1) corresponding to the processing time when the same processing is performed by one processor. Steps,
The parallel efficiency calculation method according to appendix 29, including:

(Appendix 37)
Wherein when the parallel performance impediment factor is only redundant processing, using said data stored in the log data storage unit, the parallel disincentive processing time R specified from the processing time of the redundant processing R _i The supplementary note 34 or further comprising the step of calculating a processing time τ (1) corresponding to the third processing time based on the sum of the processing times γ _i (p) of the parallel computing portion and storing it in the storage device 36. The parallel efficiency calculation method according to 36.

(Appendix 38)
If the parallel performance impediment factor exists in addition to the redundant processing, the processing time X _{i, j} (p) due to the parallel performance impediment factor j that occurs at p> 1 and depends on p is calculated in the parallel computer system. Measuring and storing in the storage unit of the parallel computer system;
Acquiring the processing time X _{i, j} (p) from the storage unit of the parallel computer system by the data acquisition unit and storing it in the log data storage unit;
Parallel performance specified based on a time obtained by subtracting the processing time X _{i, j} (p) due to the parallel performance impediment factor j from the processing time χ _{i, j} (p) of the parallel performance impediment factor j other than redundant processing The sum of all the parallel performance impediment factors of the processing time χ _{1, j} of the inhibition factor j at p = 1 and the sum of the processing times γ _i (p) of the parallel computation portion is Calculating a processing time τ (1) and storing it in the storage device;
37. The parallel efficiency calculation method according to appendix 34 or 36, further including:

(Appendix 39)
The parallel efficiency calculation method according to any one of claims 28 to 38, wherein the processing time is represented by a confirmation count of a corresponding event.

(Appendix 40)
The first process time ρ or the parallel disincentive processing time R is a sum value obtained by dividing the number of processors in the processing time of the redundant processing R _i (p), the processing time of the redundant processing R _i of (p) The maximum value, the minimum value of the processing time R _i (p) of the redundant processing, the processing time γ _i (p) of the parallel computing portion of the processing executed in each processor included in the parallel computer system, and the parallel performance impediment factor 38. The parallel efficiency calculation method according to appendix 32 or 37, wherein the processing time is a value of the processing time of the redundant processing in the processor having the maximum total processing time.

(Appendix 41)
The processing time χ _{1, j} when the first processing time ρ or the parallel performance impediment factor j is p = 1 is parallel performance other than redundant processing among the processing executed in each processor included in the parallel computer system. The fourth processing time is obtained by subtracting the processing time X _{i, j} (p) due to the parallelization inhibition factor j that occurs at p> 1 and depends on p from the processing time χ _{i, j} (p) due to the inhibition factor j. A value obtained by dividing the value added for the processor by the number of processors, the maximum value of the fourth processing time in all processors, or the minimum value of the fourth processing time in all processors. 39. The parallel efficiency calculation method according to attachment 32 or 38.

It is a figure showing the state by which the load balance is maintained between processors. It is a figure which shows the example of classification | category of the processing time in each processor. It is a figure showing the state (when assigning four processors and processing with one of the processors among them) where the load balance is not maintained between processors. It is a figure which shows an example of modeling of the relationship between (gamma) ₁ and (gamma) _i (p). It is a figure showing the state which has dispersion | variation in CPU performance and is performing data parallel processing. (A) is a figure showing the processing time in the case of processing by one processor, (b) is a figure showing the processing time in the case of processing by four processors. (A) is a diagram showing the processing time when the time of the parallel processing unit γ and the communication unit χ _C is considered, and (b) is a diagram showing the processing time when the rise time χ _TC is further taken into consideration. is there. It is a figure for showing the change of the parallel performance evaluation index at the time of adding a parallel performance impediment factor. It is a figure showing the example in case the load balance is maintained between processors, but the load balance of each processing time is not maintained. It is a figure showing the processing time in the case of processing by one processor. It is a figure which shows the example in case the load balance is not maintained between processors. It is a figure for showing the existence of the parallel performance impediment factor which becomes apparent when highly parallelized. It is a figure showing the example of calculation of a parallel performance evaluation index. It is a figure showing the relationship between the sum total of working time and processing time. It is a figure showing the relationship between working time, processing time, and processing time which considered parallel efficiency. It is a figure showing the example of the processing time at the time of implementing data parallel with a distributed memory parallel computer system. It is a figure for comparing the parallel performance evaluation index based on the original CPU performance and the estimated parallel performance evaluation index when the CPU performance is replaced with a system of 5 times. It is a figure showing the data for trial calculation when it replaces | exchanges for the system of CPU performance 5 times. It is a functional block diagram concerning one embodiment of the present invention. It is a conceptual diagram showing confirmation and count of event occurrence by sampling. It is a figure showing the example of a sampling result at the time of the program execution of Table 1. It is a figure showing an example of the processing flow of a parallel performance analyzer. It is a figure showing the example of a measurement result of processing time by time measurement. It is a figure showing the example of a measurement result of processing time by sampling. It is a figure showing an example of the 1st part of the processing flow of a processor number optimization process. It is a figure showing an example of the 2nd part of the processing flow of a processor number optimization process. It is a figure showing an example of the processing flow of a processor expansion estimation process. It is a figure showing an example of the processing flow of a system replacement data process. It is a figure for expressing the performance guideline about communication when CPU performance is 5 times and target parallel efficiency is 0.6. It is a figure which shows an example of the processing flow for a system operation efficiency improvement process. It is a figure which shows an example of the processing flow of a tuning process. It is a figure showing the change of the parallel performance evaluation parameter | index before implementing tuning after the tuning before and 1st time. It is a figure showing the processing time by the parallel processing program based on the algorithm which is not suitable for parallel processing. It is a figure showing the processing time by the parallel processing program based on the algorithm suitable for parallel processing. It is a figure for the comparison etc. of the parallel performance parameter | index of the algorithm which is not suitable for parallel processing, and the algorithm which is suitable for parallel processing. It is a figure showing the processing flow of an algorithm selection process. It is a figure which shows an example of the log data of a certain parallel processing system. It is a figure showing the measurement result of processing time in Example 1. FIG. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 1. FIG. It is a figure showing the measurement result of the processing time in Example 2. FIG. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 2. FIG. It is a figure showing the measurement result of the processing time in Example 3. FIG. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 3. FIG. It is a figure showing the measurement result of the processing time in Example 4. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 4. FIG. It is a figure showing the measurement result of processing time in Example 5. FIG. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 5. FIG. It is a figure showing the measurement result of the processing time in Example 6 (data parallel using redundant processing). It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 6 (data parallel using a redundant process). It is a figure showing the measurement result of the processing time in Example 6 (data parallel which processes the part which cannot be processed in parallel with a specific processor). It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 6 (data parallel which processes the part which cannot be processed in parallel with a specific processor). It is a figure showing the measurement result of the processing time in Example 7. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 7. It is a figure showing the measurement result of the processing time in Example 8. FIG. 20 is a diagram illustrating a calculation result of a parallel performance evaluation index in Example 8. It is a figure showing the measurement result of the processing time in Example 9. FIG. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 9. It is a figure showing the measurement result of processing time in Example 10. FIG. It is a figure showing the calculation result of the parallel performance evaluation parameter | index in Example 10. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Data acquisition part 11 Load balance contribution rate calculation part 12 Virtual parallelization rate calculation part 13 Parallel performance impediment factor contribution rate calculation part 14 Parallel efficiency calculation part 15 Auxiliary index calculation part 21 Processor number optimization process part 22 Processor expansion estimation process part 23 System Replace Data Processing Unit
24 Operation efficiency data processing unit 25 Tuning processing unit 26 Algorithm selection processing unit 27 Parallel performance evaluation processing unit 30 Log data storage unit
DESCRIPTION OF SYMBOLS 100 Parallel performance analyzer 110 Output device 200 Parallel computer system 201 Measuring part

Claims (10)

A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the total processing when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to the processing times τ _i (p) of the p processors. The ratio of processing time to the time when parallel processing is not performed,
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
By the data acquisition unit of the computer having a data acquisition unit, a load balance contribution rate calculation unit, a virtual parallelization rate calculation unit, a parallel performance impediment factor contribution rate calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device, From the storage unit of the parallel computer system, the processing time γ _i (p) of the parallel calculation part and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are obtained and stored in the log data storage unit Storing, and
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
A virtual representing a ratio of time of a part calculated in parallel by each processor in processing executed in the parallel computer system by using the data stored in the log data storage unit by the virtual parallelization rate calculation unit A virtual parallelization rate calculating step of calculating a parallelization rate Rp (p) and storing it in the storage device;
Using the data stored in the log data storage unit by the parallel performance inhibition factor contribution rate calculation unit, the processing time χ of each parallel performance inhibition factor part j relative to the total processing time of all processors included in the parallel computer system calculating a parallel performance impediment factor contribution ratio Rj (p) representing a ratio of _{i, j} (p) and storing it in the storage device;
Using the load balance contribution rate Rb (p), the virtual parallelization rate Rp (p), and the parallel performance impediment factor contribution rate Rj (p) stored in the storage device by the parallel efficiency calculation unit. , Parallel efficiency E _p (p)

And calculating and storing in the storage device;
Parallel efficiency calculation method including A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the parallel processing with respect to the total processing time when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to each processing time of the p processors. Is the ratio of the processing time when not performing
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
The data acquisition unit of the computer having a data acquisition unit, a load balance contribution rate calculation unit, an auxiliary index calculation unit, a parallel performance impediment factor contribution rate calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device allows the parallel The processing time γ _i (p) of the parallel computing portion and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are acquired from the storage unit of the computer system and stored in the log data storage unit Steps,
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
The auxiliary index calculation unit uses the data stored in the log data storage unit, and uses the data stored in the log data storage unit to express the acceleration rate A _p (p ) And calculating an acceleration rate to be stored in the storage device,
Using the data stored in the log data storage unit by the parallel performance inhibition factor contribution rate calculation unit, the processing time χ of each parallel performance inhibition factor part j relative to the total processing time of all processors included in the parallel computer system calculating a parallel performance impediment factor contribution ratio Rj (p) representing a ratio of _{i, j} (p) and storing it in the storage device;
Using the load balance contribution rate Rb (p), the acceleration rate A _p (p), and the parallel performance impediment factor contribution rate Rj (p) stored in the storage device by the parallel efficiency calculation unit, Parallel efficiency E _p (p)

And calculating and storing in the storage device;
Parallel efficiency calculation method including A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the total processing when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to the processing times τ _i (p) of the p processors. The ratio of processing time to the time when parallel processing is not performed,
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
The data acquisition unit of the computer having a data acquisition unit, a load balance contribution rate calculation unit, a parallel performance impediment factor contribution rate calculation unit, a parallel efficiency calculation unit, a log data storage unit, and a storage device allows the storage of the parallel computer system Obtaining the processing time γ _i (p) of the parallel computing portion and the processing time χ _{i, j} (p) of each parallel performance impediment factor j from the unit, and storing the log data in the log data storage unit;
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
Using the data stored in the log data storage unit by the parallel performance inhibition factor contribution rate calculation unit, the processing time χ of each parallel performance inhibition factor part j relative to the total processing time of all processors included in the parallel computer system calculating a parallel performance impediment factor contribution ratio Rj (p) representing a ratio of _{i, j} (p) and storing it in the storage device;
The parallel efficiency calculation unit calculates the parallel efficiency E _p (p) using the load balance contribution rate Rb (p) and the parallel performance impediment factor contribution rate Rj (p) stored in the storage device.

And calculating and storing in the storage device;
Parallel efficiency calculation method including A parallel efficiency calculation method for calculating a parallel efficiency E _p (p) of a parallel computer system,
The parallel efficiency E _p (p) is the total processing when it is assumed that the longest processing time when parallel processing is performed by p processors is equal to the processing times τ _i (p) of the p processors. The ratio of processing time to the time when parallel processing is not performed,
In the parallel computer system, the processing time γ _i (p) (i indicates the processor number) of the parallel calculation part in the processing and the processing time χ _{i, j} (p) of each parallel performance impediment factor j are measured, Storing in the storage unit of the parallel computer system;
The parallel computer system includes the data acquisition unit, the load balance contribution rate calculation unit, the virtual parallelization rate calculation unit, the parallel efficiency calculation unit, the auxiliary index calculation unit, the log data storage unit, and the storage device. Obtaining the processing time γ _i (p) of the parallel computing portion and the processing time χ _{i, j} (p) of each parallel performance impediment factor j from the storage unit of the storage unit, and storing in the log data storage unit; ,
Using the data stored in the log data storage unit, the load balance contribution rate calculation unit calculates a load balance contribution rate Rb (p) that represents the degree of load balance among the processors included in the parallel computer system. And a load balance contribution ratio calculating step for storing in the storage device,
A virtual representing a ratio of time of a part calculated in parallel by each processor in processing executed in the parallel computer system by using the data stored in the log data storage unit by the virtual parallelization rate calculation unit A virtual parallelization rate calculating step of calculating a parallelization rate Rp (p) and storing it in the storage device;
Using the data stored in the log data storage unit by the auxiliary index calculation unit, the sum of the processing times γ _i (p) of the parallel calculation part of the processes executed in each processor included in the parallel computer system an auxiliary index calculating step of calculating α and a sum β of processing times of processing performed in each of the processors, and storing in the storage device;
Using the α, β, the load balance contribution rate Rb (p), and the virtual parallelization rate Rp (p) stored in the storage device by the parallel efficiency calculation unit, a parallel efficiency E _p ( p)

And calculating and storing in the storage device;
Parallel efficiency calculation method including The load balance contribution ratio calculating step includes:
A step of calculating a sum β of processing times of processes executed in each processor by using the data stored in the log data storage unit by the load balance contribution rate calculation unit, and storing the sum β in the storage device;
Using the data stored in the storage device and the log data storage unit by the load balance contribution rate calculation unit, the load balance contribution rate Rb (p) is calculated as the processing time of processing performed in each processor. Dividing the sum β by the longest processing time τ (p) when processing is performed by the p processors and the number p of processors used in the parallel computer system;
The parallel efficiency calculation method according to claim 1, comprising: The parallel performance impediment factor contribution rate calculating step includes:
The parallel performance impediment factor contribution rate calculation unit calculates the sum of the processing times χ _{i, j} (p) of a specific parallel performance impediment factor part j and the processing time β of the processing performed in each processor. Storing in the storage device;
Using the data stored in the log data storage unit and the storage device, the parallel performance inhibition factor contribution rate calculation unit calculates the parallel performance inhibition factor contribution rate Rj (p) for the specific parallel performance inhibition factor, Calculating by dividing the sum of the processing times χ _{i, j} (p) of the specific parallel performance impediment factor part j by the sum of processing times β of the processing performed in each of the processors;
The parallel efficiency calculation method according to claim 1, comprising: The virtual parallelization rate calculation step includes:
The virtual parallelization rate calculation unit calculates the sum of the processing times γ _i (p) of the parallel calculation part using the data stored in the log data storage unit, and stores it in the storage device;
By the virtual parallelization rate calculation unit, the virtual parallelization rate is calculated using the data stored in the log data storage unit and the storage device, and the sum of the processing times γ _i (p) of the parallel calculation part is obtained, Calculating by dividing by a third processing time τ (1) corresponding to the processing time when the same processing is performed by one processor;
Including
Wherein when the parallel performance impediment factor is only redundant processing, using said data stored in the log data storage unit, the parallel disincentive processing time R specified from the processing time of the redundant processing R _i The processing time τ (1) corresponding to the third processing time is calculated based on the sum of the processing time γ _i (p) of the parallel calculation portion and further stored in the storage device. 4. The parallel efficiency calculation method according to 4. The virtual parallelization rate calculation step includes:
The virtual parallelization rate calculation unit calculates the sum of the processing times γ _i (p) of the parallel calculation part using the data stored in the log data storage unit, and stores it in the storage device;
By the virtual parallelization rate calculation unit, the virtual parallelization rate is calculated using the data stored in the log data storage unit and the storage device, and the sum of the processing times γ _i (p) of the parallel calculation part is obtained, Calculating by dividing by a third processing time τ (1) corresponding to the processing time when the same processing is performed by one processor;
Including
If the parallel performance impediment factor exists in addition to the redundant processing, the processing time X _{i, j} (p) due to the parallel performance impediment factor j that occurs at p> 1 and depends on p is calculated in the parallel computer system. Measuring and storing in the storage unit of the parallel computer system;
Acquiring the processing time X _{i, j} (p) from the storage unit of the parallel computer system by the data acquisition unit and storing it in the log data storage unit;
Parallel performance specified based on a time obtained by subtracting the processing time X _{i, j} (p) due to the parallel performance impediment factor j from the processing time χ _{i, j} (p) of the parallel performance impediment factor j other than redundant processing The sum of all the parallel performance impediment factors of the processing time χ _{1, j} of the inhibition factor j at p = 1 and the sum of the processing times γ _i (p) of the parallel computation portion is Calculating a processing time τ (1) and storing it in the storage device;
The parallel efficiency calculation method according to claim 1 or 4, further comprising: The parallel impediments processing time R is the sum divided by the number of processors of the redundant processing of the processing time R _i (p), the maximum value of the redundant processing of the processing time R _i (p), the processing of the redundant processing The minimum value of the time R _i (p), the sum of the processing time γ _i (p) of the parallel computing portion and the processing time of the parallel performance impeding factor among the processing executed in each processor included in the parallel computer system is maximum The parallel efficiency calculation method according to claim 7, wherein the processing time is a value of a processing time of redundant processing in the processor. The processing time χ _{1, j} at the time p = 1 of the parallel performance impediment factor j is the processing time χ _i due to the parallel performance impediment factor j other than the redundant processing among the processing executed in each processor included in the parallel computer system. _{, j} (p), the number of processors is obtained by adding the fourth processing time generated by p> 1 and subtracting the processing time X _{i, j} (p) due to the parallelization inhibiting factor j depending on p for all processors. 9. The parallel efficiency calculation according to claim 8, wherein the value is any one of a value divided by a value, a maximum value of the fourth processing time in all processors, and a minimum value of the fourth processing time in all processors. Method.

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