JP3812405B2 - Disk array system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk array system having a plurality of disk volumes, and more particularly to a disk array system having a function of dividing and assigning input / output performance provided by a disk array system to a host computer for each disk volume.
[0002]
[Prior art]
In recent years, there has been a remarkable increase in performance and capacity of storage devices in computer systems. Among them, the disk array system called Redundant Array of Inexpensive Disks (RAID) realizes high performance and large capacity by operating multiple disks in parallel, and high redundancy by having redundant information such as data parity. Reliability is achieved. In the disk array, there are a CPU that interprets an I / O processing request received from a host computer and instructs disk access and data transfer, and a bus serving as a data transfer path. Data transfer using DMA (Direct Memory Access) allows CPU processing and data transfer to be executed at the same time, thereby increasing the utilization efficiency of hardware resources.
[0003]
With the spread of such high-performance, large-capacity disk array systems, each host computer creates multiple logical disk volumes on a single disk array instead of having independent storage devices. Assigning to a host computer has become common.
[0004]
When one disk array is shared by a plurality of host computers, the capacity allocated to each host computer is determined by the capacity of the logical volume to be created. In addition, for example, by the method disclosed in Japanese Patent Application Laid-Open No. 2001-147886, each host computer shares a disk array in a time-sharing manner, assigns a collective use time to each computer, and designates the time ratio, It is also possible to assign performance.
[0005]
[Problems to be solved by the invention]
In general, in a disk array, if the I / O processing issued by the host computer is random access, a large number of I / O requests are processed in a short time, so the overhead of command transmission / reception is large and the CPU is heavily loaded. . On the other hand, in sequential access, one I / O process requires a large data transfer, so the data transfer time per request is long and a heavy load is applied to the bus. That is, the performance is determined by the processing time in the CPU for random access, and the bus transfer time for sequential access. In the above-described performance allocation method in which usage time is allocated to each host computer, I / O from other computers is not processed while a certain computer is using the disk array. Thus, for example, when computer A requesting random access and computer B requesting sequential access share a disk array, random access and sequential access are executed exclusively, and A uses the disk array. The time when the bus usage is low and the time when B is using the disk array is lower than the CPU usage efficiency, compared to the case where sequential access data transfer and random access CPU processing are executed simultaneously. Resource utilization efficiency decreases, and the performance of the disk array is limited.
[0006]
The object of the present invention is to divide the entire I / O access processing performance provided by the disk array and assign the performance to the disk volume used by each host computer. It is to provide a disk array device having a function of enhancing.
[0007]
[Means for Solving the Problems]
In the present invention, the usage time of the CPU and data transfer path (bus) is independently assigned to each disk volume. That is, a lot of CPU time can be allocated to a volume with many random accesses, and a long usage time can be allocated to a volume with many sequential accesses. Inside the disk array, the CPU and data transfer path (bus) usage time is always measured for each disk volume, and the processing volume is limited so that the usage time ratio specified for each disk volume is not exceeded. Make an assignment. I / O processing requests issued from multiple host computers are queued in the disk array. For example, when data transfer or disk access is being executed for a certain process, another process is processed by the CPU. By doing so, a plurality of processes can be executed in parallel. As a result, high resource utilization efficiency can be maintained for both random access and sequential access while performing performance allocation control.
[0008]
In addition, by selecting an allocation criterion such as a disk volume to be performance-allocated, CPU time, bus usage time, cache memory capacity to be used, etc., flexible performance management can be performed based on access characteristics to the disk volume.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The first embodiment is an example in which performance allocation is performed by specifying a ratio of CPU to be used and bus time for each disk volume of a disk array.
(1) Overall system configuration
FIG. 1 shows the overall configuration of this embodiment.
[0010]
Two host computers 100 and 101 are connected to the fiber channel interfaces 111 and 112 of the disk array 110 via the fiber channel cables 103 and 104, and read / write data stored in the disk volumes in the disk array. The management console 102 executes a disk array management program and instructs the disk array to start and end the performance allocation process. The management console is connected to the LAN interface 113 of the disk array via a LAN (Local Area Network) cable 105, and instructs the disk array of performance to be allocated to each disk volume.
[0011]
The disk array 110 includes a CPU 120 that controls the overall operation, a timer 121 that is used to measure the CPU usage time of each volume, a memory 122, disk drives 130, 131, and 132 that serve as data recording media, and access to the disk drives. And a transfer time measuring device 123 that measures the communication time between the memory and disk controller and the fiber channel interface.
[0012]
The memory 122 records a performance management table 125, which is management information necessary for performance allocation control, cache data 126 of data recorded in the disk drive, and other management information 127 necessary for general disk array operation. The management information 127 has, for each LU, a ready queue for tasks that wait for CPU free and a wait queue for tasks that are executing processing that does not require the CPU, such as during disk access. An access request issued from the host computer to each LU enters the Ready queue first, and is processed by the CPU when it comes to the head of the queue. In the case of performing disk access or DMA transfer processing, it is placed in the Wait queue. The end of the disk access or transfer process is notified by an interrupt, and the corresponding process enters the Read queue again. Which queue the CPU selects a task from among the queues for each LU is determined by, for example, a round robin method.
[0013]
The timer 121 provides the current time with a high accuracy of about 10 ns, for example, and has a timer interrupt function for interrupting the CPU when a specified time elapses. The transfer time measuring device is connected to a fiber channel interface, CPU, memory, and disk controller, and an existing bus such as a PCI bus can be used for these transfer paths. Each storage area of the disk drives 130, 131, 132 forms a disk volume singly or in plurality. The disk volume can be used as an LU (Logical Unit) defined by, for example, a SCSI (Small Computer System Interface) standard. Here, for simplicity, it is assumed that the disk drives 130, 131, and 132 have LUs 140, 141, and 142, respectively, and the LUs have LU numbers 1, 2, and 3, respectively.
(2) Configuration of transfer time measuring device
Details of the transfer time measuring device 123 are shown in FIG. The LU information addition / deletion means 200 adds information such as the LU number to the data of each LU flowing from the fiber channel interfaces 111 and 112. For example, when the Fiber Channel interface receives a data storage request from a host computer to a certain LU, the request is notified to the CPU, the CPU sets information to be added to the LU information addition / deletion means, and then the Fiber Channel interface transfers it. By sending data to the time measuring device 123, appropriate LU information can be added. All LU data recorded in the memory or disk drive is transferred and recorded together with the LU information. Details of the LU information addition / deletion means are disclosed in, for example, Japanese Patent Laid-Open No. 2000-347815.
[0014]
The transfer time measuring device has a DMA 204 and performs data transfer processing in parallel with CPU processing. When the CPU instructs the DMA 204 to transfer the data of each LU, the LU information of the data to be transferred to a predetermined area in the memory is always prepared, and the LU discriminating means 201 refers to the LU number included in the information As a result, it is determined which LU the data to be transferred is. When the transfer is completed, the LU discriminating unit 201 invalidates the LU information on the memory. When transferring data other than LU data, for example, when notifying the reception of an I / O request from the Fiber Channel interface to the CPU, the CPU does not set valid LU information in the memory. Can be determined. The transfer time measuring means 202 always monitors the data transfer start signals of the buses 114 and 115 and measures the time from the transfer start signal detection to the transfer end. This is realized, for example, by referring to a count of the number of clocks of the bus or a timer in the disk array. The measured time is recorded in the transfer time recording table 203 according to the LU number determined by the LU determination means 201.
[0015]
As shown in FIG. 3, the transfer time recording table 203 records the transfer time for each LU. The transfer time measuring means 202 adds the measured time to the column corresponding to the LU number of the transfer time 302. If the measured data transfer is other than LU data, it is added to the column corresponding to “other than data”.
(3) Configuration of performance management table
Details of the performance management table 125 recorded on the memory 122 are shown in FIG.
[0016]
The performance management table records management data and performance allocation designation data corresponding to each LU and the whole. The processing number upper limit 402 column represents the upper limit of the processing number allocated to each LU within a unit time specified in advance. The number of processes referred to here is the number of times the CPU has taken out and processed from the Ready queue of each LU in the management information 127. The number of processes 403 is the number of processes for each LU up to now. The allocation ratio (CPU) 404 and the allocation ratio (bus) 405 record a ratio indicating how much CPU usage time and bus usage time are allocated to each LU, respectively. The measurement result (CPU usage time) 406 and the measurement result (bus time) 407 record the measurement results of the CPU time and bus time used by each LU within the unit time. The total number of processes, not the individual LUs, does not record the maximum number of processes 402, number of processes 403, allocation ratio (CPU) 404, allocation ratio (bus) 405, and CPU usage time measurement result 406, but the number of processes and CPU usage The time can be calculated by summing the values recorded in each LU. The bus use time measurement result 407 for the whole records a value obtained by removing the transfer time unrelated to the LU data from the measured time.
(4) Explanation of overall operation
When performance allocation is not performed, I / O requests issued from the host computer to the disk array are loaded into the Ready queue for each LU as tasks to be processed in the disk array, and are sequentially processed from the head of the queue. There is no limit to task processing other than selecting a queue from which a task is to be retrieved in a round robin manner. On the other hand, a case where performance allocation is performed will be described with reference to the flowchart of FIG. First, the system administrator designates the ratio of CPU time and bus time allocated to each LU from the management console 102. The specified value is transmitted to the disk array via the LAN 105 and recorded in the fields of the allocation ratios 404 and 405 of the performance management table 125. For example, FIG. 4 shows a state in which 20% of the total CPU time and 70% of the bus time are assigned to LU1. Also, the upper limit of the number of processes is designated as 0 (step 501). The upper limit 0 represents a state where no upper limit is set.
[0017]
Next, the recording of each transfer time in the transfer time recording table 203 in the transfer time measuring device 123 is initialized to 0 (step 502). Further, the measurement result of the performance management table is initialized to 0 (step 503), and the unit time for allocation control management is set to the timer 121 (step 504). This unit time may be a fixed value determined in advance or may be specified from the management console. For example, if 1 second is specified as the unit time, a timer interrupt is notified from the timer to the CPU after 1 second. Until the timer interrupt is received, the CPU and transfer time measuring device process the task and measure the usage time of the CPU and bus for each LU (step 505). When the timer interrupt is received, the transfer time of each LU recorded in the transfer time record table 203 is recorded in the corresponding measurement result 407 in the performance management table. Further, the total transfer time other than each LU and data is recorded in the entire column of the measurement result 407 (step 506). Next, it is determined whether or not the management console has instructed to end the performance allocation control during processing (step 507) .If there is an end instruction, the performance allocation control is ended and the normal operation is resumed (step 507). 509). If an end instruction has not been received, the processing number upper limit 402 of each LU in the performance management table is corrected (step 508), and the process returns to step 502.
(5) Task processing and resource usage time measurement
The operation during task processing in step 505 will be described with reference to the flowcharts of FIGS.
[0018]
FIG. 6 shows the operation of the CPU at step 505. In order to process each LU by the round robin method, a variable n representing the LU number to be processed is initialized to 1 (step 601). If the ready queue of LU n is empty, the process proceeds to step 608 (step 602). If it is not empty, refer to the upper limit (402) of the processing number of LU n in the performance management table and the current processing number (403), and if the upper limit is non-zero and the processing number has reached the upper limit, the process proceeds to step 608 ( Step 603). Otherwise, the current time is acquired from the timer (step 604), and one task is processed from the ready queue (step 605). When the task is completed, the task is deleted. When processing other than the CPU is performed, the task is loaded in the wait queue. When the task processing is completed, the current time is acquired again from the timer, and the elapsed time from the time acquired in step 604 is added to the measurement result (CPU usage time) 406 of the performance management table (step 606). Add to the entire column as well as the column corresponding to LU n. Further, 1 is added to the processing number 403 (step 607). When the above processing is completed, 1 is added to n to process the next LU. If n exceeds the number of LUs, n is initialized to 1 again (step 609), and the processing returns to step 603. With this series of processing, the tasks of each LU can be processed without exceeding the upper limit of the number of processes recorded in the performance management table, and the CPU time used at that time can be measured.
[0019]
FIG. 10 shows the operation of the LU discriminating means 201 and the transfer time measuring means 202 when data and control information are transferred via the transfer time measuring device in step 505. When the DMA 204 or the fiber channel interface in the transfer time measuring device transfers data or control information via the bus 114 or 115, a transfer start signal defined by the bus protocol flows prior to actual data transfer. When the transfer time measuring means detects this signal, the transfer time measurement is started (step 1000). The signal on the bus can be easily detected by constantly monitoring the signal line through which the signal flows. Next, the LU discriminating unit 201 confirms whether valid LU information exists in a predetermined area on the memory (step 1001). If LU information does not exist, it is determined that data other than LU data is being transferred, and the process proceeds to step 1005. If the LU data is being transferred, the LU number is acquired from the LU information (step 1002). Next, the time until the end of transfer is measured (steps 1003 and 1005), and the measurement result is recorded in the transfer time recording table 203. If it is LU data transfer, the measurement result is added to the column corresponding to the LU number of the transfer time 302 (step 1004). If it is not LU data, the measurement result is added to the column corresponding to others (step 1006). With these processes, it is possible to measure the time during which the bus is used for each LU and other data transfer within a unit time.
(6) Calculation of the maximum number of processes
In step 508, the upper limit of the number of processes in the next unit time is calculated based on the CPU and bus usage time of each LU measured within the unit time. Details of the calculation method will be described with reference to FIG.
[0020]
In order to calculate each LU individually, a variable n indicating the number of the LU to be calculated is initialized to 1 (step 701). In the performance management table 125, the processing number 403 of LU n is referred. If the processing number is 0, there is no measurement data for calculating a new upper limit, so the current upper limit is used as it is, and the process proceeds to step 710 (step 702 ). If the number of processes is non-zero, the average CPU usage rate and bus usage rate per process are calculated (step 703). The CPU usage rate is the value obtained by dividing the CPU usage time for the unit time (measured time) by the number of processes, and the bus usage rate is the bus usage time for the time excluding the time for transferring data other than LU data from the unit time. Is divided by the number of processes. Next, the number of processes (integer) that does not exceed the allocation ratios 404 and 405 is calculated based on the usage rate per process (step 704). These values are calculated by dividing the designated allocation ratio by the usage rate per process calculated in step 703. Compare the number of processes calculated based on the CPU usage rate and the number of processes calculated based on the bus usage rate, and record the smaller one as the upper limit of the new processing number in the column of the upper limit of processing number 402 in the performance management table (step 705-707). If this upper limit is 0 (step 708), processing for that LU is not performed at all, so the upper limit is corrected to 1 (step 709). With these series of processes, it is possible to calculate the upper limit of the number of processes appropriate for the allocation ratio designated from the previous measurement result for LU n. This is repeated for all LUs (steps 710 and 711).
[0021]
In the example of LU1 in FIG. 4, the number of processes is 20, the measurement result of CPU usage time is 40ms, and the bus usage time is 500ms. Therefore, if the measurement time is 1 second, the upper limit of the number of processes based on the CPU usage time Is 20% / (40ms * 100% / (1000ms * 20)) = 100, and the upper limit of the number of processes based on the bus usage time is 70% / (500ms * 100% / (995ms * 20)) = 27.86, The new processing limit is 27.
[0022]
Since the usage time of each LU of the CPU or bus is directly measured, highly accurate assignment processing is possible, especially when the transfer length and random sequential characteristics of access from the host computer to each LU are constant. It becomes. Even when the access characteristic changes, it is possible to automatically adjust the upper limit of the number of processing of each LU following the change of the characteristic.
(7) Effect
By assigning the CPU and bus usage time ratios independently, it is possible to assign performance suitable for the access characteristics of each LU. That is, a lot of CPU time can be allocated to an LU with many random accesses, and a much longer usage time can be allocated to an LU with many sequential accesses. In addition, since access to each LU can be executed in parallel within the disk array regardless of random or sequential, high usage efficiency of the CPU and bus can be maintained even when performance allocation control is performed. Furthermore, since the upper limit of the number of tasks to be used as an index value for allocation control is recalculated at regular intervals, allocation control can be performed in accordance with temporal variations in access characteristics. In this embodiment, the transfer time of the buses 114 and 115 is measured by the transfer time measuring device, and the usage time allocation control is performed, but the same applies to the transfer path 127 to the memory, the transfer path to the disk controller, and the like. The usage time allocation can be controlled based on the above principle.
[0023]
In the second embodiment, in addition to the CPU usage time and the bus usage time, a cache capacity allocation ratio is added as a performance allocation criterion, and an arbitrary criterion is selected. Only the parts different from the first embodiment will be described below.
(1) Configuration of the performance management table
The configuration of the performance management table in the present embodiment is shown in FIG. The cache allocation column 809 in the table records the capacity ratio of the cache memory allocated to each LU. This ratio is the ratio of the capacity that can be used in each LU to the total capacity of the cache data area 126 allocated in the memory 122. The used cache capacity column 810 records the ratio of the cache memory currently used by each LU. In the entire column, the memory capacity that the disk array can use as a cache is recorded. In the present embodiment, the performance management table record 810 is updated whenever there is a change in the used cache capacity when the CPU processes a task. In other words, regardless of whether performance allocation control is being executed or not, if a new cache capacity is allocated or a cache capacity that has already been allocated is released by processing of a certain LU, the performance management table of the corresponding LU Correct the record. The assignment attribute column 802 indicates which assignment criterion each LU uses. In the example of FIG. 8, LU2 assigns performance based on CPU usage time, and LU3 assigns performance based on bus usage time and also limits the available cache capacity. LU1 allows unlimited access because no assignment criteria are specified.
(2) Explanation of operation
In the flowchart of FIG. 5, in step 501, a process of recording which allocation attribute is applied to each LU received from the management console in the allocation attribute column 802 of the performance management table is added. In step 605 of FIG. 6, when a new cache capacity is secured for a certain LU, as shown in the flowchart of FIG. 11, the allocation attribute 802 of the performance management table is first referred to and the performance allocation of the LU is It is confirmed whether the cache capacity is set in the attribute (step 1101). If the attribute is not set, the cache is secured (step 1104), but if it is set, it is determined whether or not the capacity ratio specified by the cache allocation ratio 809 is exceeded by newly securing the cache (step 1102). ). If it exceeds, among the cache capacities already secured, the same capacity as the newly secured cache is released in advance (step 1103). Thereafter, by securing the cache, the specified cache allocation capacity ratio can be maintained. Also, as described above, when there is a change in the used cache capacity, the cache capacity record 810 of the performance management table is corrected.
[0024]
In the flowchart of FIG. 7, in step 702, in addition to the case where the number of processes is 0, the allocation attribute column 802 of the performance management table is referenced, and no allocation attribute is set or only the cache attribute is set. Also in this case, change is made to proceed to step 710. In steps 703 and 704, the usage rate and the number of processes are calculated only for the set allocation attribute. In step 705, if the bus use time is not set in the assignment attribute, the process proceeds to step 706. If the CPU use time is not set, the process proceeds to step 707. If both the CPU usage time and the bus usage time are set in the assignment attribute, the smaller processing number is set as a new upper limit, as in step 705 of FIG.
(3) Effect
According to this embodiment, the cache capacity used for each LU can be limited. As a result, a small cache capacity is allocated in advance to LUs with many accesses that can hardly be expected, such as sequential access to extremely large data, and a large number of caches are allocated to other LUs to improve the cache hit rate. Can be made. In addition, by setting one or more combinations of CPU usage time, bus usage time, and cache capacity as performance allocation criteria, or setting nothing, flexible performance management becomes possible. For example, for an LU that is known to issue only a random access with a small transfer length, the management can be simplified by omitting the setting ratio of the bus usage time.
[0025]
In the third embodiment, a function for reporting the current hardware resource usage rate to the management console is added to the second embodiment. Only the parts different from the first embodiment will be described below.
(1) Configuration of the performance management table
FIG. 9 shows a performance management table in this embodiment. In the accumulated CPU usage time 911 and the accumulated bus usage time 912, the total of the CPU usage time 907 and the bus usage time 908 measured for each unit time is recorded.
(2) Explanation of operation
In the flowchart of FIG. 5, processing for initializing each accumulated time in the performance management table to 0 is added to step 501. Further, in step 508, after the upper limit of the number of processes is corrected, a process of adding the CPU and bus usage time measurement results 905 and 906 to the respective accumulated times 911 and 912 is added.
[0026]
Furthermore, when a usage status report instruction is received from the management console 102 via the LAN 105, the used cache capacity 910, accumulated CPU usage time 911, and accumulated bus usage time 912 for each LU in the performance management table 900 are transmitted to the management console. To do. In addition, the accumulated CPU usage time and the accumulated bus usage time are initialized to 0 after transmission.
(3) Effect
By referencing the usage status periodically from the management console, it is possible to check whether the current performance allocation setting is appropriate. In addition, by accumulating the acquired time series data of the usage status in the management console, it recognizes the time zone when the load of each LU is peaked, and can be used for system performance tuning or for prediction of future performance demand. Can be. In this embodiment, usage data is transmitted to the management console via the LAN, but it is also possible to transfer the data from the fiber channel interface to the host computer.
[0027]
【The invention's effect】
As described above, according to the present invention, CPU usage time, bus usage time, and usage cache capacity can be independently assigned to each disk volume in the disk array. As a result, it is possible to perform performance allocation management that is flexible and has high use efficiency of hardware resources in accordance with the access characteristics to the disk volume.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.
FIG. 2 shows a configuration of a transfer time measuring device according to the embodiment of the present invention.
FIG. 3 is a configuration of a transfer time recording table in the embodiment of the present invention.
FIG. 4 is a configuration of a performance management table in the first embodiment of the present invention.
FIG. 5 is a flowchart of performance allocation processing according to the embodiment of the present invention.
FIG. 6 is a flowchart for limiting the number of processes in the first embodiment of the present invention.
FIG. 7 is a flowchart of processing number upper limit calculation according to the first embodiment of the present invention.
FIG. 8 is a configuration of a performance management table in the second embodiment of the present invention.
FIG. 9 is a configuration of a performance management table according to the third embodiment of the present invention.
FIG. 10 is a flowchart of bus usage time measurement according to the embodiment of the present invention.
FIG. 11 is a flowchart of cache securing processing according to the second embodiment of the present invention.
[Explanation of symbols]
100, 101 ... Host computer, 102 ... Management console, 110 ... Disk array, 120 ... CPU, 121 ... Timer, 122 ... Memory, 123 ... Transfer time measuring device, 124 ... Disk controller, 125 ... Performance management table, 130, 131, 132 ... a disk drive.

Claims (11)

For each disk volume, a means for measuring the CPU usage time used to access the disk volume,
Means for calculating the upper limit of the processing amount of each disk volume per unit time based on the measurement result and the ratio of the CPU usage time allocated in advance to each disk volume;
And a means for limiting the processing amount of each disk volume per unit time so as not to exceed the calculated upper limit. In claim 1,
Means for measuring, for each disk volume, at least part of the data transfer path in the disk array, the time used for access processing to the disk volume;
A disk array system comprising: means for calculating an upper limit of a processing amount of each disk volume per unit time based on the measurement result and a ratio of a transfer path usage time previously assigned to each disk volume. In claim 2,
A disk array system comprising means for receiving, via a LAN, a percentage of CPU usage time and a percentage of transfer path usage time allocated to each disk volume. In claim 3,
A disk array system comprising: means for periodically recalculating the upper limit of the processing amount of each disk volume per unit time calculated based on CPU usage time or transfer path usage time. In claim 4,
Means for adding attribute information related to the disk volume to the write data to the disk volume received from the host computer;
A disk array system comprising: means for determining a disk volume to which the data being transferred belongs based on attribute information added to the data being transferred by the bus. In claim 5,
A disk array system comprising a bus connected to a channel interface to a host computer as part of a data transfer path for which usage time is measured. In claim 4,
And a means for limiting the cache capacity allocated to each disk volume so as not to exceed a predetermined upper limit. In claim 7,
A disk array system comprising: means for selecting a disk volume to which means for limiting so as not to exceed the specified upper limit is selected. In claim 8,
For each disk volume, a means for accumulating CPU usage time and transfer path usage time per unit time over a period instructed by the management console,
A disk array system comprising: means for transmitting one or more of the accumulated usage time and the current usage cache capacity recorded for each disk volume to a management console. For each disk volume, measure the CPU usage time used to access the disk volume,
Based on the measurement result and the percentage of CPU usage time allocated in advance to each disk volume, calculate the upper limit of the processing amount of each disk volume per unit time,
A disk array performance allocation method, characterized in that a processing amount of each disk volume per unit time is limited so as not to exceed the calculated upper limit. In claim 10,
For at least a part of the data transfer path in the disk array, for each disk volume, measure the time used to access the disk volume,
A disk array performance allocation method, comprising: calculating an upper limit of a processing amount of each disk volume per unit time based on the measurement result and a ratio of transfer path usage time allocated to each disk volume in advance.

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