JP3811556B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
According to the present invention, when a plurality of integrated circuits of chips formed on a semiconductor wafer are simultaneously inspected in a wafer state, the operations of the plurality of integrated circuits can be inspected while causing a delay, and the plurality of integrated circuits The present invention relates to a semiconductor integrated circuit device capable of inspecting a specific integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art In recent years, electronic devices equipped with semiconductor integrated circuit devices have made remarkable progress in downsizing and cost reduction, and accordingly, demands for downsizing and cost reduction of semiconductor integrated circuit devices have become stronger.
[0003]
Usually, in a semiconductor integrated circuit device, after a semiconductor chip and a lead frame are electrically connected by a bonding wire, the semiconductor chip is supplied in a state of being sealed with resin or ceramics and mounted on a printed board. However, due to the demand for downsizing of electronic equipment, a method of directly mounting a semiconductor integrated circuit device on a circuit board in a state where the semiconductor integrated circuit device is cut out from a semiconductor (hereinafter, the semiconductor integrated circuit device in this state is referred to as a bare chip or simply a chip). Has been developed and it is desired to supply bare chips with guaranteed quality at a low price.
[0004]
In order to perform quality assurance for a bare chip, it is necessary to burn in the semiconductor integrated circuit device in a wafer state.
[0005]
However, the burn-in performed collectively in the state of a semiconductor wafer (hereinafter referred to as wafer burn-in) cannot meet the demand for cost reduction because the handling of the semiconductor wafer becomes very complicated. In addition, since it takes a lot of time to perform burn-in by dividing a plurality of bare chips formed on one semiconductor wafer one by one or several times many times, it is realistic in terms of time and cost. Therefore, it is required that all bare chips be burned in simultaneously in a wafer state.
[0006]
Here, a burn-in apparatus capable of performing the wafer burn-in disclosed in Japanese Patent Application Laid-Open No. 8-5666 will be described.
[0007]
FIG. 7 shows an overview of a conventional wafer burn-in apparatus. As shown in FIG. 7, the wafer burn-in apparatus 100 includes a rack 110 that can store a plurality of wafer cassettes 103 in which the wafer tray 101 and the probe card 102 are depressurized and pressed together, and a vacuum that maintains the depressurized state of the wafer cassette 103. A pump 111 and a drive circuit 112 that electrically drives a plurality of semiconductor integrated circuit devices formed on the semiconductor wafer held in the wafer cassette 103 are configured.
[0008]
[Problems to be solved by the invention]
However, in the conventional wafer burn-in apparatus, a plurality of semiconductor integrated circuit devices formed in a matrix form on a semiconductor wafer are inspected against the semiconductor integrated circuit devices arranged in a lump or in rows (columns). Therefore, the current flowing in a plurality of semiconductor integrated circuit devices selected from an external device transiently increases in the order of several tens of nanoseconds at the start of operation. In addition, each selected semiconductor integrated circuit device has a problem that it becomes electrically unstable.
[0009]
Further, since a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are collectively inspected, there is a problem that the individual states of the semiconductor integrated circuit devices cannot be grasped during the inspection.
[0010]
The present invention solves the above-described conventional problems, and distributes current at the start of operation of a selected semiconductor integrated circuit device when inspecting a plurality of semiconductor integrated circuit devices at a wafer level. A first object is to make it possible to monitor the state of one of the plurality of semiconductor integrated circuit devices during the inspection.
[0011]
[Means for Solving the Problems]
In order to achieve the first object, a first semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device that operates based on a clock signal, and a plurality of semiconductor integrated circuits formed on a semiconductor wafer. An ID selection for holding a chip ID for identifying one semiconductor integrated circuit device among a plurality of semiconductor integrated circuit devices and selecting one semiconductor integrated circuit device when the circuit devices are collectively inspected When a signal is input, a chip ID holding unit that outputs a chip ID, a clock signal that receives an ID selection signal, a chip ID, and an external clock signal and starts outputting an internal clock signal based on the value of the chip ID Control means, and the clock signal control means counts the number of pulses of the external clock signal so as to have a period whose upper limit is the maximum value of the chip ID. It has other.
[0012]
According to the first semiconductor integrated circuit device, the chip ID holding means for holding the chip ID for identifying one of the plurality of semiconductor integrated circuit devices selects the semiconductor integrated circuit device ( When an ID selection signal (which is activated) is input, the clock signal control means for outputting the chip ID and receiving the chip ID, the ID selection signal, and the external clock signal is based on the value of the chip ID. If a unique ID is assigned to each of the plurality of semiconductor integrated circuit devices, the output start timing of the internal clock signal is shifted for each unique ID.
[0013]
In the first semiconductor integrated circuit device, the clock signal control means includes a counter for accumulating the number of pulses of the external clock signal so as to have a period whose upper limit is the maximum value of the chip IDs, a predetermined value of the counter and an external It is preferable to have a clock generation unit that generates an internal clock signal using the clock signal.
[0014]
In order to achieve the second object, a second semiconductor integrated circuit device according to the present invention includes a plurality of semiconductors when a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer are collectively inspected. One semiconductor integrated circuit device is selected by holding a chip ID for identifying one of the integrated circuit devices and inputting ID data having the same value as the chip ID. Chip ID holding means for outputting a chip selection signal indicating that the signal has been received, and unique data output means for receiving the chip selection signal and outputting an electrical signal indicating the electrical characteristics specific to one semiconductor integrated circuit device. Yes.
[0015]
According to the second semiconductor integrated circuit device, the chip ID holding means for holding the chip ID for identifying one of the plurality of semiconductor integrated circuit devices is the chip ID of the semiconductor integrated circuit device. When the matching ID data is input, it outputs a chip selection signal indicating that it has been selected, receives the chip selection signal, and outputs unique data indicating an electrical characteristic specific to the semiconductor integrated circuit device Since the output means is provided, for example, an internal voltage or the like that is an electric signal unique to the chip can be output to the outside.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
An object of the present application is to obtain individual semiconductor integrated circuit devices capable of performing a stable inspection collectively on a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer. However, in the following embodiments, only the components of the invention incorporated in each semiconductor integrated circuit device are described for convenience of explanation.
[0017]
(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 shows a circuit configuration of an internal clock signal generation circuit of a semiconductor integrated circuit device according to the first embodiment of the present invention. In the present embodiment, a semiconductor integrated circuit device that operates with a plurality of clock signals such as a logic circuit, a microcomputer, or a synchronous DRAM is assumed.
[0019]
As shown in FIG. 1, the internal clock signal generation circuit 30 includes a chip ID holding circuit 10 and a clock signal control circuit 20.
[0020]
The chip ID holding circuit 10 includes a first chip ID recording unit 11 that records the first chip ID (ID0), a second chip ID recording unit 12 that records the second chip ID (ID1), 3 and a third chip ID recording unit 13 for recording the chip ID (ID2). Each chip ID recording unit 11, 12, 13 gates, for example, an ID selection signal 1 output from the burn-in device. And the source voltage is applied to the drain, the source is connected to the output terminal side, and the transistor is grounded via the fuse connected to the source. The output data of each transistor is a clock signal control circuit. 20 respectively. Here, the presence / absence of a fuse in each of the chip ID recording units 11, 12, and 13 determines the chip ID. In this case, since three chip ID recording units are provided, 2 to the third power, that is, 0 8 types of IDs from 1 to 7 can be assigned.
[0021]
The clock signal control circuit 20 includes a counter 21 that receives the ID selection signal 1, the external clock signal 2, and the outputs of the first to third chip ID recording units 11 to 13 and outputs a carry signal B. ing. Further, it comprises an AND-OR circuit, an inverter circuit, and a shift register, and generates and outputs an internal clock signal 3 from a latch circuit 22 that latches a carry signal B, an output of the latch circuit 22 and an external clock signal 2. And a generation circuit 23 as a clock generation unit.
[0022]
The chip ID holding circuit 10 has three chip ID recording units, and the fuses of the first chip ID recording unit 11 and the third chip ID recording unit 13 are previously cut as shown in FIG. When the gate is turned on, high data is output from the first and third chip ID recording units 11 and 13, and the second chip ID recording unit 12 outputs a ground potential via a fuse. Is output. Therefore, if the first chip ID (ID0) side is MSB, it represents 101B (B represents a binary number. The same shall apply hereinafter) as 3-bit data. That is, the chip ID of this integrated circuit device is 5 in decimal, and this chip ID of 5 is the initial value of the counter 21.
[0023]
On the other hand, the counter 21 in the clock signal control circuit 20 forms one cycle with the maximum value of 3-bit data, such as 0, 1,..., 6, 7, 0, 1,. For example, an accumulator (register) is provided to output the carry signal B at the timing of returning to (1).
[0024]
Hereinafter, the operation of the internal clock signal generation circuit 30 configured as described above will be described with reference to the drawings.
[0025]
2A shows the timing at which the internal clock signal 3 is generated when the chip ID is 5, and FIG. 2B shows the timing at which the internal clock signal 3 is generated when the chip ID is 3. It represents. As shown in FIG. 2A, first, when the ID selection signal 1 is input, the chip ID 5 is output from the chip ID holding circuit 10 to the counter 21. Here, since the load timing until the chip ID that is the initial value of the counter is completely input from the chip ID holding circuit 10 to the counter 21 is provided, the ID selection signal 1 is the load signal A with a predetermined delay. And input to the counter 21.
[0026]
Next, each time the external clock signal 2 is input to the counter 21, the integrated value of the counter 21 is integrated one by one from the initial value of 5. When the integrated value returns to 0, a carry signal B is generated to generate a latch circuit. 22 for output. At the timing when the next external clock signal 2 is input, the generation circuit 23 outputs the internal clock signal 3 from the external clock signal 2 and the latch signal C.
[0027]
Similarly, in FIG. 2B, since the chip ID is 3, the timing at which the carry signal B is output from the counter 21 is shifted as compared with the case where the chip ID is 5.
[0028]
As described above, according to the present embodiment, when the electrical characteristics of a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are inspected collectively, different chips are provided in each of the plurality of semiconductor integrated circuit devices. Since the ID is recorded and the initial value of the counter having one cycle is determined according to the chip ID, the timing at which the counter is cleared to 0 is different, so that the internal clock signal is generated with a shift. Will be. As a result, even when the ID selection signals 1 are simultaneously turned on (high) from the external devices and a plurality of semiconductor integrated circuit devices are selected, the timings at which currents start to flow in the respective semiconductor integrated circuit devices are shifted from each other and delayed. As a result, the operation of the inspection apparatus and each semiconductor integrated circuit device will not become unstable.
[0029]
The fuses of the chip ID recording units 11 to 13 in the chip ID holding circuit 10 can be easily blown by trimming using a laser beam.
[0030]
Further, not only a fuse but also a storage element such as an antifuse or EPROM can electrically set an ID.
[0031]
The chip IDs do not necessarily have to be different for each semiconductor integrated circuit device, and may be unique for each selected block.
[0032]
Furthermore, when the number of semiconductor integrated circuit devices formed on one semiconductor wafer is very large and it is desired to simplify the internal clock signal generation circuit 30, it is appropriate within a range in which an increase in current amount can be suppressed. The same chip ID may be assigned to any number of semiconductor integrated circuit devices.
[0033]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0034]
FIG. 3 shows a circuit configuration of the internal voltage monitor of the semiconductor integrated circuit device according to the second embodiment of the present invention. As shown in FIG. 3, the internal voltage monitor 31 includes a chip ID holding circuit 40 and an internal voltage output circuit 50 as specific data output means.
[0035]
The chip ID holding circuit 40 has four chip ID recording units 41 to 44, and indicates that the chip ID can be held as 4-bit data. Each of the chip ID recording units 41 to 44 is configured such that a power supply voltage is applied to one end, a resistor having the other end connected to the output terminal, and a fuse for determining the chip ID are connected between the output terminal and the ground. Has been. As shown in FIG. 3, since the fuses of the chip ID recording units 41 and 42 are cut in advance, and the fuses of the chip ID recording units 43 and 44 are connected, the chip ID recording unit 44 side is connected to the MSB. Then, this chip ID is 0011B, which represents 3 in decimal.
[0036]
The chip ID holding circuit 40 includes a shift register 45 that receives the ID data from the external inspection device and the clock signal CLK and outputs the ID data, and an EXNOR circuit, and the ID data output from the shift register 45. A first comparator 46 that receives and compares each ID signal output from each of the chip ID recording units 41 to 44 and outputs high data if the comparison result is true, and each first comparator 46 includes: A second comparator 47 for determining a comparison result to be output and outputting a chip selection signal D indicating that the selected result is true.
[0037]
The internal voltage output circuit 50 includes a transistor having a gate receiving a chip selection signal D, an internal voltage Vcc applied to the drain, and a source connected to the internal pad 60.
[0038]
The internal pad 60 is connected to a probe terminal of a probe card for inspection, and is connected to the inspection apparatus as a monitor signal line from the probe terminal.
[0039]
Hereinafter, the operation of the internal voltage monitor 31 configured as described above will be described with reference to the drawings.
[0040]
FIG. 4 shows the timing at which the chip selection signal D is generated. In this embodiment, since the ID data D0 to D3 are input as serial signals, the chip ID recording units 41, 42, 43, and 44 are shifted to each cycle of the clock signal CLK, respectively, and finally If the ID data input from the outside is 3 when the ID data is input in the order of D0, D1, D2, and D3, the chip selection signal is sent from the second comparator 47 in the chip ID holding circuit 40. As a result, the internal voltage Vcc is read from the internal voltage output circuit 50 in the selected semiconductor integrated circuit device.
[0041]
As a matter of course, when the ID data input from outside is a value other than 3, the internal voltage output circuit 50 does not output the internal voltage value.
[0042]
The fuses of the chip ID recording units 41 to 44 in the chip ID holding circuit 40 can be easily blown by trimming using a laser beam.
[0043]
Further, not only a fuse but also a storage element such as an antifuse or EPROM can electrically set an ID.
[0044]
As described above, according to the present embodiment, when the electrical characteristics of a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are inspected collectively, different chips are provided in each of the plurality of semiconductor integrated circuit devices. If the ID is recorded and a desired chip ID is input from an external inspection device, the internal voltage Vcc of the semiconductor integrated circuit device corresponding to the input chip ID can be read. Therefore, since it is possible to read the unique data of one of the plurality of semiconductor integrated circuit devices, it is possible to specify whether or not an electrical abnormality has occurred.
[0045]
Further, since the output data line for monitoring can be shared, the wiring of the probe card or the like can be simplified.
[0046]
In the present embodiment, the internal voltage Vcc is monitored. However, the present invention is not limited to this, and may be specific data such as a substrate potential.
[0047]
(One Modification of Second Embodiment)
Hereinafter, a modification of the second embodiment of the present invention will be described with reference to the drawings.
[0048]
FIG. 5 shows a circuit configuration of an internal voltage monitor of a semiconductor integrated circuit device according to a modification of the second embodiment of the present invention. In FIG. 5, the same components as those shown in FIG. As shown in FIG. 5, the internal voltage monitor 31 includes a chip ID holding circuit 40A and an internal voltage output circuit 50 as specific data output means.
[0049]
Unlike the second embodiment, this modification is configured to cope with the case where ID data D3 to D0 input from an external device are input in parallel.
[0050]
That is, the first comparators 46 in the chip ID holding circuit 40A receive the outputs of the chip ID recording units 41 to 44, and the external devices are sequentially installed from the first comparator 46 on the chip ID recording unit 44 side. Are input in parallel as D3, D2, D1 and D0.
[0051]
The output side of the second comparator 47 is connected to the shift register 45 activated by the ID selection signal 1, and the output signal of the shift register 45 is output to the internal voltage output circuit 50 as the chip selection signal D. Is done.
[0052]
Hereinafter, the operation of the internal voltage monitor 31 configured as described above will be described with reference to the drawings.
[0053]
FIG. 6 shows the timing at which the chip selection signal D is generated. In this modification, since the ID data D3 to D0 are input as parallel signals, the ID data D3 to D0 are input, and when the ID selection signal 1 is input, the input ID data D3 to D0 are input. If it is 3, the chip select signal D is output from the shift register 45 in the chip ID holding circuit 40A, and as a result, the internal voltage Vcc is read from the internal voltage output circuit 50 in the selected semiconductor integrated circuit device. become.
[0054]
Further, by using a DQ signal line or an address signal line as input means for the ID data D3 to D0, it is possible to suppress an increase in the number of wires in the probe card or the like.
[0055]
As described above, according to the present embodiment, when the electrical characteristics of a plurality of semiconductor integrated circuit devices formed on one semiconductor wafer are inspected collectively, different chips are provided in each of the plurality of semiconductor integrated circuit devices. If the ID is recorded and a desired chip ID is input from an external inspection device, the internal voltage Vcc of the semiconductor integrated circuit device corresponding to the input chip ID can be read. Therefore, since it is possible to read the unique data of one of the plurality of semiconductor integrated circuit devices, it is possible to specify whether or not an electrical abnormality has occurred.
[0056]
In addition, since the output data line for monitoring can be shared, wiring of the probe card and the like is simplified.
[0057]
In the present embodiment, the internal power supply Vcc is a monitoring target. However, the present invention is not limited to this, and may be specific data such as a substrate potential.
[0058]
【The invention's effect】
According to the first semiconductor integrated circuit device of the present invention, when a plurality of semiconductor integrated circuit devices are formed on a single semiconductor wafer, when the plurality of semiconductor integrated circuit devices are collectively checked, the chip ID is retained. When the means receives an ID selection signal indicating that the semiconductor integrated circuit device has been selected, the clock signal control means outputs the chip ID and receives the chip ID, the ID selection signal, and the external clock signal. Since the output of the internal clock signal is started based on the value of the chip ID, if each of the plurality of semiconductor integrated circuit devices has a unique ID, the output start time of the internal clock signal is shifted for each unique ID. Become. As a result, even if an ID selection signal is input from an external device and a plurality of semiconductor integrated circuit devices are selected, each semiconductor integrated circuit device is supplied with current by an internal clock that starts to operate separately based on different chip IDs. Therefore, a large current generated in a very short time immediately after being selected is dispersed. Accordingly, the timing at which current begins to flow in each semiconductor integrated circuit device is shifted, so that the operations of the inspection device and each semiconductor integrated circuit device do not become unstable.
[0059]
In the first semiconductor integrated circuit device, a counter that accumulates the number of pulses of the external clock signal so as to have a period with the maximum value of the chip ID as an upper limit, and a predetermined value of the counter and the external clock signal are used. Since the initial value of the counter is given from the chip ID holding means when the internal clock signal is generated, the counter having a period whose upper limit is the maximum value of the chip ID is the external clock signal. The integration of pulses is started from the initial value given. For this reason, for example, if the clock generation unit starts to output an internal clock signal based on an external clock signal when the counter exceeds the maximum value and returns to the reset state, the internal clock signal starts for each chip ID. The time can be surely shifted.
[0060]
According to the second semiconductor integrated circuit device according to the present invention, when a plurality of semiconductor integrated circuit devices are formed in one semiconductor wafer and the plurality of semiconductor integrated circuit devices are collectively tested, When ID data that matches the chip ID of the device is input, a chip selection signal indicating that the semiconductor integrated circuit device has been selected is output, the chip selection signal is received, and an electrical characteristic specific to the semiconductor integrated circuit device is received. Since there is provided unique data output means for outputting an electrical signal indicating the target characteristic, for example, an internal voltage or the like that is an electrical signal unique to the chip can be output to the outside. Therefore, since it is possible to read the unique data of one of the plurality of semiconductor integrated circuit devices, it is possible to specify whether or not an electrical abnormality has occurred.
[0061]
In addition, since the output data line for monitoring can be shared, the wiring of the probe card or the like can be simplified.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an internal clock signal generation circuit of a semiconductor integrated circuit device according to a first embodiment of the present invention.
FIG. 2A is a timing chart showing an operation of an internal clock signal generation circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 4B is a timing chart showing the operation of the internal clock signal generation circuit of the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing an internal voltage monitor of a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 4 is a timing chart showing an operation of an internal voltage monitor of a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing an internal voltage monitor of a semiconductor integrated circuit device according to a modification of the second embodiment of the present invention.
FIG. 6 is a timing chart showing an operation of an internal voltage monitor of a semiconductor integrated circuit device according to a modification of the second embodiment of the present invention.
FIG. 7 is a schematic view showing a conventional wafer burn-in apparatus.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ID selection signal 2 External clock signal 3 Internal clock signal A Load signal B Carry signal C Latch signal D Chip selection signal 10 Chip ID holding circuit 11 1st chip ID recording part 12 2nd chip ID recording part 13 3rd Chip ID recording unit 20 Clock signal control circuit 21 Counter 22 Latch circuit 23 Generation circuit (clock generation unit)
30 Internal clock signal generation circuit 31 Internal voltage monitor 41 Chip ID recording unit 42 Chip ID recording unit 43 Chip ID recording unit 44 Chip ID recording unit 45 Shift register 46 First comparator 47 Second comparator 50 Internal voltage output circuit (Unique data output means)
60 internal pads

Claims (3)

A semiconductor integrated circuit device that operates based on a clock signal,
When inspecting collectively to a plurality of said semiconductor integrated circuit device formed on a semiconductor wafer, hold the chip ID for identifying one of a semiconductor integrated circuit device of the plurality of semi-conductor integrated circuit device And a chip ID holding means for outputting the chip ID by receiving an ID selection signal for selecting the one semiconductor integrated circuit device;
A semiconductor integrated circuit device comprising: clock signal control means for receiving the ID selection signal, the chip ID, and an external clock signal, and starting output of an internal clock signal based on the value of the chip ID . The clock signal control means includes
A counter for accumulating the number of pulses of the external clock signal so as to have a period with the maximum value of the chip ID as an upper limit;
2. The semiconductor integrated circuit device according to claim 1, further comprising: a clock generation unit that generates the internal clock signal using a predetermined value of the counter and the external clock signal. When a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer are collectively inspected, a chip ID for identifying one of the plurality of semiconductor integrated circuit devices is held. Chip ID holding means for outputting a chip selection signal indicating that the one semiconductor integrated circuit device is selected by inputting ID data having the same value as the chip ID;
A semiconductor integrated circuit device comprising: a unique data output means for receiving the chip selection signal and outputting an electrical signal indicating electrical characteristics unique to the one semiconductor integrated circuit device.

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