JP3809432B2 - Received signal processing apparatus and satellite positioning system - Google Patents

Description

The present invention relates to a received signal processing apparatus and a satellite positioning system.

In a positioning satellite (for example, GPS) receiver or the like, the code is demodulated by synchronizing the same code generated inside the receiver with the radio wave code from the received satellite.
However, since the positioning satellite is moving, the Doppler effect occurs, and therefore the frequency of the received radio wave is different from that transmitted from the satellite. Therefore, Doppler correction is performed by a GPS receiver or the like to make this frequency the same as when it was transmitted from the satellite.

Further, if there is a frequency error of the local oscillator in the receiver, the error after the frequency conversion is superimposed on the error of the local oscillator in addition to the frequency error due to the Doppler effect of the satellite's confidence.
At this time, if the Doppler correction is to be performed only by the receiver itself, it is necessary to try the frequency range that can be considered by estimating the frequency error by itself, and it is necessary to repeat until the code demodulation is possible. There was a drawback that a long processing time was required. That is, it has a fatal defect that it takes a considerable time to demodulate the code.

In addition, even if an accurate satellite frequency error is obtained from outside, if the error of the local oscillator is unknown, Doppler correction needs to try the frequency range that can be considered by estimating the frequency error by itself as in the above case. There is a drawback that it is necessary to repeat the calculation until the code can be demodulated.
In order to completely eliminate the error of the local oscillator, an ultra-stable oscillator is required. For example, an expensive rubidium oscillator or the like is required, resulting in a disadvantage that the system becomes expensive.

In order to solve this drawback, it has been widely practiced to incorporate a signal having an accurate frequency from the outside and detect an error in the oscillation frequency inside the receiver by this phase detection circuit. That is, means (radio timepiece, JJY, etc.) that locks the oscillation frequency inside the receiver to a signal having an accurate frequency from the outside by a phase-locked loop circuit and uses the same frequency is generally widely used. This means is generally known as a PLL (Phase Lock Loop) circuit (see, for example, Patent Document 1).
JP-A-7-321644

  The problem to be solved is that the signal taken from the outside has a restriction that the frequency stability is sufficiently accurate than the frequency stability inside the receiver and the signal electric field strength is more than the corresponding strength. . Also, with this means, the received signal received from the outside is subjected to the Doppler effect from the outside, or the signal is devoted to noise. Accurate detection has the disadvantage that it is extremely difficult.

The received signal processing device of the present invention includes a high frequency amplifier that receives a PN signal, an internal oscillator that oscillates a frequency signal, and a frequency converter that is connected to the internal oscillator and converts the PN signal into a predetermined frequency region. A first calculation unit that performs FFT on the received PN code obtained from the signal processed by the frequency conversion unit, a pattern calculation unit that generates an internal PN code pattern, and a second that performs FFT on the internal PN code pattern A component obtained by applying the frequency component of the signal obtained by the second computing unit to the frequency component of the signal obtained by the computing unit and the first computing unit is computed, and the frequency signal of the frequency signal by the internal oscillating unit is calculated. A third calculation unit that detects a frequency error, and the first calculation unit includes a first separation processing unit that separates an FFT-calculated signal into a real part and an imaginary part, and the second calculation Part is the FFT-calculated signal A second separation processing unit that separates the real number part and the imaginary number part; and the third calculation unit divides the signal for one period obtained by the first separation processing unit into predetermined bandwidths. to-obtained data, shall to have a processing unit for adding multiplied by data obtained by dividing one period of the signal obtained by the second separation processing unit for each predetermined bandwidth synchronization It is.

Also, the processed signal by the frequency converting unit with a Doppler correction unit for Doppler correction, the received PN code obtained by correcting at the doppler correction unit causes the FFT calculation by the first calculation unit .
In addition, an I signal conversion unit and a Q signal conversion unit that obtain an I signal and a Q signal from the signal processed by the frequency conversion unit, and the I signal and the Q signal are the Doppler correction unit and the first signal, respectively. The third arithmetic unit includes a synthesis processing unit that performs a synthetic operation on the I component and the Q component obtained by processing by one arithmetic unit and the arithmetic processing unit.

Further, the satellite positioning system of the present invention is a satellite positioning system in which a receiver terminal receives a satellite signal from a satellite, and the receiver terminal obtains a pseudorange between the satellite and the received PN signal. The receiver terminal receives a PN signal, a high-frequency amplification unit, an internal oscillation unit that oscillates a frequency signal, a frequency conversion unit that is connected to the internal oscillation unit and converts the PN signal into a predetermined frequency region, A first calculation unit that performs FFT on the received PN code obtained from the signal processed by the frequency conversion unit; a pattern calculation unit that generates an internal PN code pattern; and a second calculation unit that performs FFT on the internal PN code pattern; The component obtained by applying the frequency component of the signal obtained by the second computing unit to the frequency component of the signal obtained by the first computing unit is computed, and the frequency error of the frequency signal by the internal oscillating unit is calculated. detection A third arithmetic unit that, and a pseudo distance detection unit for determining the pseudorange from the signals the frequency error is canceled of the frequency signal, the first operation unit, the real part and imaginary FFT operation signal A second separation processing unit for separating the FFT-calculated signal into a real part and an imaginary part, and the third computation The unit obtains one cycle of data obtained by the second separation processing unit for data obtained by dividing the signal of one cycle obtained by the first separation processing unit for each predetermined bandwidth. An arithmetic processing unit that multiplies data obtained by dividing the signal into predetermined bandwidths and performs synchronous addition .

Also, the receiver terminal, the processed signal in the frequency converting unit with a Doppler correction unit for Doppler correction, the received PN code obtained by correcting at the doppler correction unit, said first arithmetic FFT calculation is performed in the unit.
The receiver terminal includes an I signal conversion unit and a Q signal conversion unit that obtain an I signal and a Q signal from the signal processed by the frequency conversion unit, and the I signal and the Q signal are respectively The third calculation unit includes a synthesis processing unit that performs a synthesis operation on the I component and the Q component obtained by processing by the Doppler correction unit, the first calculation unit, and the calculation processing unit.

  The present invention makes it possible to make the signal-to-noise ratio remarkably improved and to detect the frequency error of the internal oscillating unit even if the signal is very weak due to noise. Processing time can be shortened. That is, high accuracy and high processing speed can be achieved.

Therefore, in the satellite positioning system of the present invention, even when a signal from a satellite is received in a building or the like, that is, even from a very weak satellite that has been subjected to Doppler fluctuation due to noise. Therefore, it is possible to detect an oscillation frequency error of the internal oscillator included in the receiver terminal with high sensitivity and good response.
In other words, in the past, an ultra-high precision and expensive oscillator was required in order to make Doppler correction respond quickly and accurately. However, in the present invention, Doppler correction can be performed even for an inexpensive oscillator that is commonly used. It can be done accurately and quickly.

FIG. 1 is an overall block diagram showing an outline of an embodiment of a satellite positioning system according to the present invention. A ₁ , A ₂ , A ₃ , and A ₄ are positioning satellites, and 1 is a base station. The base station 1 is provided to send Doppler information of each positioning satellite A to the receiver terminal 11.
The base station 1 includes a receiving antenna 2 installed in an environment with a good view, receives a GPS reference signal by the server receiver 3, and extracts Doppler information from the GPS signal by the calculation unit 4.

  And the information in the calculating part 4 is transmitted to the receiver terminal 11 side by the transmission part (transmitter) 5. L is a communication line, and information of the calculation unit 4 is transmitted to the receiver terminal 11 via the communication line L. The communication line L is a communication path for sending the information of the calculation unit 4 to the receiver terminal 11 side. The communication line L covers all possible communication lines, and may be an electromagnetic communication means, for example, terrestrial broadcasting It may be a mobile phone communication, a communication that broadcasts information via a communication satellite, or an Internet line.

The receiver terminal 11 receives information of the calculation unit 4 from the base station 1 by broadcasting or the like. Information of the calculation unit 4 is received by the reception unit 12 included in the GPS receiver terminal 11.
The GPS receiver terminal 11 assumes that many terminals 11 can simultaneously receive information such as broadcasts (cell phones, the Internet, etc.). FIG. 1 shows a case where there is one receiver terminal 11 for ease of explanation.

Reference numeral 14 denotes an antenna unit of the receiver terminal 11. The location of the receiver terminal 11 (antenna unit 14) is not only where satellite A can be seen directly, but in places other than normal open fields, such as in the shade of trees or in buildings where GPS signal strength is very weak. It also assumes.
Reference numeral 13 denotes a GPS receiver for A / D converting a PN signal (C / A code) obtained by down-converting the GPS signal (removing the carrier wave), and 15 is a part (memory: RAM) for storing the signal. . Then, the Doppler correction unit 16 performs Doppler correction of the carrier wave from the Doppler information of the carrier wave from the base station 1 for the accumulated PN signal (I component, Q component) of the GPS signal.

This corrected signal is subjected to carrier wave Doppler correction, but is a PN signal (I component, Q component) including a Doppler component due to a frequency error of the internal oscillation unit (local oscillator) 34.
With respect to the PN signal including the Doppler component, that is, the PN signal including the Doppler component generated by the frequency error of the internal oscillation unit 34 (I component and Q component), the oscillation frequency error detecting device 17 Perform frequency error detection.

If the local frequency error is obtained, the Doppler correction of the PN signal can be easily performed from the detected frequency error. A portion that performs Doppler correction of the PN signal is a correction unit 18.
Then, the pseudorange detection unit 19 obtains the pseudorange between the receiver terminal 11 and the satellite A based on the signal from which the frequency error of the internal oscillation unit 34 has been canceled. The pseudo distance detection unit 19 obtains the pseudo distance from the signal from which the frequency error of the frequency signal has been canceled, and can be used by a normal means, and the description is omitted.
That is, in the satellite positioning system according to the present invention, the receiver terminal 11 receives the satellite signal from the satellite A, and the receiver terminal 11 obtains the pseudo distance to the satellite A from the received PN signal.

Hereinafter, the operation in each processing block will be described in detail. FIG. 2 is a block diagram showing the configuration of the receiver terminal 11.
14 is a reception antenna unit, 32 is a high frequency amplification unit that receives a PN signal from the reception antenna unit 14, and 33 is a frequency conversion unit that down-converts the frequency.
The internal oscillating unit 34 is a local oscillating unit (frequency synthesizer), 35 is an I signal converting unit (I signal converting carrier removing unit), 36 is a Q signal converting unit (Q signal converting carrier removing unit), and 37 is 90 Phase shifters, 38 and 39 are A / D converter units, 15 is a memory unit (RAM) for temporarily storing signals, 41 is a DSP unit, 42 is a CPU unit, 22 is a pattern calculation unit, and 44 is a DSP unit. Reference numeral 41 is a ROM, 45 is a RAM, and 46 is a ROM connected to the CPU unit 42.
Reference numeral 12 denotes a receiving unit for obtaining information from the base station 1 shown in FIG.
The Doppler correction unit 16, the oscillation frequency error detection device 17, and the correction unit 18 in FIG. 1 correspond to the signal processing unit 21 in FIG.

  FIG. 3 is a diagram showing an outline of operations in an I signal conversion (carrier wave removal) unit 35 and a Q signal conversion (carrier wave removal) unit 36 that obtain an I signal and a Q signal from the signal processed by the frequency conversion unit 33. . In FIG. 3, 47 and 48 are multipliers, and 49 and 50 are low-pass filters.

The operation will be described with reference to FIG. 2 and FIG. 3. A 1.5 GHz band GPS signal subjected to spread spectrum modulation with a PN signal is received by the high frequency amplifier 32 from the receiving antenna unit 14. The PN signal is down-converted by the internal oscillating unit (frequency synthesizer) 34 and the frequency converting unit 33, and converted into a frequency region of, for example, 70 MHz band.
The internal oscillator 34 and the 90-degree phase shifter 37 multiply each other by the 70 MHz carrier wave having a phase difference of 90 degrees, that is, the I signal converter 35 and the Q signal converter 36. The carrier 70 MHz is removed, and the PN code (C / A code code) of I component and Q component orthogonal to each other is taken out.
The internal oscillator 34 is a local oscillator (frequency synthesizer), and a generally used inexpensive crystal oscillator can be used. The internal oscillator 34 has a frequency error.

The operation for removing the carrier wave will be described with reference to FIG. 3. The GPS signal down-converted to the 70 MHz band is represented by PN.cos ((W + ΔW) t + Φ). ΔW is the Doppler frequency, and ΔW is a combination of the Doppler frequency fluctuation of the satellite signal captured by the antenna unit 14 and the frequency fluctuation of the internal oscillation unit 34 (frequency synthesizer). Here, if the Doppler frequency fluctuation of the satellite signal is Δ W _C and the frequency fluctuation of the internal oscillator 34 is Δ W _L , then ΔW = ΔW _C + ΔW _L.

Then, the signal from the internal oscillating unit 34 in FIG. 2 and the 90-degree phase shifter 37 represent signals having a phase difference of 90 degrees as carrier waves cos (Wt) and sin (Wt) orthogonal to each other. When these orthogonal signals and the signal PN.cos ((W + ΔW) t + Φ) from the frequency converter 33 are multiplied by multipliers 47 and 48 and passed through the low-pass filters 49 and 50, PN.cos (ΔWt + Φ), −PN.sin (Δwt + Φ). These conversions are generally used as I and Q converters.
In FIG. 3, in each of the I and Q signal conversion units 35 and 36, the input signal PN.cos ((W + ΔW) t + Φ) is multiplied by carrier waves cos (Wt) and sin (Wt) orthogonal to each other. Since both carrier frequencies W 1 are the same, the carrier component is removed in both cases.

Next, the signals (analog signals) orthogonal to each other from which the carrier wave components are removed are converted from analog signals into digitized discretized signals by the A / D converter units 38 and 39, respectively. Then, these two signals are stored in the memory unit (RAM) 15 for a predetermined time.
The high frequency amplification unit 32, frequency conversion unit 33, internal oscillation unit 34, I signal conversion unit 35, Q signal conversion unit 36, 90 degree phase shifter 37, and A / D converter units 38 and 39 described above are generally used. This is a part and is generally used, and a description of the specific configuration is omitted.
In the embodiments of the present invention, the PN signal is described as a PN signal from which a carrier wave component is removed. However, the PN signal may be configured as a PN signal including a carrier wave component.
That is, in FIG. 2, the I signal conversion unit 35 and the Q signal conversion unit 36 may be configured as a circuit that does not remove the carrier wave.
Further, in this case, the low-pass filter 49 in the I signal conversion unit 35 and the low-pass filter 50 in the Q signal conversion unit 36 in FIG. 3 can also be constituted by a band pass filter (BPF).

In FIG. 2, a digital signal processing unit 21 includes a CPU unit 42 connected to the receiving unit 12 to process data obtained through the receiving unit 12, a RAM (memory) 45 and a ROM connected to the CPU unit 42. (Memory) 46, DSP section 41 connected to memory section (RAM) 15, ROM (memory) 44 connected to DSP section 41, and pattern calculation section 22.
The pattern calculation unit 22 is a calculation storage part that generates an internal PN code pattern and stores it in advance. The CPU unit 42 and the DSP unit 41 are connected to each other, and the CPU unit 42, the RAM 45, and the ROM 46 operate as a microprocessor.
Further, the pattern calculation unit 22 may be configured by a portion in which an internal PN code pattern created in advance is stored in a memory.

The internal PN code pattern (replica PN signal) will be briefly described.
In general, a plurality of positioning satellites (eg, GPS) travel around the earth, and from each satellite, a carrier wave (1575.42 MHz in the case of GPS) and a PN signal (also called a C / A code) corresponding to each individual satellite. Is spread spectrum modulated and transmitted to the earth.
For example, suppose that 1575.42 MHz is transmitted by spectrum spread modulation with satellite A _{1 using} PN signal a and satellite A _{2 using} PN signal b. In order to take out (demodulate) the signal of the satellite A ₁ at the receiver terminal 11, the receiver terminal 11 stores the PN signal a ′ that is the same as the PN signal a in advance and uses the PN signal a ′ to store the satellite. A ₁ demodulates the PN signal a at the receiver terminal 11.
In order to receive the PN signal b from the satellite A ₂ , the same PN signal b ′ as the PN signal b must be stored in the receiver terminal 11 in advance.
Therefore, if the receiver terminal 11 does not have all the PN signals corresponding to each satellite A transmitted from each satellite A in advance, the signal of each satellite A cannot be received.
In the present invention, the PN signal prepared in advance is used as an internal PN code pattern (replica PN signal).

  The ROM 46 is a part that mainly stores a digital signal processing execution program. The hardware part of the digital signal processing unit 21 is a configuration of a DSP unit 41, a CPU unit 42, a RAM 45, a ROM 46, and a ROM 44. These configurations have been widely used as general-purpose digital signal processing configurations using a CPU, DSP, and memory (RAM and ROM), and will not be described here.

Then, the hardware unit of the digital signal processing unit 21 executes the functional blocks of the Doppler correction unit 16, the detection device 17, and the correction unit 18 of FIG. The case where this functional block is executed by digital signal processing by software will be described. The signal obtained by the I signal conversion unit 35 and the Q signal conversion unit 36 includes a Doppler component. The Doppler frequency ΔW is information from the base station (server) 1 and is obtained from the receiving unit 12 of the receiver terminal 11.

That is, the receiver terminal 11 includes a Doppler correction unit 16 that performs Doppler correction on the signal processed by the frequency conversion unit 33, and a received PN code obtained by correcting the signal by the Doppler correction unit 16 is a first calculation described later. The unit 7 performs an FFT operation.
The correction performed by the Doppler correction unit 16 can be performed by external Doppler information or by internal processing. In other words, the receiver terminal 11 may receive the external Doppler information from the base station 1 or may perform the Doppler correction by calculating from the received PN signal in a calculation unit (not shown) of the receiver terminal 11. May be.

FIG. 4 shows an operation for performing Doppler correction based on external Doppler correction information. In FIG. 4, 26, 27, 28 and 29 are multipliers, 30 is an adder, and 31 is a subtractor. The input signals here are discretized data stored in the memory unit 15, respectively. Further, t represents a discretized value.
The data of the input signal I signal and the Q signal in FIG. 4 are expressed by PN.cos (ΔWt + Φ) and −PN.sin (ΔWt + Φ), respectively.

For these signals, the signals cos (ΔWct) and sin (ΔWct) obtained from the Doppler frequency fluctuation component ΔWc of the satellite signal obtained from the receiving unit 12 are multiplied by multipliers 26, 27, Multiplying by 28 and 29 and passing through the adder 30 and the subtractor 31 yields −PN.sin (ΔW _L t + Φ) and PN.cos (ΔW _L t + Φ). These signals are discretized digital signals. The output PN code is subjected to Doppler due to the frequency error of the internal oscillation unit 34.
This PN code is used as an input signal to the oscillation frequency error detection device 17 shown in FIG.

As described above, the receiver terminal 11 includes a received signal processing unit (apparatus) that performs processing such as correction of the PN signal, and a pseudo distance detecting unit that obtains a pseudo distance from the PN signal corrected by the received signal processing unit. 19 is provided.
The received signal processing device unit includes a high frequency amplification unit 32 that receives a PN signal, an internal oscillation unit 34 that oscillates a frequency signal, and a frequency conversion unit 33 that is connected to the internal oscillation unit 34 and converts the PN signal into a predetermined frequency region. And.

  Further, the received signal processing unit generates a first PN code pattern that FFT (receives PN code) obtained from the signal processed by the frequency converter 33 (described in detail later) and an internal PN code pattern. The pattern calculation unit 22, the second calculation unit 8 that performs FFT on the internal PN code pattern, and the frequency component of the signal obtained by the second calculation unit 8 are applied to the frequency component of the signal obtained by the first calculation unit 7. And a third calculation unit 9 for calculating the component obtained in this manner and detecting the frequency error of the frequency signal by the internal oscillation unit 34.

FIG. 5 is an operation explanatory diagram for explaining the oscillation frequency error detection device 17 including the first calculation unit 7, the second calculation unit 8, and the third calculation unit 9, and shows an oscillation frequency error detection algorithm execution block. .
B ₁ , B ₂ and B ₃ are FFT blocks having a function of performing Fourier transform (FFT) on the input signal (reception PN code) and the replica signal (internal PN code pattern).
That is, the first calculation unit 7 corresponds to the FFT blocks B ₁ and B ₃ for calculating the input signal, and the second calculation unit 8 corresponds to the FFT block B ₂ for calculating the replica signal.

B ₄ , B ₅ , and B ₆ are separation processing blocks having a function of separating each FFT operation result into a real part and an imaginary part. B ₉ and B ₁₀ encode the polarity of the peak value generated at each predetermined frequency (KHz) after separating the replica signal that has been subjected to FFT into a real part and an imaginary part (large values of +1 or −1). This is an arithmetic block having a function of converting to
That is, the first calculation unit 7 includes a first separation processing unit 23 that separates the FFT-calculated signal into a real part and an imaginary part, and the first separation processing unit 23 is divided into separation processing blocks B ₄ and B ₆ . Correspond.
The second calculation unit 8 includes a second separation unit 24 for separating the FFT operation signal into a real part and an imaginary part, the second separation unit 24 corresponds to the separation processing block B _5.

In FIG. 5, M ₁ , M ₂ , M ₃ , M ₄ , M ₅ , and M ₆ are obtained by performing FFT on the input signal and separating the result into a real part and an imaginary part, with (integer) × 1000 (Hz) as the center. A memory unit (RAM) that stores numerical values divided by a predetermined bandwidth when the frequency is used.
The memory part M ₁ and the memory part M ₂ store the real part and the imaginary part as a result of performing the FFT on the I signal component, and the memory part M ₃ and the memory part M ₄ perform the FFT on the replica signal. The real part and imaginary part of the result are saved, and the memory part M ₅ and the memory part M ₆ save the real part and imaginary part of the result of performing FFT on the Q signal component.

Further, the third calculation unit 9 obtains the data obtained by dividing the signal for one cycle obtained by the first separation processing unit 23 for each predetermined bandwidth by the second separation processing unit 24. There is an arithmetic processing unit 25 that multiplies the data obtained by dividing the signal for one period for each predetermined bandwidth and performs synchronous addition.
That is, the I signal calculation block B ₇ and the Q signal calculation block B ₈ are calculation units having multiplication and synchronous addition functions, and the I signal calculation block B ₇ and the Q signal calculation block B ₈ correspond to the calculation processing unit 25. To do.
That is, a component obtained by applying (multiplying) the polarity of the frequency component obtained by FFT of the internal PN code pattern to the frequency component obtained by FFT of the received signal is synchronously added many times. . Thereby, even if the received PN signal is a signal strayed by noise, the oscillation frequency error inside the receiver terminal 11 can be accurately detected.

Then, the operation result data S _1, to the value of each digit stored in the memory unit M _1, the data corresponding to the numerical value stored is stored in the memory unit M ₃ and the memory unit M ₁ polarity ( This is the output obtained by multiplying ±) and performing synchronous addition.
Operation result data S _2, relative to each of the numerical values stored in the memory unit M _1, the data corresponding to the numerical value stored is stored in the memory unit M ₄ and the memory unit M ₁ polarity (±) Is the output of synchronous addition by multiplying by.
Operation result data S _3, relative to each of the numbers stored in the memory unit M _2, the data corresponding to the numerical value stored is stored in the memory unit M ₄ and the memory unit M ₂ polarity (±) Is the output of synchronous addition by multiplying by.
Operation result data S ₄ are for each of the numerical values stored in the memory unit M _2, the data corresponding to the numerical value stored is stored in the memory unit M ₃ and the memory unit M ₂ polarity (±) Is the output of synchronous addition by multiplying by.

The calculation result data S _5, relative to each of the numerical values stored in the memory unit M _5, the data corresponding to the numerical value stored is stored in the memory unit M ₃ and the memory unit M ₅ polar ( This is the output obtained by multiplying ±) and performing synchronous addition.
Operation result data S ₆ are for each of the numerical values stored in the memory unit M _5, the data corresponding to the numerical value stored is stored in the memory unit M ₄ and the memory unit M ₅ polarities (±) Is the output of synchronous addition by multiplying by.
Operation result data S ₇ are for each of the numerical values stored in the memory unit M _6, the data corresponding to the numerical value stored is stored in the memory unit M ₄ and the memory unit M ₆ polarity (±) Is the output of synchronous addition by multiplying by.
Operation result data S ₈ are for each of the numerical values stored in the memory unit M _6, the data corresponding to the numerical value stored is stored in the memory unit M ₃ and the memory unit M ₆ polarity (±) Is the output of synchronous addition by multiplying by.

Sa ₉ , Sa ₁₀ , Sa ₁₁ , Sa ₁₂ , Sa ₁₃ , Sa ₁₄ , Sa ₁₅ are arithmetic blocks having an addition (addition / subtraction) function. The operation block Sa ₉ calculates the sum (S ₁ + S ₃ ) of the operation result data S ₁ and S ₃ , and the operation block Sa ₁₀ calculates the difference (S ₂ −S ₄ ) between the operation result data S ₂ and S _4. The operation block Sa ₁₁ calculates the sum (S ₅ + S ₇ ) of the operation result data S ₅ and S ₇ , and the operation block Sa ₁₂ calculates the difference (−S ₆ + S ₈ ) between the operation result data S ₈ and S _6. To do.
In the operation block Sa ₁₃ , the operation result data S ₉ and S ₁₂ are added (S ₉ + S ₁₂ ), and in the operation block Sa ₁₄ , the operation result data S ₁₀ and S ₁₁ are added (S ₁₀ + S ₁₁ ). square of the operation result data S ₁₃ in block Sa ₁₅ adds the (operation result by the block Pa ₁₇₎ and the operation result squared data S ₁₄ (result of the calculation block ^{_{Pa 18) (S 13 2 +}} S 14 2), thereby, A value for estimating the frequency fluctuation component ΔW _L of the internal oscillation unit 34 is obtained.

That is, these calculation blocks Sa _{9 to} Sa ₁₅ , calculation block Pa _17, and calculation block Pa ₁₈ correspond to the synthesis processing unit 40 that performs a synthesis operation on the I component and the Q component. And the 3rd calculating part 9 is provided with this synthetic | combination process part 40 and the said arithmetic processing part 25 which performs the pre-processing.

The processing in the oscillation frequency error detection device 17 will be described more specifically. The input signal to the block shown in FIG. 5 is the output signal obtained in FIG. 4, and the signal subjected to Doppler correction in FIG. -0.25PN (t) .sin (ΔW _L t + Φ), 0.25PN (t) .cos (Δ W _L t + Φ). This signal and that has been discretized, for simplicity of explanation, the input signal g _I [k] the number 1 to the respective FFT blocks B _1, the input signal g _Q to FFT block B ₂ [ k] is expressed by the equation (2).

Here, T is a sampling interval, and k is a data number for t in FIG. Here, it is assumed that data is obtained in a section of k = 0, 1,..., N−1, N, N + 1,. Here, m is the number of PN code periods, N is the number of samples per PN code period, and the total number of sampled data is mN.
At this time, the following processing (Equation 3, Equation 4, Equation 5) is performed in the FFT blocks B ₁ , B ₂ , B ₃ in FIG.

Further, in the separation processing blocks B ₄ , B ₅ and B ₆ , the output from the FFT block B ₁ , the output from the FFT block B _2, and the output from the FFT block B ₃ are respectively divided into a real part and an imaginary part. the output of the separation processing block B ₄ (6), the output of the separation processing block B ₅ (7), the output of the separation processing block B ₆ (8) is obtained.
Re represents a real part and Im represents an imaginary part.

  Here, the FFT calculation result of the PN code has a characteristic that a peak value (non-zero value) occurs at an m-point cycle (1000 Hz cycle) as shown in FIG. 6 and a zero value in other regions. In addition, as indicated by Re [PN [n]] in the data RP1 and Im [PN [n]] in the data RP2 in FIG. 6, in the real part and imaginary part of PN [n], the m-point period ( The peak value and polarity that occur in the 1000 Hz period) are different from each other. Further, paying attention only to the polarity of the peak value in the period of m point (1000 Hz period), the polarity of the peak value in Re [PN [n]] is represented in Equation 9 and data SPN2 as represented in the data SPN1 of FIG. Thus, the polarity of the peak value in Im [PN [n]] is converted to Equation 10.

  Further, the polarities corresponding to the respective peak values generated in the m point period (1000 Hz period) are set to Equation 11 for data VSPN1 and Equation 12 for data VSPN2 in FIG.

The data VSPN1 and data VSPN2 which are the polarity values (± 1) obtained in this way are stored in the memory units M ₃ and M ₄ in FIG. 5, respectively.

Here, if the output from the FFT block B ₁ and the output from the FFT block B ₃ are re-divided into a real part and an imaginary part, they are output from the separation processing block B ₄ and the separation processing block B _6. The numerical values are Equation 13, Equation 14, Equation 15, and Equation 16.

The numerical values output from the separation processing block B ₄ and the separation processing block B ₆ are obtained in a form in which the real part and the imaginary part of the FFT operation value of the PN code are shifted ± f _L on the frequency axis. FIG. 7 shows Re [G _I [n]] when the initial phase ψ = 0 in the FFT operation results output from the separation processing block B ₄ and the separation processing block B ₆ as data GI1, and Im [ In this example, G _I [n]] is plotted on data GI2, Re [G _Q [n]] is plotted on GQ1, and Im [G _Q [n]] is plotted on data GQ2.

As shown in this example, when ψ = 0 as shown in FIG. 7, the peak value of Re [G _I [n]] is ± f according to the polarity of Re [PN [n]] as shown in data GI1. _A peak value is generated in the same direction by shifting _L, and the peak value of Im [G _I [n]] is shifted by ± f _L in the same direction according to the polarity of Im [PN [n]] as shown in data GI2. A peak value has occurred.
The peak value of Re [G _Q [n]] is shifted by ± f _L according to the polarity of Im [PN [n]] as shown in the data GQ1, and the peak of the corresponding PN code in the −f _L direction. In the + f _L direction, a peak value is generated in the same direction as the peak value of the corresponding PN code. The peak value of Im [G _Q [n]] is represented by Re [ Shift by ± f _L according to the polarity of PN [n]], in the same direction as the peak value of the corresponding PN code in the −f _L direction, and in the opposite direction to the peak value of the corresponding PN code in the + f _L direction There is a peak value.

Re [G _I [n]], Im [G _I [n]], Re [G _Q [n]], and Im [G _Q [n]] obtained in this way are shown in FIG. To divide. In FIG. 8, the data RGI is Re [G _I [n]], the data IGI is Im [G _I [n]], the data RGQ is Re [G _Q [n]], and the data IGQ is Im [G _Q [n]]. It corresponds to.
The matrix notation data obtained by dividing Re [G _I [n]] is represented by Equation 17 in the data VRGI, the matrix notation data obtained by dividing Im [G _I [n]] is represented by Equation 18 in the data VIGI, and Re [G _Q Data in matrix notation obtained by dividing [n]] is stored as data 19 in the data VRGQ, and data in matrix notation obtained by dividing Im [G _Q [n]] as data 20 in the data VIGQ.

The width of dividing Re [G _I [n]], Im [G _I [n]], Re [G _Q [n]], Im [G _Q [n]] on the frequency axis is the center frequency (integer ) × 1000 (Hz) and divided by a width of ± 500 (Hz). When this is adapted to the data number on the frequency axis, it becomes (integer) × m ± m / 2.
Numerical values in the matrix format data VRGI, VIGI, VRGQ, and VIGQ obtained by dividing the FFT values obtained as described above are stored in the memory units M ₁ , M ₂ , M ₅ , and M ₆ in FIG.

As described above, the data VRGI, VIGI, VRGQ, and VIGQ shown in FIG. 8 are stored in the memory units M ₁ , M ₂ , M ₅ , and M ₆ in FIG. ₅ and the memory units M ₃ and M ₄ are stored in FIG. some data VSPN1, VSPN2, the input signal to the I signal calculation block B ₇ and Q signal computing unit B ₈ in FIG. The arithmetic blocks Sa _{1 to} Sa ₈ in FIG. 5 are numerical values stored in the memory units M ₁ , M ₂ , M ₅ , M ₆ , the above-mentioned formulas 17, 18, 18, 19 (data in FIG. 8). The polarity of the peak value in each row of VRGI, VIGI, VRGQ, and VIGQ is a numerical value obtained by encoding the peak value in the FFT calculation result of the replica PN code: the above formulas 9 and 10 (data VSPN1, shown in FIG. 6) (VSPN2, stored in the memory units M ₃ and M ₄ in FIG. 5) are multiplied to have the same polarity.

As for the output of the multiplier section obtained here, when attention is paid to the memory section M ₁ in FIG. 5, the multipliers used are Sa ₁ and Sa ₂ , the calculation result data S ₁ is expressed by Equation 21, and the calculation result data S ₂ is given by Equation 22.

Hereinafter, similarly, the numerical values stored in the memory units M ₂ , M ₅ , and M ₆ will be described. With respect to the memory unit M ₂ , the calculation result data S ₄ is represented by Equation 23 and the calculation result data S ₃ is represented by a number. In the memory unit M ₅ , the operation result data S ₅ is expressed by Equation 25, the operation result data S ₆ is expressed by Equation 26, and in the memory unit M ₆ , the operation result data S ₈ is expressed by Equation 27, and the operation result data S ₇ is expressed by Equation 28.

As described above, the numerical values stored in the memory units M ₁ , M ₂ , M ₅ , and M ₆ are multiplied by both of the code values in the memory units M ₃ and M ₄ . Since the output from the separation processing blocks B ₄ and B ₆ in FIG. 5 includes both the real part and the imaginary part of the FFT value of the PN code, it is performed in order to make both polarities the same.
The calculation results in the I signal calculation block B ₇ and the Q signal calculation block B ₈ are as follows (Equation 29, Equation 30, Equation 31, Equation 32, Equation 33, Equation 34, Equation 35, Equation 36).

FIG. 9 shows an outline of the processing from the I signal calculation block B ₇ and the Q signal calculation block B ₈ and the calculation blocks Sa _{1 to} Sa ₈ in FIG. The example shown in FIG. 9 deals with a case where attention is paid to the calculation result data S ₁ and S ₂ of the calculation block B ₇ in FIG. 5 when the initial phase ψ = 0.
Multiplying data PR1 in FIG. 9 corresponds to data S ₁ in FIG. 5, is multiplied by the sign value of the number 11 corresponding to the numerical value of each row of the number 17.
Multiplying data PR2 in Fig. 9 corresponds to the data S ₂ in FIG. 5, is multiplied by the sign value of the number 12 corresponding to the numerical value of each row of the number 17. In the case shown in FIG. 9, since the initial phase ψ = 0, only the following expression 37 is strengthened in the above expression 17. Therefore, the results of the multiplication data PR1 all have the same peak value polarity, and the multiplication data PR2 results in different peak value polarities.
Then, addition is performed on the multiplication result data PR1 and PR2 obtained in this way (synchronous addition on the frequency axis).

In FIG. 9, the result of adding the multiplication result data PR1 is data ADD1, and the result of adding the data PR2 is data ADD2. In the case of data ADD1, since all the multiplication result data PR1 have the same polarity, the peak value increases. On the other hand, in the case of the data ADD2, since the multiplication result data PR2 shows different polarities in each row, the peak value does not increase even if they are added.
The foregoing has described the effects of polarity multiplication and synchronous addition on the frequency axis when attention is paid to the data S ₁ and S ₂ of the operation block B ₇ in FIG. 5. Similarly, the data S _{3 to} S ₈ are also described below. Synchronous addition in the state of the same polarity results in strengthening.

  That is, the first calculation unit 7 collects (stores) data for a predetermined time for the received PN signal, obtains the real part and imaginary part of the FFT, and is an integer multiple of the frequency of one period of the PN signal. The data divided for each predetermined bandwidth, centered on, is multiplied by the polarity of the real part and imaginary part of the FFT for one period of the internal PN code pattern, and their synchronous addition is performed. Thus, the frequency error of the internal oscillator 34 is detected.

Next, a process performed in operation block (adder) Sa ₉ -SA ₁₂ in FIG. 5, the operation block Sa ₉ in S ₁ + S _3, operation block Sa ₁₀ in S ₂ -S _4, operation block Sa ₁₁ calculates S ₅ + S ₇ , and the calculation block S ₁₂ calculates −S ₆ + S ₈ . That is, the following calculation is performed (Equation 38, Equation 39, Equation 40, Equation 41).

Further, S ₉ + S ₁₂ and S ₁₀ + S ₁₁ are performed in the operation blocks Sa ₁₃ and Sa ₁₄ . That is, the following calculation is performed (Equation 42, Equation 43).

As can be seen from the outputs of the arithmetic blocks Sa ₁₃ and Sa ₁₄ in FIG. 5, the arithmetic block Sa ₁₃ calculates the arithmetic block Sa ₉ and the arithmetic block Sa ₁₂ results, and the arithmetic block Sa ₁₄ calculates the arithmetic block Sa ₁₀ and arithmetic results. and adding the result of the block Sa _11.
As described above, only the FFT value of the PN code shifted by the frequency + f _L is extracted by the processing from the arithmetic blocks Sa _{9 to} Sa ₁₄ . However, since the components of the initial phase ψ remain in both the computation blocks Sa ₁₃ and Sa ₁₄ outputs, the computation block Pa ₁₇ takes the square of the output in the computation block Sa ₁₃ and the computation block Pa ₁₈ outputs the output in the computation block Sa ₁₄ . The square is taken and the resultant sum is obtained in the operation block Sa ₁₅ .
That is, the following processing is performed (Equation 44).

This is the final output: OUT of the execution block shown in FIG. Here, the addition up to the number 45 obtained by OUT is the addition in a state where the polarities of the peak values are all aligned.
On the other hand, the addition processing result in Expression 46 can be ignored because the peak values are canceled each other.

Therefore, an enhanced peak value is generated on the frequency axis shifted from the center frequency by the local shift component + f _L , and the transmitter frequency error component + f _L can be detected.

On the other hand, consider the case where the received input signals g _I [k] and g _Q [k] in FIG.
Considering the transmitter frequency error component + f _L process, the received signal g _I [k], g _Q [k] is input in FIG. 5 in the above calculation process, and then the transmitter frequency error component + f _L The number of input synchronization additions is mN in the process up to detection of.
In this case, assuming that the noise superimposed on the input signal (corresponding to the thermal noise in the receiver terminal 11) is Gaussian that matches the statistical properties, the noise component is 1 / √ (mN) by mN synchronous additions. It is known to decrease in proportion to.
Therefore, in the process of obtaining the transmitter frequency error component of the present invention, even if there is noise in the received input signals g _I [k] and g _Q [k] in FIG. 5, the noise can be reduced by increasing mN. Even when a signal having an extremely weak electric field, for example, a satellite is received in a building, the frequency error component of the transmitter can be detected.

As described above, according to the received signal processing apparatus of the present invention, even if the received signal is very weak, the signal-to-noise ratio is remarkably improved and the frequency error of the internal oscillator 34 is self-detected. In addition, the processing time can be shortened. That is, high accuracy and high processing speed can be achieved.
In addition, since the reception signal processing apparatus has the Doppler correction unit 16, it can detect a frequency error between the internal oscillation unit 34 and the reception PN signal, and can perform highly accurate processing.

Further, according to the satellite positioning system of the present invention, even when the signal from the satellite A is received in a building or the like, that is, from the very weak satellite A that has been subjected to Doppler fluctuations that have been affected by noise. Even with this signal, it is possible to self-detect the oscillation frequency error of the internal oscillation unit 34 of the receiver terminal 11 with ultrahigh sensitivity and good response.
In other words, in the past, an ultra-high precision and expensive oscillator was required in order to make Doppler correction respond quickly and accurately. However, in the present invention, Doppler correction can be performed even for an inexpensive oscillator that is commonly used. It can be done accurately and quickly.

  Further, since the satellite positioning system has the Doppler correction unit 16, it can detect a frequency error between the internal oscillation unit 34 and the received PN signal, and can perform highly accurate processing. Therefore, the receiver terminal 11 can obtain a more accurate pseudorange even from a weak signal.

It is a whole block diagram which shows the outline of one Embodiment of this invention. It is a block diagram which shows the structure of a receiver terminal. It is operation | movement explanatory drawing explaining an I signal conversion part and a Q signal conversion part. It is operation | movement explanatory drawing explaining the Doppler correction part which performs the Doppler correction of a carrier wave from IQ signal. It is operation | movement explanatory drawing explaining an oscillation frequency error detection part. It is explanatory drawing explaining the operation | movement which carries out FFT of an internal PN code pattern, isolate | separates into a real part and an imaginary part, and produces polarity data. It is explanatory drawing which shows the waveform of the state which carried out FFT of the received input signal, and was isolate | separated into the real part and the imaginary part. It is explanatory drawing explaining the operation | movement which divides | segments by a fixed width | variety from the waveform which isolate | separated the received input signal into the real part and the imaginary part, and accumulate | stores it in memory. It is explanatory drawing explaining the operation | movement which carries out synchronous addition. It is explanatory drawing which shows the state by which the frequency error was detected by the peak value.

Explanation of symbols

7 1st operation part 8 2nd operation part 9 3rd operation part
11 Receiver terminal
16 Doppler correction section
19 Pseudo distance detector
22 Pattern calculator
23 First separation processing section
24 Second separation processor
25 Arithmetic processing section
32 High frequency amplifier
33 Frequency converter
34 Internal oscillator
35 I signal converter
36 Q signal converter
40 Composition processing section

Claims (6)

A high-frequency amplification unit (32) that receives a PN signal, an internal oscillation unit (34) that oscillates a frequency signal, and a frequency conversion unit that is connected to the internal oscillation unit (34) and converts the PN signal into a predetermined frequency region (33), a first calculation unit (7) that performs FFT on the received PN code obtained from the signal processed by the frequency conversion unit (33), and a pattern calculation unit (22) that generates an internal PN code pattern And the second arithmetic unit (8) that performs FFT on the internal PN code pattern, and the frequency component of the signal obtained by the first arithmetic unit (7) is the frequency component of the signal obtained by the second arithmetic unit (8). A third calculation unit (9) for calculating a component obtained by applying the frequency component and detecting a frequency error of the frequency signal by the internal oscillation unit (34) , wherein the first calculation unit (7) The first separation processing unit (23) for separating the FFT-calculated signal into a real part and an imaginary part The second calculation unit (8) includes a second separation processing unit (24) that separates an FFT-calculated signal into a real part and an imaginary part, and the third calculation unit (9). Is obtained by the second separation processing unit (24) with respect to the data obtained by dividing the signal for one period obtained by the first separation processing unit (23) for each predetermined bandwidth. reception signal processing apparatus according to claim 1 cycle of the signal processing unit for adding synchronization multiplying data obtained by dividing each predetermined bandwidth Rukoto which have a (25) was. A Doppler correction unit (16) for performing Doppler correction on the signal processed by the frequency conversion unit (33), and the received PN code obtained by the correction by the Doppler correction unit (16) The received signal processing apparatus according to claim 1, wherein FFT processing is performed by the unit (7) . An I signal conversion unit (35) and a Q signal conversion unit (36) for obtaining an I signal and a Q signal from the signal processed by the frequency conversion unit (33) are provided, and each of the I signal and the Q signal is provided. A synthesis processing unit (40) for performing a synthesis operation on the I component and the Q component obtained by processing in the Doppler correction unit (16), the first calculation unit (7), and the calculation processing unit (25); The received signal processing device according to claim 2, which the third arithmetic unit (9) has . In a satellite positioning system, a receiver terminal (11) receives a satellite signal from a satellite (A), and the receiver terminal (11) obtains a pseudorange with the satellite (A) from the received PN signal. The receiver terminal (11) is connected to the high frequency amplifying unit (32) that receives the PN signal, the internal oscillating unit (34) that oscillates the frequency signal, and the internal oscillating unit (34). A frequency converter (33) that converts the signal into a predetermined frequency region, a first arithmetic unit (7) that performs FFT on the received PN code obtained from the signal processed by the frequency converter (33), and an internal PN A pattern calculation unit (22) that generates a code pattern, a second calculation unit (8) that performs FFT on the internal PN code pattern, and the second frequency component of the signal obtained by the first calculation unit (7) Calculate the component obtained by applying the frequency component of the signal obtained in the computation unit (8). A third calculation unit (9) that detects a frequency error of the frequency signal by the internal oscillation unit (34), and a pseudo distance detection unit (19) that calculates the pseudo distance from a signal in which the frequency error of the frequency signal is canceled The first calculation unit (7) includes a first separation processing unit (23) that separates an FFT-calculated signal into a real part and an imaginary part, and the second calculation unit (8) ) Has a second separation processing unit (24) that separates the FFT-computed signal into a real part and an imaginary part, and the third computation unit (9) is connected to the first separation processing unit (23). For the data obtained by dividing the obtained signal for one period for each predetermined bandwidth, the signal for one period obtained by the second separation processing unit (24) is obtained for each predetermined bandwidth. A satellite positioning system comprising an arithmetic processing unit (25) for multiplying and adding synchronously the data obtained by division. The receiver terminal (11) includes a Doppler correction unit (16) that performs Doppler correction on the signal processed by the frequency conversion unit (33), and is obtained by correcting the Doppler correction unit (16). The satellite positioning system according to claim 4, wherein the received PN code is subjected to an FFT calculation by the first calculation unit (7) . The receiver terminal (11) includes an I signal conversion unit (35) and a Q signal conversion unit (36) for obtaining an I signal and a Q signal from the signal processed by the frequency conversion unit (33), The I signal and the Q signal are combined and calculated with the I component and the Q component obtained by processing in the Doppler correction unit (16), the first calculation unit (7), and the calculation processing unit (25), respectively. The satellite positioning system according to claim 5 , wherein the third processing section (9) has a synthesis processing section (40) .

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