JP3796510B2 - DRIVE DEVICE, DRIVE CIRCUIT, AND IMAGE DISPLAY DEVICE - Google Patents

Description

  The present invention relates to a matrix panel driving device and an image display device used for monitors such as television receivers and computers, and in particular, a matrix in which modulation elements such as semiconductor light-emitting elements and electron-emitting elements are arranged at intersections of matrices. The present invention relates to a panel driving device, a driving circuit, and an image display device.

  Hereinafter, an electron-emitting device will be described as an example of the modulation device. FIG. 31 schematically shows a matrix panel used in a display device or the like.

  In FIG. 31, 1 schematically shows an electron-emitting device as a modulation device, 2 is a column wiring, and 3 is a row wiring. The column wiring 2 and the row wiring 3 have wiring resistances 4 and 5 corresponding to the specific resistance and dimensions of the constituent materials. For convenience of illustration, a 4 × 4 matrix is shown. However, the size of the matrix is not limited to this. For example, in the case of a multi-electron beam source for an image display device, a desired image display is performed. This is to arrange and wire enough elements.

  In a multi-electron beam source in which electron-emitting devices are wired in a simple matrix, appropriate electric signals are applied to row wiring and column wiring in order to output a desired electron beam.

  FIG. 32 shows column wiring drive waveforms and row wiring drive waveforms supplied to the matrix panel. For example, in order to drive any one row of the electron-emitting devices in the matrix, a row selection signal having the selection voltage Vs is applied to the row wiring of the selected row, and non-selection is applied to the row wiring of the non-selected row. A selection voltage Vns is applied. In synchronization with this, a driving voltage Ve for outputting an electron beam to the column wiring is applied for a predetermined period.

  According to this method, a voltage of Ve−Vs is applied to the electron-emitting devices in the selected row, and a voltage of Ve−Vns is applied to the electron-emitting devices in the non-selected rows. If Ve, Vs, and Vns are set to appropriate voltages according to the electron emission threshold value of the electron-emitting device, an electron beam having a desired intensity is output only from the electron-emitting device in the selected row. Further, since the response speed of the cold cathode device is high, an electron beam is output if the length of time for applying the drive voltage Ve, that is, the pulse width of the voltage Ve as shown by the arrow in FIG. 32 is changed. You can also change the length of time.

  The electron beam can also be controlled by a modulation method that controls the luminance by changing the voltage amplitude or current value applied to the column wiring.

  In the above example, a 4 × 4 matrix is described. However, an image display device that actually displays a television image requires a horizontal 640 × vertical 480 matrix, for example, in a VGA (Video Graphics Array), and color display is performed. Further, a horizontal 1920 × vertical 480 matrix is required.

For example, if the current flowing into the electron source is 1 mA, the current necessary for driving the column wiring is 1 mA, but the current necessary for driving the row wiring flows from all the column wirings. Therefore, 1 mA × 1920 = 1.92 A. Therefore, a row wiring driver for driving the row wiring is required to have a current driving capability of several A.

  Since the row wiring driver is an example of the above-mentioned VGA and has a large number of outputs of 480, it is often implemented as an IC because it is costly to configure with a discrete device, but it is considered to drive a current of several amperes. The output buffer is required to have a low on-resistance.

As a method of reducing the on-resistance of the output buffer of the IC, there is a method of increasing the chip area of the IC. When the chip area is increased, for example, in the case of a high breakdown voltage MOS, it is necessary to use a double diffusion structure. Therefore, the occupied area of the chip increases, and if an output on resistance (Ron) of 100 mΩ is obtained, about 1 mm ^2. Occupy.

Therefore, in the case of an IC having an output of 80 channels, 80 mm ² is occupied only by the output buffer. Furthermore, since a pre-buffer is required to drive the output buffer, a chip area close to 100 mm ² is actually required only with the output buffer.

  As described above, in order to lower the resistance of the output buffer unit of the IC, it is necessary to increase the chip area. As a result, when the chip area increases, the number of chips taken from one wafer decreases, Unit price increases. In particular, the influence is large in a multi-output IC.

  In order to cope with such a problem, the present inventor has studied a correction circuit for correcting the voltage fluctuation due to the on-resistance of the row driving circuit. However, it has been found that using only this correction circuit is insufficient.

  For example, when the column wiring is driven by simple pulse width modulation (PWM) together with the correction circuit, the current to the row wiring changes abruptly during one horizontal scanning period depending on the gradation information to be displayed on one row of pixels. For this reason, the influence of the response characteristic of the correction circuit may become obvious.

  Also, the effective drive voltage actually applied to the modulation element may be lower than the allowable range due to the resistance of the connection portion that electrically connects the modulation element and the drive circuit.

  The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to suppress voltage fluctuation due to on-resistance of a row driving circuit.

  Another object of the present invention is to suppress the influence of the response characteristic of the correction circuit.

  Still another object of the present invention is to combine a row driving circuit capable of correcting the influence of a voltage drop and a column driving circuit suitable for the same into a low-cost and highly reliable driving device and an image display device including the same. Is to provide.

  Another object of the present invention is to correct a voltage drop in a resistor outside the drive circuit without complicating the structure of the connecting portion.

In order to achieve the above object, the driving device of the present invention provides:
A matrix panel driving device in which a modulation element is arranged at an intersection of a matrix formed by row wiring and a plurality of column wirings,
A row driving circuit for supplying a row signal to the row wiring;
A column driving circuit for supplying a modulation signal modulated in accordance with gradation information to the plurality of column wirings;
A first correction circuit for correcting the voltage of the row signal by feeding back potential information of the output terminal of the row driving circuit;
A second correction circuit for correcting a voltage drop caused by a resistance of a connection member between the output terminal and the matrix panel and a current flowing therethrough;
It is characterized by comprising.

In a drive circuit having a drive output terminal connected to a light emitting element or an electron emitting element via a connection member,
A driving transistor having a pair of main electrodes connected to the driving output terminal side and the reference voltage source side; a control circuit for controlling an output voltage output from the driving transistor; and the driving transistor A detection transistor for detecting a flowing current, and a correction circuit for correcting an output voltage from the drive output terminal,
The correction circuit includes a feedback loop that detects a current flowing through the detection transistor and feeds it back to the control circuit.

In a drive circuit having a drive output terminal connected to a light emitting element or an electron emitting element via a connection member,
A driving transistor having a pair of main electrodes connected to the driving output terminal side and the reference voltage source side; a control circuit for controlling an output voltage output from the driving transistor; and the driving transistor A detection transistor for detecting a flowing current, and a correction circuit for correcting an output voltage from the drive output terminal,
The correction circuit detects a voltage output from the drive output terminal and feeds it back to the control circuit; and a correction circuit detects a current flowing through the detection transistor and feeds back to the control circuit. And a feedback loop.

A matrix panel having a plurality of row wirings and a plurality of column wirings, and a plurality of modulation elements respectively arranged at intersections of a matrix formed by the plurality of row wirings and the plurality of column wirings;
Driving means for driving the matrix panel;
A connection member for electrically connecting the matrix panel and the driving means and supplying a signal for driving the modulation element;
In an image display device comprising:
The drive means
A driving transistor having a pair of main electrodes connected to a driving output terminal side and a reference voltage source side for supplying the signal; a control circuit for controlling an output voltage output from the driving transistor; A detection transistor for detecting a current flowing through the drive transistor, and a correction circuit for correcting an output voltage from the drive output terminal,
The correction circuit includes a feedback loop that detects a current flowing through the detection transistor and feeds it back to the control circuit.

  According to the present invention, by selecting a modulation signal to be combined with a correction circuit that corrects a voltage drop due to the on-resistance of the output stage, errors due to correction are greatly reduced. As a result, the performance required for the row drive circuit including the correction circuit can be relaxed, and the cost can be further reduced.

  According to another aspect of the present invention, it is possible to obtain an output voltage in which a voltage drop caused by a resistor connected before the driving output terminal and a current flowing therethrough is corrected.

  The best mode for carrying out the present invention will be exemplarily described in detail below with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the component parts described in the embodiments are not intended to limit the scope of the present invention only to those unless otherwise specified. .

  FIG. 1 shows a matrix panel driving apparatus according to the first aspect of the present invention.

  11 is a matrix panel, 12 is a column driving circuit for supplying a modulation signal to the column wiring, 13 is a row driving circuit for supplying a row selection signal to the selected row wiring, and 14 is a row selecting circuit such as a shift register. , 15 is an output buffer as an output stage of the row drive circuit, and 16 is a correction circuit for correcting a voltage drop due to at least the on-resistance of the output buffer 15.

  When the output buffer 15 is, for example, a CMOS inverter, the on-resistance is the resistance when the nMOS or pMOS transistor itself is on. Here, for convenience, the on-resistance of the output buffer is denoted by reference numeral 17 in FIG. .

  The correction circuit 16 is a circuit that suppresses the voltage variation of the row selection signal due to a voltage drop caused by at least the ON resistance of the output buffer 15 of the row driving circuit 13 and the current flowing through the selected row wiring in accordance with the gradation information. This corrects the voltage of the row selection signal. For example, if the voltage (potential information) at the output terminal of the output buffer 15 is detected and the potential information is fed back, the output buffer 15 can be controlled to suppress the output fluctuation of the output buffer 15.

  Here, as the modulation signal supplied from the column drive circuit 12 to the column wiring, as shown in FIG. 2A, the reference time of pulse width modulation is set to t0 in the modulation signals supplied to all four column wirings. For example, at time t1, the current flowing in the row wiring changes rapidly. This is because the falling edges of the three modulation signal pulses corresponding to the same gradation level coincide at the time t1. When the current flowing through the row wiring changes rapidly, the current flowing through the output buffer 15 connected thereto also changes rapidly. Therefore, although the correction circuit 16 is present, the response characteristics of the output buffer 15 may not catch up with it, and the matrix panel may malfunction.

  Therefore, in one embodiment of the present invention, as shown in FIG. 2B, by changing the reference time of the pulse width modulation in several modulation signals, the probability that the pulse voltage falls at the same time is reduced, Abrupt fluctuations in the current flowing in the row wiring and the output buffer connected to the row wiring are suppressed to prevent malfunction.

  As described above, in the present invention, the modulation signal modulated according to the gradation information is used so as to suppress a rapid change in the current flowing through the row wiring selected in one horizontal scanning period.

  The correction circuit 16 used in the present invention does not have to be the negative feedback circuit as described above, and display information (gradation information) to be displayed on the pixels (display elements) on one row as shown in FIG. It may be a feedforward circuit that controls the output voltage of the output stage according to DATA.

When a feedback type correction circuit is used as the correction circuit of the present invention, potential information detection points include, for example, an output terminal of a semiconductor integrated circuit chip, an output terminal of a package on which the semiconductor integrated circuit chip is mounted, and a terminal of a flexible wiring Or an input terminal of a matrix panel. When the detection point is far from the output terminal of the output buffer and the wiring resistance component up to that point cannot be ignored, the voltage setting value of the row selection signal to be supplied can be determined by taking the resistance component into account, and more accurate High correction can be made.

  It is also preferable to provide a switch for selectively connecting the detection point and the comparison means by using a common comparison means for comparing the potential information of the detection point and the reference value.

  Further, the correction circuit need not always be operated, and the malfunction may be further suppressed by performing correction only for a predetermined period within one horizontal scanning period.

  The correction circuit can easily perform the correction by controlling the source voltage or the emitter voltage of the transistor constituting the output stage of the row driving circuit, or by controlling the gate voltage or the gate voltage of the transistor. . In the former case, a driving transistor may be provided in series with the main electrode of the switching transistor that performs row selection, and the potential of the control electrode may be controlled. The latter can be considered that the switching transistor and the driving transistor are shared by one transistor.

  Further, as will be described later, it is also preferable to provide a correction circuit for correcting a voltage drop at the connection portion on the matrix panel side from the detection point.

  The modulation signal used in the present invention is not limited to a modulation signal having a different start reference time within one horizontal scanning period as in the form shown in FIG. 2B. The modulation signal may be a combination of modulation and voltage amplitude modulation. In other words, the column drive circuit preferably distributes the unit pulse component constituting the modulation signal in order to suppress a change in the current flowing through the selected row wiring within one horizontal scanning period.

  For example, in addition to making the start reference time different, a modulation scheme that performs pulse width modulation with a predetermined amplitude within a low gradation level range and performs pulse width modulation with a larger amplitude within a high gradation level range is adopted. Good. In other words, pulse width modulation is performed with the voltage amplitude kept constant within a predetermined period of one horizontal scanning period in the low gradation level range, and the voltage amplitude is increased by one step in the next intermediate gradation level range. It is also preferable to employ a modulation method in which pulse width modulation is performed and the voltage amplitude is further increased by one step and pulse width modulation is performed in the range of the next high gradation level. It is also preferable to use this method in combination with the above-described method for making the start reference time different.

  Furthermore, it is also preferable to raise or lower the voltage pulse stepwise in order to suppress a malfunction at the rise and / or fall of the voltage pulse of the modulation signal.

  Specifically, the modulated signal is pulse-width controlled in units of slot width Δt and has n stages of amplitudes A1 to An in each slot (where n is an integer equal to or greater than 2 and 0 <A1 <A2 <... < An) is controlled in amplitude, and all of the drive waveforms having a portion that rises up to a predetermined amplitude Ak (where k is an integer of 2 or more and n or less) have respective peak values from the reference level to amplitude A1 to amplitude Ak-1. The waveform rises up to the predetermined amplitude Ak through at least one slot in order.

  Alternatively, the modulated signal is pulse-width controlled in units of slot width Δt, and the amplitude in each slot is n stages of A1 to An (where n is an integer of 2 or more, and 0 <A1 <A2 <... <An). All of the drive waveforms that are amplitude-controlled and have a portion that falls from a predetermined amplitude Ak (where k is an integer not less than 2 and not more than n) are sequentially switched from the predetermined amplitude Ak to the amplitude Ak-1 to the amplitude A1. The waveform falls to the reference level after at least one slot.

  The matrix panel used in the present invention is typified by a display panel using a semiconductor light emitting element such as an organic EL or an inorganic EL as a modulation element, a fluorescent display panel using an electron emitting element as a modulation element and a phosphor. A self-luminous display panel or an electron emission panel composed of an electron emitter array not using a phosphor is preferably used. In particular, the present invention has a remarkable effect in a modulation element such as a semiconductor light emitting element or a surface conduction electron-emitting element in which the current flowing through the row wiring tends to increase as the screen becomes larger and the definition becomes higher.

  As the electron-emitting device used in the present invention, two types, a hot cathode device and a cold cathode device, are known. Among these, as the cold cathode device, for example, a surface conduction type emission device, a field emission type device (hereinafter referred to as FE type), a metal / insulating layer / metal type emission device (hereinafter referred to as MIM type), and the like are known. Yes. The surface conduction electron-emitting device is, for example, M.I. I. Elinson, Radio Eng. Electron Phys. , 10, 1290 (1965), etc., and utilizes a phenomenon in which electron emission occurs when a current flows in parallel to the film surface of a small-area thin film formed on a substrate. .

  A typical example of the device configuration of these surface conduction electron-emitting devices is shown in FIG. In FIG. 4, 3001 is a substrate, and 3004 is a conductive thin film made of metal oxide formed by sputtering. The conductive thin film 3004 is formed in an H-shaped planar shape as shown. By applying an energization process called energization forming to be described later to the conductive thin film 3004, an electron emission portion 3005 is formed. The interval L in the figure is set to 0.5 to 1 (mm), and W is set to 0.1 (mm). For convenience of illustration, the electron emission portion 3005 is shown in a rectangular shape in the center of the conductive thin film 3004. However, this is a schematic shape and faithfully represents the actual position and shape of the electron emission portion. I don't mean.

  M.M. In the surface conduction electron-emitting devices described above, including the device by Hartwell et al., The electron emission portion 3005 is generally formed by applying an energization process called energization forming to the conductive thin film 3004 before electron emission. It is.

  That is, energization forming means applying a constant DC voltage or a DC voltage boosted at a very slow rate of about 1 V / min to both ends of the conductive thin film 3004 to energize the conductive thin film 3004. It is to locally destroy, deform, or alter and form an electron emitting portion 3005 in an electrically high resistance state. Note that a crack is generated in a part of the conductive thin film 3004 that is locally broken, deformed, or altered. When an appropriate voltage is applied to the conductive thin film 3004 after the energization forming, electrons are emitted in the vicinity of the crack.

  An example of the FE type is shown in FIG. In FIG. 5, 3010 is a substrate, 3011 is an emitter wiring made of a conductive material, 3012 is an emitter cone, 3013 is an insulating layer, and 3014 is a gate electrode. This element causes field emission from the tip of the emitter cone 3012 by applying an appropriate voltage between the emitter cone 3012 and the gate electrode 3014. Further, as another element configuration of the FE type, there is an example in which an emitter and a gate electrode are arranged on the substrate substantially parallel to the substrate plane, instead of the laminated structure as shown in FIG.

  Further, a carbon fiber called CNT (carbon nanotube) or GNF (graphite nanofiber) may be provided at the tip of the emitter cone 3012. Alternatively, the emitter cone 3012 may be replaced with carbon fiber.

An example of the MIM type is shown in FIG. In FIG. 6, reference numeral 3020 denotes a substrate, 3021 denotes a lower electrode made of metal, 3022 denotes a thin insulating layer having a thickness of about 100 angstroms, and 3023 denotes a thickness of 80
It is an upper electrode made of a metal of about ~ 300 angstroms. In the MIM type, electron emission is caused from the surface of the upper electrode 3023 by applying an appropriate voltage between the upper electrode 3023 and the lower electrode 3021.

(First embodiment)
With reference to FIGS. 7-22, the drive device which concerns on the 1st Embodiment of this invention, and the image display apparatus provided with the drive device are demonstrated.

  In this embodiment, a circuit that outputs a waveform combining voltage amplitude modulation and pulse width modulation is used for a column drive circuit of a cold cathode display, and a row selection signal voltage generated by an on-resistance (Ron) of an output transistor of the row drive circuit. An example in which the voltage drop is corrected by controlling the power supply voltage of the row driving circuit by feedback control will be described.

  First, an image display apparatus to which a driving apparatus and a driving method according to an embodiment of the present invention are applied will be described with reference to FIG. FIG. 7 is a block diagram showing a multi-electron source drive circuit according to the first embodiment of the present invention.

  In FIG. 7, 101 is a multi-electron source as a matrix panel in which modulation elements are arranged, 102 is a column wiring driver (modulation circuit) as a column driving circuit, and 103 is a row wiring as a row driving circuit including a correction circuit 16. A driver (scanning circuit) 104 is a timing generation circuit for generating various timing signals such as a clock signal, a load signal, a horizontal synchronization signal and a vertical synchronization signal, 105 is a data conversion circuit, and 106 is for supplying a plurality of reference voltages. It is a multi power supply circuit.

  With this configuration, the multi-electron source 101 is driven. As shown in FIG. 31, the multi-electron source 101 is configured such that an electron source (electron emitting element: display element) 1 is formed at the intersection of the column wiring 2 and the row wiring 3. As described above, SCE type, FE type, and MIM type electron-emitting devices are known as electron sources. In this embodiment, SCE type electron-emitting devices are used.

  The data conversion circuit 105 is a circuit that converts drive data for driving the multi-electron source 101 from the outside into a format suitable for the modulation circuit 102. For example, the data conversion circuit 105 is input using a hardware arithmetic circuit as shown in FIG. From the 10-bit drive data, V1PWMSW to V4PWMSW output for selecting from four reference voltages V1, V2, V3, and V4, PWM data output, and V1 to V3 as reference voltages for pulse width modulation Each of the outputs of a flag V1PWM fixed SW to V3PWM fixed SW for determining on / off of use of built-in fixed data as PWM data of the PWM.

  The operation of the data conversion circuit will be described in more detail based on the flowchart of FIG. The data conversion circuit 105 classifies the output operation according to the value of the input drive data.

  For example, when drive data DATA of 0 to 259 is input (S401), only the output V1PWMSW is turned on so as to perform PWM with the reference voltage V1, and the outputs V2PWMSW, V3PWMSW, V4PWMSW, V1PWM fixed SW, V2PWM fixed SW, V3PWM The fixed SW is turned off (S402), the PWM data is calculated using the value of the input drive data DATA (S403), and is output to the column wiring driver.

When drive data DATA of 260 to 516 is input (S404), the V1PWM fixed SW is turned on so that the output at the reference voltage V1 has a fixed pulse width that rises at 0 and falls at 259, The output V2PWMSW is turned on so that PWM is performed with the reference voltage V2, and the outputs V3PWMSW, V4PWMSW, V2PWM fixed SW, and V3PWM fixed SW are turned off (S405). Then, PWM data is calculated using a value obtained by subtracting 259 from the input drive data (S406), and is output to the column wiring driver.

  When drive data of 517 to 771 is input (S407), the output V1PWM fixed SW is turned on so that the output at the reference voltage V1 has a fixed pulse width that rises at 0 and falls at 259, The output at the reference voltage V2 turns on the output V2PWM fixed SW so as to have a fixed pulse width that rises at 1 and falls at 258, turns on the output V3PWMSW so as to perform PWM at the reference voltage V3, and outputs V4PWMSW. The V3PWM fixed SW is turned off (S408). Then, PWM data is calculated using a value obtained by subtracting 516 from the input drive data (S409), and output to the column wiring driver.

  When drive data of 772 to 1023 is input, the output V1PWM fixed SW is turned on so that the output at the reference voltage V1 has a fixed pulse width that rises at 0 and falls at 259, and the reference voltage V2 The output at 2 is turned on so that the fixed pulse width rises at 1 and falls at 258, the output V2PWM fixed SW is turned on, and the output at the reference voltage V3 has a fixed pulse width that rises at 3 and falls at 257 The output V3PWM fixed SW is turned on so that the output V4PWMSW is turned on so that PWM is performed with the reference voltage V4 (S410). PWM data is calculated using a value obtained by subtracting 771 from the input drive data (S411), and is output to the column wiring driver.

  The column wiring driver 102 is connected to the column wiring of the multi-electron source 101, and inputs a modulation signal to the multi-electron source 101 according to the drive data converted from the data conversion circuit 105.

  The column wiring driver 102 will be described in detail with reference to FIG.

  The column wiring driver 102 includes a shift register 107, a pulse width modulation (PWM) circuit 108, and an output stage circuit 109.

  The shift register 107 shifts the modulation data from the data conversion circuit 105 to the corresponding position of the multi electron source.

  The PWM circuit 108 and the output stage circuit 109 output a drive waveform in which voltage amplitude modulation and pulse width modulation described below are combined based on the modulation data from the data conversion circuit 105.

  This drive waveform is further subjected to pulse width control in units of slot width Δt in order to cause the display element to emit light with luminance corresponding to luminance data, and n stages of amplitudes A1 to An in each slot (where n is 2 or more) The drive waveform is amplitude-controlled with 0 <A1 <A2 <... <An), and this drive waveform is derived from the amplitude at which the display element is not substantially driven, from the amplitude A1 to the amplitude Ak-1. A portion that rises up to a predetermined amplitude Ak (where k is an integer not less than 2 and not more than n) through at least one slot in order, and each amplitude from the predetermined amplitude Ak to the amplitude Ak-1 to the amplitude A1 And a portion that falls to an amplitude at which the element is not substantially driven through at least one slot in order.

  The slot width Δt is a unit time obtained by dividing one horizontal period by the maximum number of slots S. If the amplitude is constant, the pulse width of the modulation signal is determined by multiplying the slot width by a coefficient corresponding to gradation information. Is done.

  Further, a unit drive waveform block determined by the amplitude difference An−An−1,..., A2−A1 or the amplitude difference between the amplitude A1 and the amplitude serving as the drive threshold value of the display element and the slot width Δt is k = The drive waveform is formed by preferentially adding to the position where the maximum amplitude Ak including 1 is lower and the maximum amplitude continues, and the maximum amplitude Ak is set with S as the maximum number of slots in one horizontal period. When the gradation information is further increased by one gradation with respect to the drive waveform whose number of slots is S-2 (k-1), the amplitude of an arbitrary slot among the (k + 1) th to (Sk) th slots is set to Ak. It is characterized by changing from to Ak + 1.

  FIG. 11 is a diagram for more specifically explaining the relationship between the drive waveform and the drive data.

  In the case of 10-bit drive data, the circuit that generates this drive waveform performs pulse width modulation with the voltage V1 up to the drive data in the low gradation level range 1 to 259, as shown in FIG. In the driving data in the gradation level range 260 to 516 above that, the pulse width modulation is performed with the voltage V2 from the time shifted by at least one slot from the PWM start time of the voltage V1 so as to be stepped at the time of rising. Further, up to the driving data in the upper gradation level range 517 to 771, pulse width modulation is performed with the voltage V3 from the time shifted by at least one slot from the PWM start time of the voltage V2. In the case of drive data in the high gradation level range 772 to 1023, pulse width modulation is performed from the time at which the voltage V4 is shifted by at least one slot from the PWM start time of the voltage V3. In this way, a maximum of 1023 unit pulse components are stacked in a pyramid shape while being distributed within one horizontal scanning period.

  Next, the PWM circuit 108 and the output stage circuit 109 will be described in detail with reference to FIG. FIG. 12 is a block diagram showing the internal configuration of the PWM circuit 108.

  The output of the data conversion circuit 105 is shifted to a predetermined column by the shift register 107 and is taken into the latch 110 in the PWM circuit at the timing of the load signal output from the timing generation circuit 104. For example, when the drive data is 500 between 260 and 516, the PWM data in the modulation data is output by the data conversion circuit 105 as 500−259 = 241.

  Among the data fetched into the latch 110, the outputs V1PWMSW, V3PWMSW, and V4PWMSW are off, so the V4Start circuit 114, V4End circuit 118, V3Start circuit 113, and V3End circuit 117 are off, and the output V1PWM fixed SW is on. Therefore, a fixed value of 259 is input to the V1Start circuit 111 from a table (not shown) in the latch 110, and a fixed value of 259 is input to the V1End circuit 115 from a table (not shown) in the latch 110.

  Since the output V2PWMSW is on, 1 is input to the V2Start circuit 112 and 241 of PWM data is input to the V2End circuit 116. Since 0 is input to the V4PWM generation circuit 122 and the V3PWM generation circuit 121, the output is 0. The V1PWM generation circuit 119 counts up to 259 with a counter value of 0, and then falls. The V2PWM generation circuit 120 rises when the counter value is 1 and falls at 241. The outputs TV1, TV2, TV3, TV4 of the V1PWM generation circuit 119, V2PWM generation circuit 120, V3PWM generation circuit 121, and V4PWM generation circuit 122 are input to the output stage circuit 109.

An example of the output stage circuit 109 is shown in FIG. As shown in FIG. 13, the output stage circuit 109 includes a logic gate, an inverter, and an FET switch. When the output TV4 becomes Hi, the input terminals OUTPUT and V4 are connected, and when the output TV3 becomes Hi. The output terminal OU when the output terminal OUTPUT and the input terminal of V3 are connected and the output TV2 becomes Hi.
The input terminals of TPUT and V2 are connected. When TV1 becomes Hi, the input terminals of the output terminal OUTPUT and V1 are connected.

  Four reference voltages V1, V2, V3, and V4 generated by the multi power supply circuit 106 are supplied to the four input terminals (V1, V2, V3, and V4). Each voltage is adjusted to a relationship of V4> V3> V2> V1. In this way, a drive waveform as shown in FIG. 11 is obtained.

  Next, a change within one horizontal period of the current flowing through the selected row wiring due to the difference in the drive waveform will be compared with reference to FIGS.

  FIG. 14 is a diagram showing the column drive waveforms (X1 to X6) and the current waveform (Yq) flowing through the selected row wiring when the start reference times of the pulse width modulation are aligned (prealigned drive).

  FIG. 15 shows column driving waveforms (X1 to X6) and current waveforms (Yq) flowing through selected row wirings in modulation driving (hereinafter referred to as new Vn driving for convenience) combining pulse width modulation and voltage amplitude modulation. FIG.

  In FIG. 16, the start reference time of pulse width modulation of the new Vn drive is set to the start time or end time of the horizontal scanning period (1H) for each column (both front alignment driving and rear alignment driving). -X6) and the current waveform (Yq) flowing through the selected row wiring.

  When comparing the time variation of the current flowing into the row wiring within one horizontal scanning period, in the case of the pulse width modulation of FIG. 14, for example, the column wiring drive from X1 to X6 causes a rapid current variation in the row wiring of Yq. Current flows in, but by adopting the new Vn drive, in the case of FIG. 15, since the voltage change of the column wiring drive from X1 to X6 is small, the peak current Yq flowing into the row wiring driver is reduced and the current change is suppressed. Is done.

  Further, as shown in FIG. 16, the pulse width modulation start reference time from X1 to X6 is held at the beginning of one horizontal scanning period, and pre-alignment driving in which the pulse width is extended from the left in the drawing as the gradation level increases, The current change of the row wiring current Yq is obtained by performing driving (front-rear driving) combined with back-aligned driving that is held behind one horizontal scanning period and increases the pulse width from the right in the drawing as the gradation level increases. It is further suppressed.

  Although not shown, the current concentration is dispersed and the change in the row wiring current Yq is suppressed even by combining the pulse width modulation and the front-rear drive shown in FIG.

  That is, by averaging the voltage amplitude of the modulation signal applied to the column wiring within one horizontal scanning period, it is possible to suppress a change in the current flowing through the column wiring within one horizontal scanning period. Further, it is possible to suppress a change in current flowing to one selected row wiring (or flowing from the selected row wiring to a plurality of column wirings).

  As described above, if the unit pulse component is continuously distributed within one horizontal scanning period or distributed so that the position of the unit pulse component within one horizontal scanning period is different for each column wiring, the abrupt current flowing in the row wiring is increased. The change in current is suppressed. As described above, the “distribution of unit pulse component” in the present invention means that the pulse is prioritized over the voltage amplitude increase in the case of front-rear driving or when voltage amplitude modulation and pulse width modulation are combined. This is to determine the drive waveform so as to extend the width, and is in a broad sense, not limited to the meaning of discretely distributing the unit pulse components within one horizontal scanning period.

  After suppressing a change in the current flowing through the selected row wiring in this way, output voltage correction of the row wiring driver described below, in other words, on-resistance correction (Ron correction) is performed.

  The row selection driver 103 is connected to the row wiring of the multi electron source 101. The row selection driver 103 will be described with reference to FIG. FIG. 17 is a block diagram showing the Ron correction circuit 16 of the row wiring driver according to the present embodiment.

  The shift register 201 shifts the input row selection signal in order from the top at the timing of the shift clock. The output of the shift register 201 is converted into a voltage defined by the output voltage of the output voltage correction circuit 202 in the output buffer 203 and converted into a current, and the row wiring of the matrix electron source is passed through the output terminal 207 of the row wiring driver. To be supplied.

  Reference numeral 204 denotes the on-resistance (Ron) of the driver of the output buffer 203. In order to ignore the voltage drop due to the on-resistance, it is necessary to set it to a low value of several hundred mΩ or less.

  Current flows from all the column wiring drivers into the output buffer 203 via the output terminal 207, the column wiring 2, the electron source 1, and the row wiring 3.

  Therefore, for example, even if the current is 1 mA per channel (one dot), for example, a current of 1 mA × 640 dots × 3 (RGB) = 1920 mA flows in the VGA.

  Conventionally, it is necessary to use a discrete power MOSFET as the output buffer 203 or a large output buffer with low output on-resistance when integrated with a shift register or the like. Therefore, the row driving circuit is in the form of a hybrid IC or an IC having a large chip area, resulting in high costs.

  In this embodiment, by performing feedback control of the output buffer, it is possible to provide a low-cost IC that can suppress fluctuations in the output voltage. Hereinafter, a case of a matrix panel having a VGA compatible display element will be described as an example.

  First, 480 rows are divided into 6 modules, and one feedback circuit is provided for each module, and feedback control is performed on the output buffer 203 of 80 rows.

  When outputting the first row in FIG. 17, the output buffer 203 causes a voltage drop due to the ON resistance 204.

  For example, in the case of an IC with a high breakdown voltage MOS process, the on-resistance requires a certain chip size because it is necessary to connect a large number of double-diffused transistors (DMOS transistors) in parallel. Further, when the chip size is to be suppressed as much as possible, the on-resistance becomes a value of about 0.5Ω to several Ω. Therefore, for example, when a column wiring driver passes 1 mA of current per output, there are 640 dots × 3 (RGB) = 1920 outputs as a whole, so that a current equivalent to 2 A flows, and the on-resistance is 0.5Ω. However, a voltage drop of about 1V is generated.

The multiplexer 206 as a switch performs switching based on the row information (row selection information) of the monitor output select signal and outputs the potential information of the output terminal 207 in the first row to the operational amplifier 205 as the control circuit. Since the multiplexer 206 is intended to acquire the detection potential of the output terminal 207, it is not necessary to reduce the resistance value, and a resistance value of several tens of kilo ohms is sufficient. Is negligible.

  The multiplexer 206 can be manufactured by, for example, a CMOS process. FIG. 18 shows a circuit diagram of a multiplexer using the CMOS process.

  A CMOS switch composed of a P-channel FET 211 and an N-channel FET 213 is used. A CMOS switch (211, 213) is connected to each input 210, and an input is selected according to which CMOS switch gate is turned on, and potential information is output to the output terminal 212.

  The output from the multiplexer 206 is amplified by the operational amplifier 205 and input to all output buffers as a correction signal by the output voltage correction circuit 202. However, since the matrix is driven only in the first row, output drivers other than the first row are turned off. In this way, feedback is applied to the selected first row, and the voltage drop described above is corrected to increase the voltage by the correction signal, and the voltage drop due to the output current can be apparently suppressed to a low level.

  Next, the output buffer 203 and the output voltage correction circuit 202 will be described with reference to FIGS. FIG. 19 shows a circuit configuration by a CMOS process, and FIG. 20 shows a circuit configuration by a bipolar process.

  In the case of the CMOS circuit shown in FIG. 19, the drive signal waveform input to the input terminal 220 is amplified by a CMOS pre-buffer composed of a P-channel FET 221 and an N-channel FET 223 because the gate capacity of the output buffer is large. . The current-amplified drive signal waveform is applied to the gate of the CMOS output buffer constituted by the P-channel FET 222 and the N-channel FET 226 to drive the output terminal 228. The output voltage at the time of row selection at this time is determined by the source voltage of the FET 226 of the output buffer, that is, the reference voltage source Vss as the output voltage correction circuit and the gate potential of the FET 227.

  Here, since Vgs (gate-source voltage) of the FET 227 is not so stable, an operational amplifier 225 is provided to thereby apply voltage feedback. Therefore, the output voltage can be corrected by applying the correction signal from the operational amplifier 205 to the input terminal 224 of the operational amplifier 225.

  In the case of the bipolar circuit of FIG. 20, the drive waveform input to the input terminal 230 is input to the base of the output buffer constituted by the PNP transistor 231 and the NPN transistor 232.

  Since the output voltage when the row of the output terminal 235 is selected is determined by the emitter voltage of the NPN transistor 232, that is, the base potential of the PNP transistor 234 as an output voltage correction circuit, the operational amplifier 205 is connected to the base (input terminal 233) of the PNP transistor 234. The correction of the output voltage is possible by adding the correction signal from.

  As described above, a combination of a column drive waveform based on a modulation method in which pulses are distributed, for example, a new Vn drive and a Ron correction circuit, can further reduce errors due to Ron correction.

FIG. 21 shows a change in the voltage at the output terminal of the row drive circuit according to the column drive waveform shown in FIG. On the other hand, FIG. 22 shows a change in the voltage at the output terminal of the row drive circuit due to the column drive waveform shown in FIG. It can be seen that an error occurring in the output voltage due to the on-resistance and the current flowing through the row wiring is suppressed by the distribution of the pulses in the time direction.

  Before and after one horizontal scanning period, there is an unavoidable large change in voltage amplitude due to the rise and fall of the pulse, but since this time is very short, it does not feel a change in luminance, so it is a problem as an image to be displayed do not become.

  As a result, the performance required for the circuit can be relaxed, and the cost can be further reduced.

(Second Embodiment)
Still another embodiment will be described below. The basic configuration is the same as that of the first embodiment.

  While there are few errors in the row wiring drive voltage output in the range B in FIG. 22, there are many correction errors in the ranges A and C.

  As shown in FIG. 23, the above-described new Vn drive employs a method of increasing the drive voltage of the column wiring in the amplitude direction in the order of 241, 242, and 243 from 240 waveforms according to the input drive data. Since the change in the voltage amplitude is small in the period B in FIG. 23, the current change in one horizontal scanning period in the row wiring is very small.

  As shown in FIG. 24, the window mask can be realized by providing a switch 300 for turning on / off correction. The switch 300 is turned off only during the period B so that correction is performed only during the period B shown in FIG. In this way, the row wiring drive voltage output of FIG. 25 can be obtained using the window mask.

(Third embodiment)
In each of the embodiments described above, the example in which the Ron correction is performed on the multi-output row selection driver by the single operational amplifier 205 which is a common comparison unit has been described. In this embodiment, as shown in FIG. 26, an operational amplifier 503 is provided for each row wiring drive output, and potential information of the output terminal of the output buffer is input to the control input terminal 504. In this way, the gate voltage of the FET 502 can be directly driven by the operational amplifier 503 so that the output 501 becomes constant, and the output is corrected.

(Fourth embodiment)
In this embodiment, a new Vn drive is used for column wiring drive of a cold cathode display as a matrix panel, and a row selection driver reduces the row selection voltage drop caused by the on-resistance of the output transistor of the row selection driver by feedforward control. An example in which correction is performed by controlling the power supply voltage is shown.

  In the previous embodiment, the voltage drop due to the on-resistance 204 of the output of the row selection driver is corrected by feedback. However, since the drive data is determined in advance, it is possible to predict the voltage drop due to the on-resistance by calculation. Yes, there is no response delay, resulting in fewer correction errors.

  As shown in FIG. 27, drive data as gradation information such as a video signal input to the column wiring driver is converted into current data by a current converter 600. The converted current data is added by an adder 601 for one row (640 × 3 (RGB) = 1920 columns in the case of VGA), and the current flowing through all the column wirings is calculated.

The voltage drop amount calculator 603 calculates the voltage drop amount according to the value of the on-resistance 204, and calculates D / A
Output to the converter 602. At this time, if there is a voltage drop due to the lead-out wiring ahead of the output terminal 207, the influence of the voltage drop in the lead-out wiring can be corrected by calculating the corresponding resistance with a voltage drop calculator.

  Since the output of the D / A converter 602 is normally a voltage output of about 0 to 2 V and does not have a current drive capability, the output voltage correction circuit 202 performs voltage conversion and current amplification. The output of the output voltage correction circuit 202 subjected to the current amplification can control the power supply of the output buffer 203, and can correct the voltage drop due to the on-resistance 204, and further the voltage drop due to the resistance of the lead-out wiring beyond the output end.

(Fifth embodiment)
FIG. 28 shows a fifth embodiment of the present invention. In the first embodiment, the configuration for correcting the voltage drop mainly due to the on-resistance has been shown. However, in this embodiment, the voltage drop caused by other wiring resistance components can also be corrected.

  Since other configurations and operations are the same as those of the first embodiment, description of the same components will be omitted.

  More specifically, in this embodiment, the output voltage is compensated including a voltage drop caused by a resistance of a bonding wire connecting a bonding pad on a silicon substrate to be an integrated circuit and an IC lead of the package of the integrated circuit. It is configured to realize a cold cathode display driver.

  The entire driving circuit of the cold cathode panel is the same as that of the first embodiment, and the description is omitted here, and only the row driving circuit is described with reference to FIG.

  The output of the shift register 700 is connected to the output buffer 704, and drives the matrix wiring outside the IC through the IC lead 709 which is the output end of the IC package.

  Reference numeral 702 denotes the on-resistance (Ron) of the driver of the output buffer 704. Since the output current is large as described above, it is necessary to avoid the influence of the voltage drop.

  In the present embodiment, a matrix drive is performed for each row, and the fact that two rows are not driven at the same time is used to perform feedback control for 80 rows of output buffers in the IC by one external feedback circuit. It has become.

  For example, when outputting the first row, the output buffer 704 causes a voltage drop due to the on-resistance (Ron) 702.

  Further, the output of the output buffer 704 is connected to a bonding pad 703 on a silicon substrate by an aluminum wiring (not shown), and the bonding pad 703 is connected to an IC lead 709 of the package via a bonding wire 708.

  In this embodiment, in order to detect the voltage drop in the IC lead 709, that is, the sum of the voltage drop caused by the output buffer, the aluminum wiring (not shown), and the bonding wire, the bonding lead 709 detects the bonding wire from the IC lead 709. The potential detected via 708 is taken into the switch 706.

Almost no current flows from the IC lead 709 to the wiring entering the switch via the bonding wire 708 and the detection bonding pad 705. Therefore, the bonding wire and the aluminum wiring do not need to have a low resistance. Small is good.

  Based on the row information from the shift register 700 obtained via the parallel signal line 701, the signal input to the switch 706 causes the switch 706 to select the detection potential of the currently driven row from the detection potential. Switch.

  The detection signal selected by the switch 706 is amplified by the operational amplifier 707 and input to the output voltage correction circuit 710, and the output voltage correction circuit 710 outputs a compensation signal to the output buffer 704.

  Thus, by providing the detection bonding pad 705 for voltage feedback from the IC lead, the bonding wire 708, the switch 706, the feedback circuit 707, and the output voltage correction circuit 710, the on resistance of the output buffer 704, the aluminum wiring resistance, It becomes possible to detect a voltage drop caused by all the resistances of the bonding wire resistance. By correcting this voltage drop, the apparent resistance value can be brought close to 0Ω, so that the chip area can be reduced and a low-cost semiconductor integrated circuit can be configured.

(Sixth embodiment)
FIG. 29 shows a sixth embodiment of the present invention.

  A flexible wiring is often used to connect the row wiring of the matrix panel and the IC. The influence of the voltage drop due to the resistance here cannot be ignored.

  Therefore, the resistance of the flexible wiring can be compensated by connecting as shown in FIG.

  In FIG. 29, reference numeral 717 denotes a bonding pad connected to the output buffer of the row drive circuit, and is connected to the corresponding output IC lead 712 by a bonding wire 711.

  Reference numeral 716 denotes a bonding pad for detecting potential information, which is also connected to an IC lead 715 for inputting potential information outside the IC by a bonding wire 711. The bonding pad 716 is connected to the switch means 706 in the IC chip, similarly to the circuit of FIG.

  The output voltage from the output IC lead 712 is connected to the row wiring 714 of the matrix panel through the flexible wiring 713. The resistance of the flexible wiring causes a voltage drop to some extent because the wiring pitch is narrowed as the resolution of the display panel is increased.

  When the row drive circuit chip is mounted on the flexible wiring as in the tape carrier package (TCP), the bonding wire 711 and the lead 715 in FIG. 29 are omitted, and the pad 716, directly on the inner lead of the flexible wiring. 717 may be bonded. In addition, the row driving circuit chip may be directly flip-chip mounted on the substrate constituting the matrix panel, such as COG. In this case, if the potential information of the output terminal of the output buffer is monitored, This is the same as monitoring the potential information of the input terminals of the matrix panel.

(Seventh embodiment)
The essence of this embodiment is a matrix panel driving device in which modulation elements are arranged at intersections of matrices formed by row wirings and a plurality of column wirings, and a row for supplying a row signal to the row wirings. A drive circuit (FIG. 30); and a column drive circuit for supplying a modulation signal modulated in accordance with gradation information to the plurality of column wirings, and potential information of the output terminal 207 of the row drive circuit The first correction circuit (206, 205, 214, 203) for correcting the voltage of the row signal by feeding back the resistance of the connecting member between the output terminal and the matrix panel and the current flowing therethrough And a second correction circuit (216, 215, 205, 214, 203) for correcting a voltage drop due to the above. As the second correction circuit, the connection member includes Flowing current Detected and converted into a voltage based on the current detected using the adjusting element 218 having a resistance value set in advance according to the resistance value of the connection member, and based on that, the voltage of the row signal is converted. It is good to correct.

  Details are described below.

  FIG. 30 shows a seventh embodiment of the present invention. In the fifth embodiment, in order to compensate for the output voltage including the voltage drop caused by the resistance of the bonding wire connecting the bonding pad and the IC lead, the potential in the row driving circuit chip is set via the potential detection bonding pad 705. The configuration to return to was adopted.

  In the present embodiment, a configuration is shown in which a voltage drop due to a resistance component outside the chip is compensated by detecting a current flowing into the output buffer of the row drive circuit chip.

  Other configurations and operations are the same as those in the first embodiment.

  FIG. 30 is a circuit diagram of the row driving circuit chip.

  In the circuit configuration shown in FIG. 30, each row is selected for each row by shifting the row selection signal in order from the top by the shift register 201. The output of the shift register 201 is input to the output buffer 203. The row selection signal from the output buffer 203 is supplied to the row wiring of the matrix panel connected thereto through the output terminal 207 of the row driving circuit chip, and drives the display element connected to the row wiring.

  At this time, in this embodiment, the voltage drop due to the ON resistance 204 of the output buffer 203 is corrected by feedback, and the voltage drop due to the resistance of the wiring member connecting the row driving circuit chip and the matrix panel is corrected by feedforward.

  The method of correcting the voltage drop due to the on-resistance 204 of the output buffer 203 and the current flowing therethrough by feedback is the same as in the above-described embodiment. That is, a row where potential information is to be detected is selected by the multiplexer 206 and input to the operational amplifier 205 as a control circuit. Since the operational amplifier 205 controls the transistor 214 constituting the output voltage correction circuit, the power supply voltage supplied to the output buffer 203 can be changed. Thus, when the voltage drop increases due to the current flowing through the transistor of the output buffer 203 and its on-resistance, feedback is applied, and the voltage of the row selection signal (difference from the row non-selection voltage) increases. Correction is made.

  On the other hand, the resistance of the connecting member connecting the row driving circuit and the matrix panel and the voltage drop due to the current flowing therethrough determine the values of the resistors 217, 216 and 218 in FIG. 30 according to the resistance value of the connecting member. That is, it is corrected by feedforward.

  The operational amplifier 205 controls the control electrode (gate electrode) of the p-channel power supply control transistor 214 to control the output voltage of the power supply control transistor 214. The output voltage of the power supply control transistor 214 is the power supply voltage of the output buffer 203.

  The power supply control FET 214 is connected to the reference voltage VEE via the output current detection resistor 217. Since a current flows through the resistor 217, the FET 214, and the transistor of the output buffer, a reference voltage control transistor (current detection transistor) The voltage of the control electrode (base electrode) of the transistor 215 changes in proportion to the output current flowing through each selected output buffer 203 of the row drive circuit chip.

  When the current flowing into the output buffer 203 increases, the base voltage of the reference voltage control transistor 215 is increased by the resistor 217. Since the base voltage increases, the collector current of the NPN-type reference voltage control transistor 215 increases. The collector current is limited by the current limiting resistor 216, and is approximately (current of the resistance of the resistor 217) / (resistance value of the limiting resistor 216) of the current flowing through the resistor 217. The reference voltage ref input to the operational amplifier 205 is lowered by this current and the reference voltage limiting resistor 218. When the reference voltage ref of the operational amplifier 205 is lowered, the output voltage of the operational amplifier 205 is lowered, so that the output voltage of the output buffer 203 is also changed.

  Since the resistance value of the connection member that connects the row drive circuit chip and the matrix panel is known in advance, the values of the output current detection resistor 217, the current limiting resistor 216, and the reference voltage limiting resistor 218 can be determined according to the resistance values. For example, a voltage obtained by adding a voltage drop due to the resistance of the connection member can be output to the output terminal 207 of the row drive circuit chip. That is, the current flowing through the connection member through the selected output terminal 207 is detected, and the current flowing through the corresponding transistor 214 is converted into voltage and fed back to the operational amplifier 205.

  In other words, it can be regarded that the voltage drop due to the resistance of the connecting member is corrected by feeding back the resistance value of the connecting member by feeding back the value of the current flowing through the connecting member. Therefore, the voltage drop in one current path that is not branched from the output terminal can be arbitrarily corrected by setting the reference voltage limiting resistor 218 and the like. That is, the definition of the connecting member that can be corrected is not uniquely determined but can be arbitrarily determined. Therefore, the connection member is defined from the output terminal 207 to the electrode of the element closest to the output terminal 207 of the matrix panel, and the resistance value of that portion is measured or calculated in advance, and the reference voltage limiting resistor 218 is accordingly measured. If the setting is made, the voltage drop in the portion can be corrected. Thus, according to the present embodiment, the on-resistance, the resistance of the wiring member, and the voltage drop due to the current flowing therethrough can be corrected.

(Eighth embodiment)
The main part of the drive circuit including the correction circuit described above is shown in FIG. In this embodiment, in a driving circuit having a driving output terminal connected to a light emitting element or an electron emitting element via a connecting member, a pair of main electrodes are connected to the driving output terminal side and the reference voltage source side Drive transistor, an operational amplifier as a control circuit for controlling an output voltage output from the drive transistor (power supply control transistor), and a detection transistor for detecting a current flowing through the drive transistor A correction circuit for correcting an output voltage from the drive output terminal, and the correction circuit detects a current flowing through the detection transistor and performs the control. It has a feedback loop that feeds back to an operational amplifier as a circuit.

In FIG. 33, a driving circuit having a driving output terminal 207 connected to a modulation element 800 such as a light emitting element (laser diode, light emitting diode, EL element) or an electron emitting element via a connecting member 801 is the driving circuit. A driving transistor 214 having a pair of main electrodes (source and drain) connected to the output terminal 207 side and the reference voltage source 804 side, and a control circuit for controlling the output voltage output from the driving transistor 214 The operational amplifier 205 and a detection transistor 215 for detecting the current flowing through the driving transistor 214, and the output voltage of the driving output terminal 207 is detected and fed back to the operational amplifier 205. 1 and the operational amplifier by detecting the current flowing through the detection transistor 215. A second feedback loop 803 is fed back to the 05, includes a, are provided with a correction circuit for correcting the output voltage from the drive output terminal 207.

  Strictly speaking, the output voltage is not the voltage of the drive output terminal 207 but the voltage of the detection node 207 ′, which is designed by the resistance between the terminal 207 and the node 207 ′. It is obvious to those skilled in the art that the detection node 207 ′ may be considered as the drive output terminal 207 if it cannot be ignored.

Here, for simplification, ignoring the base current of the detection transistor 215 and the base-emitter voltage Vbe, the on-resistance value of the driving transistor 214 is Ro, the resistance value of the resistor 217 is R1, and the resistance The resistance value of 216 is R2, the resistance value of the resistor 218 as an adjustment element is R3, the current flowing through the driving transistor 214 is i1, the current flowing through the detection transistor 215 is i2, and i1 is about several hundred times i2. R1 and R2 are set so that

  Since the correction using the first feedback loop 802 is as described above, the description thereof is omitted.

  When i1 flows as a drive current, a forward bias is applied between the base and emitter of the transistor 215 by the resistor 217, and a current i2 flows between the collector and emitter of the transistor 215. Since this current i2 is a small current proportional to the driving current flowing through the driving transistor 214, a voltage drop occurs in the correction reference voltage Ref and the resistor 218 connected to the non-inverting input terminal of the operational amplifier 205, The potential of the non-inverting input terminal changes based on the current i2 and the resistor R3. In response to this change, the output value of the operational amplifier 205 changes, so that the voltage of the control electrode (gate) of the driving transistor 214 changes, and the transistor 214 is controlled in the direction in which more current flows.

  That is, assuming that the current flowing through the output terminal 207 is Io, the potential of the output terminal 207 is Vo, and the potential of the reference voltage Ref is Vref, Vo = Vref−Io · R1 / R2 · R3. Thus, when Io changes, the potential of the output terminal 207 also changes according to the voltage determined by each resistor (216, 217, 218) as the adjustment element, so that the resistance value of the adjustment element is the resistance value of the connecting member. If the value is set in accordance with, the potential of the output terminal can be further lowered to correct the voltage drop in the connecting member.

  When a switch of the multiplexer 206 is inserted between the node 207 ′ and the operational amplifier 205 and a switching transistor of the output buffer 203 is inserted between the node 207 ′ and the transistor 214, one row of the configuration of FIG. It becomes.

(Ninth embodiment)
The present embodiment is a matrix panel driving device in which modulation elements are arranged at intersections of matrices formed by row wirings and a plurality of column wirings, and a row drive for supplying a row signal to the row wirings. A circuit and a column driving circuit for supplying a modulation signal modulated in accordance with gradation information to the plurality of column wirings, and feeding back the potential information of the output terminal of the row driving circuit to return the row As a first correction circuit for correcting a voltage of a signal, and a second correction circuit for correcting a voltage drop due to a resistance of a connection member between the output terminal and the matrix panel and a current flowing therethrough, A feedforward circuit for correcting the row signal according to the gradation information is provided.

  That is, in the embodiment of FIG. 30, as the second correction circuit, the column drive circuit side detects the gradation information from the image data, and obtains a current value that will flow through the row wiring during driving. Accordingly, the row signal is corrected. Such a feedforward circuit employs the same configuration as that of the embodiment shown in FIG. 27, and Ron can be corrected by the first correction circuit. Therefore, the calculation may be performed in consideration of the resistance value of the connecting member.

It is a block diagram for demonstrating the basic composition of the drive apparatus of the matrix panel of this invention. It is a figure which shows the modulation signal waveform by a comparative example, and the modulation signal waveform used for this invention. It is a block diagram for demonstrating the basic composition of the drive device of another matrix panel of this invention. It is a top view which shows an example of the element structure of the surface conduction type | mold emission element used for this invention. It is sectional drawing which shows an example of the element structure of FE type | mold used for this invention. It is sectional drawing which shows an example of a MIM type | mold element structure used for this invention. 1 is a block diagram of a multi-electron source drive circuit according to a first embodiment of the present invention. It is a schematic diagram for demonstrating operation | movement of a data conversion circuit. It is the figure which showed the operation | movement flowchart of a data conversion circuit. It is a block diagram of a column drive circuit. It is a figure for demonstrating the relationship between the modulation signal waveform used for this invention, and drive data. It is a block diagram showing the internal configuration of the PWM circuit. It is a block diagram showing the internal configuration of the output stage circuit in the column drive circuit. It is a figure which shows the PWM modulation signal waveform and the current waveform which flows into the selected row wiring. It is a figure which shows the PWM modulation signal waveform used for this invention, and the current waveform which flows into the selected row wiring. It is a figure which shows another PWM modulation signal waveform used for this invention, and the current waveform which flows into the selected row wiring. 1 is a block diagram of a row drive circuit according to a first embodiment of the present invention. It is a circuit diagram of a multiplexer. It is a circuit diagram which shows an example of an output buffer and an output voltage correction circuit. It is a circuit diagram which shows another example of an output buffer and an output voltage correction circuit. It is a figure which shows the voltage output of the row drive circuit by a comparative example. It is a figure which shows the voltage output of the row drive circuit by one Embodiment of this invention. It is a figure which shows the modulation signal waveform used for this invention. It is a block diagram of the row drive circuit used for another embodiment of the present invention. It is a figure which shows the voltage output of a row drive circuit. It is a circuit diagram which shows the output buffer and correction | amendment circuit in the row drive circuit used for another embodiment of this invention. FIG. 6 is a block diagram of a driving device for a matrix panel according to another embodiment of the present invention. It is a block diagram of the row drive circuit used for further another embodiment of this invention. It is a figure which shows the connection structure of the matrix panel and row drive circuit which are used for another embodiment of this invention. 1 is a block diagram of a matrix panel driving apparatus according to an embodiment of the present invention; FIG. It is a figure which shows the electrical constitution of a matrix panel. It is a figure which shows the output waveform of the conventional column drive circuit and row drive circuit. 1 is a circuit configuration diagram of a matrix panel drive device according to an embodiment of the present invention; FIG.

Explanation of symbols

1 Electron source (electron emitter)
2 column wiring 3 row wiring 4 5 wiring resistance 101 multi electron source 102 modulation circuit (column wiring driver)
103 Scanning circuit (row wiring driver)
104 Timing generation circuit 105 Data conversion circuit 106 Multi power supply circuit 107 Shift register 108 PWM circuit 109 Output stage circuit 110 Latch 111 V1 start circuit 112 V2 start circuit 113 V3 start circuit 114 V4 start circuit 115 V1 end circuit 116 V2 end circuit 117 V3 End circuit 118 V4 end circuit 119 V1PWM generation circuit 120 V2PWM generation circuit 121 V3PWM generation circuit 122 V4PWM generation circuit 201 Shift register 202 Output voltage correction circuit 203 Output buffer 204 On-resistance (Ron)
205 Control circuit (operational amplifier)
206 Multiplexer 207 Output terminal 210 Input terminal of multiplexer 211 P-channel FET
212 Output terminal of multiplexer 213 N channel FET
214 FET for power supply control
215 Reference voltage control transistor 216 Current limiting resistor 217 Output current detection resistor 218 Reference voltage limiting resistor 220 Input terminal 221 Pre-buffer P-channel FET
222 P-channel FET with final buffer
223 N-channel FET with pre-buffer
224 Reference input 225 Operational amplifier 226 Final buffer N-channel FET
227 P-channel FET for power supply voltage control
228 Output terminal 230 Row selection signal input 231 PNP transistor 232 NPN transistor 233 Input terminal 234 PNP transistor 235 Output terminal 240 Modulation signal waveform for low gradation 241 Modulation signal waveform for medium gradation 242 For medium gradation Modulation signal waveform 243 Modulation signal waveform for high gradation 300 Feedback on / off switch 500 P-channel FET
501 Row selection signal output terminal 502 N-channel FET
503 operational amplifier 504 N-channel FET
505 Row selection signal input terminal 600 Current converter 601 Adder 602 D / A converter 603 Voltage drop calculator 700 Shift register 701 Signal line 703 Bonding pad 704 Output buffer 705 Detection bonding pad 706 Switch 707 Operational amplifier 708 Bonding wire 709 Lead 710 Output voltage correction circuit 711 Bonding wire 712 Lead 713 Flexible wiring 714 Row wiring 715 Lead 716 Bonding pad 717 Bonding pad 800 Modulating element 801 Connection member 802 First feedback loop 803 Second feedback loop 804 Reference voltage source 3001 Substrate 3004 Conductivity Thin film 3005 electron emitting portion 3010 substrate 3011 emitter wiring 3012 emitter cone 3013 insulating layer 014 gate electrode 3020 substrate 3021 under the electrode 3022 insulating layer 3023 above the electrode

Claims (5)

A matrix panel driving device in which a modulation element is arranged at an intersection of a matrix formed by row wiring and a plurality of column wirings,
A row driving circuit for supplying a row signal to the row wiring;
A column driving circuit for supplying a modulation signal modulated in accordance with gradation information to the plurality of column wirings;
A first correction circuit for correcting the voltage of the row signal by feeding back potential information of the output terminal of the row driving circuit;
A second correction circuit for correcting a voltage drop caused by a resistance of a connection member between the output terminal and the matrix panel and a current flowing therethrough;
A drive device comprising: In a drive circuit having a drive output terminal connected to a light emitting element or an electron emitting element via a connection member,
A driving transistor having a pair of main electrodes connected to the driving output terminal side and the reference voltage source side; a control circuit for controlling an output voltage output from the driving transistor; and the driving transistor A detection transistor for detecting a flowing current, and a correction circuit for correcting an output voltage from the drive output terminal,
The drive circuit according to claim 1, wherein the correction circuit includes a feedback loop that detects a current flowing through the detection transistor and feeds back the current to the control circuit. In a drive circuit having a drive output terminal connected to a light emitting element or an electron emitting element via a connection member,
A driving transistor having a pair of main electrodes connected to the driving output terminal side and the reference voltage source side; a control circuit for controlling an output voltage output from the driving transistor; and the driving transistor A detection transistor for detecting a flowing current, and a correction circuit for correcting an output voltage from the drive output terminal,
The correction circuit detects a voltage output from the drive output terminal and feeds it back to the control circuit; and a correction circuit detects a current flowing through the detection transistor and feeds back to the control circuit. A drive circuit comprising a feedback loop. A matrix panel having a plurality of row wirings and a plurality of column wirings, and a plurality of modulation elements respectively arranged at intersections of a matrix formed by the plurality of row wirings and the plurality of column wirings;
Driving means for driving the matrix panel;
A connection member for electrically connecting the matrix panel and the driving means and supplying a signal for driving the modulation element;
In an image display device comprising:
The drive means
A driving transistor having a pair of main electrodes connected to a driving output terminal side and a reference voltage source side for supplying the signal; a control circuit for controlling an output voltage output from the driving transistor; A detection transistor for detecting a current flowing through the drive transistor, and a correction circuit for correcting an output voltage from the drive output terminal,
The image display apparatus, wherein the correction circuit includes a feedback loop that detects a current flowing through the detection transistor and feeds back the current to the control circuit.   Using the adjustment element having a resistance value set in advance according to the resistance value of the connection member, the detected current flowing through the detection transistor is converted into a voltage, and the output voltage is corrected based on the voltage. The image display device according to claim 4.

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