JP3795043B2 - Associative memory, search method therefor, router and network system - Google Patents

Description

  The present invention relates to an associative memory, a search method thereof, a router, and a network system. In particular, the present invention relates to an associative memory having a search mask function, a search method thereof, and a router and a network system using the same.

  In a network router (hereinafter referred to as “router”) used in a conventional computer network system, a function for calculating an optimum transfer destination is indispensable as shown below.

  A connection example of the configuration of a conventional computer network is shown in FIG. A user device participating in a network (eg, a computer terminal) is assigned a specific network address according to a predetermined rule when that device joins the network in order to distinguish it from other user devices. . Here, description will be made assuming that the network address is expressed by a multi-digit numerical value, for example, a 4-digit numerical value (abcd). In addition, the predetermined rule is, for example, the first numerical value of the network address indicates the country of England, Germany, Japan, etc., the second numerical value indicates the city name in the country, and the third numerical value. It shows a hierarchical structure, such as showing the name of a company in the city. Hereinafter, this hierarchy is referred to as a segment. FIG. 19 schematically shows the hierarchical structure of segments. In the figure, one rectangle surrounded by a thick line is one segment. In FIG. 19, the segment 1 with the first numerical value of the network address, the segment 2 with the first numerical value of 2, and the segment 3 with the first numerical value of 3 exist as the highest segment. . There is a segment 4 having a network address whose upper two numerical values are 1.2 in the hierarchy below the segment 1, and a segment having a network address whose upper three numerical values are 1.2.2 below it. 6 and a user equipment PC 401-1 having a network address of 1.2.2.1 is connected thereto. Further, there is a segment 5 having a network address whose upper two numerical values are 2.1 in the lower layer of the segment 2, and a network address whose upper three numerical values are 2.1.1 is further below that. There is segment 7 to have. In the address illustrated in the figure, * means don't care.

  Each segment has a router for transferring communication data between user devices participating in the network. 19, the segment 1 is the router 400-1, the segment 2 is the router 400-2, the segment 3 is the router 400-3, the segment 4 is the router 400-4, and the segment 5 is the router 400-5. Segment 6 has a router 400-6, and segment 7 has a router 400-7. The router in the segment calculates the optimal transfer route based on the connection relationship between the transfer destination address and the network device attached to the transfer data, based on the transfer data input from the user device or other router connected to the router. Then, the data is transferred to the transfer destination via the optimum route. In the configuration example of FIG. 19, each router is connected to a router or user equipment directly under the segment. The router 400-3 is also connected to the router 400-1, the router 400-4, the router 400-6, the router 400-2, and the router 400-7.

  Instead of connecting each user device directly with a communication line, the communication control function of the router is used to control the transfer of communication data for communication, thereby efficiently using a finite communication line.

Next, these routers will be described with reference to FIG. Although the router 400-3 is shown as an example in the figure, other routers have the same configuration.
The router 400-3 stores network address information of segments other than the network address (3. *. *. *) Of the segment to which the router 400-3 belongs. Each of these network addresses is assumed to be represented by a bit string of 8 bits as a whole in which each digit is represented by a quaternary number. For example, the network address (1. *. *. *) Is represented by a bit string (01.00.00.00). Hereinafter, the bit string of this expression is referred to as stored data. Here, since * is don't care, it is necessary to indicate that the upper 2 bits of the bit string of (01.00.00.00) are valid and the bits below are invalid. Therefore, information called mask information is stored in pairs with stored data. In this example, it is (00.11.11.11). Here, “0” indicates a mask invalid state and “1” indicates a mask valid state. These stored data and mask information are stored in the content addressable memory 116 in the router as shown in the figure. The associative memory word 117-1 stores the network address (1. *. *. *) Of segment 1 to which the router 400-1 belongs. The associative memory word 117-2 stores the network address (2. *. *. *) Of segment 2 to which the router 400-2 belongs. The associative memory word 117-3 stores the network address (1.2.2. *) Of the segment 6 to which the router 400-6 belongs. The associative memory word 117-4 stores the network address (1.2. *. *) Of the segment 4 to which the router 400-4 belongs. The associative memory word 117-5 stores the network address (2.1.1. *) Of the segment 7 to which the router 400-7 belongs. The associative memory 116, in addition to the function of writing and reading stored data by designating an address in the same manner as a normal memory, stores matching data as a result of comparison with input search data 102 in consideration of corresponding mask information. In the data, the mask matching lines 119-1 to 119-5 corresponding to the stored data having the least number of valid bits of the mask information have a function of valid. The mask match lines 119-1 to 119-5 output from the associative memory 116 are encoded into the memory address signal 403 by the encoder 402.

  The memory 404 stores the network address of the router corresponding to the network address of the segment constituted by the storage data and the mask information stored in each associative memory word of the associative memory 116, and the storage address of the associative memory 116. It is stored in the word at the same address. For example, the address (1. *. *. *) Is stored in the associative memory word 1 of the associative memory 116, and the network address of the router 400-1 in FIG. 1 is stored. Similarly, the address of router 400-2 is stored in word 2 of memory 404, the address of router 400-6 is stored in word 3, the address of router 400-4 is stored in word 4, and the address of router 400-7 is stored in word 5. The address is stored. The memory 404 outputs the storage data specified by using the memory address signal 403 as a read address as the memory data signal 405.

  The cooling device 414 cools the conventional associative memory 116 that generates a large amount of heat. This is composed of, for example, an air cooling fan.

  Although not shown in the figure, each router has a CPU therein, and the operation of the router is controlled by the CPU.

  Next, an operation example of data transfer in a conventional network controlled by each router will be described. For example, when the destination network address of the transfer data input to the router 400-3 is (1.2.1.1), searching in the conventional associative memory 116 (1. *. *) Of the associative memory word 1 . *) And (1.2. *. *) Of the associative memory word 4 match, but among them, the mask match line 119 corresponding to the associative memory word 4 having the least number of valid bits of the mask information. Only -4 is valid. As a result, the encoder 402 outputs “4” as the memory address 403, and the memory 404 outputs the network address of the router 400-4 as the memory data signal 405. Thereby, the router 400-3 transfers the input transfer data of the destination address (1.2.1.1) toward the router 300-4. The router 300-4 performs the same operation as described above based on the transferred data, transfers the data to the router one after another, and connects to the network address (1.2.1.1) of the final destination. Transfer data to the user equipment.

  FIG. 15 is a block diagram showing a configuration example of a conventional associative memory. Conventionally, as this type of associative memory, for example, one disclosed in Japanese Patent Application Laid-Open No. 11-073782 can be cited. The associative memory 116 includes an n-bit 2-input 1-output selector 128, an n-bit m-word associative memory word 117-1 to 117-m, an n-bit latch 126, and a control circuit 131. The memory word 117-j includes n associative memory cells 118-j-1 to 118-jn and one latch 123-j. Each associative memory word 117-j is connected with a corresponding data word line 106-j, mask word line 111-j for input, a corresponding mask match line 119-j, and n shortest lines. Mask lines 122-1 to 122-n are connected for output, and n bit lines 103-1 to 103-n are connected for input / output.

  Each associative memory cell 118-j-k is connected with a corresponding data word line 106-j and mask word line 111-j for input, and has a corresponding data match line 107-j and mask match line. 119-j and the shortest mask line 122-k are connected for output, and the bit line 103-k is connected for input / output.

  Each associative memory cell 118-jk stores data cells 108-jk storing bit information corresponding to stored data input from the outside via bit lines 103-k, and stores them in the data cells. A comparator 113-j-k for comparing the received bit information with the corresponding bit information 102-k of the search data 102 input from the outside, and mask information input from the outside via the bit line 103-k Mask cell 112-j-k storing corresponding bit information, bit information stored in the mask cell, and corresponding bit information 127-k of shortest mask information 127 output from n-bit latch 126 A mask comparator 120-jk for comparison and a logic gate 121-jk are provided.

  In this example, the valid state of the mask information is “1”, the invalid state is “0”, the valid state of the shortest mask lines 122-1 to 122-n is “1”, and the invalid state is “0”. . The valid state of the data match lines 107-1 to 107-m is “1”, and the invalid state is “0”. Further, the valid state of the mask coincidence lines 119-1 to 119-m is set to “1”, and the invalid state is set to “0”.

  The data cells 108-1-1 to 108 -mn are stored as stored data when the corresponding data word line 106 is valid, and write data is driven to the corresponding bit line 103. If the bit line 103 to be driven is not driven, the stored data stored therein is output to the corresponding bit line 103. If the corresponding data word line 106 is in an invalid state, no operation is performed on the bit line 103. Regardless of the value of the corresponding data word line 106, the stored data is output to the comparator 113 in the same associative memory cells 118-1-1-1 to 118-mn.

  The mask cells 112-1-1 to 112 -mn store the write data as mask information if the corresponding mask word line 111 is valid and the write data is driven to the corresponding bit line 103. If the corresponding bit line 103 is not driven, the stored mask information is output to the corresponding bit line 103. If the corresponding mask word line 111 is in an invalid state, no operation is performed on the bit line 103. Regardless of the value of the corresponding mask word line 111, the stored mask information is output to the comparator 113 in the same associative memory cells 118-1-1-1 to 118-mn.

  The data match line 107 is precharged to a high level before the search operation is started, or is pulled up by a resistor (not shown) and is in a valid state “1”.

  The comparator 113 inputs the corresponding bit line 103 and the stored data of the data cell 108 and the mask information of the mask cell 112 in the same associative memory cells 118-1-1-1 to 118-mn. If the mask information is valid or the value of the bit line 103 matches the stored data, the corresponding data match line 107 is opened, otherwise the invalid state “0” is output. When all n comparators 113 in the associative memory word 117 have the data match line 107 open, the data match line 107 is in the valid state “1”, otherwise, the invalid state “ A wired AND logical connection of 0 ″ is configured. That is, at the time of the search operation, only when the storage data stored in the associative memory word 117 and the bit lines 103-1 to 103-n completely match except for the bits excluded from the comparison target by the mask information, The data match line 107 is in the valid state “1”, otherwise it is in the invalid state “0”. Of course, a normal logic gate may be used for the same operation.

  The logic gates 121-1-1 to 121 -m-n have the data matching lines 107-1 to 107 -m in the same associative memory word 117-1 to 117 -m being in the valid state “1” and the same. When the mask information stored in the mask cells 112-1-1-1 to 112-mn in the associative memory cells 118-1-1-1 to 118-mn is the invalid state “0” The invalid state “0” is output to the shortest mask lines 122-1 to 122-n to be performed, and in other cases, the inactive state is set.

  Each of the shortest mask lines 122-1 to 122-n is pulled up by resistors 125-1 to 125-n, and the corresponding m logic gates 121-1 to 121-mn and a wired AND. Configures a logical connection. Therefore, when all the m logic gates 121 connected have the shortest mask line 122 open, the shortest mask line 122 is in the valid state “1”, otherwise it is in the invalid state “0”. It becomes.

  The latches 123-1 to 123-m are connected to the data match lines 107-1 to 107-m in the same associative memory word 117-1 to 117-m when the latch control line 124 is in the valid state. To store. In order to output the stored state, wired logical connection is made corresponding to the mask match lines 119-1 to 119-m in the same associative memory word 117-1 to 117-m. The latches 123-1 to 123-m output “0” to the corresponding mask match lines 119-1 to 119-m when the stored data is in the invalid state “0”, and the stored data Is in the valid state “1”, the corresponding mask coincidence lines 119-1 to 119-m are opened.

  The mask match lines 119-1 to 119-m correspond to the stored data with the smallest number of bits excluded from the search target by the mask information among the stored data that matches the search data 102 at the end of the search operation. Only becomes valid, otherwise it becomes invalid. The mask coincidence lines 119-1 to 119-m are pulled up by a resistor (not shown) before the search operation is started, or are pre-charged to a high level to be in the valid state “1”. To do.

  The mask comparator 120 compares the state of the mask information stored in the corresponding mask cell 112 with the shortest mask information on the corresponding bit line 103, and if it matches, sets the corresponding mask match line 119 to the open state. If they do not match, an invalid state “0” is output to the corresponding mask match line 119. Therefore, when the n associative memory cells 118 in the associative memory word 117 and the one latch 123 all have the mask match line 119 open, the mask match line 119 is in the valid state “1”. In other cases, a wired AND logical connection in which the invalid state is “0” is configured.

  That is, during the search operation, the mask information stored in the associative memory word 117 and the bit lines 103-1 to 103-n completely match, and the state of the data match line 107 stored in the latch 123 is Only in the valid state “1”, the mask match line 119 is in the valid state “1”, and in other cases, it is in the invalid state “0”. The n-bit latch 126 stores the state of the shortest mask lines 122-1 to 122-n inside when the latch control signal 124 is valid. Further, the stored state is output to the latch output lines 127-1 to 127-n.

  The n-bit 2-input 1-output selector 128 selects the data to be output to the bit lines 103-1 to 103-n and the search data 102-1 to 102-n and the latch output lines 127-1 to 127 according to the state of the selection signal 129. Select from one of -n.

  The control circuit 130 outputs a latch control signal 124 and a selection signal 129 in synchronization with the clock signal 130 in order to control the operation of the associative memory 116.

  Next, FIG. 16 shows an example of the configuration of a conventional content addressable memory cell 118. Here, the two bit lines 103a and 103b correspond to the bit lines shown in FIG. 15, but are represented by 103-i in FIG. Data is read from and written to the memory cell and search data 102 is input via these two bit lines. When writing data or inputting search data, a value obtained by inverting the value of the bit line 103a is input to the bit line 103b. The data cell 108 has an inverted logic gate (G101) 301, an inverted logic gate (G102) 302, and an output of the inverted logic gate (G102) 302, whose inputs and outputs are connected to each other, connected to the bit line 103a to form a data word The MOS transistor (T101) 303, which becomes conductive when the line 106 is high level, and the output of the inverting logic gate (G101) 301 are connected to the bit line 103b, and is conductive when the data word line 106 is high level. This is a general static SRAM element constituted by the MOS transistor (T102) 304 to be in a state.

  The mask cell 112 is also connected to the inverted logic gate (G103) 309, the inverted logic gate (G104) 310, and the output of the inverted logic gate (G104) 310 whose inputs and outputs are connected to each other and connected to the bit line 103a. When the output of the MOS transistor (T107) 311 and the inversion logic gate (G103) 309, which are in a conductive state when the word line 111 is high level, is connected to the bit line 103b and the mask word line 111 is high level This is a general static SRAM element constituted by a MOS transistor (T108) 312 which is in a conductive state.

  The comparator 113 includes a MOS transistor (T103) 305, a MOS transistor (T104) 306, a MOS transistor (T105) 307, and a MOS transistor (T106) 308. The MOS transistor (T103) 305 and the MOS transistor (T104) 306 are inserted in series between the bit lines 103a and 103b. The MOS transistor (T103) 305 becomes conductive when the output of the inverting logic gate (G101) 301 in the data cell 108 is at a high level. The MOS transistor (T104) 306 becomes conductive when the output of the inverting logic gate (G102) 302 in the data cell 108 is high. The MOS transistor (T105) 307 and the MOS transistor (T106) 308 are inserted in series between the low potential and the data matching line 107. The MOS transistor (T105) 307 becomes conductive when the potential at the connection point between the MOS transistor (T103) 305 and the MOS transistor (T104) 306 is high. The MOS transistor (T106) 308 becomes conductive when the output of the inverting logic gate (G103) 309 in the mask cell 112 is at a high level. When both the output of the bit line 103a and the inversion logic gate (G101) 301 are at a high level, or both the output of the bit line 103b and the inversion logic gate (G102) 302 are at a high level, the MOS transistor (T103) 305 and the MOS The connection point of the transistor (T104) 306 becomes high level, and the MOS transistor (T105) 307 is turned on.

  Therefore, when the stored data stored in the data cell 108 and the search data 102 on the bit lines 103a and 103b are different, the MOS transistor (T105) 307 becomes conductive. The MOS transistor (T106) 308 is open when the mask information stored in the mask cell 112 is "1", and is conductive when "0". It is assumed that the data match line 107 is pulled up to a high potential by a resistor (not shown) or precharged to a high potential before the search operation is started. As a result, when a plurality of associative memory cells 118 are connected to the data match line 107 via the MOS transistor (T106) 308, if one associative memory cell 118 outputs a low level, the data match The line 107 has a wired AND connection that is at a low level.

  The associative memory cell 118 outputs an invalid state “0” to the data match line 107 when both the MOS transistor (T105) 307 and the MOS transistor (T106) 308 are conductive, and otherwise the data match line 107 is opened. State. That is, when the mask information is “1”, the data match line 107 is always opened, and when the mask information is “0”, it is stored in the search data 102 and the data cell on the bit lines 103a and 103b. When the stored data matches, the open state is set, and when they are different, the invalid state “0” is output.

  Next, functions of the logic gate 121 and the shortest mask line 122 will be described. The shortest mask line 122 is pulled up by the resistor 125 of FIG. 15 and is in a valid state “1” before the search operation. The logic gate 121 includes a MOS transistor (T109) 313 and a MOS transistor (T110) 314 inserted in series between the shortest mask line 122 and a low potential. The MOS transistor (T109) 313 is conductive when the data match line 107 is in the valid state “1”, and is open when the data match line 107 is in the invalid state “0”. The MOS transistor (T110) 314 is conductive when the output of the inversion logic gate (G103) 309 in the mask cell 112 is high level, and is open when the output is low level. That is, when the mask information stored in the mask cell 112 is in the invalid state “0”, the conductive state is established, and when the mask information is in the valid state “1”, the open state is established. Thus, the logic gate 121 outputs the invalid state “0” to the shortest mask line 122 when the data match line 107 is in the valid state “1” and the mask information stored in the mask cell 112 is in the invalid state “0”. Otherwise, it is opened.

  Next, functions of the mask comparator 120 and the mask coincidence line 119 will be described. It is assumed that the mask match line 119 is pulled up to a high potential by a resistor (not shown) or precharged to a high potential before the search operation is started.

  The mask comparator 120 includes a MOS transistor (T111) 315, a MOS transistor (T112) 316, and a MOS transistor (T113) 317. The MOS transistor (T111) 315 and the MOS transistor (T112) 316 are inserted in series between the bit lines 103a and 103b. The MOS transistor (T111) 315 becomes conductive when the output of the inversion logic gate (G103) 309 in the mask cell 112 is at a high level. The MOS transistor (T112) 316 becomes conductive when the output of the inverting logic gate (G104) 310 in the mask cell 112 is at a high level. The MOS transistor (T113) 317 is inserted between the low potential and the mask match line 119. The MOS transistor (T113) 317 becomes conductive when the potential at the connection point between the MOS transistor (T111) 315 and the MOS transistor (T112) 316 is high.

  When both the output of the bit line 103a and the inversion logic gate (G103) 309 are at a high level, or both the output of the bit line 103b and the inversion logic gate (G104) 310 are at a high level, the MOS transistor (T111) 315 and the MOS The connection point of the transistor (T112) 316 is at a high level, the MOS transistor (T113) 317 is in a conductive state, and in other cases, it is in an open state.

  Accordingly, when the mask information stored in the mask cell 112 and the search data 102 on the bit lines 103a and 103b are different, the MOS transistor (T113) 317 becomes conductive and the mask match line 119 has an invalid state “0”. Is output, and if they match, the mask match line 119 is opened.

  As a result, when a plurality of associative memory cells 118 are connected to the mask match line 119 via the MOS transistor (T113) 317, if one associative memory cell outputs a low level, the mask match line 119 is a low level, and in other cases, a wired AND connection is set to a high level.

Next, the operation when the above-described conventional associative memory 116 is used for the calculation of the transfer destination network address in the router 400-3 in FIG. 19 will be described with reference to FIG. A timing chart at that time is shown in FIG.
Assume that the associative memory 116 is composed of 8 bits and 5 words. Accordingly, the stored data and mask information stored in each associative memory word 117-1 to 117-5 are exactly the same as those in the associative memory of FIG. 20, and the network address of the router 400-3 in FIG. Connection information other than (3. *. *. *) Is stored. In other words, the associative memory word 117-1 is binary to realize (1. *. *. *), And (01.00.00.00) is used as mask information (10.11) as stored data. .11.11) are stored. Similarly, the associative memory word 117-2 has (2. *. *. *), 117-3 has (1.2.2. *), And 117-4 has (1.2. *. *). *) Is stored in 117-5 as (2.1.1. *).

  Hereinafter, the operation when the search operation is performed by inputting the quaternary network address (1.2.2.1) of the PC 401-1 in FIG. 19 as the search data 102 will be described.

First, at the timing (1) in FIG. 18, all the data match lines 107-1 to 107-8 are precharged to the high level and are in the valid state “1”.
Next, at timing (2) in FIG. 18, the n-bit 2-input 1-output selector 128 selects the search data 102 in accordance with the selection signal 129 output from the control circuit 131 and outputs it to the bit lines 103-1 to 103-8. . Thus, the quaternary representation (1. *. *. *) Stored in the associative memory word 117-1 of the associative memory 116 and the quaternary representation stored in the associative memory word 117-3. (1.2.2. *) And (1.2. *. *) In quaternary representation stored in the associative memory word 117-4 are the data on the bit lines 103-1 to 103-8. Match. Therefore, the three data matching lines 107-1, 107-3 and 107-4 are in the valid state "1", and the remaining data matching lines 107-2 and 107-5 are in the invalid state "0".

  Here, from the shortest mask line 122-1, mask information “0” corresponding to the shortest mask line 122-1 in the associative memory word 117-1 and the shortest mask line 122 in the associative memory word 117-3 are displayed. The logical product “0” of the mask information “0” corresponding to −1 and the mask information “0” corresponding to the shortest mask line 122-1 in the associative memory word 117-4 is output. From the shortest mask line 122-2, to the mask information "0" corresponding to the shortest mask line 122-2 in the associative memory word 117-1 and the shortest mask line 122-2 in the associative memory word 117-3. The logical product “0” of the corresponding mask information “0” and the mask information “0” corresponding to the shortest mask line 122-2 in the associative memory word 117-4 is output. Similarly, the logical product “0” of “1”, “0”, and “0” from the shortest mask line 122-3, and “1”, “0”, and “0” from the shortest mask line 122-4. Is "0" from the shortest mask line 122-5, and "0" is "1" and "0" from the shortest mask line 122-6. AND of "1" is "0" from the shortest mask line 122-7, and "1" of "1", "1" and "1" is "1" from the shortest mask line 122-8. AND “1” of “1” and “1” is output, respectively. Therefore, “00000011” is output in binary representation to the shortest mask lines 122-1 to 122-8. In this state, the latch control signal 124 output from the control circuit 131 becomes valid, and the latches 123-1 to 123-5 store the states of the corresponding match lines 107-1 to 107-5 internally, and n bits The latch 126 stores the state of the shortest mask lines 122-1 to 122-8 therein. Therefore, "1" is stored in the latch 123-1, "0" is stored in the latch 123-2, "1" is stored in the latch 123-3, "1" is stored in the latch 123-4, and the latch 123-5. “0” is stored in the “n”, and “00000011” is stored in the n-bit latch 126 in binary representation. The n-bit latch 126 outputs the stored state “00000011” to the latch output lines 127-1 to 127-8.

  Next, at the timing (3) in FIG. 18, all the mask coincidence lines 119-1 to 119-8 are precharged to the high level and are in the valid state “1”.

  Next, at timing (4) in FIG. 18, the n-bit 2-input 1-output selector 128 selects the latch output line 127 according to the selection signal 129 output from the control circuit 131, and the bit line 103 corresponding to the information “00000011” is selected. After outputting to -1 to 103-8, the content addressable memory starts a second search operation. In the second search operation, the states of the mask match lines 119-1 to 119-8 are used, and the states of the data match lines 107-1 to 107-8 are ignored.

  The mask information stored in the associative memory words 117-3 and 117-5 completely matches the state "00000011" of the bit lines 103-1 to 103-8, and the corresponding mask match lines 119-3 and 119 are stored. -5 is opened. Since the mask information stored in the other associative memory words 117-1, 117-2, and 117-4 does not match, the corresponding mask match lines 119-1, 119-2, and 119-4 have an invalid state “0”. Is output.

  Since the latch 123-1 is in the stored state “1”, the corresponding mask match line 119-1 is released, and the latch 123-2 outputs the stored state “0” to the corresponding mask match line 119-2. Since the latch 123-3 is in the stored state "1", the corresponding mask match line 119-3 is opened, and the latch 123-4 is in the stored state "1" so that the corresponding mask match line 119-4 is set. The latch 123-3 outputs the stored state “0” to the corresponding mask match line 119-5.

  Accordingly, the mask coincidence line 119-1 is released by the latch 123-1, but the mask comparators 120-1-1-1 to 120-1-8 in the associative memory word 117-1 set “0”. Since it is outputting, it becomes an invalid state “0”. On the mask match line 119-2, the mask comparators 120-2-1 to 120-2-8 of the associative memory word 117-2 output "0", and the latch 123-2 also outputs "0". Therefore, the invalid state becomes “0”. The mask match line 119-3 is in the valid state “1” because the mask comparators 120-3-1 to 120-3-8 of the associative memory word 117-3 are all open and the latches 123-3 are open. ”. In the mask match line 119-4, the latch 123-4 is in an open state, but the mask comparators 120-4-1 to 120-4-8 of the associative memory word 117-4 output “0”. Therefore, the invalid state is “0”. The mask match line 119-5 is opened by the mask comparators 120-5-5-1 to 120-5-8 of the associative memory word 117-5, but the latch 123-5 outputs "0". Therefore, the mask match line 119-5 is in an invalid state “0”.

  Thus, in the first search operation at timing (2), the stored data stored in advance matches the search data 102 in consideration of the mask information, and in the second search operation at timing (4), Mask match corresponding to the associative memory words 117-1 to 117-5 such that the stored mask information matches the state of the shortest mask lines 122-1 to 122-8 obtained as a result of the first search operation. Only the line 119-3 becomes the valid state “1” at the end of the second search operation. Therefore, only the mask coincidence line 119-3 corresponding to the storage data having the least number of valid bits of the mask information among the storage data that matches as a result of comparing the input search data 102 with the corresponding mask information in consideration. It can be seen that the valid state is output at.

  In the first associative memory 116 described above, in the first search operation, the result of comparing the stored data stored in the m word associative memory words 117-1 to 117-m and the search data 102 is the m data match. The result of comparison between the mask information stored in the associative memory words 117-1 to 117-m of m words and the value of the latch output line 127 in the second search operation is output to the lines 107-1 to 107-m. Are output to m mask matching lines 119-1 to 119-m. Therefore, the n associative memory cells 118-1-1-1 to 118-mn in each associative memory word 117-1 to 117-m include comparators 113-1- for comparing stored data. Two comparators, 1-113-mn and mask comparators 120-1-1-1 to 120-mn for comparing mask information, are required.

  If the inversion logic gate is composed of two MOS transistors, the associative memory cell 118 is composed of 21 MOS transistors as shown in FIG. Among them, since the data cell 108 and the mask cell 112 are static RAM elements, the area of each MOS transistor constituting them is generally the minimum area allowed when the conventional associative memory 116 is manufactured. It is equal to the MOS transistor.

  However, as shown in FIG. 15, each data match line 107-1 to 107-m requires a wiring length for making a wired logical connection with n comparators 113 in one word associative memory word 117. Therefore, the wiring capacitance is very large, and the wiring capacitance is driven, so that the area of the MOS transistor constituting the comparator 113 is very large. For example, in the case of a 0.25 μm manufacturing process, a wiring length of about 1 mm is required to connect 64 comparators, and the wiring capacity of this wiring length is about 0.3 pF. The transistor size for driving this capacitor needs to be 10 to 30 times the MOS transistor of the minimum area allowed in the manufacturing process. Similarly, each mask match line 119-1 to 119-m also needs a wiring length for making a wired logic connection with n mask comparators 120, and the area of the MOS transistor constituting the logic gate 121 is also minimized. 10 to 30 times the area of the MOS transistor is necessary. Further, as shown in FIG. 15, each shortest mask line 122-1 to 122-n also needs a wiring length for making a wired logic connection with m logic gates 121, and the MOS transistors constituting the logic gate 121 Also, the area of 10 to 30 times that of the MOS transistor having the minimum area is required.

  Therefore, the area of the MOS transistors constituting the comparator 113, the mask comparator 120, and the logic gate 121 is 10 times that of the MOS transistor having the minimum area, and the area of a general static RAM element is 6 times that of the MOS transistor having the minimum area. Assuming that, as can be easily understood from FIG. 16, the area of the associative memory cell 118 is 102 times that of the MOS transistor having the smallest area. That is, there is a problem that the conventional associative memory 116 can store only 1/17 compared with the storage capacity of the static SRAM having the same chip area.

  Further, as described above, the result of the first search operation is output to the m data matching lines 107-1 to 107-m, and the result of the second search operation is output to m. These are the mask matching lines 119-1 to 119-m. Therefore, it is necessary to hold the result of the first search operation until the second search operation is executed. Here, for example, when the associative memory 116 has a structure of 64 bits per word and 32768 words, assuming that the latch 123 is composed of 10 MOS transistors, in order to configure 32768 latches 123, Approximately 330,000 MOS transistors are required. That is, there is a problem that the chip area is increased by the number of m latches 123-1 to 123-m regardless of the number of bits n of stored data.

  Further, each of the m data match lines 107-1 to 107-m and the mask match lines 119-1 to 119-m is one before the search except for one which finally outputs a valid state for each search operation. The charges pre-charged to the effective state are discharged through the corresponding MOS transistors. Therefore, in the case of 32768 words composed of 64 words per word, the data match line 107 and the mask match line 119 must be combined to precharge the wiring capacity of 32768 × 2-1 = 65535 lines for each search operation. . Since the shortest mask lines 122-1 to 122-n are n, and 64 in the above example, they can be ignored. That is, it can be seen that the power consumption of the conventional associative memory is almost the power required to pre-charge the data match line 107 and the mask match line 119 for each search operation. Here, in the case of the 0.25 μm manufacturing process as described above, it is assumed that the wiring capacity of the data match line 107 and the mask match line 119 is 0 and 3 pF, respectively, the power supply voltage is 2.5 V, and the cycle of the clock signal 130 is 20 ns. Then, the power consumption of the entire chip is as large as (0.3 pF × 2.5 V) ÷ 20 ns × 2.5 V × 65535 = 6.1 W. Therefore, the data matching lines 107-1 to 107-m and the mask matching lines 119-1 to 119-m, which are m in the conventional associative memory 116, finally output a valid state at each search operation. There is a problem that power consumption is very large because it is necessary to pre-charge to a valid state before searching except for one.

  As described above, since the conventional associative memory 116 has a small storage capacity, when a router is used, it is necessary to use a plurality of associative memories 116. Therefore, the amount of heat generated by the router becomes very large, and it is necessary to incorporate a cooling device 414 as shown in FIG. In addition, since it is necessary to compare the search results of a plurality of associative memories 116 to obtain a final search result, there is a problem in that the data transfer speed is reduced.

  Therefore, an object of the present invention is to output a signal for identifying the storage data having the smallest number of valid bits of the corresponding mask information among the storage data that matches the search data, and the storage capacity per unit chip area. The purpose is to provide a large associative memory.

  As another object, there is provided an associative memory that outputs a signal for identifying the stored data having the smallest number of valid bits of the corresponding mask information among the stored data that matches the search data, and that consumes less power per word. It is to provide a router that does not require a cooling device, and to provide a network system that can transfer data at high speed.

  To achieve the above object, an associative memory according to the present invention includes: a) n data cells for storing m pieces of stored data having an n-bit length; and whether each bit of the stored data is excluded from a search target. N mask cells for storing mask information to be set according to whether the corresponding bits are mask valid state or mask invalid state; words in which input data and the stored data are compared in word units and the comparison results match N comparators for outputting a match signal on the match line; n data for logically operating the data on the match line and the stored data in units of bit strings and outputting the operation result to the match data intermediate logic line; M associative memory words including logic gates; (m and n are natural numbers); b) a latch circuit for storing n-bit intermediate match data output on the match data intermediate logic line; c A selector circuit that selectively supplies either the search data or the intermediate match data as the input data to the associative memory word; and d) the mask information when the search data is selected as the input data. And a control circuit for controlling the comparator to perform the comparison by ignoring when the intermediate coincidence data is selected.

  In the content addressable memory of the present invention, the comparator outputs a comparison result for the search data and a comparison result for the intermediate match data on the same match line.

  The associative memory according to the present invention is characterized in that pre-charge means for pre-charging the coincidence line and the coincidence data intermediate logic line to a predetermined potential prior to a search operation is provided.

  The content addressable memory of the present invention sets the valid state of the mask information to “0”, the invalid state to “1”, the valid state of the stored data to “1”, the invalid state to “0”, and the matching data intermediate logic The valid state of the line is set to “1”, the invalid state is set to “0”, the valid state of the matching line is set to “1”, and the invalid state is set to “0”.

  The content addressable memory according to the present invention is characterized in that the comparator constitutes a wired AND logical connection in which the valid state “1” of the match line is true.

  The content addressable memory according to the present invention is characterized in that the logic gate constitutes a wired AND logic connection in which a valid state “1” of the coincidence data intermediate logic line is true.

  The associative memory according to the present invention is characterized in that as the intermediate match data, logical sum operation data in which the valid state “1” of the stored data is true is obtained.

  The content addressable memory according to the present invention sets the valid state of the mask information to “0”, the invalid state to “1”, the valid state of the stored data to “0”, the invalid state to “1”, and the matching data intermediate logic The valid state of the line is set to “1”, the invalid state is set to “0”, the valid state of the matching line is set to “1”, and the invalid state is set to “0”.

  The content addressable memory according to the present invention is characterized in that the comparator constitutes a wired AND logical connection in which the valid state “1” of the match line is true.

  The content addressable memory according to the present invention is characterized in that the logic gate constitutes a wired AND logic connection in which a valid state “1” of the coincidence data intermediate logic line is true.

  The associative memory according to the present invention is characterized in that as the intermediate match data, logical sum operation data in which the valid state “0” of the stored data is true is obtained.

  The associative memory according to the present invention also includes: a) m × n first data cells storing m pieces of stored data having an n-bit length; and whether to exclude each bit of the stored data from the search target Mxn mask cells for storing mask information to be set according to the mask valid state and mask invalid state of the corresponding bit; search data and the stored data are compared in word units in consideration of the mask information; M × n first comparators that output coincidence signals on the intermediate coincidence line for words having the same comparison result; data on the intermediate coincidence line and the stored data are logically operated in units of bit strings; A first memory including: m × n logic gates for outputting a result on the coincidence data OR line; and b) storing the stored data in association with the first data cell for each word. Xn second data Data cell; the data on the coincidence data OR line and the stored data stored in the second data cell are compared in word units, and the coincidence signal coincides with the word having the coincidence result of the comparison. And m × n second comparators for outputting on the line.

  The content addressable memory according to the present invention is characterized in that precharge means for precharging the match line, the intermediate match line, and the match data OR line to a predetermined potential prior to a search operation is provided.

  In the content addressable memory according to the present invention, the valid state of the mask information is “0”, the invalid state is “1”, the valid state of the stored data is “1”, the invalid state is “0”, and the coincidence data OR The valid state of the line is “0”, the invalid state is “1”, the valid state of the intermediate match line is “1”, the invalid state is “0”, the valid state of the match line is “1”, and the invalid state Is set to "0".

  The content addressable memory according to the present invention is characterized in that the first comparator forms a wired AND logical connection in which the valid state “1” of the intermediate match line is true.

  The content addressable memory according to the present invention is characterized in that storage means for temporarily storing data on the coincidence data logical sum line is interposed between the first memory and the second memory.

  The router of the present invention is a router incorporating an associative memory that uses a destination network address as search data, and includes the associative memory according to any one of claims 1 to 16 as the associative memory.

  The network system according to the present invention is characterized in that data communication is performed between devices connected to the network via the router.

  As described above, the associative memory of the present invention includes a first search operation for comparing search data given from the outside with stored data in consideration of stored mask information, Two search operations of the second search operation for comparing the stored data with the value calculated using the result of the search operation are identically matched using the same comparator for each word. Since means for outputting to the line is provided, the transistor area of the unit cell storing 1 bit can be reduced by about 25% as compared with the conventional associative memory. That is, the storage capacity per unit chip area can be increased by about 33%. Further, as the area is reduced, the wiring capacity is also reduced, so that the operating frequency can be increased by about 32% compared to the conventional associative memory.

  Further, when compared with the same number of words, the power consumption of the conventional associative memory can be reduced by about 50%.

  Furthermore, if the associative memory of the present invention is incorporated in a router that performs network address calculation, the power consumption is reduced compared to the conventional one, so that the cooling device is not required and the cost can be reduced. .

  When applied to a router of a computer network system, the data transfer speed can be increased. Because the operating frequency can be improved as described above, and the number of associative memory chips built in the router is reduced by increasing the storage capacity per chip, so that comparison processing of search results output from multiple chips is not necessary. is there.

[Configuration of the first embodiment]
Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an associative memory 1 according to the present invention. The associative memory 1 includes an n-bit 2-input 1-output selector 23, an n-bit m-word associative memory word 2-1 to 2-m, an n-bit latch 21, a control circuit 30, and a logic gate 16-1. 16-n, and each associative memory word 2-j includes n associative memory cells 7-j-1 to 7-jn. Each associative memory word 2-j is connected to the corresponding data word line 3-j, mask word line 6-j, and comparison control signal 4 for input, and the corresponding match line 5-j. j and n coincidence data intermediate logic lines 14-1 to 14-n are connected for output, and n bit lines 13-1 to 13-n are connected for input / output.

  Each associative memory cell 7-j-k is connected with a corresponding data word line 3-j, a mask word line 6-j, and a comparison control signal 4 for input. 5-j and match data intermediate logic line 14-k are connected for output, and bit line 13-k is connected for input / output.

  Each associative memory cell 7-jk includes a data cell 8-jk for storing bit information corresponding to stored data inputted from the outside via the bit line 13-k, and a data cell 8- Comparator 10-j-k for comparing bit information stored in j-k with information inputted from outside via bit line 13-k, and inputted from outside via bit line 13-k A mask cell 9-jk for storing bit information corresponding to the mask information and a logic gate 11-jk are provided. Here, when the bit information stored in the mask cell 9-jk is the valid state of the mask information, the invalid state of the stored data is stored in the corresponding data cell 8-jk.

  In this example, the valid state of the mask information is “0”, the invalid state is “1”, the valid state of the stored data is “1”, and the invalid state is “0”. Like the stored data, the valid state of the coincidence data logical sum lines 17-1 to 17-n is set to “1”, and the invalid state is set to “0”. The valid state of the match lines 5-1 to 5-m is “1”, and the invalid state is “0”.

  The operation of the data word lines 3-1 to 3-m and the data cells 8-1-1-1 to 8-mn is performed in accordance with the data word lines 106-1 to 106-m of the conventional associative memory and the data. The operation is the same as that of the cells 108-1-1-1 to 108-mn. The operations of the mask word lines 6-1 to 6-m and the mask cells 9-1-1 to 9-mn are the same as those of the mask word lines 111-1 to 111-m of the conventional associative memory. The operation of the mask cells 112-1-1-1 to 112-mn is the same.

  The match line 5 is precharged to a high level before the search operation is started, and is in a valid state “1”.

  The comparator 10 includes the corresponding bit line 13, the stored data stored in the data cell 8 in the same associative memory cells 7-1-1 to 7 -mn, and the mask cell 9. And the comparison control signal 4 are input. When the comparison control signal 4 is in the invalid state “0” and the mask information is in the valid state, the comparator 10 releases the corresponding match line 5. Otherwise, the value of the bit line 13 and the stored data are stored. If they match, the corresponding match line 5 is opened, and if they do not match, the invalid state “0” is output. When all n comparators 10 in the associative memory word 2 have the match line 5 open, the match line 5 is in the valid state “1”; otherwise, it is in the invalid state “0”. Thus, a wired AND logical connection in which the valid state “1” of the match line 5 is true is configured. In other words, during the search operation, the memory stored in the associative memory word 2 except for the bits excluded from the comparison target because the comparison control signal 4 is in the invalid state “0” and the mask information is in the valid state “0”. Only when the data and the bit lines 13-1 to 13-n completely coincide with each other, the coincidence line 5 is in the valid state “1”, otherwise, it is in the invalid state “0”. Of course, a normal logic gate may be used for the same operation.

  The logic gates 11-1-1-1 to 11-mn have matching lines 5-1 to 5-m in the same associative memory words 2-1 to 2-m being in the valid state “1” and the same When the stored data stored in the data cells 8-1-1 to 8 -mn in the associative memory cells 7-1-1 to 7 -mn are valid, the corresponding match data intermediate “0” is output to the logic lines 14-1 to 14-n, and in other cases, the logic lines 14-1 to 14-n are opened. In this example, since the valid state of the stored data is “1”, the stored data stored in the data cells 8-1-1 to 8 -mn is “1” and the match lines 5-1 to 5-5. When -m is "1", "0" is output to the corresponding coincidence data intermediate logic lines 14-1 to 14-n, and the release state is output otherwise.

  Each of the coincidence data intermediate logic lines 14-1 to 14-n is pulled up by resistors 15-1 to 15-n, and the corresponding m logic gates 11-1-1-1 to 11-mn Configure a wired logical connection. Therefore, when all of the m logic gates 11 connected to open the coincidence data intermediate logic line 14, the coincidence data intermediate logic line 14 becomes “1”, otherwise, “0”. It becomes. That is, the wired AND connection is true with “1” being true. Of course, a normal logic gate may be used for the same operation.

  The logic gates 16-1 to 16-n invert the logic states of the corresponding coincidence data intermediate logic lines 14-1 to 14-n and output them as coincidence data logical sum lines 17-1 to 17-n.

  Therefore, the coincidence data OR line 17-k includes m logic gates 11-1-k to 11-mk, coincidence data intermediate logic line 14-k, resistor 15-k, and logic gate 16-k. Thus, the data cell 8- in all the associative memory cells 7-1-k-7-m-k having the matching lines 5-1 to 5-m which are in the valid state "1" during the search operation. As a result, a result of logical OR operation between the stored data stored in 1-k to 8-m-k with the effective state of the stored data being true is obtained. In this example, a logical sum operation result with the valid state “1” of the stored data being true is obtained. Of course, a normal logic gate may be used for the same operation. By these operations, the coincidence data logical sum lines 17-1 to 17-n are the same as the storage data having the smallest number of bits in the invalid state “0” among the storage data matching the search data 12 during the search operation. A value will be output. The n-bit latch 21 stores the states of the coincidence data OR lines 17-1 to 17-n when the latch control signal 22 is valid. The stored state is output to the latch output lines 20-1 to 20-n.

  The n-bit 2-input 1-output selector 23 selects the data to be output to the bit lines 13-1 to 13-n according to the state of the selection signal 24 and the search data 12-1 to 12-n and the latch output lines 20-1 to 20--20. Select from one of -n.

  The control circuit 30 outputs a latch control signal 22, a selection signal 24, and a comparison control signal 4 in synchronization with the clock signal 31 in order to control the operation of the associative memory 1.

[Configuration details of the first embodiment]
Next, a configuration example of the content addressable memory cell 7 will be described with reference to FIG. As can be seen from comparison with the conventional associative memory cell 118 shown in FIG. 16, the bit lines 13a and 13b, the data word line 3, the data cell 8, and the mask word line of the associative memory cell 7 of the present invention. 6 and mask cell 9 are similar to conventional associative memory cell 118.

  Therefore, only the parts different from the conventional one will be described. It should be noted that the mask comparator 120 and the mask match line 119 that the conventional associative memory cell 118 has are not necessary in the associative memory cell of the present invention.

  The comparator 10 includes a MOS transistor (T3) 205, a MOS transistor (T4) 206, a MOS transistor (T5) 207, a MOS transistor (T6) 208, and a MOS transistor (T7) 209. The MOS transistor (T3) 205 and the MOS transistor (T4) 206 are inserted in series between the bit lines 13a and 13b. The MOS transistor (T3) 205 becomes conductive when the output of the inverting logic gate (G1) 201 in the data cell 8 is at a high level. The MOS transistor (T4) 206 becomes conductive when the output of the inverting logic gate (G2) 202 in the data cell 8 is at a high level. The MOS transistor (T6) 208 and the MOS transistor (T7) 209 are connected in parallel, and the two MOS transistors connected in parallel are inserted in series between the match line 5 and the low potential together with the MOS transistor (T5) 207. The The MOS transistor (T6) 208 becomes conductive when the output of the inverting logic gate (G4) 211 in the mask cell 9 is at a high level. The MOS transistor (T7) 209 becomes conductive when the comparison control signal 4 is in the valid state “1”.

  The MOS transistor (T5) 207 becomes conductive when the potential at the connection point between the MOS transistor (T3) 205 and the MOS transistor (T4) 206 is high. When both the output of the bit line 13a and the inverted logic gate (G1) 201 are high level, or both the output of the bit line 13b and the inverted logic gate (G2) 202 are high level, the MOS transistor (T3) 205 and the MOS The connection point of the transistor (T4) 206 becomes high level, and the MOS transistor (T5) 207 is turned on.

  Therefore, when the stored data stored in the data cell 8 and the search data 12 on the bit lines 13a and 13b are different, the MOS transistor (T5) 207 becomes conductive. The MOS transistor (T6) 208 is open when the mask information stored in the mask cell 9 is "0", and is conductive when "1". It is assumed that the match line 5 is precharged to a high potential before the search operation is started. Thus, when a plurality of associative memory cells 7 are connected to the match line 5 via the MOS transistor (T6) 208 and the MOS transistor (T7) 209, even one associative memory cell 7 is set to the low level. When output, the coincidence line 5 is in a wired AND connection so that it is at a low level.

  When the MOS transistor (T5) 207 is conductive, the associative memory cell 7 is matched line 5 when any one of the MOS transistor (T6) 208 and the MOS transistor (T7) 209 connected in parallel is conductive. The invalid state “0” is output to the other, and the match line 5 is opened in other cases. That is, when the mask information is in the valid state “0” and the comparison control signal 4 is in the invalid state “0”, the match line 5 is opened regardless of the comparison result between the search data 12 and the stored data. Is opened when the search data 12 on the bit lines 13a and 13b and the stored data stored in the data cell 8 coincide with each other, and an invalid state "0" is output when they are different.

  Next, functions of the logic gate 11 and the coincidence data intermediate logic line 14 will be described. The coincidence data intermediate logic line 14 is pulled up by the resistor 15 in FIG. 1 and is set to “1” before the search operation. The logic gate 11 includes a MOS transistor (T10) 214 and a MOS transistor (T11) 215 inserted in series between the coincidence data intermediate logic line 14 and a low potential. The MOS transistor (T10) 214 becomes conductive when the match line 5 is in the valid state “1”, and becomes open when the coincidence state is “0”. The MOS transistor (T11) 215 becomes conductive when the output of the inverting logic gate (G2) 202 inside the data cell 8 is high level, and becomes open when it is low level. That is, when the stored data stored in the data cell 8 is in the valid state “1”, the conductive state is established, and when the stored data is in the invalid state “0”, the open state is established. Thereby, the logic gate 11 outputs “0” to the coincidence data intermediate logic line 14 when the coincidence line 5 is in the valid state “1” and the stored data stored in the data cell 8 is in the valid state “1”. In other cases, it is opened.

[Operation of the first embodiment]
Next, the operation when the above-mentioned associative memory 1 is used for the calculation of the transfer destination network address in the router 400-3 in FIG. 19 will be described with reference to FIG. A timing chart at that time is shown in FIG.
Assuming that the associative memory 1 has an 8-bit 5-word configuration, the stored data and mask information stored in each associative memory word 2-1 to 2-5 include the network address of the router 400-3 in FIG. It is assumed that connection information other than (3. *. *. *) Is stored. At this time, the bit of the don't care “*” state in the connection information indicates that the corresponding bit of the stored data is the invalid state “0” of the stored data, and the corresponding bit of the mask information is the valid state “0” of the mask data. It is expressed by doing.

  That is, the associative memory word 2-1 is a binary number for realizing (1. *. *. *), And (01.00.00.00) is used as mask information (11.00 for the stored data). 0.00.00) is stored. Similarly, the associative memory word 2-2 is a binary number to realize (2. *. *. *), (10.00.00.00) is stored as mask information (11.00) 0.00.00) is stored. The associative memory word 2-3 has a binary number to realize (1.2.2. *), And (01.10.10.00) is stored as mask information (11.11.11). .00) are stored. The associative memory word 2-4 is a binary number to realize (1.2. *. *), The stored data is (01.10.00.00) as mask information (11.1.00) .00) are stored. The associative memory word 2-5 has a binary number to realize (2.1.1. *), And (10.01.01.00) is stored as mask information (11.11.11). .00) are stored.

  Hereinafter, the operation when the search operation is performed by inputting the quaternary network address (1.2.2.1) of the PC 401-1 in FIG. 19 as the search data 12 will be described.

First, at the timing (1) in FIG. 4, all the coincidence lines 5-1 to 5-5 are precharged to the high level and are in the valid state “1”.
Next, at timing (2) in FIG. 4, the n-bit 2-input 1-output selector 23 selects the search data 12 according to the selection signal 24 output from the control circuit 30, and outputs it to the bit lines 13-1 to 13-8. . Further, the control circuit 30 outputs an invalid state “0” to the comparison control signal 4, and in each associative memory cell 7-1-1 to 7 -mn, the corresponding bit of the stored data and the search data 12 is stored. Regardless of the comparison result, if the mask information therein is in the valid state “0”, the corresponding match line 5 is permitted to be released. In other words, don't care "*" is also taken into consideration for comparison. As a result, (1. *. *. *) Of the quaternary representation stored in the associative memory word 2-1 of the associative memory 1 and the quaternary representation stored in the associative memory word 2-3. (1.2.2. *) And (1.2. *. *) Of the quaternary representation stored in the associative memory word 2-4 are the search data on the bit lines 13-1 to 13-8. Matches 12. Accordingly, three match lines 5-1, 5-3 and 5-4 are in the valid state "1", and the remaining match lines 5-2 and 5-5 are in the invalid state "0".

  Here, from the coincidence data OR line 17-1, the storage data “0” corresponding to the coincidence data intermediate logical line 14-1 in the associative memory word 2-1 and the associative memory word 2-3 “1” for storage data “0” corresponding to match data intermediate logic line 14-1 and storage data “0” corresponding to match data intermediate logic line 14-1 in associative memory word 2-4. The logical sum result “0” is set to be true. From the coincidence data OR line 17-2, the stored data “1” corresponding to the coincidence data intermediate logical line 14-2 in the associative memory word 2-1 and the coincidence data intermediate in the associative memory word 2-3 “1” for storage data “1” corresponding to logical line 14-2 and storage data “1” corresponding to coincidence data intermediate logical line 14-2 in associative memory word 2-4 is true. The logical sum result “1” is output. Similarly, from the coincidence data logical sum line 17-3, a logical sum result "1" with "1" for "0", "1", and "1" being true is obtained as a coincidence data logical sum line 17 From -4, the logical sum result “0” with “1” for “0”, “0” and “0” being true, and “0” and “1” from the coincidence data logical sum line 17-5. "1" with respect to "0" and "0" is true, and "1" with respect to "0", "0" and "0" from the coincidence data OR line 17-6. The logical sum result “0” in which “1” is true is obtained from the coincidence data logical sum line 17-7, and the logical sum result “1” in relation to “0”, “0” and “0” is true. “0” is output from the coincidence data logical sum line 17-8, and the logical sum result “0” with “1” for “0”, “0”, and “0” being true is output. Accordingly, “01101000” is output in binary representation to the coincidence data logical sum lines 17-1 to 17-8.

  In this state, the latch control signal 22 output from the control circuit 30 becomes valid, and the n-bit latch 21 stores the states of the coincidence data logical sum lines 17-1 to 17-8 therein. Therefore, the n-bit latch 21 stores “01101000” in binary representation and outputs the value to the latch output lines 20-1 to 20-8.

  In this example, the timing (3) in FIG. 4 is inserted so that the states of the clock signals 31 at both the timing (2) and the timing (4) are the same. Keep the final state. When the control circuit 30 operates even if the timing signals (2) and (4) are not in the same state, the timing (3) need not be inserted.

  Next, at timing (4) in FIG. 4, the n-bit 2-input 1-output selector 23 selects the latch output line 20 according to the selection signal 24 output from the control circuit 30, and the bit line 13 corresponding to the information “01101000” is selected. After outputting to -1 to 13-8, the associative memory 1 starts the second search operation. In the second search operation, the result of the first search operation executed at the timing (2) held in the match lines 5-1 to 5-5 is used. In this example, three of the match lines 5-1, 5-3 and 5-4 hold the valid state “1”, and the data match lines 5-2 and 5-5 hold the invalid state “0”. is doing. It goes without saying that the result of the first search operation may be stored in the storage means, and the storage state may be used when searching at the timing (4). Further, the control circuit 30 outputs a valid state “1” to the comparison control signal 4. As a result, each of the associative memory cells 7-1-1 to 7 -mn is in the case where the comparison result between the stored data and the corresponding bit line 13 does not match regardless of the mask information therein. The invalid state “0” is output to the match line 5. That is, don't care “*” is not taken into consideration, and the stored data stored in each associative memory word 2-1 to 2-5 is compared with the state “01101000” of the bit lines 13-1 to 13-8. If they do not match, the invalid state “0” is output to the corresponding match lines 5-1 to 5-5.

  In this example, the stored data stored in the associative memory word 2-3 completely match the state “01101000” of the bit lines 13-1 to 13-8, and the corresponding match line 5-3 is opened. To. Since the stored data stored in the other associative memory words 2-1, 2-2, 2-4, and 2-5 do not match, the corresponding match lines 5-1, 5-2, 5-4, and 5 The invalid state “0” is output to −5. Accordingly, among the three match lines 5-1, 5-3, and 5-4 that have been in the valid state “1” before the second search operation starts, the valid state after the second search operation “ Only the match line 5-3 keeps holding 1 ″.

  Accordingly, only the match line 5-3 corresponding to the stored data having the least number of valid bits of the mask information among the stored data that matches the input search data 12 and the corresponding mask information in consideration of the corresponding mask information. It can be seen that the valid state is output.

  As described above, the associative memory 1 according to the first embodiment of the present invention executes the first search operation and the second search operation with the comparators 10-1-1 to 10-mn, and the result. Are output to match lines 5-1 to 5-m. Therefore, as shown in FIG. 2, the content addressable memory cell 7 can be deleted by the mask comparator as compared with the content addressable memory cell 118 shown in FIG. Here, therefore, it is assumed that the area of the MOS transistor constituting the comparator 10 and the logic gate 11 is 10 times that of the MOS transistor having the smallest area, and that the area of the general static RAM element is 6 times that of the MOS transistor having the smallest area. Then, as can be easily understood from FIG. 2, the area of the associative memory cell 7 is 82 times that of the MOS transistor having the minimum area. Since the area of the conventional associative memory cell 118 is 102 times that of the MOS transistor having the smallest area as described above, the associative memory cell 7 of the present invention has an area of about 20% as compared with the conventional associative memory cell 118. Can be reduced.

  Further, since the result of the first search operation and the result of the second search operation are output to the same match lines 5-1 to 5-m, the first search required in the conventional associative memory 116 is performed. Latches 123-1 to 123-m for holding the operation result until the second search operation is executed are unnecessary. Therefore, the area can be further reduced as compared with the conventional associative memory 116. For example, in the case of a configuration of 32768 words with 64 bits per word, assuming that the latch 123 is composed of 10 MOS transistors, the area of about 330,000 MOS transistors can be reduced. Therefore, when combined with the area reduction of the associative memory cell described above, the area can be reduced by about 25% in the entire chip.

  In addition, since the result of the first search operation and the result of the second search operation are output to the same match lines 5-1 to 5-m, m pre-charges for each search operation are also performed. Only 5-1 to 5-m and n matching data intermediate logic lines 14-1 to 14-n are sufficient. That is, (m + n) pre-charges may be performed each time a search operation is performed. In the conventional associative memory 116, as described above, the m data matching lines 107-1 to 107-m, the m mask matching lines 119-1 to 119-m, and the n shortest mask lines 122-1 to 122-1 are used. 122-n is required to be precharged, and therefore (2m + n) precharges are required for each search operation. Here, in the case of 32768 words with 64 bits per word, the number of wirings to be pre-charged in the entire chip is 65600 in the conventional associative memory 116 and 32832 in the associative memory 1 of the present invention. Compared with the associative memory 116, power consumption can be reduced by about 50%.

  As the area of the associative memory cell 7 is reduced, the wiring lengths of the bit lines 13-1 to 13-n and the coincidence data intermediate logic lines 14-1 to 14-n are also shortened. Assuming that the size of the MOS transistors constituting the associative memory cell 7 is as in the above example, the wiring length is reduced by about 25% compared with the conventional associative memory cell 118, as can be easily seen from FIG. become. Since the wiring capacity is reduced accordingly, there is an effect that the frequency of the clock signal 31 can be increased by about 32%.

[Configuration of the second embodiment]
Next, a second embodiment of the present invention will be described in detail with reference to FIGS. Compared with the associative memory 1 of the first embodiment, the associative memory 28 of this example has the stored data in the valid state “0” and the invalid state “1”, and the logic gates 16-1 to 16-16. -N has been changed to logic gates 27-1 to 27-n, and associative memory cells 7-1-1 to 7-mn in associative memory words 2-1 to 2-m Are changed to associative memory cells 26-1-1-1 to 26-mn, and the other parts are configured similarly. The associative memory cells 26-1-1 to 26 -mn are different from the associative memory cells 7-1-1 to 7 -mn of the first embodiment in that they are logic gates 11-1-1. ˜11-mn is different from the logic gates 25-1-1-1 to 25-mn, and other portions are configured in the same manner. Therefore, only differences from the first embodiment will be described. As in the first embodiment, when the bit information stored in the mask cell 9-jk is in the valid state of the mask information, the corresponding data cell 8-jk stores the bit information. Stores the invalid state of data.

  Similarly to the logic gates 11-1-1-1 to 11-mn of the first embodiment, the logic gates 25-1-1 to 25-mn are the same associative memory words 2-1 to 2-2. Match lines 5-1 to 5-m in -m are in the valid state "1" and data cells 8-1-1 in the same associative memory cells 7-1-1 to 7-mn. When the stored data stored in .about.8-mn is in a valid state, "0" is output to the corresponding coincidence data intermediate logic lines 14-1 to 14-n, and in other cases it is opened. To do. In this example, since the valid state of the stored data is “0”, the stored data stored in the data cell 8-1-1 is “0” and the match lines 5-1 to 5-m are “1”. In this case, “0” is output to the corresponding coincidence data intermediate logic lines 14-1 to 14-n, and in other cases, the release state is output.

  Each of the coincidence data intermediate logic lines 14-1 to 14-n is pulled up by resistors 15-1 to 15-n as in the first embodiment, and the corresponding m logic gates 25-1 are provided. -1 to 25-mn and a wired logical connection are configured. Therefore, when all of the m logic gates 25 connected to open the coincidence data intermediate logical line 14, the coincidence data intermediate logical line 14 becomes “1”, otherwise “0”. It becomes. That is, the wired AND connection is true with “1” being true. Of course, a normal logic gate may be used for the same operation.

  The logic gates 27-1 to 27-n output the logical states of the corresponding match data intermediate logic lines 14-1 to 14-n as match data OR lines 17-1 to 17-n as they are. The logic gates 27-1 to 27-n are logically meaningless and are inserted to shape a signal generated by the wired AND logic. Needless to say, the logic gates 27-1 to 27-n are not required if the operating frequency of the clock signal 31 is sufficiently low.

  Therefore, the coincidence data OR line 17-k includes m logic gates 25-1-k to 25-mk, coincidence data intermediate logic line 14-k, resistor 15-k, and logic gate 27-k. Thus, the data cell 8- in all associative memory cells 26-1-k to 26-mk having the matching lines 5-1 to 5-m which are in the valid state "1" during the search operation. As a result, the result of logical sum operation between the storage data stored in 1-1 to 8-mk with the effective state of the storage data being true is obtained. In this example, a result of logical sum operation with the valid state “0” of the stored data as true is obtained. Of course, a normal logic gate may be used for the same operation. By these operations, the coincidence data logical sum lines 17-1 to 17-n are the same as the storage data having the smallest number of bits in the invalid state “1” among the storage data that matches the search data 12 during the search operation. A value will be output.

[Operation of the second embodiment]
Next, the operation when the above-mentioned associative memory 28 is used for calculation of the transfer destination network address in the router 400-3 in FIG. 19 will be described with reference to FIG.
Assuming that the associative memory 28 has an 8-bit 5-word configuration, the stored data and mask information stored in each associative memory word 2-1 to 2-5 include the network address of the router 400-3 in FIG. It is assumed that connection information other than (3. *. *. *) Is stored. At this time, in the don't care “*” state bits in the connection information, the corresponding bit of the stored data is set to the invalid state “1” of the stored data, and the corresponding bit of the mask information is set to the valid state “0” of the mask information. It is expressed by that.

  In other words, the associative memory word 2-1 is a binary number for realizing (1. *. *. *), (01.11.11.11) is used as mask information (11.00 as mask information). 0.00.00) is stored. Similarly, the associative memory word 2-2 is a binary number to realize (2. *. *. *), The stored data is (10.11.11.11) as mask information (11.00) 0.00.00) is stored. The associative memory word 2-3 has a binary number to realize (1.2.2. *), And (01.10.10.11) is stored as mask information (11.11.11). .00) are stored. The associative memory word 2-4 is a binary number to realize (1.2. *. *), The stored data is (01.10.11.11) as mask information (11.1.00) .00) are stored. The associative memory word 2-5 is a binary number to realize (2.1.1. *), And (10.01.01.11) is used as the mask data (11.11.11) as the stored data. .00) are stored.

Thereafter, the operation when the search operation is performed by inputting the quaternary network address (1.2.2.1) of the PC 401-1 in FIG. 19 as the search data 12 is different from the first embodiment. Only will be described.
In the first search operation, associative memory words 2-1, 2-3, and 2-4 match, as in the first embodiment. Accordingly, three match lines 5-1, 5-3 and 5-4 are in the valid state "1", and the remaining match lines 5-2 and 5-5 are in the invalid state "0".

Here, from the coincidence data OR line 17-1, the storage data “0” corresponding to the coincidence data intermediate logical line 14-1 in the associative memory word 2-1 and the associative memory word 2-3 As described above for the storage data “0” corresponding to the coincidence data intermediate logical line 14-1 and the storage data “0” corresponding to the coincidence data intermediate logical line 14-1 in the associative memory word 2-4. A logical sum result “0” with “0” being true is output. From the coincidence data OR line 17-2, the storage data “1” corresponding to the coincidence data intermediate logical line 14-2 in the associative memory word 2-1 and the coincidence data intermediate in the associative memory word 2-3 “0” for storage data “1” corresponding to logical line 14-2 and storage data “1” corresponding to coincidence data intermediate logical line 14-2 in associative memory word 2-4 is true. The logical sum result “1” is output. Similarly, from the coincidence data logical sum line 17-3, a logical sum result “1” in which “0” is true for “1”, “1”, and “1” is obtained as the coincidence data logical sum line 17 From -4, the logical sum “0” in which “0” is true for “1”, “0”, and “0” is obtained, and “1” and “1” are obtained from the coincidence data logical sum line 17-5. "1" for which "0" is true for "1" and "1" is "1", "0" and "1" from the coincidence data OR line 17-6.
The logical OR result “0” in which “0” is true with respect to “1”, and “0” with respect to “1”, “1”, and “1” is true from the coincidence data logical sum line 17-7. The logical sum result “1” is the logical sum result “1” from the coincidence data logical sum line 17-8 with “0” for “1”, “1”, and “1” being true. Is output. Therefore, “01101011” is output in binary representation to the coincidence data OR lines 17-1 to 17-8 and stored in the n-bit latch 21.

  In the second search operation, the stored data stored in the associative memory word 2-3 completely match the state “01101011” of the bit lines 13-1 to 13-8, and the corresponding match line 5- 3 is opened. Since the stored data stored in the other associative memory words 2-1, 2-2, 2-4, and 2-5 do not match, the corresponding match lines 5-1, 5-2, 5-4, and 5 The invalid state “0” is output to −5. Accordingly, among the three match lines 5-1, 5-3, and 5-4 that have been in the valid state “1” before the second search operation starts, the valid state after the second search operation “ Only the match line 5-3 keeps holding 1 ″.

  Accordingly, only the match line 5-3 corresponding to the stored data having the least number of valid bits of the mask information among the stored data that matches the input search data 12 and the corresponding mask information in consideration of the corresponding mask information. It can be seen that the valid state is output.

  In both the first embodiment and the second embodiment, the valid state of the mask information has been described as “0”. However, even when the valid state of the mask information is set to “1”, as in the above, each association In the memory word, the invalid state of the stored data is stored in the bit of the stored data corresponding to the mask information bit in the mask valid state, and the coincidence line which is in the valid state at the first search operation The result of performing an OR operation with all stored data in the associative memory word having the true value of the stored data as true is set as the bit line state during the second search operation. Needless to say, the content addressable memory of the present invention can be realized.

  In both the first embodiment and the second embodiment, in each associative memory word, the invalid state of the stored data is stored in the bit of the stored data corresponding to the bit of the mask information in the mask valid state. However, at the time of the second search operation in which the comparison control signal 4 is in the valid state, the stored data corresponding to the mask information bit in the mask valid state in the comparator 10 stores the invalid state of the stored data. It can be easily understood that the same result can be obtained even if the comparison is performed.

[Configuration of the third embodiment]
Next, a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 8 is a block diagram showing a configuration of the associative memory 42 according to the third embodiment of this invention.

  The associative memory 42 includes an associative memory 33 with an n-bit m word coincidence data OR signal output function and an n-bit m word associative memory 101 without a mask function. In this example, the associative memory 33 with the coincidence data logical sum signal output function performs the first search operation to calculate the coincidence data logical sum signal 38 and uses the obtained coincidence data logical sum signal 38 to provide the associative memory without a mask function. 101 performs the second search operation and outputs match lines 5-1 to 5-m.

  The associative memory 33 with n-bit m-word match data logical sum signal output function includes search data 12 input to n bit lines 13-1 to 13-n and m associative memory words 43-1 to 43-n. The stored data stored in the internal data cells 8-1-1 to 8 -mn and the mask information stored in the mask cells 9-1-1 to 9 -mn for every 43 -m The calculated match data OR signal 38 is output to n match data OR lines 17-1 to 17-n. The coincidence data logical sum signal 38 is calculated by the same operation as that of the associative memory 1 of the first embodiment. Here, when the bit information stored in the mask cell 9-jk is the valid state of the mask information, the invalid state of the stored data is stored in the corresponding data cell 8-jk.

  The associative memory 101 without the mask function receives the coincidence data logical sum signal 38 input from the bit lines 103-1 to 103-n in the internal data cell for every m associative memory words 104-1 to 104-m. As a result of comparison with the second stored data stored in 105-1-1 to 105-mn, the data match lines 107-1 to 107- corresponding to the matched associative memory word 104 are obtained. The valid state “1” is output to m. The states of the data match lines 107-1 to 107-m are output from the associative memory 42 as match lines 5-1 to 5-m. Here, when the bit information stored in the mask cell 9-jk of the associative memory 33 with the coincidence data logical sum signal output function is the valid state of the mask information, the corresponding data cell 105-jk Stores the invalid state of the stored data.

  In this example, the valid state of the mask information is “0”, the invalid state is “1”, the valid state of the stored data is “1”, and the invalid state is “0”. Similarly to the stored data, the valid state of the coincidence data logical sum lines 17-1 to 17-n is set to “1”, and the invalid state is set to “0”. The valid state of the match lines 5-1 to 5-m is “1”, and the invalid state is “0”.

  FIG. 9 shows a configuration example of the associative memory 33 with an n-bit m-word match data OR signal output function. The associative memory 33 with the coincidence data logical sum signal output function includes associative memory words 43-1 to 43-m of n bits and m words and logic gates 16-1 to 16-n. The word 43-j includes n associative memory cells 44-j-1 to 44-jn. The operation of the logic gates 16-1 to 16-n is exactly the same as that of the associative memory 1 of the first embodiment.

  Each associative memory word 43-j is connected with a corresponding data word line 3-j and a mask word line 6-j for input, a corresponding intermediate match line 41-j, and n Match data intermediate logic lines 14-1 to 14-n are connected for output, and n bit lines 13-1 to 13-n are connected for input / output.

  Each associative memory cell 44-j-k has a corresponding data word line 3-j and a mask word line 6-j connected for input, a corresponding intermediate match line 41-j, and a match. Data intermediate logic line 14-k is connected for output, and bit line 13-k is connected for input / output.

  Each associative memory cell 44-jk includes a data cell 8-jk for storing bit information corresponding to storage data inputted from the outside via the bit line 13-k, and a data cell 8- a comparator 32-jk for comparing the bit information stored in jk with information inputted from the outside via the bit line 13-k, and inputted from the outside via the bit line 13-k A mask cell 9-jk for storing bit information corresponding to the mask information and a logic gate 11-jk are provided.

  The operations of the data word line 3, the mask word line 6, the coincidence data intermediate logic line 14, the bit line 13, the data cell 8, the mask cell 9, and the logic gate 11 of the associative memory cell 44 are as follows. This is exactly the same as the content addressable memory cell 7 of the content addressable memory 1 of the embodiment. The match line 5 of the content addressable memory cell 7 of the content addressable memory 1 of the first embodiment has been renamed as an intermediate match line 41. Therefore, only differences from the content addressable memory cell 7 of the content addressable memory 1 of the first embodiment will be described.

  In this example, when the mask information stored in the mask cell 9 corresponding to each data cell 8 is valid, the invalid state of the stored data is stored in the corresponding data cell 8.

  It is assumed that the intermediate match line 41 is precharged to a high level before the search operation is started or pulled up by a resistor (not shown) and is in a valid state “1”.

  The comparator 32 stores the data stored in the data cell 8 in the corresponding bit line 13 and the same associative memory cells 44-1-1-1 to 44-mn, and the mask cell 9 The mask information stored in is input. The comparator 32 releases the corresponding intermediate match line 41 if the mask information is valid, and otherwise outputs the corresponding intermediate match line 41 if the value of the bit line 13 matches the stored data. Is in an open state, and if they do not match, an invalid state “0” is output. When all n comparators 32 in the associative memory word 43 have the intermediate match line 41 open, the intermediate match line 41 is in the valid state “1”, otherwise it is in the invalid state “ A wired AND logical connection in which the valid state “1” of the intermediate coincidence line 41 is “0” is true. In other words, at the time of the search operation, the stored data stored in the associative memory word 43 and the bit lines 13-1 to 13-n are excluded except for the bits excluded from the comparison target because the mask information is in the valid state “0”. The intermediate coincidence line 41 is in the valid state “1” only when they completely match, and in the invalid state “0” otherwise. Of course, a normal logic gate may be used for the same operation.

  Next, a configuration example of the content addressable memory cell 44 will be described with reference to FIG. As can be seen from comparison with the content addressable memory cell 7 of the first embodiment shown in FIG. 2, the content addressable memory cell 44 of the present invention has the comparison control line 4 and the in-comparator MOS transistor (T7) 209 removed. Except for the fact that the coincidence line 5 is renamed to the intermediate coincidence line 41, it is the same as the associative memory cell 7 of the first embodiment. Therefore, only the parts different from the content addressable memory cell 7 will be described.

  The comparator 32 comprises a MOS transistor (T3) 205, a MOS transistor (T4) 206, a MOS transistor (T5) 207, and a MOS transistor (T6) 208, and the operation thereof is the content addressable memory cell of the first embodiment. 7 is the same.

  Therefore, when the MOS transistor (T5) 207 is conductive, the associative memory cell 44 outputs the invalid state “0” to the intermediate match line 41 when the MOS transistor (T6) 208 is conductive. Sometimes the intermediate coincidence line 41 is opened. That is, when the mask information is in the invalid state “0”, the intermediate match line 41 is opened regardless of the comparison result between the search data 12 and the stored data, and in other cases, the search data on the bit lines 13a and 13b. When the data stored in 12 and the data stored in the data cell 8 coincide with each other, the open state is set, and when they are different, the invalid state “0” is output.

  FIG. 11 shows a configuration example of the associative memory 101 having no n-bit and m-word mask function. The associative memory 101 without mask function is composed of associative memory words 104-1 to 104-m, and each associative memory word 104-j includes n associative memory cells 105-j-1 to 105-j-. n. Each associative memory word 104-j has a corresponding data word line 106-j connected for input, a corresponding data match line 107-j connected for output, and n bit lines 103 -1 to 103-n are connected for input / output.

  Each associative memory cell 105-j-k has a corresponding data word line 106-j connected for input, a corresponding data match line 107-j connected for output, and a bit line 103- k is connected for input and output. In addition, each associative memory cell 105-j-k has a data cell 108-j-k that stores bit information corresponding to the second storage data, and coincidence data input via the bit line 103-k. A comparator 109-jk for comparing the logical sum signal 38 with the bit information stored in the data cell 108-jk is provided. Bits in which the mask information is valid in the mask cells 9-j-1 to 9-jn of the corresponding associative memory word 43-j of the associative memory 33 with the match data OR signal output function Corresponding data cells 108-j-1 to 108-jn store the invalid state of the stored data in advance. Data cells 108-j-1 to 108-jn of other bits have corresponding data cells 8-j-1 to 8-jn in the associative memory 33 with a coincidence data logical sum signal output function. The same value as is stored in advance.

  In each associative memory cell 105-1-1 to 105-mn, the operations of the bit line 103, the data word line 106, the data cell 108, and the data match line 107 are the same as those of the conventional associative memory 116. is there.

  The data match line 107 is precharged to a high level before the search operation is started, or is pulled up by a resistor (not shown) and is in a valid state “1”.

  The comparator 109 compares the corresponding bit line 103 with the second stored data stored in the data cell 108 in the same associative memory cells 105-1-1 to 105-mn. If they match, the corresponding data match line 107 is opened, and if they do not match, the invalid state “0” is output. When all n comparators 109 in the associative memory word 104 have the data match line 107 open, the data match line 107 is in the valid state “1”; otherwise, it is in the invalid state “ A wired AND logical connection in which the valid state “1” of the data matching line 107 becomes “0” is set as true. That is, during the search operation, the data match line 107 is in the valid state “1” only when the second stored data stored in the associative memory word 104 and the bit lines 103-1 to 103-n completely match. In the case of mismatch, the invalid state is “0”. Of course, a normal logic gate may be used for the same operation.

  Next, a configuration example of the content addressable memory cell 105 of the content addressable memory 101 without a mask function will be described with reference to FIG. As can be seen from comparison with the conventional associative memory cell 118 shown in FIG. 16, the bit lines 103a and 103b, the data word line 106, and the data cell 108 of the associative memory cell 105 of the associative memory 101 without the mask function are This is the same as the conventional content addressable memory cell 118. Therefore, only the parts different from the conventional one will be described.

  The comparator 109 includes a MOS transistor (T103) 305, a MOS transistor (T104) 306, and a MOS transistor (T105) 307. In the comparator 113 of the conventional associative memory cell 118, the MOS transistor (T106) 308 is deleted from the MOS transistor inserted in series between the data match line 107 and the low potential, and the data match line 107 and the MOS transistor T105 are removed. The only difference is that a wired AND connection is made via (307).

  Accordingly, during the search operation, when the second storage data stored in the data cell 108 and the search data 102 on the bit lines 103a and 103b are different, the MOS transistor (T105) 307 becomes conductive, and the content addressable memory The cell 105 outputs the invalid state “0” to the data match line 107, and otherwise makes the data match line 107 open.

[Operation of the third embodiment]
Next, the operation when the above-mentioned associative memory 42 is used for the calculation of the transfer destination network address in the router 400-3 in FIG. 19 will be described with reference to FIG.

  Assuming that the associative memory 42 has a configuration of 8 bits and 5 words, the stored data and mask information stored in each of the associative memory words 43-1 to 43-5 of the associative memory 33 with the coincidence data OR signal output function include Assume that connection information other than the network address (3. *. *. *) Of the router 400-3 in FIG. At this time, the bit of the don't care “*” state in the connection information is expressed by setting the corresponding bit of the mask information to the valid state “0” of the mask data. The invalid state “0” of the stored data is stored in the corresponding bit of the stored data.

  That is, the associative memory word 43-1 is a binary number to realize (1. *. *. *), (01.00.00.00) is used as mask information (11.00) as the stored data. 0.00.00) is stored. Similarly, the associative memory word 43-2 is a binary number to realize (2. *. *. *), (10.00.00.00) is stored as mask information (11.00). 0.00.00) is stored. The associative memory word 43-3 is a binary number to realize (1.2.2. *), The stored data is (01.10.10.00) as mask information (11.11.11) .00) are stored. The associative memory word 43-4 is a binary number for realizing (1.2. *. *), The stored data is (01.10.00.00) as mask information (11.1.00) .00) are stored. The associative memory word 43-5 is a binary number for realizing (2.1.1. *), The stored data is (10.01.01.00) as mask information (11.11.11) .00) are stored.

  As the second storage data stored in the associative memory words 104-1 to 104-5 of the associative memory 101 without the mask function, the connection information of the router 400-3 in FIG. It is assumed that a value in which the bit is an invalid state “0” of stored data is stored. That is, (01.00.00.00) is assigned to the associative memory word 104-1, (10.00.00.00) is assigned to the associative memory word 104-2, and the associative memory word 104-3 is assigned. Is (01.10.10.00), (01.10.00.00) for associative memory word 104-4, (10.01.01.00) for associative memory word 104-5 Are stored respectively.

  Hereinafter, the operation when the search operation is performed by inputting the quaternary network address (1.2.2.1) of the PC 401-1 in FIG. 19 as the search data 12 will be described.

  First, before the search operation, all the intermediate match lines 41-1 to 41-5 and the data match lines 107-1 to 107-5 are precharged to a high level or pulled by resistors not shown.・ It is assumed that the status is up and the valid state is “1”.

  When the search data 12 is input to the bit lines 13-1 to 13-8, the quaternary representation (1. *. *) Stored in the associative memory word 43-1 of the associative memory 33 with a match data logical sum signal output function. *. *), (1.2.2. *) Of the quaternary representation stored in the associative memory word 43-3 and (4. 1.2. *. *) Matches the search data 12 on the bit lines 13-1 to 13-8. Therefore, three of the intermediate match lines 41-1, 41-3, and 41-4 are in the valid state “1”, and the remaining intermediate match lines 41-2 and 41-5 are in the invalid state “0”.

  Here, from the coincidence data logical sum line 17-1, the storage data “0” corresponding to the coincidence data intermediate logical line 14-1 in the associative memory word 43-1 and the associative memory word 43-3 “1” for storage data “0” corresponding to match data intermediate logic line 14-1 and storage data “0” corresponding to match data intermediate logic line 14-1 in associative memory word 43-4. The logical sum result “0” is set to be true. From the match data OR line 17-2, the stored data “1” corresponding to the match data intermediate logic line 14-2 in the associative memory word 43-1 and the match data intermediate in the associative memory word 43-3 “1” for storage data “1” corresponding to logic line 14-2 and storage data “1” corresponding to coincidence data intermediate logic line 14-2 in associative memory word 43-4 is true. The logical sum result “1” is output. Similarly, from the coincidence data logical sum line 17-3, a logical sum result "1" with "1" for "0", "1", and "1" being true is obtained as a coincidence data logical sum line 17 -4 shows a logical sum “0” with “1” for “0”, “0” and “0” being true, and “0” and “1” from the coincidence data logical sum line 17-5. “1” for “0” and “0” is true, and “1” for “0”, “0” and “0” is obtained from the coincidence data logical sum line 17-6. The logical sum result “0” in which “1” is true is obtained from the coincidence data logical sum line 17-7, and the logical sum result “1” in relation to “0”, “0”, and “0” is true. “0” is outputted from the coincidence data logical sum line 17-8 as a logical sum “0” in which “1” is true for “0”, “0”, and “0”. Accordingly, “01101000” in binary representation is output as the coincidence data logical sum signal 38 to the coincidence data logical sum lines 17-1 to 17-8.

  The state “01101000” of the coincidence data logical sum signal 38 is input to the bit lines 103-1 to 103-8 of the associative memory 101 without mask function, and the associative memory 101 without mask function starts a second search operation. In this example, the second storage data stored in the associative memory word 104-3 completely matches the state “01101000” of the bit lines 103-1 to 103-8, and the corresponding data match line 107- 3 is opened. Since the second stored data stored in the other associative memory words 104-1, 104-2, 104-4, and 104-5 do not match, the corresponding data match lines 107-1, 107-2, 107- 4 and 107-5, the invalid state “0” is output. Therefore, only the data matching line 107-3 keeps the valid state “1” in the data matching lines 107-1 to 107-5 after the second search operation. Since the states of the data match lines 107-1 to 107-5 are output to the outside as match lines 5-1 to 5-5, it is the match line 5 that is still valid after the second search operation. -3 only.

  Accordingly, only the match line 5-3 corresponding to the stored data having the least number of valid bits of the mask information among the stored data that matches the input search data 12 and the corresponding mask information in consideration of the corresponding mask information. It can be seen that the valid state is output.

  As described above, if the content addressable memory according to the third embodiment is used, a word having the shortest mask information can be selected in one clock. Here, the memory means is inserted between the bit lines 103-1 to 103-n and the coincidence data logical sum lines 17-1 to 17-n, and the coincidence data logical sum signal in which the associative memory 101 without mask function is stored is stored. The pipeline processing may be configured such that the associative memory 33 with the coincidence data logical sum signal output function executes the first search operation for the next search data 12 at the same time when the second search operation for 38 is executed. Needless to say, you can. Of course, it goes without saying that the place where the storage means is inserted is not limited to the place described above.

[Fourth embodiment]
Next, FIG. 14 is a block diagram showing a configuration example of a router using the associative memory 1 of the first embodiment of the present invention for the transfer destination network address calculation. The router 400 receives the input transfer data 408 and outputs output transfer data 409. The input transfer data 408 includes a destination network address 411, a transfer destination network address 410, and a data part 412. The output transfer data 409 includes a destination network address 411, a second transfer destination network address 413, and a data part 412. The conventional router shown in FIG. 20 has the cooling device 414 because the power consumption of the conventional associative memory 116 is large, but the cooling device 414 is unnecessary in the router of the present invention using the associative memory 1 of the present invention. It is.

The transfer destination network address 410 of the input transfer data 408 is naturally the network address of the router 400. The router 400 includes a destination network address extracting unit 406, an associative memory 1, an encoder 402, a memory 404, and a transfer destination network address changing unit 407.
Here, when applied to the router 400-3 in FIG. 19, the network address (1. *. *. *) Or (2. *. *) Is transmitted from the device having the network address (3. *. *. *). The case of transferring to a device of *. *) Will be described. In FIG. 14, the valid state of the stored data is “1” and the invalid state is “0”. The valid state of the mask information is “0”, and the invalid state is “1”. In addition, the valid states of the match lines 5-1 to 5-5 are “1”, and the invalid state is “0”.

  The destination network address extraction unit 406 extracts the destination network address 411 of the input transfer data 408 and inputs it to the associative memory 1 as the search data 12.

  The associative memory 1 stores connection information other than the network address (3. *. *. *) Of the router 400-3. At this time, the bit of the don't care “*” state in the connection information indicates that the corresponding bit of the stored data is the invalid state “0” of the stored data, and the corresponding bit of the mask information is the valid state “0” of the mask data. It is expressed by doing. That is, the associative memory word 2-1 is a binary number for realizing (1. *. *. *), And (01.00.00.00) is used as mask information (11.00 for the stored data). 0.00.00) is stored. Similarly, the associative memory word 2-2 is a binary number to realize (2. *. *. *), (10.00.00.00) is stored as mask information (11.00) 0.00.00) is stored. The associative memory word 2-3 has a binary number to realize (1.2.2. *), And (01.10.10.00) is stored as mask information (11.11.11). .00) are stored. The associative memory word 2-4 is a binary number to realize (1.2. *. *), The stored data is (01.10.00.00) as mask information (11.1.00) .00) are stored. The associative memory word 2-5 has a binary number to realize (2.1.1. *), And (10.01.01.00) is stored as mask information (11.11.11). .00) are stored.

  Match lines 5-1 to 5-5 corresponding to associative memory word 2-1 to associative memory word 2-5 are output to encoder 402. The encoder 402 encodes the match lines 5-1 to 5-5 into the memory address signal 403 and outputs it to the memory 404.

  The memory 404 stores the network address of the router corresponding to the network address constituted by the stored data and mask information of the associative memory words 2-1 to 2-5 of the associative memory 1 in the same word. It is. For example, although the network address (1. *. *. *) Is stored in the content addressable memory word 2-1 of the content addressable memory 1, the network address of the router 400-1 corresponding to this is stored in the memory 404. It is also stored in word 1. Similarly, the word 2 of the memory 404 has the network address of the router 400-2, the word 3 has the network address of the router 400-6, the word 4 has the network address of the router 400-4, and the word 5 has the same address. Stores the network address of the router 400-7. Further, the memory 404 outputs the data stored in the word designated with the memory address signal 403 as the read address as the memory data signal 405.

  The transfer destination network address changing unit 407 changes the second transfer destination address 413 of the output transfer data 409 to the value of the memory data signal 405, and then transfers the transfer to the network device corresponding to the second network address. Do.

  For example, when the destination network address 411 of the input transfer data 408 is (1.2.2.1), the associative memory word 2-3 is stored at the end of the search operation in the associative memory 1 (1. Only the match line 5-3 corresponding to 2.2. *) Is enabled. As a result, the encoder 402 outputs “3” as the memory address 403, and the memory 404 outputs the network address of the router 400-6 as the memory data signal 405. The transfer destination network address changing unit 407 changes the second transfer destination network address 413 of the output transfer data 409 to the network address of the router 400-6, and the output transfer data 409 is sent to the router 400-6. Forward.

  As described above, when the associative memory 1 of the present invention is incorporated in the router 400 that performs network address calculation, the power consumption is reduced as compared with the conventional one, so that the cooling device 414 is not required and the cost can be reduced.

  Further, the number of associative memories 1 built in the router 400 can be reduced as the storage capacity per chip increases. Therefore, the comparison processing of search results output from a plurality of associative memories is not required, and the data transfer speed of the computer network system using the router 400 can be increased.

It is a block diagram which shows the structural example of the content addressable memory of 1st embodiment of this invention. It is a circuit diagram which shows the structural example of the content addressable memory cell of 1st embodiment of this invention. It is a figure which shows the operation example of the content addressable memory of 1st embodiment of this invention. It is an operation | movement timing chart of the content addressable memory of 1st embodiment of this invention. It is a block diagram which shows the structural example of the content addressable memory of 2nd embodiment of this invention. It is a circuit diagram which shows the structural example of the content addressable memory cell of 2nd embodiment of this invention. It is a figure which shows the operation example of the content addressable memory of 2nd embodiment of this invention. It is a block diagram which shows the structural example of the content addressable memory of 3rd embodiment of this invention. It is a block diagram which shows the structural example of the associative memory with a coincidence data OR signal output function of 3rd embodiment of this invention. It is a circuit diagram which shows the structural example of the content addressable memory cell of 3rd embodiment of this invention. It is a block diagram which shows the structural example of an associative memory without a mask function. It is a circuit diagram which shows the structural example of the content addressable memory cell of the content addressable memory without a mask function. It is a figure which shows the operation example of the content addressable memory of 3rd embodiment of this invention. It is a block diagram which shows the structural example of the router which used the content addressable memory of this invention for the transfer destination network address calculation. It is a block diagram which shows the example of 1 structure of the conventional content addressable memory. It is a circuit diagram which shows one structural example of the conventional content addressable memory cell. It is a figure which shows the operation example of the conventional content addressable memory. It is an operation | movement timing chart of the conventional associative memory. It is a connection diagram which shows the structural example of a network. It is explanatory drawing at the time of using the conventional associative memory for the transfer destination address calculation of a router.

Explanation of symbols

1 associative memory 2-1 to 2-m associative memory word 3-1 to 3-m data word line 4 comparison control signal 5-1 to 5-m coincidence line 6-1 to 6-m mask word line 7 -1-1 to 7-mn Content addressable memory cell 8-1-1 to 8-mn Data cell 9-1-1 to 9-mn Mask cell 10-1-1 to 10- mn comparator 11-1-1 to 11-mn logic gate 12-1 to 12-n search data 13-1 to 13-n bit line 14-1 to 14-n coincidence data intermediate logic line 15- 1-15-n resistor 16-1-16-n logic gate 17-1-17-n coincidence data OR line 20-1-20-n latch output line 21 n-bit latch 22 latch control signal 23 n-bit 2 Input 1 output selector 24 selection signal 25-1-1 to 25-mn logic gate 26-1-1 to 26-mn associative memory cells 27-1 to 27-n logic gate 28 associative memory 30 control circuit 31 clock signal 32-1-1 to 32-m-n comparator 33 match data logic Associative memory with sum signal output function 38 Match data logical sum signal 41-1 to 41-m Intermediate match line 42 Associative memory 43-1 to 43-m Associative memory word 44-1-1-1 to 44-mn Associative memory Cell 101 Associative memory without mask function 102-1 to 102-n Search data 103-1 to 103-n Bit lines 104-1 to 104-m Associative memory Words 105-1-1 to 105-mn Associative memory Cells 106-1 to 106-m Data word lines 107-1 to 107-m Data match lines 108-1 to 108-mn Data cells 109-1 to 10 9-mn comparator 110 associative memory 111-1 to 111-m mask word line 112-1-1-1 to 112-mn mask cell 113-1-1-1 to 113-mn comparator 116 associative Memories 117-1 to 117-m associative memory words 118-1-1-1 to 118-mn associative memory cells 119-1 to 119-m mask match lines 120-1-1 to 120-mn mask comparison Units 121-1-1-1 to 121-mn logic gates 122-1 to 122-n shortest mask lines 123-1 to 123-m latch 124 latch control signals 125-1 to 125-n resistor 126 n-bit latch 127 -1 to 127-n Latch output line 128 n-bit 2-input 1-output selector 129 selection signal 130 clock signal 131 control circuit 201 inversion logic gate G1
202 Inversion logic gate G2
203 MOS transistor T1
204 MOS transistor T2
205 MOS transistor T3
206 MOS transistor T4
207 MOS transistor T5
208 MOS transistor T6
209 MOS transistor T7
210 Inverting logic gate G3
211 Inverting logic gate G4
212 MOS transistor T8
213 MOS transistor T9
214 MOS transistor T10
215 MOS transistor T11
301 Inverting logic gate G101
302 Inverting logic gate G102
303 MOS transistor T101
304 MOS transistor T102
305 MOS transistor T103
306 MOS transistor T104
307 MOS transistor T105
308 MOS transistor T106
309 Inversion logic gate G103
310 Inverting logic gate G104
311 MOS transistor T107
312 MOS transistor T108
313 MOS transistor T109
314 MOS transistor T110
315 MOS transistor T111
316 MOS transistor T112
317 MOS transistor T113
400-1 to 400-7 Router 401-1 PC
402 Encoder 403 Memory Address Signal 404 Memory 405 Memory Data Signal 406 Destination Network Address Extraction Unit 407 Destination Network Address Change Unit 408 Input Transfer Data 409 Output Transfer Data 410 Destination Network Address 411 Destination Network Address 412 Data part 413 Second transfer destination network address 414 Cooling device

Claims (18)

a) n data cells for storing m stored data of n bits length;
N mask cells for storing mask information set by mask valid state and mask invalid state of corresponding bits as to whether or not to exclude each bit of the stored data from the search target;
N comparators that compare the input data and the stored data in word units and output a match signal on the match line for the words whose comparison results match;
The logical operation is performed on the data on the match line and the stored data in units of bit strings. When both data are valid, the first logical value is matched , and otherwise, the second logical value representing the open state is matched. N logic gates outputting on the data intermediate logic line; and m associative memory words including m and n are natural numbers;
b) a latch circuit for storing n-bit intermediate coincidence data output on the coincidence data intermediate logic line;
c) a selector circuit that selectively supplies one of search data and the intermediate match data as the input data to the associative memory word;
d) Control the comparator so that the comparison is performed in consideration of the mask information when the search data is selected as the input data, and the comparison is performed ignoring when the intermediate match data is selected. A control circuit to
An associative memory comprising: The associative memory according to claim 1,
The associative memory, wherein the comparator outputs a comparison result for the search data and a comparison result for the intermediate match data on the same match line. The associative memory according to claim 1,
An associative memory comprising pre-charge means for pre-charging the match line and the match data intermediate logic line to a predetermined potential prior to a search operation. The associative memory according to claim 1,
The valid state of the mask information is “0”, the invalid state is “1”,
The valid state of the stored data is “1”, the invalid state is “0”,
The valid state of the coincidence data intermediate logic line is “1”, the invalid state is “0”,
An associative memory, wherein the valid state of the coincidence line is set to “1” and the invalid state is set to “0”. The associative memory according to claim 4,
An associative memory, wherein the comparator constitutes a wired AND logical connection in which the valid state “1” of the coincidence line is true. The associative memory according to claim 4,
An associative memory, wherein the logic gate constitutes a wired AND logic connection in which a valid state “1” of the coincidence data intermediate logic line is true. The associative memory according to claim 4,
An associative memory characterized by obtaining logical sum operation data in which the valid state "1" of the stored data is true as the intermediate match data. The associative memory according to claim 1,
The valid state of the mask information is “0”, the invalid state is “1”,
The valid state of the stored data is “0”, the invalid state is “1”,
The valid state of the coincidence data intermediate logic line is “1”, the invalid state is “0”,
An associative memory, wherein the valid state of the coincidence line is set to “1” and the invalid state is set to “0”. The content addressable memory according to claim 8,
An associative memory, wherein the comparator constitutes a wired AND logical connection in which the valid state “1” of the coincidence line is true. The content addressable memory according to claim 8,
An associative memory, wherein the logic gate constitutes a wired AND logic connection in which a valid state “1” of the coincidence data intermediate logic line is true. The content addressable memory according to claim 8,
An associative memory characterized by obtaining logical sum operation data in which the valid state "0" of the stored data is true as the intermediate match data. a) m × n first data cells storing m pieces of stored data of n bits length;
M × n mask cells for storing mask information to be set according to whether the corresponding bits are excluded from the search target according to the mask valid state and mask invalid state;
M × n first comparators that compare the search data and the stored data in units of words in consideration of the mask information, and output a match signal on the intermediate match line for the words whose comparison results match. ;
A logical operation is performed on the data on the intermediate coincidence line and the stored data in units of bit strings. When both data are valid, a first logical value is obtained. Otherwise, a second logical value representing an open state is obtained. and the m × n logic gate for outputting on the matching data logical line;
A first memory comprising:
b) m × n second data cells storing the stored data in association with the first data cells for each word;
The data on the coincidence data OR line and the stored data stored in the second data cell are compared in word units, and a coincidence signal is output on the coincidence line with respect to a word with a coincidence result of comparison m × an associative memory comprising: n second comparators; The content addressable memory according to claim 12,
An associative memory comprising precharge means for precharging the match line, the intermediate match line, and the match data OR line to a predetermined potential prior to a search operation. The content addressable memory according to claim 12,
The valid state of the mask information is “0”, the invalid state is “1”,
The valid state of the stored data is “1”, the invalid state is “0”,
The valid state of the coincidence data OR line is set to “0”, the invalid state is set to “1”,
The valid state of the intermediate match line is “1”, the invalid state is “0”,
An associative memory, wherein the valid state of the coincidence line is set to “1” and the invalid state is set to “0”. The associative memory according to claim 14,
An associative memory, wherein the first comparator constitutes a wired AND logical connection in which a valid state “1” of the intermediate match line is true. The associative memory according to claim 14,
An associative memory characterized in that storage means for temporarily storing data on the coincidence data OR line is interposed between the first memory and the second memory. In a router with an associative memory that uses the destination network address as search data,
A router comprising the content addressable memory according to claim 1 as the content addressable memory.   A network system for performing data communication between devices connected to a network via a router according to claim 16.

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