JP3792504B2 - Dial pulse receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an improvement in reception result reading processing in a dial pulse receiver.
[0002]
[Prior art]
In general, an exchange or the like receives a dial pulse signal transmitted when dialing a telephone and converts it into a dial number, and a call is realized by connecting a line based on the dial number. Various dial pulse receivers have been proposed and put to practical use.
[0003]
For example, a dial pulse receiver disclosed in Japanese Patent Application Laid-Open No. 56-75790 (hereinafter abbreviated as prior art # 1) uses a logic circuit and a memory to count dial pulses, detect midway abandonment, and determine interdigits. This is a configuration that reads the reception result (dial number and halfway abandonment display) from the control unit every time one digit is received (between digits and halfway abandonment detection) by scanning the number reception completion display from the host control unit. ing.
[0004]
FIG. 3 is a block diagram showing a configuration of a conventional dial pulse receiving apparatus # 1. FIG. 4 is a memory map diagram showing the configuration of each memory and the contents of internal data of the reception result holding unit 4 of the dial pulse receiver of the prior art # 1.
[0005]
The dial pulse receiver of prior art # 1 has an input terminal 1 for inputting a dial pulse signal, a dial pulse receiving circuit 2 for performing dial pulse counting, halfway abandonment detection and interdigit determination using a logic circuit and a memory, An ACT memory 3 that holds the setting state of dial pulse reception valid or invalid, a reception result holding unit 4 that holds the contents of each reception result, a control circuit 8 having an interface function with a host control device (not shown), and control A terminal 9 is used.
[0006]
The reception result holding unit 4 includes an SP memory 5 that holds a number reception completion display, a CAN memory 6 that holds a halfway abandonment detection display, and a DP memory 7 that holds a dial number. Each memory of the reception result holding unit 4 is composed of a memory of “1 digit × required number of lines m” as shown in FIG.
[0007]
By scanning the contents of the SP memory 5 from a host control device (not shown) and reading the CAN memory 6 and DP memory 7 of the corresponding line on which the number reception completion display is performed, every time one digit (one digit) is received. The reception result reading process is executed.
[0008]
In addition, the dial pulse receiver disclosed in Japanese Patent Application Laid-Open No. 59-133793 (hereinafter referred to as prior art # 2) performs counting of dial pulses, detection of halfway abandonment, and interdigit determination as in the above publication. This is performed by a logic circuit and memory, and the reception result (line number, digit reception completion display, halfway abandonment detection display, dial number) is stored in the queue buffer memory in correspondence with the line number, and this queue buffer memory is stored from the host controller. A configuration is shown in which a reception result (line number, digit reception completion display, halfway abandonment detection display, dial number) is read by scanning.
[0009]
FIG. 5 is a block diagram showing a configuration of a dial pulse receiving apparatus according to prior art # 2. FIG. 6 is a memory map diagram showing the contents of the internal data in the Q memory 13 of the dial pulse receiver of the prior art # 2.
[0010]
As in the case of the prior art # 1, the prior art # 2 dial pulse receiving device uses the input terminal 10 for inputting a dial pulse signal, dial pulse counting, halfway abandonment detection and interdigit determination as a logic circuit. Dial pulse receiving circuit 11 that performs in memory, ACT memory 12 that holds the setting state of valid / invalid dial pulse reception of the corresponding line, control circuit 14 having an interface function with a host control device (not shown), and control terminal 15 Consists of.
[0011]
In addition, the reception results of the number reception completion, the halfway abandonment detection display, and the dial number are stored in the Q memory 13 of the queue buffer memory configuration in association with the line number. The Q memory 13 is constituted by a queue buffer memory of “required number of digits n × required number of lines m” as shown in FIG. By scanning the contents of the Q memory 13 from a higher-level control device (not shown), the reception results of each line are read.
[0012]
[Problems to be solved by the invention]
In the case of the prior art # 1, the dial pulse reception result is held in a memory for one digit (one digit), and the content of the reception result holding unit memory is updated at every digit determination period. It is necessary to read the reception result from the upper control device software at a cycle earlier than the determination cycle.
[0013]
Therefore, if the processing capability of the host controller software is limited due to processing other than dial pulse reception processing, and reading processing cannot be performed at a period earlier than the interdigit determination period, the reception result before the reading processing is performed. Since the contents of the holding unit memory are updated, there is a problem that dial pulse reception results may be lost (digits dropped), and line misconnection may occur.
[0014]
In the case of the prior art # 2, since the dial pulse reception result is stored in one queue buffer memory in association with the line number, depending on the state of dial pulse reception processing of each line, a large number of receptions are stored in the queue buffer memory. The result stays, and there is a possibility that the time required for reading the dial pulse reception result of the line held near the back in the queue buffer memory increases and a delay occurs in the process associated with the line connection. In particular, when abandonment detection is detected, the reception result of the corresponding line number staying in the queue buffer memory becomes unnecessary, but the abandonment detection display is already read before reading. Since unnecessary reception result reading processing has to be performed, there is a problem that further delay may occur in processing associated with line connection.
[0015]
A main object of the present invention is to provide a dial pulse receiving apparatus that prevents erroneous connection of a line and the occurrence of a delay in processing associated with the line connection, which leads to deterioration of service quality as a system such as an exchange.
[0016]
[Means for Solving the Problems]
In the dial pulse receiving apparatus according to the present invention, the dial pulse reception result holding unit (19) is provided with a queue buffer memory (22) corresponding to the required number of digits n for each line unit and holds the dial number corresponding to the digit number. It is characterized by doing.
[0017]
In addition, among the dial pulse reception results, a numeric reception completion display and a halfway abandonment display are held in a memory (5, 6) different from the queue buffer memory described above.
[0018]
Since the dial number corresponding to the required number of digits n is stored in the queue buffer memory in correspondence with the digit number, the processing capacity of the host controller software becomes limited due to processing other than dial pulse reception processing, and the inter-digit determination cycle Even when the reading process cannot be performed at an early cycle, the dial number up to the required number of digits n is held in the queue buffer memory, so that the reception result is not lost (digit loss). Therefore, it is possible to prevent an erroneous connection of the line due to a lack of reception result (digit loss).
[0019]
In addition, since the queue buffer memory is provided for each line unit, the reception result reading process for the corresponding line can be performed without being affected by the state of the dial pulse reception process for other lines. Therefore, it is possible to prevent an increase in the reading processing time of the corresponding line due to the influence of the dial pulse reception processing state of other lines.
[0020]
In addition, since the number reception completion display and halfway abandonment display are held in a memory different from the queue buffer memory, when the reception result is read, it is not affected by the reception result stay state in the queue buffer memory of the corresponding line. The number reception completion display and the abandonment display status can be notified, so that it is possible to prevent delays in processing associated with line connection.
[0021]
Since the digit number can be read together with the dial number, it is possible to obtain the effect of improving the reliability of the dial pulse reception process by checking the normality of the digit number with the upper control device software or the like. is there.
[0022]
That is, the present invention relates to the determination results of the means for counting the dial pulse signal, the memory means for holding the counting result of the means for counting, the means for determining the completion of reception of the dial pulse signal, and the means for performing this determination. A dial pulse receiving device comprising: a memory means for holding; a means for detecting abandonment of a dial pulse signal; and a memory means for holding a detection result of the means for detecting the dial pulse signal.
[0023]
Here, a feature of the present invention is that each of the memory means is provided for each line, and the memory means for holding the counting result has a predetermined dial number as a reception result of the dial pulse signal. There is a means for holding corresponding to the digit number for n digits.
[0024]
It is desirable to provide means for displaying the digit number together with the dial number when reading the dial number, which is the count result of the dial pulse signal.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
The configuration of the dial pulse receiving apparatus according to the embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a dial pulse receiver according to an embodiment of the present invention. FIG. 2 is a memory map diagram showing the configuration of each memory of the reception result holding unit and the contents of internal data according to the embodiment of the present invention.
[0026]
In the present invention, as shown in FIG. 1, the dial pulse receiving circuit 2 is provided with means for counting dial pulse signals, means for determining completion of reception of dial pulse signals, and means for detecting halfway abandonment of dial pulse signals. Q memory 22 for holding the counting result of the means for counting, SP memory 5 for holding the determination result of the means for making the determination, and CAN memory 6 for holding the detection result of the means for making the detection Is a dial pulse receiving device.
[0027]
Here, as shown in FIG. 2, the SP memory 5, the CAN memory 6, and the Q memory 22 are provided for each line as shown in FIG. 2, and the Q memory 22 is a dial pulse signal reception result. The dial number is held in correspondence with a predetermined digit number for n digits.
[0028]
Further, the control circuit 8 displays the digit number together with the dial number at the time of reading processing of the dial number which is the counting result of the dial pulse signal.
[0029]
In the following, embodiments of the present invention will be described in more detail.
[0030]
The dial pulse receiving apparatus according to the embodiment of the present invention shown in FIG. 1 includes an input terminal 1 for inputting a dial pulse signal, a dial pulse receiving circuit 2 for counting dial pulses, determining an interval between digits, and detecting midway abandonment, and a corresponding line. ACT memory 3 for holding the dial pulse reception valid / invalid setting state, a reception result holding unit 19 for holding each content of the dial pulse reception result, and an interface function with a host control device (not shown) A control circuit 8 and a control terminal 9 are included.
[0031]
The reception result holding unit 19 also includes an SP memory 5 that holds a numeric reception completion display (Q memory status display), a CAN memory 6 that holds an abandonment detection display, and a queue buffer that holds dial numbers and digit numbers. It is composed of a Q memory 22 having a memory configuration. The configuration of the dial pulse receiving circuit 2 in FIG. 1 is well known by the above-mentioned publication and those skilled in the art, and is not directly related to the features of the present invention, so that the detailed description of the configuration is omitted.
[0032]
FIG. 2 is a memory map diagram showing the configuration of each memory and the contents of internal data of the reception result holding unit 19 of the dial pulse receiver of the embodiment of the present invention. For each required line number m, the SP memory 5 displays a digit reception completion display (SP) for one digit, the CAN memory 6 displays an abandonment detection display (CAN) for one digit, and is stored in the Q memory 22. Holds a dial number corresponding to the required number n of digits corresponding to the digit number.
[0033]
Next, the operation of the dial pulse receiver shown in FIG. 1 will be described with reference to FIG. 1 and FIG. When dial pulse reception valid is set to the ACT memory 3 from a host control device (not shown), the dial pulse signal of the corresponding line inputted from the input terminal 1 is dialed by the dial pulse receiving circuit 2. Pulse counting, halfway abandonment detection, and interdigit determination are performed, and each reception result is output to the reception result holding unit 19.
[0034]
The reception result holding unit 19 holds the dial number corresponding to the digit number in the Q memory 22 and the numeric reception completion display (status display with or without data on the Q memory 22) held in the SP memory 5.
[0035]
Further, when a halfway abandonment is detected, a halfway abandonment detection display is held in the CAN memory 6. Scanning the contents of the SP memory 5 from a host control device (not shown) and reading the CAN memory 6 and Q memory 22 of the corresponding line on which the numeric reception completion display is performed, thereby reading the dial pulse reception result. Do.
[0036]
As shown in FIG. 2, the SP memory 5 and the CAN memory 6 are different memories from the Q memory 22, and no data stays on the Q memory 22, so the scanning of the SP memory 5 and the CAN memory 6 At the time of reading, the number reception completion display (with or without data on the Q memory 22) and the abandonment detection display state at that time and the state of the abandonment detection display at that time are read out. Can be performed.
[0037]
Since the Q memory 22 has a capacity for the required number n of digits, the dial number can be held up to the n-th digit. Further, since the Q memory 22 is provided for each line, it is possible to directly read the Q memory 22 of the required line, and the Q of the line that no longer needs to be read, such as a line with an abandonment detection display. It is possible to stop reading the memory 22.
[0038]
Further, since the Q memory 22 holds the dial pulse in correspondence with the digit number, the digit number can be read together with the dial number, so that the normality of the digit number for each line can be read by the upper control software or the like. By checking this, it is possible to improve the reliability of the dial pulse reception result reading process.
[0039]
【The invention's effect】
As described above, according to the present invention, a queue buffer memory corresponding to the required number of digits is provided for each line unit in the dial pulse reception result holding unit, and the dial number is held in correspondence with the digit number. Among the pulse reception results, the number reception completion display and halfway abandonment detection display are stored in a memory different from the above-mentioned queue buffer memory, so that reception results are missing (digits) and unnecessary processing in dial pulse reception result processing. Since an increase in the procedure can be avoided, there is an effect that it is possible to prevent the occurrence of a delay due to line misconnection and line connection processing that leads to deterioration in service quality as a system such as an exchange.
[Brief description of the drawings]
FIG. 1 is a block diagram of a dial pulse receiver according to an embodiment of the present invention.
FIG. 2 is a memory map diagram showing the configuration of each memory and the contents of internal data of a reception result holding unit of the dial pulse receiver according to the embodiment of the present invention.
FIG. 3 is a block diagram of a conventional dial pulse receiving apparatus # 1.
FIG. 4 is a memory map diagram showing the configuration of each memory and the contents of internal data of the reception result holding unit of the dial pulse receiving device of prior art # 1.
FIG. 5 is a block diagram of a conventional dial pulse receiving apparatus # 2.
FIG. 6 is a memory map diagram showing the contents of internal data in a Q memory of a dial pulse receiver of prior art # 2.
[Explanation of symbols]
1, 10 Input terminals 2, 11 Dial pulse receiving circuit 3, 12 ACT memory 4, 19 Reception result holding unit 5 SP memory 6 CAN memory 7 DP memory 8, 14 Control circuit 9, 15 Control terminal 13, 22 Q memory

Claims (2)

Means for counting dial pulse signals;
A queue buffer memory means for holding the dial number of the counting result of the counting means for n digits corresponding to the digit number ;
Means for determining completion of reception of the dial pulse signal;
Number reception completion display memory means for holding the presence / absence of completion of number reception, which is a determination result of the means for performing this determination, for one digit ;
Means for detecting midway abandonment of dial pulse signals;
Halfway abandonment display memory means for holding the presence or absence of halfway abandonment detection, which is the detection result of the means for performing this detection, for one digit ;
The queue buffer memory means, the numeral reception completion display memory means, and the halfway abandonment display memory means are provided individually for each line,
A dial pulse receiving apparatus characterized in that a host control device scans the numeric reception completion display memory means when reading a dial pulse reception result and reads the queue buffer memory means and the halfway abandonment display memory means . 2. The dial pulse receiving apparatus according to claim 1, further comprising means for displaying a digit number together with the dial number at the time of reading the dial number which is a counting result of the dial pulse signal.

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