JP3789275B2 - Subcarrier frequency signal demodulator - Google Patents

Description

【００４７】
但し、Ｅ[x]はｘの期待値、x^*はxの複素共役を表す。また、ＮはＦＦＴ（高速フーリエ変換）サイズである。
【００４８】
周波数オフセットが存在する場合、雑音を無視するとs_n+Nは、s_nと周波数オフセットδfを用いて次の式（２）のように表される。
【００４９】
【数２】

【００５０】
式（２）を式（１）に代入すると、次の式（３）が得られる。
【００５１】
【数３】

【００５２】
ここで、期待値Ｅ[x]の計算をガードインターバル期間ＧＩにおける時間平均で近似できると仮定すると、式（１）は次の式（４）のように示される。
【００５３】
【数４】

【００５４】
従って、式（４）で得られる複素データから、その中の位相成分を抽出することによって、周波数オフセットδfを次の式（５）に示すように推定することができる。
【００５５】
【数５】

【００５６】
この周波数オフセットδfの式（５）から、位相誤差δθを次の式（６）に示すように求めることができる。
【００５７】
【数６】

【００５８】
上記から、式（１）〜式（４）に示したように、ガードインターバル期間とそれに対応する有効シンボル期間の最後部との相関特性を求め、式（５）〜式（６）に示したようにその中から位相成分を抽出することにより、数式的にも復調信号の位相誤差を検出することができることがわかる。
【００５９】
図２の（ｄ）〜（ｇ）は、上記のマルチパス遅延波復調信号と通常の復調信号との関係を示すタイミングチャートである。
【００６０】
図２の（ｄ）はマルチパス遅延波復調信号を示し、（ｅ）は（ａ）の復調信号とマルチパス遅延波復調信号とを上下段に重ねて示し、（ｆ）は（ｃ）の相関特性検出期間中の相関特性が変化した期間と相関特性が変化しない期間を示し、（ｇ）は（ｂ）の相関検出用に遅延された復調信号とマルチパス遅延波復調信号が遅延された復調信号とを上下段に重ねて示している。
【００６１】
図２の（ｄ）に示したマルチパス遅延波復調信号中の各シンボル期間ＭＳ０〜ＭＳ２は、マルチパス伝送路中の遅延経路（以下、マルチパス遅延経路と記す）を経由するため、（ａ）に示した通常の復調信号中の各シンボル期間ＳＴ０〜ＳＴ２に対して各々期間ｄｔ分だけ遅延する。そのため、図２の（ｅ）の上段に示した通常経路を経由する復調信号中のＲＧ０に対し、図２の（ｅ）の下段に示したマルチパス遅延経路を経由する復調信号中のＭＥ０ｂ（上記ＲＧ０に対応するマルチパス遅延波復調信号中の期間）も、期間ｄｔ分だけ遅延する。従って、復調信号中のＲＧ０の最初から期間ｄｔまでの間、即ち、図２の（ｆ）に示した相関特性変化期間ＤＴ０ａについては、マルチパス遅延経路を経由する復調信号中のＭＥ０ａ（有効シンボル期間ＥＳ０中の非ＲＧ０部分に対応するマルチパス遅延波復調信号中の期間）の影響を受ける。同様にして、図２の（ｆ）に示した相関特性変化期間ＤＴ０ｂについては、マルチパス遅延経路を経由する復調信号中のＭＥ０ｂの影響を受ける。ここで、ＲＧ０とＭＥ０ｂとは遅延関係にある同一信号同士であるので相関を有しているが、ＲＧ０とＭＥ０ａとは相関を有していない。
【００６２】
一方、図２の（ｇ）の上段に示した通常経路を経由する復調信号が相関検出用に遅延された信号中のＤＧ０に対し、図２の（ｇ）の下段に示したマルチパス遅延経路を経由する復調信号が相関検出用に遅延された信号中のＭＩ０（相関検出用に遅延されたマルチパス遅延波復調信号中の上記ＤＧ０に対応する期間）も、期間ｄｔ分だけ遅延する。従って、相関検出用に遅延された復調信号中のＤＧ０の最初から期間ｄｔまでの間、即ち、図２の（ｆ）に示した相関特性変化期間ＤＴ０ａについては、マルチパス遅延経路を経由する復調信号が相関検出用に遅延された信号中のＭＤ０ｂ（有効シンボル期間ＥＳ０中の非ＲＧ０部分に対応するマルチパス遅延波復調信号中の期間）の影響を受ける。同様にして、図２の（ｆ）に示した相関特性変化期間ＤＴ０ｂについては、マルチパス遅延経路を経由する復調信号が相関検出用に遅延された信号中のＭＩ０の影響を受ける。ここで、ＤＧ０とＭＩ０とは遅延関係にある同一信号同士であるので相関を有しているが、ＤＧ０とＭＤ０ｂとは相関を有していない。
【００６３】
従って、ＲＧ０とＭＥ０ａとは相関が無いので、復調信号中のＲＧ０の最初から期間ｄｔまでの間の相関は低くなり、ＤＧ０とＭＤ０ｂとは相関が無いので、復調信号が相関検出用に遅延された信号中のＤＧ０の最初から期間ｄｔまでの間の相関は低くなり、その結果、例えば、図１０に示した従来の副搬送波周波数信号復調部２０では、検出する位相誤差の精度が劣化してしまう。
【００６４】
本実施の形態では、図２におけるＲＧ０の最初から期間ｄｔまでの間と、ＤＧ０の最初から期間ｄｔまでの間とを検出して、その期間の重み付けを低くすることにより、最終的な位相誤差の精度が劣化しないようにしている。
【００６５】
図３は、図２の（ｃ）、（ｅ）、（ｆ）、（ｇ）の信号を時間軸を拡大して示すと共に、相関特性検出期間を細分した細分期間を（ｈ）に示したタイミングチャートである。
【００６６】
図３の（ｃ）、（ｅ）〜（ｇ）は、図２に示した同番号の信号の時間軸を拡大して示した図であり、（ｈ）は、本実施の形態の位相誤差検出回路５により相関特性検出期間を細分した細分期間を示している。この細分期間は、微細に分割したほうが好ましいが、相関を検出する能力はクロック信号の波長よりも細かくはならないため、本実施の形態では所定値Ｎ（Ｎは２以上の整数且つ前記1シンボル期間のガードインターバル期間中に用いられるクロック信号のパルス総数よりも小さい数）に分割した細分期間とした。
【００６７】
このように、相関特性検出期間を細分することにより、マルチパス遅延経路を経由した副搬送波周波数信号の遅延する期間ｄｔを特定でき、従って、マルチパス遅延経路を経由した副搬送波周波数信号が通常経路を経由した副搬送波信号に加算されることにより、相関が低下する期間である相関特性変化期間ＤＴ０ａを特定することができる。
【００６８】
本実施の形態では、重み関数回路６により、相関特性変化期間ＤＴ０ａに対する重み関数を低く設定し、相関特性変化期間ＤＴ０ｂに対する重み関数を高く設定する。すると、演算回路８において演算される最終的な位相誤差信号中では、マルチパス遅延経路を経由した副搬送波周波数信号の影響が少なくなる。
【００６９】
以上説明したように、本実施の形態に係る副搬送波周波数信号復調装置２１は、相関特性検出期間をいくつかの細分期間に分割して細分期間毎に第1の位相分割誤差値を出力する位相誤差検出回路５、第1の位相分割誤差値に重み付けをするための重み関数を計算する重み関数回路６、位相誤差検出回路５の出力である第1の位相分割誤差値にそれぞれ対応する重み関数を乗算して第２の位相分割誤差値を出力する第2の乗算器７、第２の位相分割誤差値を演算する演算回路８、を備え、相関特性検出期間をいくつかの細分期間に分割し、各細分期間における位相誤差値に対して各々重み付けを行って、その重み付けされた細分期間毎の位相誤差値を演算した結果の値を最終的な位相誤差信号として出力し、位相誤差信号に基づいて副搬送波周波数の信号の再生を行って基準信号を生成し、副搬送波周波数信号を同期検波するように構成したので、マルチパス遅延経路を経由する遅延信号が存在する場合においても、その遅延信号によって相関が弱くなる期間の影響を抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出できる。
【００７０】
実施の形態２．
図４は本発明の実施の形態２である副搬送波周波数信号復調装置を示すブロック図である。尚、以下の図４〜図９においては、図１に示した第１の実施形態の副搬送波周波数信号復調装置と同じ機能の部分については同じ符号を付し、重複する説明を省略する。
【００７１】
本実施の形態２の副搬送波周波数信号復調部２２では、図１に示した重み関数回路６における重み関数の設定について、第1の位相分割誤差値の振幅の最大値を比較し、その比較結果を正規化して算出するようにしている。
【００７２】
図４において、１２は位相誤差検出回路５から出力される細分期間毎の各第1の位相分割誤差値から最大値を検出する最大値検出回路、１３は最大値検出回路１２が検出した最大値によって位相誤差検出回路５の各細分期間の出力を正規化して重み関数を計算する正規化回路である。
【００７３】
以下、本実施の形態の副搬送波周波数復調部２２の動作を説明する。
【００７４】
本実施の形態の副搬送波周波数信号変調部２４が、初期状態において位相誤差が修正されていない復調信号ＤＳを乗算器２から出力してから、位相誤差検出回路５により細分された各第1の位相分割誤差値を出力するまでの動作は実施の形態１と同様である。
【００７５】
重み関数回路６は、位相誤差検出回路５の各第1の位相分割誤差値値に基づいて各細分期間に対する重み関数を計算する。本実施の形態では、位相誤差検出回路５の出力である各第1の位相分割誤差値は最大値検出回路１２に入力され、各第1の位相分割誤差値中の最大となる位相誤差値が最大値として検出される。検出された最大値を例えば１として各第1の位相分割誤差値を正規化回路１３によって正規化し、この正規化結果を各細分期間の重み関数とする。各第1の位相分割誤差値を正規化することにより、相関の強い細分期間については重み関数が大きくなり、相関の弱い細分期間、即ち、マルチパス遅延経路を経由した遅延信号によって位相誤差検出精度が低くなった期間については重み関数が小さくなる。
【００７６】
重み関数回路６から出力された位相誤差検出回路５の各第1の位相分割誤差値に対応する各重み関数を、第2の乗算器７によって位相誤差検出回路５の各第1の位相分割誤差値と乗算することにより、各第1の位相分割誤差値に対して重み付けを行い第２の位相分割誤差値とする。演算回路８は、全ての第2の乗算器７からの出力される第２の位相分割誤差値が入力され、各入力信号に対して例えば加算等の演算を実施することによって、第2の位相誤差値である位相誤差信号ＥＳを出力する。以下の動作は、実施の形態１と同様である。
【００７７】
このように重み関数を設定することにより、位相誤差値が他の期間に比べ小さい期間、即ち、マルチパス遅延波の影響により相関が弱い期間の位相誤差検出値の振幅が抑えられる。従って、マルチパス遅延経路を経由した遅延信号によって相関が弱くなった細分期間の影響を抑えることができる。
【００７８】
以上説明したように、本実施の形態に係る副搬送波周波数復調部２２は、重み関数回路６にて計算する重み関数を、最大値検出回路１２及び正規化回路１３により第1の位相分割誤差値の振幅の比に基づいて算出するように構成したので、比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響を第１の実施形態よりもさらに抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出できる。
【００７９】
実施の形態３．
図５は本発明の実施の形態３である副搬送波周波数信号復調装置を示すブロック図である。
【００８０】
本実施の形態の副搬送波周波数信号復調部２３では、図１に示した重み関数回路６における重み関数の設定について、細分期間毎に入力する各第1の位相分割誤差値の振幅のべき乗を比較し、その比較結果を正規化して算出するようにしている。
【００８１】
図５において、１４は位相誤差検出回路５の各細分期間から出力する第1の位相分割誤差値をべき乗するべき乗回路、１２はべき乗回路１４の各出力から最大値を検出する最大値検出回路、１３は最大値検出回路１２が検出した最大値によってべき乗回路１４の各細分期間の出力を正規化して重み関数を計算する正規化回路である。
【００８２】
以下、本実施の形態の副搬送波周波数復調部２３の動作を説明する。
【００８３】
本実施の形態の副搬送波周波数信号変調部２４が、初期状態において位相誤差が修正されていない復調信号ＤＳを乗算器２から出力してから、位相誤差検出回路５により細分された第1の位相分割誤差値を出力するまでの動作は実施の形態１と同様である。
【００８４】
重み関数回路６は、位相誤差検出回路５の各第1の位相分割誤差値に基づいて各細分期間に対する重み関数を計算する。本実施の形態では、位相誤差検出回路５の各第1の位相分割誤差値は各べき乗回路１４に入力され、各々のべき乗回路１４にて各第1の位相分割誤差値のべき乗値が計算される。各べき乗回路１４の出力は最大値検出回路１２に入力され、最大となる位相誤差値が最大値として検出される。検出された最大値を例えば１として各細分期間の位相誤差値を正規化回路１３によって正規化し、この正規化結果を各細分期間の重み関数とする。各細分期間の位相誤差値正規化することにより、相関の強い細分期間については重み関数が大きくなり、相関の弱い細分期間、即ち、マルチパス遅延経路を経由した遅延信号によって位相誤差検出精度が低くなった期間については重み関数が小さくなる。
【００８５】
重み関数回路６から出力された位相誤差検出回路５の各出力に対応する各重み関数を、第2の乗算器７によって位相誤差検出回路５の出力である各第1の位相分割誤差値と乗算し、細分期間毎の各第1の位相分割誤差信号に対して重み付けを行い第2の位相分割誤差値とする。演算回路８は、全ての第2の乗算器７からの出力される第2の位相分割誤差値が入力され、各入力信号を演算することによって、第2の位相誤差値である位相誤差信号ＥＳを出力する。以下の動作は、実施の形態１と同様である。
【００８６】
このように重み関数を設定することにより、第１の位相分割誤差値が他の期間に比べ小さい期間、即ち、マルチパス遅延波の影響により相関が弱い期間の位相誤差検出値の振幅が抑えられる。従って、マルチパス遅延経路を経由した遅延信号によって相関が弱くなった細分期間の影響を抑えることができる。
【００８７】
以上説明したように、本実施の形態に係る副搬送波周波数復調部２３は、重み関数回路６にて計算する重み関数を、べき乗回路１４、最大値検出回路１２及び正規化回路１３により第１の位相分割誤差値の振幅のべき乗の比に基づいて算出するように構成したので、第２の実施形態よりも重み付けの比率をさらに強調することができ、比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響をより一層抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出できる。
【００８８】
実施の形態４．
図６は本発明の実施の形態４である副搬送波周波数信号復調装置を示すブロック図である。
【００８９】
本実施の形態の副搬送波周波数信号復調部２４では、図１に示した演算回路８において、重み関数回路６及び第2の乗算器７にて重み付けされた各第1の位相分割誤差値を平均する演算を行うようにしている。
【００９０】
図６において、１５は第2の乗算器７の出力である各第２の位相分割誤差値の平均を計算する平均回路であり、演算回路８内に設けられている。
【００９１】
以下、本実施の形態の副搬送波周波数復調部２４の動作を説明する。
【００９２】
本実施の形態の副搬送波周波数信号変調部２４が、初期状態において位相誤差が修正されていない復調信号ＤＳを乗算器２から出力してから、重み関数回路６と第2の乗算器７によって細分期間毎の各第1の位相分割誤差値に対して重み付けが行われるまでの動作は実施の形態１と同様である。
【００９３】
演算回路８は、全ての第2の乗算器７からの出力される各第２の位相分割誤差値が入力され、各入力信号を演算することによって、第2の位相誤差値である位相誤差信号ＥＳを出力する。
【００９４】
ここで、本実施の形態の演算回路８は平均回路１５であることから、全ての第2の乗算器７の出力信号である各第２の位相分割誤差値が平均回路１５に入力すると、平均回路１５では平均値を計算し、その平均値を第2の位相誤差値である位相誤差信号ＥＳとして平均回路１５から出力する。以下の動作は、実施の形態１と同様である。
【００９５】
このように各位相誤差信号の平均値を計算することにより、マルチパス遅延経路を経由した遅延信号によって相関が弱くなった細分期間の影響を抑えることができる。
【００９６】
以上説明したように、本実施の形態に係る副搬送波周波数復調部２４は、演算回路８を平均回路１５により構成し、重み付けを行った各第２の位相分割誤差値の平均を演算回路８において計算することにより第2の位相誤差値を得るようにしたので、比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響をより一層抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出できる。
【００９７】
実施の形態５．
図７は本発明の実施の形態５である副搬送波周波数信号復調装置を示すブロック図である。
【００９８】
本実施の形態の副搬送波周波数信号復調部２５では、図１に示した演算回路８において、重み関数回路６及び第2の乗算器７にて重み付けされた各第２の位相分割誤差値をべき乗平均する演算を行うようにしている。
【００９９】
図７において、１６は第2の乗算器７の出力である第２の位相分割誤差値のべき乗平均を計算するべき乗平均回路であり、演算回路８内に設けられている。
【０１００】
以下、本実施の形態の副搬送波周波数復調部２５の動作を説明する。
【０１０１】
本実施の形態の副搬送波周波数信号変調部２５が、初期状態において位相誤差が修正されていない復調信号ＤＳを乗算器２から出力してから、重み関数回路６と第2の乗算器７によって細分期間毎の各第1の位相分割誤差値に対して重み付けが行われるまでの動作は実施の形態１と同様である。
【０１０２】
演算回路８は、全ての第2の乗算器７からの出力される各第２の位相分割誤差値が入力され、各入力信号を演算することによって、第2の位相誤差値である位相誤差信号ＥＳを出力する。
【０１０３】
ここで、本実施の形態の演算回路８はべき乗平均回路１６であることから、全ての第2の乗算器７の出力信号である各第２の位相分割誤差値がべき乗平均回路１６に入力すると、べき乗平均回路１６ではべき乗平均値を計算し、そのべき乗平均値を最終的な位相誤差信号としてべき乗平均回路１６から出力する。以下の動作は、実施の形態１と同様である。
【０１０４】
このように各第２の位相分割誤差値のべき乗平均値を計算することにより、マルチパス遅延経路を経由した遅延信号によって相関が弱くなった細分期間の影響を抑えることができる。
【０１０５】
以上説明したように、本実施の形態に係る副搬送波周波数復調部２５は、演算回路８をべき乗平均回路１６により構成し、重み付けを行った各第２の位相分割誤差値のべき乗平均を演算回路８において計算することにより第2の位相誤差値を得るようにしたので、図６に示した実施の形態４よりも重み付けの比率をさらに強調することができ、比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響をより一層抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出できる。
【０１０６】
実施の形態６．
図８は本発明の実施の形態６である副搬送波周波数信号復調装置を示すブロック図である。
【０１０７】
本実施の形態の副搬送波周波数信号復調部２６では、副搬送波周波数信号ＢＳの位相誤差を修正して復調信号ＤＳを出力する第1の乗算器２の配置を、上記した実施の形態１とは異なる配置にしている。より具体的には、実施形態１では、数値制御発振回路１０から出力される再生された副搬送波周波数の信号である基準信号ＳＳをフィードバックするように第1の乗算器２が配置されていたが、本実施の形態では、基準信号ＳＳをフィードフォワードするように第1の乗算器２が配置される。即ち、第1の乗算器２は、その出力が有効シンボル期間遅延回路４と位相誤差検出回路５とに向けては出力されず、復調信号ＤＳとして出力されるように配置される。
【０１０８】
以下、本実施の形態の副搬送波周波数復調部２６の動作を説明する。
【０１０９】
本実施の形態の副搬送波周波数信号変調部２６の副搬送波周波数信号ＢＳは、直接に位相誤差検出回路５に入力されると共に、直接に有効シンボル期間遅延回路４にも入力される。そして、有効シンボル期間遅延回路４によって有効シンボル期間分遅延させた信号が位相誤差検出回路５に入力される。また、位相誤差検出回路５にて実施される動作以降の、数値制御発振器１０から出力された基準信号ＳＳと副搬送波周波数信号ＢＳとを第1の乗算器２により乗算することにより位相誤差を修正した復調信号ＤＳを得るところまでの動作は実施の形態１と同様である。
【０１１０】
このように副搬送波周波数信号復調部２６内の同期検波回路をフィードバック回路でなくフィードフォワード回路とすることにより、収束時間を短縮することができる。
【０１１１】
以上説明したように、本実施の形態に係る副搬送波周波数復調部２６は、同期検波回路をフィードフォワード回路としたので、比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響を抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出でき、さらに、収束時間を短縮できる。
【０１１２】
実施の形態７．
図９は本発明の実施の形態７である副搬送波周波数信号復調装置を示すブロック図である。
【０１１３】
本実施の形態の副搬送波周波数信号復調部２７では、副搬送波周波数信号ＢＳの位相誤差を修正して復調信号ＤＳを出力する第1の乗算器２の配置を、上記した実施の形態１とは異なる配置にしている。より具体的には、実施形態１では、数値制御発振回路１０から出力される再生された副搬送波周波数の信号である基準信号ＳＳをフィードバックするように第1の乗算器２が配置されていたが、本実施の形態では、基準信号ＳＳを有効シンボル期間遅延回路４の後段にフィードフォワードするように第1の乗算器２が配置される。即ち、第1の乗算器２は、有効シンボル期間遅延回路４の出力が入力されるように配置されると共に、その出力が有効シンボル期間遅延回路４と位相誤差検出回路５とに向けては出力されず、復調信号ＤＳとして出力されるように配置される。
【０１１４】
以下、本実施の形態の副搬送波周波数復調部２７の動作を説明する。
【０１１５】
本実施の形態の副搬送波周波数信号変調部２７の副搬送波周波数信号ＢＳは、直接に位相誤差検出回路５に入力されると共に、直接に有効シンボル期間遅延回路４にも入力される。そして、有効シンボル期間遅延回路４によって有効シンボル期間分遅延させた信号が位相誤差検出回路５に入力されると共に、第1の乗算器２にも入力される。また、位相誤差検出回路５にて実施される動作以降の、数値制御発振器１０から出力された基準信号ＳＳと副搬送波周波数信号ＢＳとを第1の乗算器２により乗算することにより位相誤差を修正した復調信号ＤＳを得るところまでの動作は実施の形態１と同様である。
【０１１６】
このように副搬送波周波数信号復調部２７内の同期検波回路をフィードバック回路でなくフィードフォワード回路とすることにより、収束時間を短縮することができる。
【０１１７】
以上説明したように、本実施の形態に係る副搬送波周波数復調部２７は、同期検波回路を、有効シンボル期間遅延回路４によって有効シンボル期間分遅延させた信号が第1の乗算器２に入力されるフィードフォワード回路としたので、比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響を抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出でき、さらに、収束時間を短縮でき、位相誤差を検出した実際のシンボル期間に対して位相誤差補正を行うことができ、より精度よく安定に動作する副搬送波周波数信号復調装置を得ることができる。
【０１１８】
なお、上記の各実施の形態の副搬送波周波数信号復調部は、直交周波数分割多重（ＯＦＤＭ）方式の受信機に適用したものとして記載したが、例えば、ディジタルテレビジョン受信機等の復調部の一部回路として組み込むようにしてもよい。
【０１１９】
また、本発明の副搬送波周波数信号復調装置は、上記の各実施の形態中に説明した副搬送波周波数復調部を構成する各種回路の種類、接続状態、あるいは、副搬送波周波数復調部に接続される主信号部の種類、制御方法等は前述した実施の形態中に説明したもの限られるものではない。
【０１２０】
【発明の効果】
請求項１の発明によれば、直交周波数分割多重受信機中に用いられる副搬送波周波数信号を復調する副搬送波周波数信号復調装置において、位相誤差を検出するためにガードインターバル期間とそれに対応する有効シンボル期間の後部との相関特性を求める際、相関特性検出期間をいくつかの細分期間に分割し、各細分期間における第1の位相分割誤差値に対して重み付けを行って、その演算値を第2の位相誤差値として求める手段を備えるように構成したので、
マルチパス伝送路を経由することにより遅延した副搬送波周波数信号によって相関検出期間中の相関が弱くなる期間の影響を抑え、位相誤差検出精度の劣化を防ぎ、動作を安定させることができる効果を奏する。
【０１２１】
請求項２の発明によれば、相関特性検出期間をいくつかの細分期間に分割し、各細分期間における第1の位相分割誤差値に対して重み付けを行う際、重み関数を各第1の位相誤差値の振幅の比をもとに計算する手段を備えるように構成したので、
比較的簡易な回路構成で、マルチパス伝送路を経由することにより遅延した副搬送波周波数信号によって相関検出期間中の相関が弱くなる期間の影響を抑え、位相誤差検出精度の劣化を防ぎ、動作を安定させることができる効果を奏する。
【０１２２】
請求項３の発明によれば、相関特性検出期間をいくつかの細分期間に分割し、各細分期間における第1の位相誤差値に対して重み付けを行う際、重み関数を各第1の位相誤差値の振幅のべき乗の比をもとに計算する手段を備えるように構成したので、
重み付けの比率を請求項２の構成よりもさらに強調することができ、ルチパス伝送路を経由することにより遅延した副搬送波周波数信号によって相関検出期間中の相関が弱くなる期間の影響をさらに抑え、位相誤差検出精度の劣化を防ぎ、より動作を安定させることができる効果を奏する。
【０１２３】
請求項４の発明によれば、相関特性検出期間をいくつかの細分期間に分割し、各細分期間における第1の位相分割誤差値に対して重み付けを行って、その平均値を第2の位相誤差値として求める手段を備えるように構成したので、
比較的簡易な回路構成で、マルチパス伝送路を経由することにより遅延した副搬送波周波数信号によって相関検出期間中の相関が弱くなる期間の影響を抑え、位相誤差検出精度の劣化を防ぎ、動作を安定させることができる効果を奏する。
【０１２４】
請求項５の発明によれば、相関特性検出期間をいくつかの細分期間に分割し、各細分期間における第1の位相分割誤差値に対して重み付けを行って、そのべき乗平均値を第2の位相誤差値として求める手段を備えるように構成したので、
重み付けの比率を請求項４の構成よりもさらに強調することができ、マルチパス伝送路を経由することにより遅延した副搬送波周波数信号によって相関検出期間中の相関が弱くなる期間の影響をさらに抑え、位相誤差検出精度の劣化を防ぎ、より動作を安定させる効果を奏する。
【０１２５】
請求項６の発明によれば、副搬送周波数信号が第1の乗算器に入力されて同期検波を実施するフィードフォワード方式となるように構成したので、
比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響を抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出でき、さらに、収束時間を短縮できるという効果を奏する。
【０１２６】
請求項７の発明によれば、有効シンボル期間遅延回路によって有効シンボル期間分遅延させた副搬送周波数信号が第1の乗算器に入力されて同期検波を実施するフィードフォワード方式となるように構成したので、
比較的簡易な回路構成で、マルチパス遅延経路を経由する遅延波が存在する場合においても、マルチパス遅延信号によって相関が弱くなる期間の影響を抑えることができ、検出する位相誤差の精度の劣化を抑え、安定して位相誤差を検出でき、さらに、収束時間を短縮でき、実際位相誤差を検出したシンボルに対して位相誤差補正を行うことができ、より精度よく動作を安定させることができるという効果を奏する。
【図面の簡単な説明】
【図１】 本発明の実施の形態１である副搬送波周波数信号復調装置の構成を示すブロック図である。
【図２】 （ａ）〜（ｇ）は図１の位相誤差検出回路５に入力する復調信号ＤＳ等を示したタイミングチャートである。
【図３】 図２の（ｃ）、（ｅ）、（ｆ）、（ｇ）の信号を時間軸を拡大して示すと共に、相関特性検出期間を細分した細分期間を（ｈ）に示したタイミングチャートである。
【図４】 本発明の実施の形態２である副搬送波周波数信号復調装置の構成を示すブロック図である。
【図５】 本発明の実施の形態３である副搬送波周波数信号復調装置の構成を示すブロック図である。
【図６】 本発明の実施の形態４である副搬送波周波数信号復調装置の構成を示すブロック図である。
【図７】 本発明の実施の形態５である副搬送波周波数信号復調装置の構成を示すブロック図である。
【図８】 本発明の実施の形態６である副搬送波周波数信号復調装置の構成を示すブロック図である。
【図９】 本発明の実施の形態７である副搬送波周波数信号復調装置の構成を示すブロック図である。
【図１０】 ＯＦＤＭ受信機中の従来の副搬送波周波数信号復調装置の構成を示すブロック図である。
【符号の説明】
２ 第１の乗算器、 ４ 有効シンボル期間の遅延回路、 ５ 位相誤差検出回路、 ６ 重み関数回路、 ７ 第２の乗算器、 ８ 演算回路、 ９ ループフィルタ、 １０ 数値制御発振回路、 １２ 最大値検出回路、 １３ 正規化回路、 １４ べき乗回路、 １５ 平均回路、 １６ べき乗平均回路、２０〜２７ 副搬送波周波数信号復調部、 ５０ ＯＦＤＭ受信機、 ＢＳ 副搬送波周波数信号、 ＤＳ 復調信号、 ＳＳ 基準信号（ｃｏｓ信号及びｓｉｎ信号）。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a subcarrier frequency signal demodulating apparatus for demodulating a subcarrier frequency signal used in a receiver that demodulates a modulated signal transmitted by an orthogonal frequency division multiplexing system, and more specifically, an orthogonal frequency division multiplexing system. Using the phase error signal calculated based on the correlation value between the guard interval period in one symbol period of the digital modulation signal transmitted by the above and the guard interval transfer period arranged at the last part of the corresponding effective symbol period. The present invention relates to a subcarrier frequency signal demodulating device for a receiver that demodulates a subcarrier frequency signal by controlling a subcarrier frequency reference signal and synchronously detecting the subcarrier frequency signal.
[0002]
[Prior art]
A receiver that demodulates a modulated signal transmitted by an orthogonal frequency division multiplexing transmission system will be described with reference to the drawings.
[0003]
FIG. 10 is a configuration block diagram of an OFDM receiver that receives a modulated signal of an orthogonal frequency division multiplexing (OFDM) transmission scheme.
[0004]
A receiving antenna 40 is attached to the OFDM receiver 50. The receiving antenna 40 is connected to the main carrier frequency signal demodulator 30 inside the OFDM receiver 50. The modulation signal of the OFDM transmission system received by the antenna 40 is input to the main carrier frequency signal demodulator 30 and is primarily demodulated by the main carrier frequency reference signal, and the subcarrier frequency signal is output from the main carrier frequency signal demodulator 30. BS is output, and this subcarrier frequency signal BS is secondarily demodulated by the subcarrier frequency signal demodulator 20 with the reference signal SS of the subcarrier frequency, and the demodulated signal DS is output from the subcarrier frequency signal demodulator 20.
[0005]
In FIG. 10, 2 is a multiplier, 4 is a delay circuit for an effective symbol period, 5 is a phase error detection circuit for detecting a phase error based on correlation characteristics, 9 is a loop filter capable of gain adjustment, and 10 is numerical control. And SS is an output signal of the numerically controlled oscillation circuit 10 oscillated in response to the phase error signal input at the sampling time N, and is multiplied by the subcarrier frequency signal BS by the multiplier 2. This is a reference signal of the subcarrier frequency.
[0006]
Next, the operation of the conventional subcarrier frequency signal modulation unit 20 shown in FIG. 10 will be described.
[0007]
When the OFDM receiver 50 receives the modulation signal of the OFDM transmission method, the subcarrier frequency signal BS is input from the main carrier frequency signal demodulator 30 to the multiplier 2 in the subcarrier frequency signal demodulator 20. Is output from the multiplier 2 as a demodulated signal DS whose phase error is not corrected. The demodulated signal DS and a signal obtained by delaying the demodulated signal DS by the effective symbol period delay circuit 4 by the effective symbol period are input to the phase error detection circuit 5. The phase error detection circuit 5 detects the correlation characteristics of the two input signals and outputs a phase error signal. The phase error signal is input to the loop filter 9, and the phase error signal from which high-frequency noise has been removed by the loop filter 9 is input to the numerically controlled oscillation circuit 10.
[0008]
Here, the reference signal SS output from the numerically controlled oscillation circuit 10 includes cos θ (N) and sin θ (N) (θ (N) corresponding to the output signal Δθ (N) of the loop filter 9 at an arbitrary sampling time N. = Δθ (N) + Δθ (N + 1)).
[0009]
Since the reference signal SS output from the numerically controlled oscillator 10 is controlled to be oscillated so that the phase error signal ES becomes small, the demodulated signal DS obtained by multiplying the subcarrier frequency signal BS and the reference signal SS by the multiplier 2 is used. The phase error is reduced.
[0010]
In the phase error signal ES, a correlation characteristic between the demodulated signal DS and a signal obtained by delaying the demodulated signal 3 by an amount corresponding to the effective symbol period length is detected in the phase error detection circuit 5, and the correlation value thereof is detected. Is generated by detecting the phase error of the demodulated signal based on the above. In FIG. 10, the demodulated signal DS input to the effective symbol period delay circuit 4 is output after being delayed by an amount corresponding to the effective symbol period length. In the phase error detection circuit 5, a correlation characteristic between the signal obtained by delaying the demodulated signal DS and the demodulated signal DS not delayed is detected, and a phase error signal ES is generated based on the value of the correlation characteristic. Is output. The phase error signal ES output from the phase error detection circuit 5 is output to the numerically controlled oscillation circuit 10 after the high frequency noise such as a harmonic component of the phase error signal ES is removed by the loop filter 9.
[0011]
As described above, synchronous detection is performed in the subcarrier frequency signal demodulator 20. The general operation of synchronous detection is as follows. A phase error signal ES is generated based on the demodulated signal DS, and the oscillation frequency of the reference signal SS of the subcarrier frequency output from the numerical control oscillation circuit 10 is controlled by the phase error signal ES. The subcarrier frequency signal BS and the subcarrier frequency reference signal SS are multiplied by the multiplier 2 to output a demodulated signal DS. When the phase error between the subcarrier frequency signal BS and the subcarrier frequency reference signal SS is large, the value of the phase error signal ES is also large.
[0012]
[Problems to be solved by the invention]
However, the conventional subcarrier frequency signal demodulator 20 as shown in FIG. 10 obtains the phase error based on the correlation characteristic between the demodulated signal DS and a signal obtained by delaying the demodulated signal DS by a predetermined time. When a demodulated signal received after being delayed by a multipath transmission path (multipath delay wave demodulated signal) is received, it is received by a normal transmission path that connects the transmitter and receiver with the shortest path. The multipath delayed wave demodulated signal is added to the demodulated signal, and the correlation characteristics required in the phase error detection circuit 5 change due to the influence of the multipath delayed wave demodulated signal.
[0013]
Specifically, there is no correlation between the guard interval transfer period in the demodulated signal and the portion immediately before the guard interval transfer period (non-guard interval transfer period) in the effective symbol period of the multipath delayed wave demodulated signal. The correlation between the beginning of the guard interval transfer period and the end of the period corresponding to the delay time of the multipath delayed wave is low. Further, a delay guard interval period which is a guard interval period delayed by an effective symbol period, and an effective symbol period in a multipath delayed wave delayed demodulated signal further delayed by an effective symbol period from the multipath delayed wave demodulated signal. Since there is no correlation with the guard interval transfer period, the period corresponding to the delay time of the multipath delay wave from the beginning in the delay guard interval period delayed by the effective symbol period in the demodulated signal delayed for correlation detection ends. The correlation until the time is reduced. As a result, there arises a problem that the accuracy of the detected phase error is deteriorated.
[0014]
The present invention has been made in order to solve the conventional problems as described above, and suppresses deterioration in accuracy of a phase error to be detected even when a delayed wave passing through a multipath delay path is present, and is stable. An object of the present invention is to provide a subcarrier frequency signal demodulator capable of detecting a phase error.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the subcarrier frequency signal demodulator according to the present invention described in claim 1 is characterized in that the modulation signal in the receiver for demodulating the modulation signal transmitted by the orthogonal frequency division multiplexing transmission system is mainly used. A subcarrier frequency signal demodulator that outputs a demodulated signal by synchronously detecting a subcarrier frequency signal primarily demodulated with a carrier frequency reference signal using a subcarrier frequency reference signal. A first multiplier that outputs a demodulated signal by multiplying the frequency signal by a reference signal of the subcarrier frequency, and outputs the output of the multiplier delayed by an effective symbol period length in one symbol period A correlation characteristic between the effective symbol period delay circuit, the output of the multiplier and the output signal of the effective symbol period delay circuit is detected, and a first demodulated signal is detected based on the value of the correlation characteristic And a value of the first phase error is a predetermined value N (N is an integer equal to or greater than 2 and smaller than the total number of pulses of the clock signal used during the guard interval of the one symbol period). A phase error detection circuit that outputs a first phase division error value divided into subdivided periods, and a first phase division error value that is output from the phase error detection circuit according to the influence of the multipath delay wave, respectively. A weighting function circuit for calculating a plurality of weighting functions for performing weighting based on the phase division error value, and the phase division error value subdivided from the phase error detection circuit are output from the weighting function circuit, respectively. A second multiplier that outputs a plurality of second phase division error values weighted by multiplying corresponding weight functions; and a second unit based on the plurality of second phase division error values. An arithmetic circuit that calculates an error value, a loop filter that outputs high frequency noise from the second phase error value, and an oscillation frequency that is used as a reference signal for the subcarrier frequency based on the output of the loop filter And a numerically controlled oscillating circuit for controlling and outputting the signal.
[0016]
According to a second aspect of the present invention, in the subcarrier frequency signal demodulating apparatus according to the first aspect, the weighting function circuit calculates the weighting function based on a ratio of amplitudes of the phase error values. .
[0017]
According to a third aspect of the present invention, in the subcarrier frequency signal demodulating device according to the first aspect, the weighting function circuit calculates the weighting function based on a power ratio of the amplitude of each phase error value. To do.
[0018]
According to a fourth aspect of the present invention, in the subcarrier frequency signal demodulating device according to the first aspect, the arithmetic circuit calculates an average of the weighted phase error values in order to obtain the second phase error value. It is characterized by doing.
[0019]
According to a fifth aspect of the present invention, in the subcarrier frequency signal demodulating device according to the first aspect, the arithmetic circuit calculates a power average of the weighted phase error values in order to obtain the second phase error value. It is characterized by calculating.
[0020]
The subcarrier frequency signal demodulating apparatus according to the present invention as claimed in claim 6 is a receiver for demodulating a modulated signal transmitted by an orthogonal frequency division multiplexing transmission system, wherein the modulated signal is subjected to primary demodulation by a reference signal of a main carrier frequency. A subcarrier frequency signal demodulating apparatus that outputs a demodulated signal by synchronously detecting the subcarrier frequency signal using a subcarrier frequency reference signal, wherein the subcarrier frequency signal is added to the subcarrier frequency signal. A first multiplier that outputs a demodulated signal by multiplying the signal; an effective symbol period delay circuit that outputs the subcarrier frequency signal by delaying the subcarrier frequency signal by an effective symbol period length in one symbol period; A correlation characteristic between the carrier frequency signal and the output signal of the effective symbol period delay circuit is detected, and a first phase error of the demodulated signal is detected based on the value of the correlation characteristic The first phase error value is divided into sub-periods of a predetermined value N (N is an integer equal to or greater than 2 and smaller than the total number of pulses of the clock signal used during the guard interval of the one symbol period). A phase error detection circuit that outputs as a phase division error value of 1 and a first phase division error value output from the phase error detection circuit for weighting each according to the influence of a multipath delay wave A weight function circuit that calculates a plurality of weight functions based on the phase division error value; and a corresponding weight function output from the weight function circuit to each of the phase division error values subdivided from the phase error detection circuit. A second multiplier that outputs a plurality of second phase division error values weighted by multiplication, and calculates a second phase error value based on the plurality of second phase division error values; An arithmetic circuit, a loop filter that removes high-frequency noise from the second phase error value and outputs it, and an oscillation frequency used as a reference signal for the subcarrier frequency based on the output of the loop filter to output And a numerically controlled oscillation circuit.
[0021]
In the invention of claim 6, the feed-forward method is adopted in which the subcarrier frequency signal is input to the first multiplier to perform synchronous detection.
[0022]
The subcarrier frequency signal demodulating apparatus according to the present invention as set forth in claim 7 is a receiver for demodulating a modulated signal transmitted by an orthogonal frequency division multiplex transmission system, wherein the modulated signal is subjected to primary demodulation by a reference signal of a main carrier frequency. A subcarrier frequency signal demodulating apparatus that outputs a demodulated signal by synchronously detecting a subcarrier frequency signal using a reference signal of a subcarrier frequency, wherein the subcarrier frequency signal is effective during one symbol period. An effective symbol period delay circuit that outputs a delayed signal by a symbol period length; and a first multiplier that outputs a demodulated signal by multiplying the output of the effective symbol period delay circuit by the reference signal of the subcarrier frequency; Detecting a correlation characteristic between the subcarrier frequency signal and the output signal of the effective symbol period delay circuit, and determining a first phase of the demodulated signal based on the value of the correlation characteristic An error is detected, and the value of the first phase error is subdivided into a predetermined value N (N is an integer equal to or greater than 2 and smaller than the total number of pulses of the clock signal used during the guard interval of the one symbol period). A phase error detection circuit that outputs a first phase division error value divided into periods, and a plurality of weighting functions for weighting each of the first phase division error values output from the phase error detection circuit By multiplying the phase division error value subdivided from the phase error detection circuit by the corresponding weight function output from the weight function circuit, respectively. A second multiplier that outputs a plurality of weighted second phase division error values; an arithmetic circuit that calculates a second phase error value based on the plurality of second phase division error values; A loop filter for removing high-frequency noise from the second phase error value and outputting it, and a numerically controlled oscillation circuit for controlling and outputting an oscillation frequency used as a reference signal for the subcarrier frequency based on the output of the loop filter It is characterized by comprising.
[0023]
According to the seventh aspect of the present invention, the feedforward method is adopted in which the subcarrier frequency signal delayed by the effective symbol period by the effective symbol period delay circuit is input to the first multiplier to perform synchronous detection.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on illustrated embodiments. 1 to 9, parts having the same functions as those of the conventional subcarrier frequency signal demodulator shown in FIG.
[0025]
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a subcarrier frequency signal demodulator according to Embodiment 1 of the present invention.
[0026]
In FIG. 1, 21 is a subcarrier frequency demodulator which is a subcarrier frequency signal demodulator of this embodiment, 1 is a subcarrier frequency signal, 2 is a first multiplier, 3 is a demodulated signal, and 4 is an effective symbol period. The delay circuit 5 is a phase error detection circuit that detects each phase error based on the correlation characteristics for each period obtained by subdividing the correlation detection period, and 6 is multiplied by the demodulated signal in each period obtained by subdividing the correlation detection period. A weight function circuit for calculating a weight function, 7 a second multiplier, 8 an arithmetic circuit for calculating a signal for each weighted sub-period, 9 a loop filter capable of gain adjustment, and 10 a numerical control An oscillation circuit capable of frequency control, SS is a reference signal output from the numerically controlled oscillation circuit 10, and 17 is a phase error signal ES output from the arithmetic circuit 8.
[0027]
The first multiplier 2 multiplies the subcarrier frequency signal BS by the reference signal SS output from the numerically controlled oscillation circuit 10 so as to correspond to the phase error Δθ (N), thereby reducing the phase error of the subcarrier frequency signal BS. The demodulated signal DS is output after correction. The phase error detection circuit 5 detects the correlation characteristic with the output signal of the effective symbol period delay circuit 4, detects the first phase error of the demodulated signal based on the value of the correlation characteristic, and the first phase error. As a first phase division error value obtained by dividing the value of N into sub-periods of a predetermined value N (N is an integer greater than or equal to 2 and smaller than the total number of pulses of the clock signal used during the guard interval of the one symbol period) Output. The weighting function circuit 6 uses a first multiplier 7 to calculate a plurality of weighting functions for weighting the first phase division error value according to the influence of the multipath delayed wave by the second multiplier 7. Calculate and output based on. The second multiplier 7 weights each first phase division error value by multiplying the first phase division error value by a weighting function, and outputs a second phase division error value. The arithmetic circuit 8 outputs a phase error signal ES that is a second phase error value by performing an operation such as addition for each second phase division error value. The loop filter 9 has, for example, at least one filter having different frequency characteristics and variable gain, and adds and outputs the outputs of the filters.
[0028]
Next, the operation in the subcarrier frequency signal modulation unit 21 of the present embodiment shown in FIG. 1 will be described with reference to FIG.
[0029]
When the OFDM receiver 50 receives an OFDM transmission modulation signal, the subcarrier frequency signal BS is input from the main carrier frequency signal demodulator 30 to the first multiplier 2 in the subcarrier frequency signal demodulator 21.
[0030]
Here, synchronous detection is performed in the subcarrier frequency signal demodulating unit 21, and the schematic operation of the synchronous detection is the same as the operation in the conventional subcarrier frequency signal modulating unit 20 shown in FIG. .
[0031]
In the initial state of the subcarrier frequency signal modulation unit 21, a demodulated signal DS whose phase error is not corrected is output from the first multiplier 2. The demodulated signal DS and a signal obtained by delaying the demodulated signal DS by the effective symbol period delay circuit 4 by the effective symbol period are input to the phase error detection circuit 5. The phase error detection circuit 5 detects the correlation characteristics of the two input signals and outputs a phase error signal. This phase error signal ES is output so as to synchronize the guard interval period and the last part of the effective symbol period corresponding thereto.
[0032]
The phase error signal output from the phase error detection circuit 5 is divided and output for each period obtained by subdividing the correlation characteristic detection period. That is, the phase error detection circuit 5 divides the correlation characteristic detection period into 1 to N subdivision periods, and detects and outputs a phase error based on the correlation value detected for each subdivision period.
[0033]
The weight function circuit 6 calculates a weight function for each sub-period based on the output value of each sub-period of the phase error detection circuit 5. For example, for a highly correlated sub-period, the weight function is increased, and a signal (multi-path delayed wave) obtained by demodulating a sub-period having a weak correlation, that is, a delayed wave (multi-path delayed wave) that has passed through other than the shortest path in the multi-path. The influence of the multipath delay wave on the demodulated signal is suppressed by reducing the weighting function during the period when the phase error detection accuracy is low due to the influence of the demodulated signal).
[0034]
Each weight function corresponding to each output of the phase error detection circuit 5 output from the weight function circuit 6 is multiplied by each output of the phase error detection circuit 5 by the second multiplier 7, and a phase error signal for each subdivision period is obtained. Is weighted. The arithmetic circuit 8 receives the signals output from all the second multipliers 7 and outputs a final phase error signal ES by performing an operation based on each input signal.
[0035]
The output of the arithmetic circuit 8, that is, the phase error signal ES is input to the loop filter 9 which can adjust the gain. The phase error signal from which the high frequency noise has been removed by the loop filter 9 is input to the numerically controlled oscillation circuit 10.
[0036]
The numerically controlled oscillation circuit 10 has cos θ (N) and sin θ (N) (θ (N) = Δθ (N) + Δθ (N + 1)) corresponding to the output signal Δθ (N) of the loop filter 9 at an arbitrary sampling time N. That is, the reference signal SS which is the reproduced subcarrier frequency signal is output. The reference signal SS output from the numerically controlled oscillator 10 and the subcarrier frequency signal BS are multiplied by the first multiplier 2 to obtain a demodulated signal DS in which the phase error is corrected.
[0037]
Here, a method for detecting the correlation characteristic between the signal obtained by delaying the demodulated signal DS and the demodulated signal DS not delayed will be described.
[0038]
FIG. 2 is a timing chart showing the demodulated signal DS and the like input to the phase error detection circuit 5 of FIG.
[0039]
FIG. 2A shows a demodulated signal DS that is not delayed, and ST0, ST1, and ST2 show one symbol period that is a signal unit of a transmission signal. The symbol period ST0 (hereinafter referred to as ST0) has a guard interval period GI0 (hereinafter referred to as GI0) and an effective symbol period ES0 (hereinafter referred to as ES0). Further, a period corresponding to GI0 from the last part to the front side in ES0 is a guard interval transfer period RG0 (hereinafter referred to as RG0). Similarly, each of the symbol periods ST1 and ST2 includes guard interval periods GI1 and GI2 (hereinafter referred to as GI1 and GI2) and effective symbol periods ES1 and ES2 (hereinafter referred to as ES1 and ES2). In addition, a guard interval transfer period RG1 (hereinafter referred to as RG1) is provided from the last part to the front side in the effective symbol period ES1.
[0040]
FIG. 2B shows a signal obtained by delaying the demodulated signal DS for correlation characteristic detection. DL0, DL1, and DL2 are delays corresponding to ES0, ES1, and ES2 in FIG. 2A, respectively. Indicates the period. DG0 and DG1 are delay guard interval periods in which GI0 and GI1 in FIG. 2A are delayed by the delay periods DL0 and DL1, respectively.
[0041]
As described above, ST0 to ST2, which are signal units of modulated signals transmitted by the orthogonal frequency division multiplexing system, are composed of GI0 to GI2 and ES0 to ES2. The guard interval periods GI0 to GI2 are provided at the beginning of each symbol period ST0 to ST2 in order to obtain signal synchronization between the transmitter and the receiver and to prevent reception signals from interfering with multipath delay signals. It has been. The effective symbol periods ES0 to ES2 are periods in which actually demodulated communication data is included, and the last part RG0 to RG1 in each period corresponds to each guard interval period corresponding to the symbol periods ST0 to ST2. Copied to GI0 to GI2.
[0042]
Since the demodulated signals in GI0 and GI1 in FIG. 2A are obtained by transferring the demodulated signals in RG0 and RG1 in FIG. 2A, the demodulated signals in GI0 are the same as the demodulated signals in RG0. The demodulated signal in GI1 has the same content as the demodulated signal in RG1. Therefore, the demodulated signal in DG0 in which GI0 is delayed by the delay period DL0 and the demodulated signal in RG0 have the same contents, and the demodulated signal in DG1 and the demodulated signal in RG1 in which GI1 is delayed by the delay period DL1 Are the same content. However, DG0 and RG0 or DG1 and RG1 are not always synchronized.
[0043]
Therefore, as shown in FIG. 2C, correlation characteristic detection periods DT0 and DT1 (hereinafter referred to as DT0 and DT1) are provided so as to be the same period as RG0 or RG1, and the demodulated signal in RG0 in DT0 is provided. The correlation characteristic between the contents and the contents of the demodulated signal in DG0 is detected, and the correlation characteristics between the contents of the demodulated signal in RG1 and the contents of the demodulated signal in DG1 in DT1 are detected. Since the amount of phase shift between the demodulated signal in RG0 and the demodulated signal in DG0, that is, the phase error can be detected from the detected correlation characteristic value, the phase error signal is output from the phase error detection circuit 5.
[0044]
In this way, the phase error can be detected, but this is also proved mathematically. For example, Paul H. Moose, "A Technique for Orthogonal Frequency Division Multiplexing Frequency Offset Correction" The principle of demodulation by the signal demodulator is shown mathematically.
[0045]
Here, the phase error is obtained using a frequency offset. First, the n th sample in the i th symbol of the OFDM signal including the frequency offset δf is _n And When n is in the guard interval period, the autocorrelation characteristic function R expressed by equation (1) _N Define
[0046]
[Expression 1]

[0047]
Where E [x] is the expected value of x and x ^* Represents the complex conjugate of x. N is the FFT (Fast Fourier Transform) size.
[0048]
If there is a frequency offset, ignore the noise and s _{n + N} S _n And the frequency offset δf are expressed as the following equation (2).
[0049]
[Expression 2]

[0050]
Substituting equation (2) into equation (1) yields the following equation (3).
[0051]
[Equation 3]

[0052]
Here, assuming that the calculation of the expected value E [x] can be approximated by a time average in the guard interval period GI, Expression (1) is expressed as the following Expression (4).
[0053]
[Expression 4]

[0054]
Therefore, the frequency offset δf can be estimated as shown in the following equation (5) by extracting the phase component in the complex data obtained by the equation (4).
[0055]
[Equation 5]

[0056]
From the equation (5) of the frequency offset δf, the phase error δθ can be obtained as shown in the following equation (6).
[0057]
[Formula 6]

[0058]
From the above, as shown in the equations (1) to (4), the correlation characteristics between the guard interval period and the last part of the effective symbol period corresponding to the guard interval period are obtained and shown in the equations (5) to (6). Thus, it can be seen that the phase error of the demodulated signal can be detected mathematically by extracting the phase component therefrom.
[0059]
2D to 2G are timing charts showing the relationship between the multipath delayed wave demodulated signal and the normal demodulated signal.
[0060]
(D) of FIG. 2 shows the multipath delayed wave demodulated signal, (e) shows the demodulated signal of (a) and the multipath delayed wave demodulated signal superimposed on the upper and lower stages, and (f) shows (c) In the correlation characteristic detection period, a period in which the correlation characteristic is changed and a period in which the correlation characteristic is not changed are shown. (G) is a delay of the demodulated signal and the multipath delayed wave demodulated signal delayed for correlation detection in (b). The demodulated signal is shown superimposed on the upper and lower stages.
[0061]
Since each symbol period MS0 to MS2 in the multipath delayed wave demodulated signal shown in FIG. 2D passes through a delay path in the multipath transmission path (hereinafter referred to as a multipath delay path), (a ) With respect to each symbol period ST0 to ST2 in the normal demodulated signal shown in FIG. Therefore, ME0b (in the demodulated signal passing through the multipath delay path shown in the lower part of FIG. 2 (e) is compared to RG0 in the demodulated signal passing through the normal path shown in the upper part of FIG. The period in the multipath delayed wave demodulated signal corresponding to RG0 is also delayed by the period dt. Therefore, during the period from the beginning of RG0 in the demodulated signal to the period dt, that is, the correlation characteristic change period DT0a shown in FIG. 2F, ME0a (effective symbol) in the demodulated signal passing through the multipath delay path. Affected by the non-RG0 portion in the period ES0). Similarly, the correlation characteristic change period DT0b shown in (f) of FIG. 2 is affected by ME0b in the demodulated signal passing through the multipath delay path. Here, RG0 and ME0b are correlated because they are the same signals in a delayed relationship, but RG0 and ME0a have no correlation.
[0062]
On the other hand, with respect to DG0 in the signal in which the demodulated signal passing through the normal path shown in the upper part of FIG. 2G is delayed for correlation detection, the multipath delay path shown in the lower part of FIG. MI0 in the signal in which the demodulated signal passing through is delayed for correlation detection (period corresponding to DG0 in the multipath delayed wave demodulated signal delayed for correlation detection) is also delayed by the period dt. Therefore, for the correlation characteristic change period DT0a shown in (f) of FIG. 2 from the beginning of DG0 in the demodulated signal delayed for correlation detection, that is, for the correlation characteristic change period DT0a shown in FIG. The signal is affected by MD0b in the signal delayed for correlation detection (the period in the multipath delayed wave demodulated signal corresponding to the non-RG0 portion in the effective symbol period ES0). Similarly, for the correlation characteristic change period DT0b shown in FIG. 2F, the demodulated signal passing through the multipath delay path is affected by MI0 in the signal delayed for correlation detection. Here, DG0 and MI0 are correlated because they are the same signal in a delayed relationship, but DG0 and MD0b have no correlation.
[0063]
Therefore, since there is no correlation between RG0 and ME0a, the correlation between the beginning of RG0 and the period dt in the demodulated signal is low, and there is no correlation between DG0 and MD0b, so the demodulated signal is delayed for correlation detection. The correlation between the beginning of DG0 in the received signal and the period dt becomes low. As a result, for example, in the conventional subcarrier frequency signal demodulator 20 shown in FIG. End up.
[0064]
In the present embodiment, the final phase error is detected by detecting the period from the beginning of RG0 to the period dt and the period from the beginning of DG0 to the period dt in FIG. The accuracy of the is not degraded.
[0065]
FIG. 3 shows the signals (c), (e), (f), and (g) of FIG. 2 with the time axis expanded, and the subdivision period obtained by subdividing the correlation characteristic detection period is shown in (h). It is a timing chart.
[0066]
3 (c), (e) to (g) are enlarged views of the time axis of the signal with the same number shown in FIG. 2, and (h) is the phase error of the present embodiment. A subdivision period obtained by subdividing the correlation characteristic detection period by the detection circuit 5 is shown. This subdivision period is preferably divided finely. However, since the ability to detect the correlation does not become finer than the wavelength of the clock signal, in this embodiment, a predetermined value N (N is an integer of 2 or more and the one symbol period) The subdivision period is divided into a number smaller than the total number of pulses of the clock signal used during the guard interval period.
[0067]
Thus, by subdividing the correlation characteristic detection period, the delay period dt of the subcarrier frequency signal passing through the multipath delay path can be specified. Therefore, the subcarrier frequency signal passing through the multipath delay path is the normal path. The correlation characteristic change period DT0a, which is a period during which the correlation decreases, can be specified by adding to the subcarrier signal that passes through.
[0068]
In the present embodiment, the weighting function circuit 6 sets the weighting function for the correlation characteristic change period DT0a low and sets the weighting function for the correlation characteristic change period DT0b high. Then, in the final phase error signal calculated by the arithmetic circuit 8, the influence of the subcarrier frequency signal via the multipath delay path is reduced.
[0069]
As described above, the subcarrier frequency signal demodulating apparatus 21 according to the present embodiment divides the correlation characteristic detection period into several subdivided periods and outputs the first phase division error value for each subdivided period. Error detection circuit 5, weight function circuit 6 for calculating a weight function for weighting the first phase division error value, and weight function corresponding to the first phase division error value that is the output of phase error detection circuit 5 And a second multiplier 7 that outputs the second phase division error value and an arithmetic circuit 8 that calculates the second phase division error value, and divides the correlation characteristic detection period into several subdivision periods. Then, each phase error value in each subdivision period is weighted, and a value obtained as a result of calculating the phase error value for each subdivision period is output as a final phase error signal. Based on subcarrier frequency Since the reference signal is generated by reproducing the signal and the sub-carrier frequency signal is synchronously detected, even when there is a delay signal passing through the multipath delay path, the correlation is weak due to the delay signal. The influence of a certain period can be suppressed, the deterioration of the accuracy of the detected phase error can be suppressed, and the phase error can be detected stably.
[0070]
Embodiment 2. FIG.
FIG. 4 is a block diagram showing a subcarrier frequency signal demodulating apparatus according to Embodiment 2 of the present invention. In the following FIGS. 4 to 9, parts having the same functions as those of the subcarrier frequency signal demodulating apparatus of the first embodiment shown in FIG.
[0071]
The subcarrier frequency signal demodulator 22 of the second embodiment compares the maximum amplitude value of the first phase division error value with respect to the setting of the weighting function in the weighting function circuit 6 shown in FIG. Is normalized and calculated.
[0072]
In FIG. 4, reference numeral 12 denotes a maximum value detection circuit for detecting a maximum value from each first phase division error value output for each subdivision period output from the phase error detection circuit 5, and 13 denotes a maximum value detected by the maximum value detection circuit 12. Is a normalization circuit that normalizes the output of each subdivision period of the phase error detection circuit 5 and calculates the weight function.
[0073]
Hereinafter, the operation of the subcarrier frequency demodulation unit 22 of the present embodiment will be described.
[0074]
The subcarrier frequency signal modulation unit 24 of the present embodiment outputs the demodulated signal DS whose phase error is not corrected in the initial state from the multiplier 2, and then subtracts each first subdivision by the phase error detection circuit 5. The operation until the phase division error value is output is the same as in the first embodiment.
[0075]
The weight function circuit 6 calculates a weight function for each subdivision period based on each first phase division error value value of the phase error detection circuit 5. In the present embodiment, each first phase division error value that is the output of the phase error detection circuit 5 is input to the maximum value detection circuit 12, and the maximum phase error value in each first phase division error value is obtained. It is detected as the maximum value. For example, the detected maximum value is set to 1, for example, each first phase division error value is normalized by the normalization circuit 13, and this normalization result is used as a weighting function for each subdivision period. By normalizing each first phase division error value, the weighting function becomes large for the highly correlated subdivision period, and the phase error detection accuracy by the delayed signal that passed through the multipath delay path, that is, the subcorrelation period with weak correlation The weighting function becomes smaller during the period when the value becomes lower.
[0076]
Each weight function corresponding to each first phase division error value of the phase error detection circuit 5 output from the weight function circuit 6 is converted into each first phase division error of the phase error detection circuit 5 by the second multiplier 7. By multiplying by the value, each first phase division error value is weighted to obtain a second phase division error value. The arithmetic circuit 8 receives the second phase division error value output from all the second multipliers 7, and performs an operation such as addition on each input signal to thereby obtain the second phase. A phase error signal ES which is an error value is output. The following operations are the same as those in the first embodiment.
[0077]
By setting the weight function in this way, the amplitude of the phase error detection value in a period where the phase error value is smaller than other periods, that is, a period where the correlation is weak due to the influence of the multipath delay wave is suppressed. Therefore, it is possible to suppress the influence of the subdivision period in which the correlation is weakened by the delay signal that has passed through the multipath delay path.
[0078]
As described above, the subcarrier frequency demodulation unit 22 according to the present embodiment uses the maximum value detection circuit 12 and the normalization circuit 13 to calculate the weight function calculated by the weight function circuit 6 using the first phase division error value. Since the calculation is based on the ratio of the amplitudes of the signals, even when there is a delayed wave that passes through the multipath delay path with a relatively simple circuit configuration, the correlation is weakened by the multipath delay signal. The influence can be further suppressed than in the first embodiment, the deterioration of the accuracy of the detected phase error can be suppressed, and the phase error can be detected stably.
[0079]
Embodiment 3 FIG.
FIG. 5 is a block diagram showing a subcarrier frequency signal demodulating apparatus according to Embodiment 3 of the present invention.
[0080]
The subcarrier frequency signal demodulator 23 of the present embodiment compares the power of the amplitude of each first phase division error value input for each subdivision period with respect to the setting of the weight function in the weight function circuit 6 shown in FIG. The comparison result is normalized and calculated.
[0081]
In FIG. 5, reference numeral 14 denotes a power circuit that powers the first phase division error value output from each subdivision period of the phase error detection circuit 5, and 12 denotes a maximum value detection circuit that detects the maximum value from each output of the power circuit 14. Reference numeral 13 denotes a normalization circuit that normalizes the output of each sub-period of the power circuit 14 based on the maximum value detected by the maximum value detection circuit 12 and calculates a weight function.
[0082]
Hereinafter, the operation of the subcarrier frequency demodulation unit 23 of the present embodiment will be described.
[0083]
The first phase subdivided by the phase error detection circuit 5 after the subcarrier frequency signal modulation unit 24 of the present embodiment outputs the demodulated signal DS whose phase error is not corrected in the initial state from the multiplier 2. The operation until the division error value is output is the same as in the first embodiment.
[0084]
The weight function circuit 6 calculates a weight function for each subdivision period based on each first phase division error value of the phase error detection circuit 5. In the present embodiment, each first phase division error value of the phase error detection circuit 5 is input to each power circuit 14, and each power circuit 14 calculates a power value of each first phase division error value. The The output of each power circuit 14 is input to the maximum value detection circuit 12, and the maximum phase error value is detected as the maximum value. For example, the detected maximum value is set to 1, for example, and the phase error value of each subdivision period is normalized by the normalization circuit 13, and the normalization result is used as a weighting function of each subdivision period. By normalizing the phase error value of each subdivision period, the weighting function becomes large for the subdivision period with strong correlation, and the phase error detection accuracy is low due to the subdivision period with weak correlation, i.e., the delayed signal via the multipath delay path. The weight function becomes smaller for the period.
[0085]
Each weight function corresponding to each output of the phase error detection circuit 5 output from the weight function circuit 6 is multiplied by each first phase division error value output from the phase error detection circuit 5 by the second multiplier 7. Then, each first phase division error signal for each subdivision period is weighted to obtain a second phase division error value. The arithmetic circuit 8 receives the second phase division error values output from all the second multipliers 7 and calculates each input signal, thereby calculating the phase error signal ES as the second phase error value. Is output. The following operations are the same as those in the first embodiment.
[0086]
By setting the weighting function in this way, the amplitude of the phase error detection value during the period in which the first phase division error value is smaller than the other periods, that is, the period in which the correlation is weak due to the influence of the multipath delay wave is suppressed. . Therefore, it is possible to suppress the influence of the subdivision period in which the correlation is weakened by the delay signal that has passed through the multipath delay path.
[0087]
As described above, the subcarrier frequency demodulator 23 according to the present embodiment uses the power circuit 14, the maximum value detection circuit 12, and the normalization circuit 13 to calculate the weight function calculated by the weight function circuit 6. Since the calculation is based on the ratio of the power of the amplitude of the phase division error value, the weighting ratio can be further emphasized as compared with the second embodiment, and the multipath delay can be achieved with a relatively simple circuit configuration. Even in the presence of a delayed wave that passes through the path, the influence of the period during which the correlation is weakened by the multipath delay signal can be further suppressed, the deterioration of the accuracy of the detected phase error is suppressed, and the phase error is stably suppressed. It can be detected.
[0088]
Embodiment 4 FIG.
FIG. 6 is a block diagram showing a subcarrier frequency signal demodulating apparatus according to Embodiment 4 of the present invention.
[0089]
In the subcarrier frequency signal demodulator 24 of this embodiment, the arithmetic circuit 8 shown in FIG. 1 averages each first phase division error value weighted by the weight function circuit 6 and the second multiplier 7. The operation to be performed is performed.
[0090]
In FIG. 6, reference numeral 15 denotes an averaging circuit that calculates the average of each second phase division error value that is the output of the second multiplier 7, and is provided in the arithmetic circuit 8.
[0091]
Hereinafter, the operation of the subcarrier frequency demodulator 24 of the present embodiment will be described.
[0092]
After the subcarrier frequency signal modulation unit 24 of the present embodiment outputs the demodulated signal DS whose phase error is not corrected in the initial state from the multiplier 2, it is subdivided by the weight function circuit 6 and the second multiplier 7. The operation until the first phase division error value for each period is weighted is the same as that in the first embodiment.
[0093]
The arithmetic circuit 8 receives each second phase division error value output from all the second multipliers 7 and calculates each input signal, thereby calculating a phase error signal as a second phase error value. ES is output.
[0094]
Here, since the arithmetic circuit 8 of the present embodiment is an average circuit 15, if each second phase division error value that is an output signal of all the second multipliers 7 is input to the average circuit 15, the average circuit 15 The circuit 15 calculates an average value and outputs the average value from the averaging circuit 15 as a phase error signal ES that is a second phase error value. The following operations are the same as those in the first embodiment.
[0095]
By calculating the average value of the respective phase error signals in this way, it is possible to suppress the influence of the subdivision period in which the correlation is weakened by the delay signal that has passed through the multipath delay path.
[0096]
As described above, the subcarrier frequency demodulation unit 24 according to the present embodiment has the arithmetic circuit 8 constituted by the averaging circuit 15, and the arithmetic circuit 8 calculates the average of the weighted second phase division error values. Since the second phase error value is obtained by calculation, the correlation is weakened by the multipath delay signal even when there is a delayed wave that passes through the multipath delay path with a relatively simple circuit configuration. The influence of the period can be further suppressed, the deterioration of the accuracy of the detected phase error can be suppressed, and the phase error can be detected stably.
[0097]
Embodiment 5. FIG.
FIG. 7 is a block diagram showing a subcarrier frequency signal demodulating apparatus according to Embodiment 5 of the present invention.
[0098]
In the subcarrier frequency signal demodulator 25 of the present embodiment, each second phase division error value weighted by the weighting function circuit 6 and the second multiplier 7 in the arithmetic circuit 8 shown in FIG. The average calculation is performed.
[0099]
In FIG. 7, reference numeral 16 denotes a power average circuit that calculates the power average of the second phase division error value that is the output of the second multiplier 7, and is provided in the arithmetic circuit 8.
[0100]
Hereinafter, the operation of the subcarrier frequency demodulation unit 25 of the present embodiment will be described.
[0101]
After the subcarrier frequency signal modulation unit 25 of the present embodiment outputs the demodulated signal DS whose phase error is not corrected in the initial state from the multiplier 2, it is subdivided by the weight function circuit 6 and the second multiplier 7. The operation until the first phase division error value for each period is weighted is the same as that in the first embodiment.
[0102]
The arithmetic circuit 8 receives each second phase division error value output from all the second multipliers 7 and calculates each input signal, thereby calculating a phase error signal as a second phase error value. ES is output.
[0103]
Here, since the arithmetic circuit 8 of the present embodiment is a power average circuit 16, when each second phase division error value that is an output signal of all the second multipliers 7 is input to the power average circuit 16. The power average circuit 16 calculates a power average value and outputs the power average value from the power average circuit 16 as a final phase error signal. The following operations are the same as those in the first embodiment.
[0104]
Thus, by calculating the power average value of each second phase division error value, it is possible to suppress the influence of the subdivision period in which the correlation is weakened by the delay signal that has passed through the multipath delay path.
[0105]
As described above, the subcarrier frequency demodulation unit 25 according to the present embodiment includes the arithmetic circuit 8 including the power average circuit 16, and calculates the power average of each weighted second phase division error value. Since the second phase error value is obtained by calculating in FIG. 8, the weighting ratio can be further emphasized as compared with the fourth embodiment shown in FIG. Even in the presence of a delayed wave that passes through the path delay path, the influence of the period during which the correlation is weakened by the multipath delay signal can be further suppressed, and the deterioration of the accuracy of the phase error to be detected is suppressed, and the phase is stabilized. Error can be detected.
[0106]
Embodiment 6 FIG.
FIG. 8 is a block diagram showing a subcarrier frequency signal demodulating apparatus according to Embodiment 6 of the present invention.
[0107]
In the subcarrier frequency signal demodulator 26 of the present embodiment, the arrangement of the first multiplier 2 that corrects the phase error of the subcarrier frequency signal BS and outputs the demodulated signal DS is different from that of the first embodiment described above. They are arranged differently. More specifically, in the first embodiment, the first multiplier 2 is arranged so as to feed back the reference signal SS that is a signal of the reproduced subcarrier frequency output from the numerically controlled oscillation circuit 10. In the present embodiment, the first multiplier 2 is arranged so as to feed forward the reference signal SS. That is, the first multiplier 2 is arranged so that its output is not output to the effective symbol period delay circuit 4 and the phase error detection circuit 5, but is output as the demodulated signal DS.
[0108]
Hereinafter, the operation of the subcarrier frequency demodulation unit 26 of the present embodiment will be described.
[0109]
The subcarrier frequency signal BS of the subcarrier frequency signal modulation unit 26 of this embodiment is directly input to the phase error detection circuit 5 and also directly to the effective symbol period delay circuit 4. Then, the signal delayed by the effective symbol period by the effective symbol period delay circuit 4 is input to the phase error detection circuit 5. Further, the phase error is corrected by multiplying the reference signal SS output from the numerically controlled oscillator 10 and the subcarrier frequency signal BS by the first multiplier 2 after the operation performed in the phase error detection circuit 5. The operation up to obtaining the demodulated signal DS is the same as in the first embodiment.
[0110]
In this way, by using the synchronous detection circuit in the subcarrier frequency signal demodulator 26 as a feedforward circuit instead of a feedback circuit, the convergence time can be shortened.
[0111]
As described above, since the subcarrier frequency demodulation unit 26 according to the present embodiment uses the synchronous detection circuit as a feedforward circuit, there is a delay wave that passes through a multipath delay path with a relatively simple circuit configuration. Even in this case, the influence of the period during which the correlation is weakened by the multipath delay signal can be suppressed, the deterioration of the accuracy of the detected phase error can be suppressed, the phase error can be detected stably, and the convergence time can be shortened. .
[0112]
Embodiment 7 FIG.
FIG. 9 is a block diagram showing a subcarrier frequency signal demodulating apparatus according to Embodiment 7 of the present invention.
[0113]
In the subcarrier frequency signal demodulator 27 of this embodiment, the arrangement of the first multiplier 2 that corrects the phase error of the subcarrier frequency signal BS and outputs the demodulated signal DS is different from that of the first embodiment described above. They are arranged differently. More specifically, in the first embodiment, the first multiplier 2 is arranged so as to feed back the reference signal SS that is a signal of the reproduced subcarrier frequency output from the numerically controlled oscillation circuit 10. In the present embodiment, the first multiplier 2 is arranged so as to feed forward the reference signal SS to the subsequent stage of the effective symbol period delay circuit 4. That is, the first multiplier 2 is arranged so that the output of the effective symbol period delay circuit 4 is input, and the output is output to the effective symbol period delay circuit 4 and the phase error detection circuit 5. It is arranged not to be output as a demodulated signal DS.
[0114]
Hereinafter, the operation of the subcarrier frequency demodulation unit 27 of the present embodiment will be described.
[0115]
The subcarrier frequency signal BS of the subcarrier frequency signal modulation unit 27 of this embodiment is directly input to the phase error detection circuit 5 and also directly to the effective symbol period delay circuit 4. A signal delayed by the effective symbol period by the effective symbol period delay circuit 4 is input to the phase error detection circuit 5 and also input to the first multiplier 2. Further, the phase error is corrected by multiplying the reference signal SS output from the numerically controlled oscillator 10 and the subcarrier frequency signal BS by the first multiplier 2 after the operation performed in the phase error detection circuit 5. The operation up to obtaining the demodulated signal DS is the same as in the first embodiment.
[0116]
In this way, by using the synchronous detection circuit in the subcarrier frequency signal demodulator 27 as a feedforward circuit instead of a feedback circuit, the convergence time can be shortened.
[0117]
As described above, in the subcarrier frequency demodulator 27 according to the present embodiment, the signal obtained by delaying the synchronous detection circuit by the effective symbol period delay circuit 4 by the effective symbol period is input to the first multiplier 2. Therefore, even if there is a delayed wave that passes through the multipath delay path, the influence of the period during which the correlation is weakened by the multipath delay signal can be suppressed. Degradation of the accuracy of the phase error to be detected is suppressed, the phase error can be detected stably, the convergence time can be shortened, and the phase error can be corrected for the actual symbol period in which the phase error is detected. A subcarrier frequency signal demodulator that operates stably with high accuracy can be obtained.
[0118]
The subcarrier frequency signal demodulator in each of the above embodiments has been described as being applied to an orthogonal frequency division multiplexing (OFDM) receiver. However, for example, a demodulator of a digital television receiver or the like It may be incorporated as a partial circuit.
[0119]
Further, the subcarrier frequency signal demodulating device of the present invention is connected to various circuit types, connection states, or subcarrier frequency demodulating units constituting the subcarrier frequency demodulating units described in the above embodiments. The type of main signal section, control method, and the like are not limited to those described in the above-described embodiments.
[0120]
【The invention's effect】
According to the first aspect of the present invention, in the subcarrier frequency signal demodulating apparatus for demodulating the subcarrier frequency signal used in the orthogonal frequency division multiplexing receiver, the guard interval period and the effective symbol corresponding thereto are detected in order to detect the phase error. When determining the correlation characteristics with the rear of the period, the correlation characteristic detection period is divided into several subdivision periods, the first phase division error value in each subdivision period is weighted, and the calculated value is calculated as the second subdivision period. Since it is configured to include a means for obtaining the phase error value of
It is possible to suppress the influence of the period during which the correlation during the correlation detection period is weakened by the subcarrier frequency signal delayed by passing through the multipath transmission line, prevent deterioration of the phase error detection accuracy, and stabilize the operation. .
[0121]
According to the second aspect of the present invention, when the correlation characteristic detection period is divided into several subdivision periods and the first phase division error value in each subdivision period is weighted, the weighting function is set to each first phase. Since it is configured to have a means to calculate based on the ratio of error amplitude,
With a relatively simple circuit configuration, the influence of the period during which the correlation during the correlation detection period is weakened by the subcarrier frequency signal delayed by passing through the multipath transmission line is suppressed, the deterioration of the phase error detection accuracy is prevented, and the operation is performed. There is an effect that can be stabilized.
[0122]
According to the third aspect of the present invention, when the correlation characteristic detection period is divided into several subdivided periods and the first phase error value in each subdivided period is weighted, the weight function is set to each first phase error. Since it was configured to have a means to calculate based on the ratio of the power of the amplitude of the value,
The weighting ratio can be further emphasized as compared with the configuration of claim 2, and the influence of the period during which the correlation during the correlation detection period is weakened by the subcarrier frequency signal delayed by passing through the multipath transmission path is further suppressed, and the phase It is possible to prevent the error detection accuracy from deteriorating and to stabilize the operation.
[0123]
According to the fourth aspect of the present invention, the correlation characteristic detection period is divided into several subdivision periods, the first phase division error value in each subdivision period is weighted, and the average value is set to the second phase. Since it is configured to have a means to obtain as an error value,
With a relatively simple circuit configuration, the influence of the period during which the correlation during the correlation detection period is weakened by the subcarrier frequency signal delayed by passing through the multipath transmission line is suppressed, the deterioration of the phase error detection accuracy is prevented, and the operation is performed. There is an effect that can be stabilized.
[0124]
According to the fifth aspect of the present invention, the correlation characteristic detection period is divided into several subdivided periods, the first phase division error value in each subdivided period is weighted, and the power average value is calculated as the second subdivided period. Since it is configured to include a means for obtaining the phase error value,
The weighting ratio can be further emphasized compared to the configuration of claim 4, and further suppresses the influence of the period in which the correlation during the correlation detection period is weakened by the subcarrier frequency signal delayed through the multipath transmission line, There is an effect of preventing the deterioration of the phase error detection accuracy and further stabilizing the operation.
[0125]
According to the invention of claim 6, since the subcarrier frequency signal is input to the first multiplier and is configured to be a feedforward system that performs synchronous detection,
Even in the presence of a delayed wave that passes through a multipath delay path with a relatively simple circuit configuration, the influence of the period during which the correlation is weakened by the multipath delay signal can be suppressed, and the accuracy of the detected phase error is degraded. The phase error can be detected stably, and the convergence time can be shortened.
[0126]
According to the seventh aspect of the present invention, the subcarrier frequency signal delayed by the effective symbol period by the effective symbol period delay circuit is input to the first multiplier and is configured to be a feedforward system in which synchronous detection is performed. So
Even in the presence of a delayed wave that passes through a multipath delay path with a relatively simple circuit configuration, the influence of the period during which the correlation is weakened by the multipath delay signal can be suppressed, and the accuracy of the detected phase error is degraded. The phase error can be detected stably, the convergence time can be shortened, the phase error correction can be performed on the symbol where the actual phase error is detected, and the operation can be stabilized more accurately. There is an effect.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a subcarrier frequency signal demodulating apparatus according to a first embodiment of the present invention.
2A to 2G are timing charts showing a demodulated signal DS and the like input to the phase error detection circuit 5 of FIG.
3 shows the signals of (c), (e), (f), and (g) of FIG. 2 with the time axis expanded, and the subdivision period obtained by subdividing the correlation characteristic detection period is shown in (h). It is a timing chart.
FIG. 4 is a block diagram showing a configuration of a subcarrier frequency signal demodulator according to a second embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a subcarrier frequency signal demodulator according to a third embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration of a subcarrier frequency signal demodulator according to a fourth embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a subcarrier frequency signal demodulator according to a fifth embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a subcarrier frequency signal demodulator according to a sixth embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a subcarrier frequency signal demodulator according to a seventh embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration of a conventional subcarrier frequency signal demodulator in an OFDM receiver.
[Explanation of symbols]
2 First multiplier, 4 Delay circuit of effective symbol period, 5 Phase error detection circuit, 6 Weight function circuit, 7 Second multiplier, 8 Arithmetic circuit, 9 Loop filter, 10 Numerically controlled oscillation circuit, 12 Maximum value Detection circuit, 13 normalization circuit, 14 power circuit, 15 average circuit, 16 power average circuit, 20-27 subcarrier frequency signal demodulator, 50 OFDM receiver, BS subcarrier frequency signal, DS demodulated signal, SS reference signal ( cos signal and sin signal).

Claims (7)

In a receiver that demodulates a modulated signal transmitted by an orthogonal frequency division multiplex transmission system, a reference signal of a subcarrier frequency is obtained with respect to a subcarrier frequency signal in which the modulated signal is primarily demodulated by a reference signal of a main carrier frequency. A subcarrier frequency signal demodulator that outputs a demodulated signal by using synchronous detection,
A first multiplier that outputs a demodulated signal by multiplying the subcarrier frequency signal by a reference signal of the subcarrier frequency;
An effective symbol period delay circuit that delays and outputs the output of the multiplier by an effective symbol period length in one symbol period;
A correlation characteristic between the output of the multiplier and the output signal of the effective symbol period delay circuit is detected, a first phase error of the demodulated signal is detected based on the value of the correlation characteristic, and the first phase error The value is output as a first phase division error value obtained by dividing the value into sub-periods of a predetermined value N (N is an integer equal to or greater than 2 and smaller than the total number of pulses of the clock signal used during the guard interval of the one symbol period) A phase error detection circuit that
Based on the first phase division error value, a plurality of weighting functions for weighting the first phase division error value output from the phase error detection circuit according to the influence of the multipath delayed wave, respectively. A weight function circuit to calculate,
A plurality of second phase division error values weighted by multiplying the first phase division error value outputted from the phase error detection circuit by the corresponding weight function outputted from the weight function circuit, respectively. A second multiplier to
An arithmetic circuit that calculates a second phase error value based on the plurality of second phase division error values;
A loop filter for removing high-frequency noise from the second phase error value and outputting,
A subcarrier frequency signal demodulating apparatus comprising: a numerically controlled oscillation circuit that controls and outputs an oscillation frequency used as a reference signal of the subcarrier frequency based on an output of the loop filter. 2. The subcarrier frequency signal demodulating apparatus according to claim 1, wherein the weighting function circuit calculates the weighting function based on a ratio of amplitudes of the phase error values. 2. The subcarrier frequency signal demodulating apparatus according to claim 1, wherein the weighting function circuit calculates the weighting function based on a power ratio of the amplitude of each phase error value. 2. The subcarrier frequency signal demodulating apparatus according to claim 1, wherein the arithmetic circuit calculates an average of the weighted phase error values in order to obtain the second phase error value. 2. The subcarrier frequency signal demodulating apparatus according to claim 1, wherein the arithmetic circuit calculates a power average of each of the weighted phase error values in order to obtain the second phase error value. In a receiver that demodulates a modulated signal transmitted by an orthogonal frequency division multiplex transmission system, a reference signal of a subcarrier frequency is obtained with respect to a subcarrier frequency signal in which the modulated signal is primarily demodulated by a reference signal of a main carrier frequency. A subcarrier frequency signal demodulator that outputs a demodulated signal by using synchronous detection,
A first multiplier that outputs a demodulated signal by multiplying the subcarrier frequency signal by a reference signal of the subcarrier frequency;
An effective symbol period delay circuit that delays and outputs the subcarrier frequency signal by an effective symbol period length in one symbol period;
A correlation characteristic between the output of the multiplier and the output signal of the effective symbol period delay circuit is detected, a first phase error of the demodulated signal is detected based on the value of the correlation characteristic, and the first phase error The value is output as a first phase division error value obtained by dividing the value into sub-periods of a predetermined value N (N is an integer equal to or greater than 2 and smaller than the total number of pulses of the clock signal used during the guard interval of the one symbol period) A phase error detection circuit that
Based on the first phase division error value, a plurality of weighting functions for weighting the first phase division error value output from the phase error detection circuit according to the influence of the multipath delayed wave, respectively. A weight function circuit to calculate,
A plurality of second phase division error values weighted by multiplying the first phase division error value outputted from the phase error detection circuit by the corresponding weight function outputted from the weight function circuit, respectively. A second multiplier to
An arithmetic circuit that calculates a second phase error value based on the plurality of second phase division error values;
A loop filter for removing high-frequency noise from the second phase error value and outputting,
A subcarrier frequency signal demodulating apparatus comprising: a numerically controlled oscillation circuit that controls and outputs an oscillation frequency used as a reference signal of the subcarrier frequency based on an output of the loop filter. In a receiver that demodulates a modulated signal transmitted by an orthogonal frequency division multiplex transmission system, a reference signal of a subcarrier frequency is obtained with respect to a subcarrier frequency signal in which the modulated signal is primarily demodulated by a reference signal of a main carrier frequency. A subcarrier frequency signal demodulator that outputs a demodulated signal by using synchronous detection,
An effective symbol period delay circuit that delays and outputs the subcarrier frequency signal by an effective symbol period length in one symbol period;
A first multiplier that outputs a demodulated signal by multiplying an output of the effective symbol period delay circuit by a reference signal of the subcarrier frequency;
A correlation characteristic between the output of the multiplier and the output signal of the effective symbol period delay circuit is detected, a first phase error of the demodulated signal is detected based on the value of the correlation characteristic, and the first phase error The value is output as a first phase division error value obtained by dividing the value into sub-periods of a predetermined value N (N is an integer equal to or greater than 2 and smaller than the total number of pulses of the clock signal used during the guard interval of the one symbol period) A phase error detection circuit that
Based on the first phase division error value, a plurality of weighting functions for weighting the first phase division error value output from the phase error detection circuit according to the influence of the multipath delayed wave, respectively. A weight function circuit to calculate,
A plurality of second phase division error values weighted by multiplying the first phase division error value outputted from the phase error detection circuit by the corresponding weight function outputted from the weight function circuit, respectively. A second multiplier to
An arithmetic circuit that calculates a second phase error value based on the plurality of second phase division error values;
A loop filter for removing high-frequency noise from the second phase error value and outputting,
A subcarrier frequency signal demodulating apparatus comprising: a numerically controlled oscillation circuit that controls and outputs an oscillation frequency used as a reference signal of the subcarrier frequency based on an output of the loop filter.

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