JP3779879B2 - Pulse width expansion circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pulse width expansion circuit, and more particularly to a pulse width expansion circuit using parasitic capacitance of a switching element.
[0002]
[Prior art]
As a pulse width expansion circuit used for the purpose of creating a pulse delayed by a certain time from the input pulse, for example, a circuit composed of a logic gate and a CR filter, which expands the pulse width using the CR time constant, etc. The method is introduced.
[0003]
Generally, these pulse width expansion circuits are configured using a capacitor for adjusting the pulse width. However, when the capacitor is mounted on an LSI, for example, a relatively large area is required, which is inconvenient for circuit miniaturization. For this reason, a pulse width expansion circuit using a parasitic capacitance of a switching element has been proposed as a technique for realizing a pulse width expansion circuit with a relatively simple configuration without using a capacitor (Japanese Patent Laid-Open No. 49-80961). .
[0004]
This is because a first switch element that is opened when a control pulse arrives and a second switch element that is opened when an input pulse arrives are connected in series, and a voltage is applied between both ends thereof. A third switch element that is closed by a parasitic capacitance when the second switch element is opened, and that is opened due to a change in the parasitic capacitance due to the opening of the first switch element when the second switch element is closed; A pulse width expansion circuit characterized in that a pulse output signal having a width corresponding to the closed circuit is obtained.
[0005]
[Problems to be solved by the invention]
According to the above pulse width expansion circuit, the output pulse starts when the input pulse arrives, and the output pulse ends when the control pulse (clock pulse) arrives after the input pulse ends. For this reason, the output pulse width is limited within the pulse width determined by the timing of the input pulse and the clock pulse, and adjustment of the expanding pulse width is not considered.
[0006]
An object of the present invention is to provide a circuit capable of adjusting an output pulse width in a pulse width expansion circuit using a parasitic capacitance of a switching element.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, rectifying means for passing an input signal and blocking a signal in the reverse direction;
A constant current source means connected to the output side of the rectifying means, and supplying a predetermined current in the forward direction of the rectifying means;
Switching means that enters a conductive state based on an input signal through the rectifying means, has a parasitic capacitance that is charged by a voltage based on the input signal and discharged by the constant current source means, and the parasitic capacitance Switching means for maintaining conduction by the generated voltage;
Means for generating an output signal based on the state of the switching means;
A pulse width expansion circuit is provided.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings.
[0009]
FIG. 1 is a circuit diagram for explaining the operation principle of the pulse width expansion circuit according to the first embodiment of the present invention. As shown in the figure, the pulse width expansion circuit according to the present embodiment includes a diode D that is a rectifier, a constant current source CC, and a switching element SW having an input (gate) capacitance Ci as a parasitic capacitance. In the figure, a single channel MOS is used as the switching element SW.
[0010]
The input terminal (Vi) is connected to one end of a diode D, which is a rectifying element. The other end of the diode D is applied to the input terminal and a constant current source CC that supplies current in the forward direction of the diode D. The switching element SW that becomes conductive by the voltage is connected.
[0011]
One end of the load resistor RL is connected to the output terminal (Vo) of the switching element SW, and the power supply voltage Vcc is applied to the other end of the load resistor RL. In this way, an output signal can be extracted from the load resistor RL.
[0012]
The operation of the pulse width expansion circuit of this embodiment will be described using the operation waveform diagram of FIG. First, it is assumed that the potential V1 of the input terminal (gate) of the switching element SW is 0, and the switching element SW is in a cut-off state. At this time, the state of the voltage Vo at the output terminal is “H” due to the voltage Vcc applied to the power supply terminal.
[0013]
When the pulse voltage Vi is applied to the input terminal, the diode D becomes conductive. Then, the voltage V1 at the input terminal of the switching element SW becomes (Vi−VD). Here, VD is a forward drop voltage of the diode D. With this voltage V1, the switching element SW becomes conductive, and the input capacitance Ci of the switching element SW is charged. Since the switching element SW becomes conductive, the voltage Vo at the output terminal becomes almost the ground potential and is inverted to the “L” state.
[0014]
When the input pulse to the input terminal becomes “L”, the diode D becomes non-conductive. Then, the charge accumulated in the input capacitance Ci of the switching element SW is discharged through the constant current source CC. For this reason, the terminal voltage of the input capacitance Ci decreases from (Vi−VD) with a slope of Ci / I. However, I is a current that the constant current source CC flows.
[0015]
When the potential V1 at the input terminal of the switching element SW (the terminal voltage of the input capacitor Ci) becomes smaller than the threshold voltage VTH of the switching element SW, the switching element SW is cut off. For this reason, the state of the voltage Vo at the output terminal returns to “H”.
[0016]
At this time, the output pulse width is changed to the input pulse width by the time (tp1) from when the input pulse becomes “L” until the potential V1 at the input terminal becomes smaller than the threshold voltage VTH of the switching element SW. Compared to this, it was extended. The pulse width increase tp1 can be adjusted by the input capacitance Ci of the switching element SW, the current I flowing through the constant current source CC, and the threshold voltage VTH of the switching element SW.
[0017]
In the present embodiment, even when there is no input pulse, a predetermined current, for example, a current of the order of μA flows in the forward direction in the diode D by the constant current source CC. Therefore, the operating point of the diode D is biased to a voltage VD shown in FIG. When the operating point is biased, the dynamic resistance of the diode D becomes smaller than when no bias is applied. Therefore, even when the input capacitance Ci of the switching element SW is small, the driving speed can be increased. For this reason, when the input pulse Vi is input to the input terminal, the potential of the input terminal V1 of the switching element SW can rapidly rise to (Vi−VD).
[0018]
Next, the increment tp1 of the pulse width will be described. Assuming that the change voltage (from the conductive state to the cut-off state) at the input end of the switching element SW in the above operation is ΔV, an increase tp1 of the pulse width is obtained by the following equation.
[0019]
tp1 = Ci · ΔV / I
Here, when Ci is 0.1 pF, ΔV is 1 V, and I is 1 μA, tp1 is 100 ns. Since Ci can change the size (gate length, gate width) of the switching element SW, ΔV can change the change amplitude, and I can change the current value of the constant current source CC, according to the present embodiment, tp1 Can be set to a desired value. In particular, an increased pulse width of several hundred ns to several tens of ps can be obtained with a simple circuit. It has been difficult in the prior art to realize such a short delay time with a small and simple circuit.
[0020]
As a method of changing ΔV, for example, a method of connecting a plurality of diodes D and D2 in series as shown in FIG. 4, a method of connecting a diode D10 to the source side of the switching element SW as shown in FIG. There is. In the example shown in FIGS. 1, 4 and 5, the resistor RL is used as a load for obtaining the output voltage. However, the present invention is not limited to this. For example, a constant current source may be used as a load. A specific circuit in this case will be described later with reference to FIG. Further, as the switching element SW, a CMOS inverter as shown in FIG. 6 may be used instead of the single channel MOS shown in FIGS. In this case, the threshold voltage VTH (logic threshold voltage) of the switching element SW can be set by changing the sizes of the pMOS and nMOS constituting the CMOS. Of course, the switching element SW is not limited to a single channel MOS or CMOS inverter.
[0021]
In the circuit shown in FIG. 1, the constant current source CC is preferably realized by using a current mirror circuit. This is because, as described above, when ΔV is 1 V and I is 1 μA, the output impedance Zo of the constant current source CC is Zo = ΔV / I = 1 MΩ. If this is realized on an LSI with a resistance element, there may be a case where a required area becomes large or high accuracy is difficult to obtain. However, when the current mirror circuit is used, a highly accurate resistance value can be easily realized with a small area. A specific circuit example using the current mirror circuit will be described later with reference to FIG.
[0022]
Next, a case where the present invention is applied to an edge information generation circuit will be described as a second embodiment of the present invention.
[0023]
FIG. 7 is an example of a circuit diagram of an edge information generation circuit that obtains a desired pulse width in accordance with the rising edge of the input signal. In the figure, a NAND gate NA1 is used as a switching element. An input signal applied to the NAND gate NA1 is applied to the diode D through the inverter IN1. An input signal is input to the other end of the NAND gate NA1. The constant current source CC is connected to the diode D as in FIG.
[0024]
The operation of edge information generation according to this embodiment will be described with reference to the operation waveform diagram of FIG. When there is no input at the input terminal (Vi), the output terminal (Vo) is in the “H” state. The diode D is in a conductive state, and the input capacitance Ci of the NAND gate NA1 is charged with the voltage V1 at the input terminal of the NAND gate NA1.
[0025]
When a pulse voltage having a height Vi is applied to the input terminal, the output terminal (Vo) of the NAND gate NA1 is inverted to the “L” state and the diode D is turned off. Then, the charge accumulated in the input capacitor Ci is discharged through the constant current source CC. For this reason, the terminal voltage of the input capacitance Ci decreases from V1 with a slope of Ci / I.
[0026]
When the terminal voltage of the input capacitance Ci of the NAND gate NA1 becomes smaller than the threshold voltage VTH of the NAND gate NA1, the switching element SW is turned off. For this reason, the state of the voltage Vo at the output terminal is “H”. When the input pulse becomes “L”, the state of the input terminal V1 of the NAND gate NA1 becomes “H”.
[0027]
At this time, an output pulse having a width (tp2) from when the input pulse becomes “H” until the terminal voltage of the input capacitor Ci of the NAND gate NA1 becomes smaller than the threshold voltage VTH of the NAND gate NA1 is output. Obtainable. The pulse width tp2 can be adjusted by the input capacitance Ci, the current I flowing through the constant current source CC, and the threshold voltage VTH of the NAND gate NA1.
[0028]
FIG. 9 is an example of a circuit diagram of an edge information generation circuit that obtains a desired pulse width in accordance with the falling edge of the input signal. The difference from the circuit of FIG. 7 is that a constant current source CC is added from the side of the power supply voltage Vcc, the connection of the diode D is changed so that the side with the constant current source CC becomes the anode side of the diode D, and further NAND gate Inverter gates IN2 and IN3 are added to the respective inputs of NA1. The operation of this circuit will be described with reference to the operation waveform diagram of FIG.
[0029]
Assume that an input signal Vi as shown in FIG. 10 is applied to the input terminal (Vi). When the input signal Vi is “H”, the outputs of the inverters IN1 and IN3 are “L”, so that the terminal V1 is “L” and the output terminal (Vo) is “H”. When the input signal Vi is switched to “L”, the outputs of the inverters IN1 and IN3 become “H”. For this reason, the output terminal Vo becomes “L”, and the current I of the constant current CC that has been flowing to the diode D side so far flows to the inverter IN2 side. At this time, since the input capacitance Ci of the inverter IN2 is charged, the voltage at the terminal V1 rises with a slope of Ci / I. When the voltage V1 exceeds the threshold voltage VTH of the inverter IN2, the output of the inverter IN2 is inverted to “L”. For this reason, the output terminal Vo returns to “H”.
[0030]
Thus, according to this circuit, an output pulse having a width of tp3 determined by Ci / I and the threshold voltage VTH of the inverter IN2 can be obtained from the timing of the falling edge of the input signal Vi.
[0031]
FIG. 11 is a circuit diagram showing an example of a circuit in which the input signal is gated by the output signal of the circuit shown in FIG. In this example, the input signal is connected to the circuit shown in FIG. 7 via the NAND gate NA2, and the output terminal (Vo) is connected to the other input terminal of the NAND gate NA2.
[0032]
In this example, if the slope time (Ci / I) determined by the current I of the constant current source CC and the input capacitance Ci of the switching element NA1 is set shorter than the pulse width time of the input signal Vi, it is shown in FIG. The same pulse width tp4 is obtained. On the other hand, if the inclination time is set longer, a pulse width tp4 longer than the input pulse width as shown in FIG. 12 can be obtained. At this time, during the period in which the pulse width tp4 is generated, even if the input pulse is applied again, the second and subsequent input pulses are not accepted by the NAND gate NA2. That is, the circuit shown in FIG. 11 has a gate function for an input pulse, and an output pulse having an arbitrary width can be obtained from the rising edge of the input pulse regardless of the width of the input pulse.
[0033]
Next, as a third embodiment of the present invention, a case where a pulse width expansion circuit is applied to a one-shot multivibrator will be described with reference to the circuit diagram of FIG. 13 and the operation waveform diagrams of FIGS.
[0034]
In FIG. 13, the one-shot multivibrator of this embodiment includes input terminals A and B, output terminals Q and Q (−), a reset input terminal Reset, a power supply terminal Vcc, and a ground terminal GND. . Here, the input terminal A is a clock input terminal when triggered by a rising edge, and the input terminal B is a clock input terminal when triggered by a falling edge. The output terminal Q (−) is an output terminal complementary to the output terminal Q.
[0035]
The clock terminal A is connected to one input terminal of the NOR gate NR12, and the clock terminal B is connected to the other input terminal of the NOR gate NR12 via the inverter IN20.
[0036]
The output of the NOR gate NR12 branches into two, and one is connected to the set input terminal of the first RS flip-flop FF1 composed of NAND gates NA10 and NA11. The other is connected via an inverter IN10 to a reset input terminal of a second RS flip-flop FF2 composed of NAND gates NA12 and NA13.
[0037]
The output of the second RS flip-flop FF2 branches into two, and one is connected to the input terminal of the NOR gate NR10. The other is connected to the reset input terminal of the NAND gate NA11 constituting the first flip-flop FF1.
[0038]
The output of the first RS flip-flop FF1 branches into two, and one is connected to the input terminal of the NOR gate NR10. The other is connected to the input terminal of the OR gate OR10.
[0039]
The output of the OR gate OR10 is connected to the set input terminal of the second RS flip-flop FF2.
[0040]
The output of the NOR gate NR10 is connected to the input terminal of the pulse width expansion circuit PW of the present invention, which is composed of a diode D, a constant current source CC, and a switching element SW.
[0041]
The output of the pulse width expansion circuit PW is connected to the resistor R2, the capacitor C2, and the source terminal of the MOS transistor M16. The output of the pulse width expansion circuit PW is further connected to the input terminal of the OR gate OR10 and the input terminal of the inverter IN14. Note that the potential of the input terminal of the switching element SW of the pulse width expansion circuit PW is V1, and the potential of the output terminal is V2.
[0042]
The output terminal of the inverter IN14 branches into two, and one is connected to the output terminal Q of the one-shot multivibrator via the inverters IN16 and IN17. The other is connected to the output terminal Q (−) of the one-shot multivibrator via the inverter 15.
[0043]
The reset input terminal Reset is connected to the gate electrode of the MOS transistor M16 and the set input terminal of the second RS flip-flop FF2 via inverters IN18 and IN19.
[0044]
The power supply terminal Vcc is connected to the resistor R2 and the drain electrode of the MOS transistor M16.
[0045]
The operation of the one-shot multivibrator having such a configuration will be described with reference to the operation waveform diagram of FIG.
[0046]
First, it is assumed that the switching element SW is off and V2 is at the power supply voltage Vcc. Therefore, the output terminal Q is “L” and the output terminal Q (−) is “H”. The capacitor C2 is charged with the voltage Vcc.
[0047]
At this time, it is assumed that a pulse clock as shown in FIG. Since the flip-flop FF1 is set at the falling edge of this clock pulse, when the output of the first RS flip-flop FF1 is Q1, the output Q1 (−) is inverted from “H” to “L”. Then, the switching element SW is turned on via the NOR gate NR10, and discharging of the charge charged in the capacitor C2 is started.
[0048]
When the potential of V2 falls below the logic threshold voltage VLT of the inverter IN14 and the OR gate OR10, the outputs of the inverter IN14 and the OR gate OR10 are inverted.
[0049]
Q becomes “H” by the inversion of the output of the inverter 14.
[0050]
By inversion of the output of the OR gate OR10, the second RS flip-flop FF2 is set. When the output of the second RS flip-flop FF2 is Q2, Q2 is inverted from “L” to “H”. As a result, the first RS flip-flop FF1 is reset, and the input pulse to the pulse width expansion circuit PW ends.
[0051]
Thereafter, the switching element SW is turned off after the pulse extension time t1 determined by the input capacitance Ci and the current (I1) of the constant current source CC. For this reason, a short circuit time is ensured and the voltage of V2 can become zero.
[0052]
When the switching element SW is turned off, the capacitor C2 is charged by the power supply voltage Vcc through the resistor R2. For this reason, the potential of V2 increases from 0 with a time constant C2 · R2. When the potential of V2 exceeds the logic threshold voltage VLT of the inverter IN14, the output of the inverter IN14 is inverted from “H” to “L”. Thereby, since the output terminal Q is inverted to “L”, a pulse as shown in FIG. 14 is obtained from the output terminal Q. As apparent from the above description, the width tp can be determined by the resistance R2 and the capacitance of the capacitor C2. The second RS flip-flop FF2 is reset at the rising edge of the clock input pulse B.
[0053]
When a retriggerable clock pulse as shown in FIG. 15 is input to the clock input terminal B, an operation waveform diagram as shown in FIG. That is, it is possible to perform processing for converting the clock pulse signal into direct current. .
[0054]
A typical one-shot multivibrator circuit is a Motorola CMOS logic IC / one-shot multivibrator circuit MC14528. However, in MC14528, the logic threshold voltage of the inverter corresponding to the inverter IN14 of FIG. 13 needs to be larger than the logic threshold voltage of the OR gate corresponding to the OR gate OR10 of FIG. This is for securing the time until the voltage of V2 becomes 0 by discharging the electric charge accumulated in the capacitor corresponding to the capacitor C2. On the other hand, in the one-shot multivibrator to which the present invention is applied, both can set the same logic threshold voltage (for example, 1/2 of the power supply voltage value), and even in this case, the short-circuit time of the capacitor C2 is reduced. Can be secured. Therefore, the one-shot multivibrator to which the present invention is applied can facilitate circuit design and management.
[0055]
Next, FIG. 16 shows an example of a specific circuit in which the pulse width expansion circuit PW shown in FIG. 13 is configured using MOS transistors. In the figure, a MOS transistor M10 is used as the diode D. In the MOS transistor M10, the gate electrode and the drain electrode are connected in common, and the electrode and the source electrode have a two-terminal configuration. In the figure, a current mirror circuit composed of a MOS transistor M11, a MOS transistor M12, and a current setting resistor R3 is used as the constant current source CC.
[0056]
Next, FIG. 17 shows an example of a circuit in which the resistor R2 and the capacitor C2 shown in FIG. 13 are built in an LSI. In FIG. 13, a resistor R2 sets a current flowing through the capacitor C2. As the resistor R2, a current mirror circuit composed of MOS transistors M15 and M14 and a resistor R4 can be used. In this example, the resistor R4 is also used as a current setting resistor of a current mirror circuit composed of MOS transistors M11 and M12.
[0057]
The desired pulse width obtained by this circuit can be realized by substituting the capacitance pF order and current μA order that can be easily realized in the LSI while maintaining the value of C2 / I2 of the discrete component. Since the necessary μA order current can be obtained by changing the sizes of the MOS transistors on the primary side and the secondary side in the current mirror circuit, the resistor R4 does not require a high resistance. Therefore, it does not require a large area and is suitable for LSI.
[0058]
FIG. 18 is a modification of the circuit shown in FIG. Since the basic operation contents are common, the difference between this figure and FIG. 17 will be described here. First, the input terminal is only terminal B when triggering on a falling edge, and the inverter IN20 and the NOR gate NR12 are omitted. Next, the output of the multivibrator is only the inverted output Q (−), and the inverters IN16 and IN17 are omitted. Further, in order to delay the reset timing of the first RS flip-flop FF1, a NOR gate NR11 and an inverter IN13 are used instead of the OR gate OR10. Further, in order to adjust the timing at which the output of the second RS flip-flop FF2 is applied to the NOR gate NR10, it is input to the NOR gate NR10 via the inverters IN11 and IN12.
[0059]
Next, as a fourth embodiment of the present invention, an application circuit in which the one-shot multivibrator shown in FIG. 13 and FIGS.
[0060]
First, an example of a distributed control system to which a field network is applied will be described with reference to the block diagram shown in FIG. The distributed control system shown in the figure includes various field devices such as a sensor 101, a personal computer (PC) 102, an actuator 103, and a programmable logic controller (PLC) 104 connected via a network via interface devices 100, 115, 116, and 117, respectively. 114 is configured. This configuration is an example, and the field device is not limited to these. The interface devices 100, 115, 116, and 117, the sensor 101, the personal computer 102, the actuator 103, and the programmable logic controller 104 are separate devices, and the field device includes the interface device. There is.
[0061]
The network 114 is connected to the upper network 119 via the controller 118. A control personal computer (control PC) 120 or the like is connected to the upper network 119. Of course, the hierarchy and type of the network are not limited to this figure.
[0062]
In this example, the entire distributed control system is controlled by the control personal computer 120. In the lower network, various field devices are controlled.
[0063]
Here, an example of control in the lower network will be described. A signal detected by the sensor 101 is sent over the network 114 via the interface device 100. This signal is input to various field devices via the interface devices 115, 116 and 117. Then, for example, the personal computer 102 performs a calculation based on the output signal of the sensor 101 sent to determine whether or not the state of the controlled object is normal. Further, the actuator 103 and the programmable logic controller 104 adjust the control amount of the controlled object based on the output signal of the sensor 101 that has been sent.
[0064]
In the present embodiment, the interface devices 100, 115, 116, and 117 have the same configuration. Therefore, the interface device 100 will be described. Of course, the interface devices 100, 115, 116, and 117 may have different configurations.
[0065]
The interface device 100 includes a network transceiver 113, a power supply circuit 105, insulation circuits 107, 108 and 109, a microcomputer 111, a power supply monitoring circuit 106, signal conversion circuits 110 and 112, and the like.
[0066]
As described above, the interface device 100 is equipped with the microcomputer 111 so that the lower level network can perform distributed control. The interface device 100 includes capacitive insulating circuits 107, 108, and 109, and is configured to electrically insulate the network 114 from the field device. By electrically insulating in this way, it is possible to prevent an abnormal signal from being propagated from the network 114 to the field device due to, for example, lightning. Further, propagation of abnormal signals from the field device to the network 114 can be prevented.
[0067]
The power supply of the circuit closer to the network than the insulation circuits 107, 108 and 109 of the interface device 100 is supplied from the power supply circuit 105. The power supply circuit 105 is supplied with a voltage of, for example, 24V from the network 114, and converts this to a voltage of 5V. The 5 V voltage (VccB) is supplied to a circuit on the network side from an insulating circuit such as the network transceiver 113 and the signal conversion circuit 112 in the interface device 100.
[0068]
The microcomputer 111 and the signal conversion circuit 110 on the field side of the insulation circuits 107, 108, and 109 of the interface device 100 are supplied with power (VccA) from a separate power source that is insulated from the network 114.
[0069]
The network transceiver 113 converts signals between the network 114 and various field devices. The network transceiver 113 can be switched between a non-operating state (inactive state) and an operating state (active state) in the standby mode by an external signal in order to reduce power consumption. .
[0070]
The power supply monitoring circuit 106 monitors the state of the power supply circuit 105. When the voltage from the power supply circuit 105 is within a predetermined range, it generates a pulse signal and transmits it to the insulation circuit 107. This pulse signal (the AC component thereof) is transmitted to the signal conversion circuit 110 via the insulation circuit 107. The signal conversion circuit 110 converts the pulse signal into a level (state) signal and transmits it to the microcomputer 111.
[0071]
In this way, the microcomputer 111 can detect the state of the insulated power supply circuit 105.
[0072]
The status signal transmission circuit 118 transmits the status signal output from the microcomputer 111 to the network side. Here, the status signal is a standby signal for inactivating the network transceiver 113. The status signal output from the microcomputer 111 is converted into a pulse signal by the status signal transmission circuit 118. This pulse signal is transmitted to the signal conversion circuit 112 via the insulation circuit 108. The signal conversion circuit 112 converts the pulse signal into a status signal and controls switching of the active state and the inactive state of the network transceiver 113.
[0073]
An example in which a multivibrator to which the present invention is applied is used as a specific circuit for realizing the above distributed control system will be described with reference to FIG.
[0074]
First, an example for realizing the power supply monitoring circuit 106, the insulating circuit 107, and the signal conversion circuit 110 will be described.
[0075]
The circuit shown in FIG. 19 receives a voltage VccB from the power supply circuit and a pulse signal from the oscillator OSC, and outputs a pulse signal when the voltage VccB is within a predetermined range, and a capacitor Ca. And Cb, and a signal converter that converts the input pulse into a DC state based on the voltage VccB. A one-shot multivibrator to which the present invention is applied can be used for this signal converter.
[0076]
The power supply monitoring unit modulates the voltage VccB from the power supply circuit by the NAND gate NA14 with a pulse signal from the oscillator OSC. And it outputs to an insulation part as a two-phase output with driver DRV. This corresponds to the power supply monitoring circuit 106 in FIG. The diodes D11 to D14 are used for clamping the signal voltage.
[0077]
The insulating portion configured by including the capacitors Ca and Cb corresponds to the insulating circuit 107 in FIG.
[0078]
The signal conversion unit converts the two-phase signal input through the insulating unit into a one-phase output pulse signal by the comparator COMP. The diodes D21 to D24 are used for clamping the signal voltage. Further, the inverter IN30 and the resistors Ra and Rb are used for applying a DC bias to the pulse signal via the capacitors Ca and Cb. As this DC bias voltage, a voltage that is ½ of the power supply voltage VccA is usually used. This voltage can be obtained by short-circuiting the input and output of the inverter IN30.
[0079]
The pulse signal output from the comparator COMP is demodulated by the retriggerable function of the multivibrator to which the present invention is applied, and a DC voltage based on the power supply voltage VccB can be output. Thereby, it is possible to detect whether the power supply voltage VccB is in a power supply state or a non-power supply state, and it is possible to monitor an isolated network side node power supply.
[0080]
Next, an example for realizing the state signal transmission circuit 118, the insulation circuit 108, and the signal conversion circuit 112 shown in FIG. 26 will be described.
[0081]
Also in this case, the circuit shown in FIG. 19 can be applied. At this time, the power supply monitoring unit corresponds to the state signal transmission circuit 118. However, the input voltage VccB is a status signal from the microcomputer 111 (a standby signal for deactivating the network transceiver 113).
[0082]
The insulating portion illustrated in FIG. 19 corresponds to the insulating circuit 108.
[0083]
The signal conversion unit illustrated in FIG. 19 corresponds to the signal conversion circuit 112. Then, a signal based on the output status signal from the microcomputer 111 is input to the network transceiver 113. As a result, switching between the active state and the inactive state of the network transceiver 113 can be controlled from the insulated field device side.
[0084]
As described above, according to the distributed control system implemented by applying the present invention, not only electrical insulation and bidirectional signal transmission between the network and various field devices but also the state of the power circuit on the network side A signal can be transmitted to an insulated microcomputer, and the reliability of the entire network system can be improved.
[0085]
That is, if the power supply circuit of the interface device does not operate normally for some reason, power is not supplied to the network transceiver mounted in the interface device, and the circuit operation stops. If control by the microcomputer is continued in such a state, for example, the actuator may perform control based on an erroneous signal, and the entire system may malfunction or the entire system may stop.
[0086]
However, according to the distributed control system to which the present invention is applied, the microcomputer can monitor the state of the power supply by the power supply monitoring circuit of the interface device. Signal transmission can be stopped. For this reason, malfunction of the entire system, stop of the entire system, and the like can be prevented, and the reliability of the entire system can be improved.
[0087]
Furthermore, since the interface device can transmit the status signal from the microcomputer to the insulated network side and control the circuit on the network side, the power consumption of the entire system can be reduced. That is, when the microcomputer outputs, for example, 5V as the status signal, the network transceiver can be controlled to be in the standby mode, and for example, when the microcomputer is outputting 0V, the network transceiver can be controlled to be in the normal operation mode. . At this time, since power consumption is reduced in the standby mode, power consumption can be suppressed by setting the network transceiver of the field device in the inactive state to the standby mode.
[0088]
Needless to say, the power supply monitoring circuit shown in FIG. 19 can be applied to other than the distributed control system shown in FIG.
[0089]
Next, another application example of the one-shot multivibrator to which the present invention is applied will be described as a fifth embodiment of the present invention.
[0090]
FIG. 20 is a diagram illustrating an example in which the one-shot multivibrator OSM is used for detecting the clock abnormality of the microprocessor CPU. As shown in this figure, in this embodiment, the clock output signal from the microprocessor CPU is input to the multivibrator OSM, and the output from the multivibrator OSM is output in the same manner as in the fourth embodiment shown in FIG. The state of whether or not the clock signal of the microprocessor CPU is normal is detected. In this example, the power source of the multivibrator OSM is externally provided with the resistor R2 and the capacitor C2. However, by realizing the resistor R2 with a constant current source as described above, the one-shot multivibrator OSM is provided in the microprocessor CPU. Can also be built in.
[0091]
FIG. 21 is a circuit diagram showing an example in which the pulse width expansion circuit of the present invention is applied to a variable delay circuit. This circuit generates a current I3 to be passed through the MOS transistor M12 of the current mirror circuit that constitutes a constant current source that feeds the current I1 by a current mirror circuit constituted by the MOS transistors M13 and M14. It is driven by a D / A converter DA. The output of the D / A converter DA is a current I4 weighted with a digital value inputted to the digital input terminals D0 to D3. Since the current I1 is proportional to the current I4, a pulse signal having a width inversely proportional to the magnitude of the current I4 is generated at the output terminal (Vo) of this circuit. In this way, by changing the input to the digital input terminals D0 to D3 of the D / A converter, a variable delay circuit capable of selectively setting a desired delay time of, for example, several hundred ns to several tens of ps can be realized. .
[0092]
FIG. 22 is a diagram showing an example of a specific configuration of the D / A converter DA shown in FIG. In this figure, the D / A converter DA is composed of switches SW1 to SW4 having two contacts with respect to a 4-bit digital input and constant current sources CC11 to CC13 having weighted current settings. The contacts a of the switches SW1 to SW4 are connected in common and generate the output current I4 of the D / A converter DA. Further, the contacts b side of the switches SW1 to SW4 are respectively grounded in common and have a ground potential. The constant current sources CC11 to CC14 can be realized by, for example, a MOS current mirror circuit that allows a predetermined current to flow.
[0093]
FIG. 23 is a diagram showing an example of a specific configuration of the switches SW1 to SW4 shown in FIG. 22 (only one switch is shown in the figure). The switch shown in the figure is composed of a differential pair composed of MOS transistors M1a and M1b. A digital input signal is input to one input of the differential pair, and a bias voltage Vbias is input to the input of the other differential pair.
[0094]
In this switch, when the digital input terminal D0 is “L”, the current of the constant current source CC11 flows to the MOS transistor M1b. When the digital input terminal D0 is switched to "H", the gate voltage of the MOS transistor M1a on the digital input terminal D0 side becomes higher than the gate voltage of the MOS transistor M1b on the bias voltage Vbias input side. Yes. For this reason, the MOS transistor M1a is turned on, and all the current of the constant current source CC11 flows to the MOS transistor M1a.
[0095]
Next, an example in which the variable delay circuit to which the present invention is applied is applied to a circuit for greatly extending the delay time will be described.
[0096]
FIG. 24 and FIG. 25 are diagrams showing examples of circuits in which variable delay circuits are connected in multiple stages in order to increase the delay time. 24, the capacity of the variable delay circuit is configured such that the discharge type (circuit shown in FIG. 7) and the charge type (circuit shown in FIG. 9) are alternated. In FIG. 25, the capacity of the variable delay circuit is configured using only the discharge type. In addition, although not shown in figure, you may make it comprise only using a charge type. The above-described various configuration examples can be applied to the specific configuration of the constant current source. In this way, when n stages of variable delay circuits are connected, the delay time obtained by one stage of variable delay circuit is n times (sum of delay times of each variable delay circuit). A long delay time can be obtained by using the capacity.
[0097]
The variable delay circuit described above can correct a delay time shift of each of a plurality of wiring lengths in the LSI or a delay time shift due to a difference in the number of logic stages, and is suitably used for an LSI. be able to.
[0098]
FIG. 28 is a circuit diagram showing an example in which a delay time shift due to a difference in wiring length in the circuit as shown in FIG. 27 is matched with the longer delay time. In the circuit shown in FIG. 27, a difference in delay time occurs at the output terminals Voa and Vob due to the difference in wiring length with respect to the input signal Vi. In this case, as shown in FIG. 28, a variable delay circuit DLY (for example, see FIG. 21) to which the present invention is applied is inserted between the inverters INia and INoa. By doing so, the delay time at the output terminal Voa can be matched with the delay time at the output terminal Vob.
[0099]
FIG. 30 is a circuit diagram showing an example in which a delay time shift due to a difference in the number of logic stages in the circuit as shown in FIG. 29 is matched with the delay time with the larger number of logic stages. In the circuit shown in FIG. 29, a difference in delay time occurs between the output terminals Voa and Vob due to the difference in the number of theoretical stages with respect to the input signal Vi. Even in this case, the delay time can be adjusted by inserting the variable delay circuit DLY to which the present invention is applied between the inverters INia and INoa as shown in the circuit of FIG.
[0100]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a circuit capable of adjusting the output pulse width in the pulse width expansion circuit using the parasitic capacitance of the switching element.
[Brief description of the drawings]
FIG. 1 is a circuit diagram for explaining an operation principle of a pulse width expansion circuit according to a first embodiment of the present invention.
FIG. 2 is an operation waveform diagram for explaining an operation principle of the pulse width expansion circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram for explaining a VI characteristic of a diode D in the pulse width expansion circuit according to the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing an example in which ΔV is changed by using a plurality of diodes D and D2 in the pulse width expansion circuit according to the first embodiment of the present invention.
FIG. 5 is a circuit diagram showing an example in which ΔV is changed by using a diode in the pulse width expansion circuit according to the first embodiment of the present invention.
FIG. 6 is a circuit diagram showing an example in which a CMOS inverter is used in the pulse width expansion circuit according to the first embodiment of the present invention.
FIG. 7 is a circuit diagram for explaining a circuit in which a pulse width expansion circuit is applied to an edge information generation circuit according to the second embodiment of the present invention;
FIG. 8 is an operation waveform diagram for explaining a circuit in which a pulse width expansion circuit is applied to an edge information generation circuit according to the second embodiment of the present invention.
FIG. 9 is a circuit diagram for explaining another example of a circuit in which the pulse width expansion circuit according to the second embodiment of the present invention is applied to an edge information generation circuit;
FIG. 10 is an operation waveform diagram for explaining another example of the circuit in which the pulse width expansion circuit according to the second embodiment of the present invention is applied to the edge information generation circuit.
FIG. 11 is a circuit diagram for explaining still another example of a circuit in which the pulse width expansion circuit according to the second embodiment of the present invention is applied to an edge information generation circuit;
FIG. 12 is an operation waveform diagram for explaining still another example of a circuit in which the pulse width expansion circuit according to the second embodiment of the present invention is applied to an edge information generation circuit.
FIG. 13 is a circuit diagram for explaining a circuit according to a third embodiment of the present invention in which a pulse width expansion circuit is applied to a one-shot multivibrator.
FIG. 14 is an operation waveform diagram for explaining a circuit according to a third embodiment of the present invention in which a pulse width expansion circuit is applied to a one-shot multivibrator.
FIG. 15 is an operation waveform diagram for explaining an operation when a retriggerable clock is input to the one-shot multivibrator according to the third embodiment of the present invention.
FIG. 16 is a circuit diagram for explaining a circuit in which a pulse width expansion circuit PW of a one-shot multivibrator according to a third embodiment of the present invention is configured using MOS transistors.
FIG. 17 is a circuit diagram for explaining a circuit in which the resistance of the one-shot multivibrator according to the third embodiment of the present invention is configured by a current mirror circuit;
FIG. 18 is a circuit diagram for explaining another example of a circuit in which the pulse width expansion circuit according to the third embodiment of the present invention is applied to a one-shot multivibrator.
FIG. 19 is a circuit diagram for explaining an example in which a circuit in which a pulse width expansion circuit is applied to a one-shot multivibrator is used in a distributed system;
FIG. 20 is a diagram illustrating an example in which a one-shot multivibrator OSM is used for clock abnormality detection of the microprocessor CPU.
FIG. 21 is a circuit diagram showing an example in which a pulse width expansion circuit is applied to a variable delay circuit.
22 is a diagram showing an example of a specific configuration of the D / A converter DA shown in FIG. 21. FIG.
FIG. 23 is a diagram illustrating an example of a specific configuration of switches SW1 to SW4 illustrated in FIG. 22;
FIG. 24 is a diagram illustrating an example of a circuit in which variable delay circuits are connected in multiple stages in order to increase the delay time.
FIG. 25 is a diagram illustrating an example of a circuit in which variable delay circuits are connected in multiple stages in order to increase the delay time.
FIG. 26 is a block diagram for explaining a distributed control system to which a field network is applied.
FIG. 27 is a diagram for explaining a case where a delay time shift occurs due to a difference in wiring length;
FIG. 28 is a diagram for explaining a case where a shift in delay time due to a difference in wiring length is matched with a delay time with a longer wiring length;
FIG. 29 is a diagram for explaining a case where a delay time shift occurs due to a difference in the number of theoretical plates;
FIG. 30 is a diagram for explaining a case where a delay time shift due to a difference in the number of theoretical stages is matched with a delay time with a longer wiring length;
[Explanation of symbols]
D, D2, D10 to D14, D21 to D24, Da to Dc ... Diode
CC, CC2, CC11 to CC14, CCa to CCc ... constant current source
SW: switching element, Ci: input capacitance, RL: load resistance
R2-R4, Ra, Rb ... resistance
C2, Ca, Cb ... Capacitors
M10 to M16 ... MOS transistors
IN10 to IN20, IN30, INa to INc, INia, INib,
INoa, INob, INib1 to INib4 ... Inverter
NA1, NA2, NA10-NA14 ... NAND gate
NR10 to NR12 ... NOR gate
OR10 ... OR gate
FF1, FF2 ... flip-flop
OSM: One-shot multivibrator
OSC ... Transmitter, DRV ... Driver, COMP ... Comparator
DA ... D / A converter, CPU ... Microprocessor
SW1 to SW4 ... switch
Vbias: bias voltage, Vi: input terminal, Vo: output terminal
VccA, VccB: power supply terminal, GND: ground terminal
IN1-IN3, Reset ... Reset terminal
A, B ... Clock input terminal
Q, Q (-) ... Output terminal of flip-flop
D0 to D3: Digital input terminal, CLK: Clock terminal

Claims (14)

A rectifier connected to the input terminal;
A constant current source connected to flow a predetermined current in the forward direction of the rectifying element;
A switching element connected in parallel with the constant current source and having a parasitic input capacitance;
A pulse width expansion circuit configured to generate an output signal based on an on state or an off state of the switching element. Rectifying means for passing the input signal and blocking the signal in the reverse direction;
A constant current source means connected to the output side of the rectifying means, and supplying a predetermined current in the forward direction of the rectifying means;
Switching means that enters a conductive state based on an input signal through the rectifying means, has a parasitic capacitance that is charged by a voltage based on the input signal and discharged by the constant current source means, and the parasitic capacitance Switching means for maintaining conduction by the generated voltage;
Means for generating an output signal based on the state of the switching means;
A pulse width expansion circuit comprising: The pulse width expansion circuit according to claim 2,
The pulse width expansion circuit characterized in that the switching means comprises a single channel MOS or a CMOS inverter. The pulse width expansion circuit according to claim 2 or 3,
The pulse width expansion circuit according to claim 1, wherein the rectifying means is configured using one or a plurality of diodes. The pulse width expansion circuit according to claim 2 or 3,
A pulse width expansion circuit, wherein the rectifier is driven using a logic gate. In the pulse width expansion circuit according to any one of claims 2, 3, 4 and 5,
The pulse width expansion circuit according to claim 1, wherein the constant current source means is configured using a current mirror circuit. Inverter means for inverting the input signal;
Rectifying means connected to the output side of the inverter means;
A constant current source means connected to the output side of the rectifying means, and supplying a predetermined current in the forward direction of the rectifying means;
A logic gate for generating edge information of the input signal based on the input signal and the input signal via the rectifying means, wherein the constant current source is charged by a voltage based on the input signal via the rectifying means; An edge information generation circuit comprising: a logic gate having a parasitic capacitance discharged by the means and maintaining a generation state of edge information of an input signal by a voltage generated in the parasitic capacitance. First inverter means for inverting the input signal;
Rectifying means connected to the output side of the first inverter means;
Constant current source means for supplying a predetermined current in the forward direction of the rectifying means;
A second inverter means connected to the constant current source means, the state being charged by the constant current source means and the state being discharged via the rectifier means by the output of the first inverter means; Second inverter means having a parasitic capacitance to be switched, and an output signal controlled by a voltage generated in the parasitic capacitance;
Edge information generation comprising: a logic gate for generating edge information of the input signal based on the output signal of the second inverter means and the output signal of the third inverter means for inverting the input signal circuit. The edge information generation circuit according to claim 7,
A NAND gate for applying an input signal;
An edge information generation circuit, wherein an output signal is input to the NAND gate. A one-shot multivibrator using the pulse width expansion circuit according to any one of claims 2, 3, 4, 5, and 6. A power supply monitoring circuit comprising the one-shot multivibrator according to claim 10 and monitoring a power supply circuit that is capacitively insulated. A network transceiver; a power supply circuit that supplies power to the network transceiver; and a field device controlled by a control device that is capacitively insulated from the network transceiver.
11. The field device control system according to claim 10, wherein the control device monitors the power supply circuit by a power supply monitoring circuit including the one-shot multivibrator according to claim 10. 9. One or both of the edge information generation circuits according to claim 7 and 8 are connected in a plurality of stages without using the logic gate in a connection portion, and the logic gate is provided in an output stage. Variable delay circuit. In the pulse width expansion circuit according to claim 6,
A pulse width expansion circuit characterized in that the current generated by the current mirror circuit is controlled by a current weighted with a control signal by a D / A converter.

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