JP3779038B2 - A / D converter testing method and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an operation test of an A / D converter that operates at high speed.
High-speed A / D converters with a conversion speed exceeding 10 MS / s (Mega Sample / sec) have been used for image processing, and recently a data reading device of a hard disk device, or QPSK (Quadrature Phase Shift Keying), QPM (Quadrature Amplitude). The range of application has been expanded to the field of high-speed data communication by Modulation). In such a field, ultra high-speed conversion exceeding 100 MS / s is required, and at the same time 10 ^-Ten An error rate greater than is required. Therefore, it is necessary to reliably perform an operation test of an A / D converter that operates at high speed.
[0002]
[Prior art]
The operation test of the A / D converter is performed by connecting the A / D converter as a device under measurement to a test apparatus. That is, a clock signal and an analog input signal are input from the test apparatus to the A / D converter, the A / D converter samples the analog input signal based on the input clock signal, and the sampled analog value is converted into a digital signal. And output to the test equipment. The test apparatus evaluates the digital signal output from the A / D converter to determine whether the device under measurement operates normally and sufficiently satisfies the specifications.
[0003]
[Problems to be solved by the invention]
With the recent increase in the speed of A / D converters, it is necessary to increase the frequency of clock signals and analog input signals to be input from the test apparatus to the A / D converter.
[0004]
In the operation test, the clock signal supplied from the test equipment to the A / D converter needs to be two to three times the frequency of normal use, and the analog input signal is input at a frequency of 1/4 or more of the clock signal. It is necessary to do.
[0005]
The test apparatus can supply the high-frequency clock signal as described above to the A / D converter, but it is difficult to generate and output a high-frequency analog signal corresponding to such a clock signal. It has become.
[0006]
In addition, it is difficult to evaluate a digital signal output from the A / D converter in a high-speed cycle by using a test apparatus.
Therefore, there is a problem that the current test apparatus cannot sufficiently perform the operation test of the high-speed A / D converter.
[0007]
An object of the present invention is to provide a test method and a semiconductor device that can sufficiently perform an operation test of a high-speed A / D converter.
[0008]
[Means for Solving the Problems]
According to another aspect of the present invention, a signal whose phase continuously changes with respect to the sampling clock signal is generated as an analog signal based on the sampling clock signal supplied to the A / D converter, and the analog signal is used as the sampling clock signal. Based on the sampling, A / D conversion is performed, and a digital signal generated by the A / D conversion is evaluated.
[0009]
According to a second aspect of the present invention, on the basis of the sampling clock signal supplied to the A / D converter, a signal in which the DC level or the amplitude of the sampling clock signal is continuously changed is generated as an analog signal, and the analog signal is the sampling signal Sampling and A / D conversion are performed based on the clock signal, and the digital signal generated by the A / D conversion is evaluated.
[0010]
According to another aspect of the present invention, based on an analog signal supplied to the A / D converter, a signal whose phase continuously changes with respect to the analog signal is generated as a sampling clock signal, and the analog signal is generated based on the sampling clock signal. Are sampled and A / D converted, and a digital signal generated by the A / D conversion is evaluated.
[0011]
According to another aspect of the present invention, a signal obtained by continuously changing the DC level or amplitude of the analog signal is generated as a sampling clock signal based on the analog signal supplied to the A / D converter, and the analog signal is generated by the sampling clock. Sampling and A / D conversion are performed based on the signal, and a digital signal generated by the A / D conversion is evaluated.
[0012]
According to a fifth aspect of the present invention, an analog signal is generated based on a sampling clock signal supplied to an A / D converter and input to the A / D converter, and the analog signal is sampled based on the sampling clock signal. When performing the / D conversion, the comparison reference voltage supplied to the A / D converter is continuously changed, and the digital signal generated by the A / D conversion is evaluated.
[0013]
The analog signal may have the same frequency as the sampling clock supplied to the A / D converter.
According to a seventh aspect of the present invention, the analog signal has a frequency half that of a sampling clock supplied to the A / D converter.
[0014]
In claim 8, the digital signal generated by the A / D conversion is evaluated at a rate of once every n times.
According to a ninth aspect of the present invention, on the basis of a sampling clock signal supplied to the A / D converter, an analog signal generation circuit that generates a signal whose phase continuously changes with respect to the sampling clock signal as an analog signal, and the analog signal The semiconductor device includes an A / D converter that performs sampling and A / D conversion based on the sampling clock signal.
[0015]
According to a tenth aspect of the present invention, on the basis of a sampling clock signal supplied to an A / D converter, an analog signal generation circuit that generates a signal obtained by continuously changing the DC level or amplitude of the sampling clock signal as an analog signal; The semiconductor device includes an A / D converter that samples an analog signal based on the sampling clock signal and performs A / D conversion.
[0016]
According to an eleventh aspect of the present invention, on the basis of an analog signal supplied to the A / D converter, a clock signal generation circuit that generates a signal whose phase continuously changes with respect to the analog signal as a sampling clock signal; and The semiconductor device includes an A / D converter that performs sampling and A / D conversion based on the sampling clock signal.
[0017]
The clock signal generation circuit for generating a signal obtained by continuously changing the DC level or the amplitude of the analog signal as a sampling clock signal based on the analog signal supplied to the A / D converter, and the analog signal The semiconductor device is provided with an A / D converter that samples a signal based on the sampling clock signal and performs A / D conversion.
[0018]
The analog signal generation circuit for generating an analog signal based on the sampling clock signal supplied to the A / D converter and the comparison reference for continuously changing the comparison reference voltage supplied to the A / D converter. The semiconductor device includes a voltage generation circuit and an A / D converter that samples the analog signal based on the sampling clock signal and the comparison reference voltage and performs A / D conversion.
[0019]
In the fourteenth aspect, the analog signal is frequency-divided by a frequency divider to ½ the frequency of the sampling clock signal.
According to a fifteenth aspect of the present invention, the semiconductor device includes an interleave circuit that outputs the digital output signal of the A / D converter at a rate of once every n times.
[0020]
17. The output determination circuit that determines whether or not the change in the digital output signal of the A / D converter has monotonicity, and the analog signal generation circuit based on the output signal of the output determination circuit The semiconductor device includes a clock signal generation circuit and a control signal generation circuit that generates a control signal that monotonously changes the output signal of any of the comparison reference voltage generation circuits.
[0021]
According to another aspect of the present invention, the output determination circuit is configured by a magnitude comparator.
According to another aspect of the present invention, the output determination circuit includes a logic circuit that generates an exclusive OR signal of continuous digital output signals.
[0022]
According to a nineteenth aspect, there is provided a PLL circuit that generates an internal clock signal having a higher frequency than the original clock signal based on an original clock signal supplied from the outside, and outputs the internal clock signal as the sampling clock signal or an analog signal. Prepared.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 2 shows a first embodiment embodying the present invention. The test apparatus 1 outputs the original clock signal CLK and the control signal CNTL to the semiconductor device 2 provided with the high-speed A / D converter. The original clock signal CLK is a signal of about 50 MHz that can be sufficiently generated by the conventional test apparatus 1, and the control signal CNTL is an analog whose voltage level is gradually changed by a time constant circuit or the like in the test apparatus 1. Generated as a signal.
[0024]
The original clock signal CLK is input to the PLL circuit 3 in the semiconductor device 2. The PLL circuit 3 generates an internal clock signal CK of 200 MHz, for example, based on the original clock signal CLK, and outputs it to the analog signal generation circuit 4a, the A / D converter 5, the interleave circuit 6, and other internal circuits.
[0025]
The control signal CNTL is input to the analog signal generation circuit 4a. The analog signal generation circuit 4a generates an analog signal Ain having the same frequency as that of the internal clock signal CK based on the internal clock signal CK and the control signal CNTL only during an operation test, and the A / D converter 5 Output to.
[0026]
The internal clock signal CK is output as a rectangular wave pulse signal from the PLL circuit, but is actually input to the analog signal generation circuit 4 and the A / D converter 5 as a sinusoidal signal due to the action of parasitic capacitance or the like. The analog signal Ain output from the analog signal generation circuit 4a is a signal obtained by delaying the phase of the internal clock signal CK.
[0027]
A specific configuration of the analog signal generation circuit 4a is shown in FIG. The internal clock signal CK is input to the inverter circuit 7a, and the output signal of the inverter circuit 7a is input to the inverter circuit 7b via the N-channel MOS transistor 8.
[0028]
The control signal CNTL is input to the gate of the transistor 8, and the input terminal of the inverter circuit 7b is connected to the ground GND through the capacitor 9. The analog signal Ain is output from the inverter circuit 7b.
[0029]
In the analog signal generation circuit 4a configured as described above, when the voltage level of the control signal CNTL changes, the on-resistance of the transistor 8 changes, whereby the time constant between the transistor 8 and the capacitor 9 changes. Then, based on the change in the control signal CNTL, the phase difference between the internal clock signal CK and the analog signal Ain changes.
[0030]
The analog signal Ain is input to the A / D converter 5. The A / D converter 5 operates using the internal clock signal CK as a sampling clock during an operation test, samples the analog signal Ain output from the analog signal generation circuit 4a, and converts the sampled analog value into a digital signal. To the interleave circuit 6.
[0031]
The A / D converter 5 performs A / D conversion on other analog signals and outputs them to an internal circuit or an external circuit except during an operation test.
The interleave circuit 6 operates only during an operation test, and outputs the digital signal output from the A / D converter 5 to the test apparatus 1 at a rate of once every n times.
[0032]
When performing the operation test of the A / D converter 5 of the semiconductor device 2 as described above, the original clock signal CLK and the control signal CNTL are supplied from the test device 1 to the semiconductor device 2.
[0033]
Then, the phases of the internal clock signal CK input from the PLL circuit 3 to the A / D converter 5 and the analog signal Ain input from the analog signal generation circuit 4a to the A / D converter 5 are changed with time. It will shift.
[0034]
As shown in FIG. 4, when the phase of the analog signal Ain is shifted from the sampling timing ST of the A / D converter 5 by the internal clock signal CK and is gradually shifted from the analog signal Ain1 to the same Ain2, the sampled analog The level gradually changes in the range of the comparison reference voltages VRH to VRL of the A / D converter 5.
[0035]
As a result, the analog value sampled by the A / D converter 5 sequentially changes in the range of the reference voltages VRH to VRL, and the analog value is converted into a digital signal, and the test apparatus is connected via the interleave circuit 6. 1 is output.
[0036]
The test apparatus 1 determines whether or not the A / D converter 5 is operating normally by detecting whether or not the digital value of the digital signal output from the interleave circuit 6 changes sequentially.
[0037]
In the semiconductor device 2 as described above, the following effects can be obtained.
(1) Since it is not necessary to supply an analog signal from the test apparatus 1 to the semiconductor device 2, the operation test of the high-speed A / D converter 5 mounted on the semiconductor device 2 is surely performed regardless of the operation speed of the test apparatus 1. Can be done.
(2) A high-frequency internal clock signal CK is generated in the semiconductor device 2 based on the original clock signal CLK supplied from the test apparatus 1, and an internal signal is generated by the analog signal generation circuit 4 based on the internal clock signal CK. The high frequency analog signal Ain having the same frequency as that of the clock signal CK can be easily generated.
(3) The analog signal generation circuit 4a sequentially shifts the phase of the internal clock signal CK to generate the analog signal Ain. The analog signal Ain is input to the A / D converter 5 and sampled by the internal clock signal CK. Thus, the analog value to be sampled can be changed finely. Therefore, the operation test of the A / D converter 5 can be reliably performed by evaluating the digital signal obtained by A / D converting the analog value.
(4) Since the digital output signal of the A / D converter 5 operating at high speed is output to the test apparatus 1 via the interleave circuit 6, the test apparatus having a slower operation speed than the A / D converter 5. 1, the digital output signal of the A / D converter 5 can be reliably captured and evaluated.
[0038]
When the analog signal Ain has a frequency half that of the internal clock signal CK, the internal clock signal CK may be divided by two by a frequency divider and input to the analog signal generation circuit 4a.
[0039]
Further, the PLL circuit 3 may be provided in the test apparatus 1 and the internal clock signal CK may be supplied from the test apparatus 1 to the analog signal generation circuit 4a.
In this embodiment, the internal clock signal CK is used as the sampling clock of the A / D converter 5 and the output signal of the analog signal generation circuit 4a is used as an analog signal. However, the internal clock signal CK is analog to the A / D converter 5. The signal may be input, and the output signal of the analog signal generation circuit 4a may be input to the A / D converter 5 as a sampling clock. In this case, the analog signal generation circuit 4a operates as a clock signal generation circuit.
(Second embodiment)
FIG. 5 shows a second embodiment. In this embodiment, an analog signal generation circuit 4b shown in FIG. 5 is mounted instead of the analog signal generation circuit 4a mounted in the semiconductor device 2 of the first embodiment.
[0040]
The internal clock signal CK is input to the inverter circuit 10, and the output signal of the inverter circuit 10 is output as an analog signal Ain through the capacitor 11.
[0041]
The output side terminal of the capacitor 11 is connected to the power supply VDD via the P-channel MOS transistor 12 and connected to the ground GND via the current source 13. The control signal CNTL is input to the gate of the transistor 12.
[0042]
The analog signal generation circuit 4b as described above outputs an analog signal Ain having the same frequency as the internal clock signal CK based on the input of the internal clock signal CK.
[0043]
At this time, when the voltage level of the control signal CNTL increases, the drain current of the transistor 12 decreases, so the DC level of the analog signal Ain decreases, and when the voltage level of the control signal CNTL decreases, the drain current of the transistor 12 increases. Therefore, the DC level of the analog signal Ain increases.
[0044]
When performing an operation test of the A / D converter 5 of the semiconductor device 2 including the analog signal generation circuit 4b as described above, the original clock signal CLK and the control signal CNTL are supplied from the test device 1 to the semiconductor device 2. . The control signal CNTL is a signal whose voltage level changes with the passage of time, as in the first embodiment.
[0045]
As shown in FIG. 6, the DC level of the analog signal Ain input from the analog signal generation circuit 4b to the A / D converter 5 changes with time.
When the DC level of the analog signal Ain is shifted from the sampling timing ST of the A / D converter 5 by the internal clock signal CK and is gradually shifted from the analog signal Ain3 to Ain4, the sampled analog level is A / D. The voltage gradually changes in the range of the reference voltages VRH to VRL of the D converter 5.
[0046]
As a result, the analog value sampled by the A / D converter 5 sequentially changes in the range of the reference voltages VRH to VRL, and the analog value is converted into a digital signal, and the test apparatus is connected via the interleave circuit 6. 1 is output.
[0047]
The test apparatus 1 determines whether or not the A / D converter 5 is operating normally by detecting whether or not the digital value of the digital signal output from the interleave circuit 6 changes sequentially.
[0048]
In the semiconductor device 2 as described above, the following operational effects can be obtained in addition to the operational effects (1), (2), and (4) obtained in the first embodiment.
○ The analog signal generation circuit 4b sequentially shifts the DC level of the internal clock signal CK to generate the analog signal Ain, inputs the analog signal Ain to the A / D converter 5, and samples it with the internal clock signal CK. Thus, the analog value to be sampled can be changed finely. Therefore, the operation test of the A / D converter 5 can be reliably performed by evaluating the digital signal obtained by A / D converting the analog value.
[0049]
In the second embodiment, the DC level of the analog signal is changed. However, even if the amplitude of the analog signal is changed, the analog value to be sampled can be changed finely.
[0050]
Similar effects can be obtained even when the DC level of the analog signal is kept constant and the DC level or amplitude of the sampling clock is changed.
Similarly to the first embodiment, the output signal of the analog signal generation circuit 4b is input to the A / D converter 5 as the clock signal CLK, and the internal clock signal CK is input to the A / D converter 5 as an analog signal. It can also be set as the structure input as.
(Third embodiment)
FIG. 7 shows a third embodiment. In this embodiment, the analog signal Ain input to the A / D converter 5 is not generated by changing the phase or DC level of the internal clock signal CK, but the comparison reference voltage of the A / D converter 5 is used. Is something that changes.
[0051]
As shown in FIG. 7, the control signal CNTL output from the test apparatus 1 is input to the comparison reference voltage generation circuit 14. The comparison reference voltage generation circuit 14 gradually changes the comparison reference voltage supplied to the A / D converter 5 in the range of VRH1, VRL1 to VRH2, VRL2 shown in FIG. 8 based on the control signal CNTL. .
[0052]
The A / D converter 5 receives the internal clock signal CK output from the PLL circuit 3 as a sampling signal and an analog signal Ain.
[0053]
When performing an operation test of the A / D converter 5 of the semiconductor device 2 including the comparison reference voltage generation circuit 14 as described above, the original clock signal CLK and the control signal CNTL are supplied from the test device 1 to the semiconductor device 2. .
[0054]
As shown in FIG. 8, the comparison reference voltage supplied from the comparison reference voltage generation circuit 14 to the A / D converter 5 changes in the range of VRH1, VRL1 to VRH2, VRL2 over time.
[0055]
When the comparison reference voltage is gradually shifted with respect to the sampling timing ST of the A / D converter 5 based on the internal clock signal CK, the comparison reference voltage gradually changes with respect to the sampled analog level.
[0056]
As a result, with respect to the analog value sampled by the A / D converter 5, the comparison reference voltage sequentially changes in the range of VRH1, VRL1 to VRH2, VRL2, and the analog value is converted into a digital signal. The data is output to the test apparatus 1 through the interleave circuit 6.
[0057]
The test apparatus 1 determines whether or not the A / D converter 5 is operating normally by detecting whether or not the digital value of the digital signal output from the interleave circuit 6 changes sequentially.
[0058]
In the semiconductor device 2 as described above, the following operational effects can be obtained in addition to the operational effects (1), (2), and (4) obtained in the first embodiment.
The comparison reference voltage generation circuit 14 sequentially shifts the comparison reference voltage and inputs it to the A / D converter 5, and compares the comparison reference voltage with the analog value obtained by sampling the analog signal Ain, thereby sampling the analog value. On the other hand, the comparison reference voltage can be finely changed. Therefore, the operation test of the A / D converter 5 can be reliably performed by evaluating the digital signal obtained by A / D converting the analog value.
(Fourth embodiment)
9 and 10 show a fourth embodiment. In this embodiment, an output determination circuit 15 and a control signal generation circuit 16 are added to the first embodiment, and a self-diagnosis circuit for self-diagnosis of the operation of the A / D converter 5 is provided. .
[0059]
The analog signal generation circuit 4a delays the phase of the internal clock signal CK based on the control signal CNTL, and outputs it to the A / D converter 5 as the analog signal Ain.
[0060]
The output signal of the interleave circuit 6 is input to the output determination circuit 15. The output determination circuit 15 is composed of a magnitude comparator, and sequentially compares the digital signals input from the interleave circuit 6. For example, when the digital value input later is larger, that is, when the digital signal monotonously increases. When the digital value input later is smaller, that is, when the digital signal does not increase monotonically, the H level is output.
[0061]
The output signal of the output determination circuit 15 is input to the control signal generation circuit 16. A specific configuration of the control signal generation circuit 16 will be described with reference to FIG.
The input signal IN is input to the inverter circuit 17, and the output signal of the inverter circuit 17 is output to the analog signal generation circuit 4a as the control signal CNTL via the resistor 18. The output side terminal of the resistor 18 is connected to the ground GND through the capacitor 19. The time constant set by the resistor 18 and the capacitor 19 is set sufficiently large with respect to the output signal frequency of the interleave circuit 6.
[0062]
In such a control signal generation circuit 16, when the input signal IN becomes L level, the voltage level of the control signal CNTL is gradually increased, and when the input signal IN becomes H level, the voltage level of the control signal CNTL is gradually decreased. Let
[0063]
In the self-diagnosis circuit configured as described above, when the internal clock signal CK is supplied to the analog signal generation circuit 4a, the A / D converter 5 and the interleave circuit 6, and the operation test of the A / D converter 5 is started. When the digital value of the digital signal output from the interleave circuit 6 increases, the voltage level of the control signal CNTL output from the control signal generation circuit 16 increases.
[0064]
Then, the phase of the analog signal Ain advances, the sampled analog value increases, and the digital value of the digital signal output from the A / D converter 5 increases.
[0065]
Then, the output signal of output determination circuit 15 is maintained at L level, the output signal of inverter circuit 17 of output determination circuit 15 is maintained at H level, and the voltage level of control signal CNTL output from control signal generation circuit 16 Will rise further.
[0066]
By such an operation, a positive feedback loop is formed from the analog signal generation circuit 4a, the A / D converter 5, the interleave circuit 6, the output determination circuit 15, and the control signal generation circuit 16, and the A / D converter 5 is monotonous. If there is no abnormality in sex, the digital signal output from the A / D converter 5 rises to the maximum value.
[0067]
Further, if there is an abnormality in the monotonicity of the A / D converter 5, the operation of the positive feedback loop is stopped at the time of malfunction, and the increase in the voltage level of the control signal CNTL is stopped. Therefore, the A / D converter The rise of the digital signal output from 5 stops without reaching the maximum value.
[0068]
Therefore, after the operation test is started, the A / D converter 5 is normal by checking whether or not the digital signal output from the A / D converter 5 has risen to a maximum value after a predetermined time. It becomes possible to detect whether or not.
[0069]
The high-speed A / D converter 5 is configured to convert the analog signal Ain into a gray code digital signal, and then convert the gray code digital signal into a binary code digital signal for output. Yes. Due to the nature of the gray code, when the digital value changes by “1”, only one bit changes.
[0070]
Using this property, the monotonicity of the output signal of the A / D converter 5 is obtained by taking the EOR logic of the output signal for each bit of the preceding and succeeding cycles in the digital signal of successive cycles of the Gray code. The determination can be made with a simpler configuration than the magnitude comparator.
[0071]
In this embodiment, a positive feedback loop can also be configured by using the analog signal generation circuit 4b of the second embodiment or the comparison reference voltage generation circuit of the third embodiment.
[0072]
【The invention's effect】
As described above in detail, the present invention can provide a test method and a semiconductor device that can sufficiently perform an operation test of a high-speed A / D converter.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment.
FIG. 2 is a circuit diagram showing an analog signal generation circuit.
FIG. 3 is an explanatory diagram showing a sampling operation using an analog signal whose phase is changed.
FIG. 4 is a circuit diagram showing an analog signal generation circuit of a second embodiment.
FIG. 5 is an explanatory diagram showing a sampling operation using an analog signal in which the DC level is changed.
FIG. 6 is a block diagram showing a third embodiment.
FIG. 7 is an explanatory diagram showing a sampling operation when a comparison reference voltage is changed.
FIG. 8 is a block diagram showing a fourth embodiment.
FIG. 9 is a circuit diagram showing a control signal generation circuit.
[Explanation of symbols]
4a, 4b Analog signal generation circuit
5 A / D conversion circuit
CK Internal clock signal (sampling clock signal)
Ain analog signal

Claims (19)

Based on the sampling clock signal supplied to the A / D converter, a signal whose phase continuously changes with respect to the sampling clock signal is generated as an analog signal, and the analog signal is sampled based on the sampling clock signal. A test method for an A / D converter, comprising performing A / D conversion and evaluating a digital signal generated by the A / D conversion. Based on the sampling clock signal supplied to the A / D converter, a signal obtained by continuously changing the DC level or amplitude of the sampling clock signal is generated as an analog signal, and the analog signal is generated based on the sampling clock signal. A test method for an A / D converter, characterized by sampling and A / D conversion, and evaluating a digital signal generated by the A / D conversion. Based on the analog signal supplied to the A / D converter, a signal whose phase is continuously changed with respect to the analog signal is generated as a sampling clock signal, and the analog signal is sampled based on the sampling clock signal. A method for testing an A / D converter, comprising: / D converting and evaluating a digital signal generated by the A / D conversion. Based on the analog signal supplied to the A / D converter, a signal obtained by continuously changing the DC level or amplitude of the analog signal is generated as a sampling clock signal, and the analog signal is sampled based on the sampling clock signal. A / D conversion is performed, and a digital signal generated by the A / D conversion is evaluated. When an analog signal is generated based on a sampling clock signal supplied to an A / D converter and input to the A / D converter, and the analog signal is sampled based on the sampling clock signal and A / D converted. A test method for an A / D converter, wherein a comparison reference voltage supplied to the A / D converter is continuously changed, and a digital signal generated by the A / D conversion is evaluated. 6. The test method for an A / D converter according to claim 1, wherein the analog signal has the same frequency as a sampling clock supplied to the A / D converter. 6. The test method for an A / D converter according to claim 1, wherein the analog signal has a frequency half that of a sampling clock supplied to the A / D converter. 8. The test method for an A / D converter according to claim 1, wherein the digital signal generated by the A / D conversion is evaluated at a rate of once every n times. An analog signal generation circuit that generates, as an analog signal, a signal whose phase continuously changes with respect to the sampling clock signal based on the sampling clock signal supplied to the A / D converter;
A semiconductor device comprising: an A / D converter that samples the analog signal based on the sampling clock signal and performs A / D conversion. An analog signal generation circuit that generates, as an analog signal, a signal obtained by continuously changing the DC level or amplitude of the sampling clock signal based on the sampling clock signal supplied to the A / D converter;
A semiconductor device comprising: an A / D converter that samples the analog signal based on the sampling clock signal and performs A / D conversion. A clock signal generation circuit that generates, as a sampling clock signal, a signal whose phase continuously changes with respect to the analog signal, based on the analog signal supplied to the A / D converter;
A semiconductor device comprising: an A / D converter that samples the analog signal based on the sampling clock signal and performs A / D conversion. A clock signal generation circuit that generates, as a sampling clock signal, a signal obtained by continuously changing the DC level or amplitude of the analog signal based on the analog signal supplied to the A / D converter;
A semiconductor device comprising: an A / D converter that samples the analog signal based on the sampling clock signal and performs A / D conversion. An analog signal generation circuit that generates an analog signal based on a sampling clock signal supplied to the A / D converter;
A comparison reference voltage generation circuit for continuously changing the comparison reference voltage supplied to the A / D converter;
A semiconductor device comprising: an A / D converter that samples the analog signal based on the sampling clock signal and a comparison reference voltage and performs A / D conversion. 14. The semiconductor device according to claim 9, wherein the analog signal is frequency-divided by a frequency divider to ½ the frequency of the sampling clock signal. 14. The semiconductor device according to claim 9, further comprising an interleave circuit that outputs a digital output signal of the A / D converter at a rate of once every n times. An output determination circuit for determining whether or not monotonicity exists in the change in the digital output signal of the A / D converter;
Based on the output signal of the output determination circuit, the analog signal generation circuit, the clock signal generation circuit, and a control signal generation circuit that generates a control signal that monotonously changes the output signal of any of the comparison reference voltage generation circuits. 16. The semiconductor device according to claim 9, further comprising a semiconductor device. The semiconductor device according to claim 16, wherein the output determination circuit is configured by a magnitude comparator. 17. The semiconductor device according to claim 16, wherein the output determination circuit is configured by a logic circuit that generates an exclusive OR signal of continuous digital output signals. A PLL circuit that generates an internal clock signal having a higher frequency than the original clock signal based on an original clock signal supplied from the outside and outputs the internal clock signal as the sampling clock signal or an analog signal is provided. A semiconductor device according to claim 9.

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