JP3769004B2 - Gradation conversion processing device - Google Patents

Description

  The present invention relates to a gradation conversion processing device that converts an N-value gradation image into an M-value gradation image (N <M).

In recent years, printing and display have been performed using multi-value data as output devices such as printing devices and display devices. Therefore, when the image information used for these is handled electronically, the amount of information is increasing.
For this reason, facsimiles, still image files, copying machines, etc. transmit, store, and process original images as binary signals. However, if the binarized signal is reproduced as it is on the output device, the image quality deteriorates. In order to solve this deterioration in image quality, the original image is transmitted as a binarized signal, transmitted, stored, edited, and reproduced by the output device, and the multilevel gradation signal of the original image is estimated from the binarized signal. There is a way.

Conventionally, there are a dither method and an error diffusion method as digital halftone techniques for expressing the density of an original image by a binary signal (pseudo halftone image).
Further, there is a halftone estimation method as a method for estimating the multilevel gradation signal of the original image from the binarized signal for the pseudo halftone image. (For example, Japanese Patent Laid-Open No. 61-251368)
In this halftone estimation method, the halftone is estimated according to the ratio of the number of black and white pixels in the scanning aperture.

Also, the edge in the binary image is detected by a single edge detection filter, the contour area / non-contour area / intermediate area are identified by the output of the detection filter, and the addition weight coefficient in the scanning aperture is changed to vary the smoothing characteristics. Was. (For example, JP-A-4-51378)
JP 61-251368 A JP-A-4-51378

However, in the above-described conventional configuration, when various document images handled by a facsimile, a still image file, and a copying apparatus have different image characteristics in units of pages, or when image characteristics differ in different areas in one page. There has been a problem that the optimum multi-level gradation signal cannot be estimated.
In addition, in the digital halftone technique that expresses the density of a K-value image with a binarized signal (K> 2), data is diffused during binarization conversion, and a unique texture is generated. Therefore, if the distinction between the contour region and the non-contour region is performed with only one edge detector, there is a problem that data is diffused at the time of binarization processing or affected by the texture due to the dot arrangement pattern. It was.

Further, when the scanning aperture is small, the estimated value fluctuates and there is a problem that the error is large.
Further, since facsimile machines, still image files, and copying apparatuses handle various target images, there is a problem in that desired identification processing and image quality adjustment cannot be performed in accordance with the target images.
The present invention solves the above-mentioned conventional problems, and the optimum gradation in any region in the image without affecting the contour portion and non-contour region in the image by the diffusion of binary data and texture. An object of the present invention is to provide an excellent gradation conversion processing apparatus that can perform conversion and further perform image quality adjustment in accordance with a target image.

In order to achieve this object, in a gradation conversion processing apparatus that converts an N-value gradation image into an M-value gradation image (N <M), the gradation conversion processing apparatus of the present invention has the following first configuration. , Second configuration, third configuration, fourth configuration, and fifth configuration.
In the first configuration, the first conversion means for converting the K value image data so that the K value image data is concentrated in the vicinity of the median value of the signal range of the K value image data, and the converted K value image data are converted into N-valued data. N-value conversion processing means for converting into (K> N), estimation means for estimating M-value image data (N <M) from the N-value data generated by the N-value conversion processing means, and the M-value image Second conversion means for inversely converting data (N <M) in conjunction with data conversion of the first conversion means.

In the second configuration, the first configuration further includes setting means for setting a plurality of processing modes or image quality adjustment values, and a plurality of types of conversion tables corresponding to the plurality of processing modes or image quality adjustment values, Control means for selecting one of the conversion tables according to the setting contents of the setting means and resetting the conversion table in the first conversion means and the second conversion means, respectively.
In the third configuration, the first conversion means for converting the data so that the K value image data is increased from the original value in the highlight region constituted by the image having a value smaller than the predetermined value, and the data conversion N-value conversion processing means for converting K-value image data into N-value conversion data (K> N), and M-value image data (N <M) is estimated from the N-value conversion data generated by the N-value conversion processing means. And second conversion means for converting the M-value image data (N <M) to be smaller than the original value in the highlight area.

In the fourth configuration, the first conversion means in the third configuration may reduce the K-value image data from the original value in a shadow region constituted by an image having a value greater than or equal to the predetermined value. The second conversion means converts the M-value image data to increase from the original value in the shadow area.
In the fifth configuration, the first conversion means for converting the data so that the K value image data is increased from the original value in the highlight region constituted by the image having a value smaller than the predetermined value, and the data conversion N-value conversion processing means for converting K-value image data into N-value conversion data (K> N), and M-value image data (N <M) is estimated from the N-value conversion data generated by the N-value conversion processing means. And second conversion means for performing inverse conversion of the first conversion on the M-value image data (N <M) in the highlight area.

  Further, the first configuration converts the K-value image data converted by the first conversion means into N-valued data (K> N), thereby suppressing the data diffusion range of the N-valued data. Since the M-value image data (N <M) is estimated from the digitized data, fluctuations in the estimated value can be suppressed even if the scanning aperture is reduced. Further, by using a small scanning aperture, the resolution can be secured and a circuit can be realized at low cost.

Further, according to the second configuration, the control unit can change the conversion table according to the processing mode from the setting unit or the set value of the image quality adjustment value, and can perform image quality adjustment corresponding to various images. Further, according to the second configuration, the control unit can change the conversion table according to the processing mode from the setting unit or the set value of the image quality adjustment value, and can perform image quality adjustment corresponding to various images.
Further, according to the third configuration, the K value image data obtained by converting the data so that the K value image data is increased from the original value in the highlight region constituted by the image having a value smaller than the predetermined value, is converted. Is converted into N-valued data (K> N), M-value image data (N <M) is estimated from the generated N-valued data, and the M-value image data (N <M) is calculated in the highlight region. Convert M) to be less than the original value.

Further, according to the fourth configuration, in the third configuration, in the shadow region constituted by an image having a value larger than or equal to the predetermined value, data conversion is performed so that the K value image data is reduced from the original value, In the shadow area, conversion is performed so that the M-value image data is increased from the original value.
Further, according to the fifth configuration, the K value image data obtained by performing data conversion so that the K value image data is increased from the original value in the highlight region constituted by the image having a value smaller than the predetermined value, and the data converted. Is converted into N-valued data (K> N), M-value image data (N <M) is estimated from the generated N-valued data, and the M-value image data (N <M) is calculated in the highlight region. The inverse transformation of the transformation is performed on M).

  As described above, according to the present invention, the optimum gradation conversion is performed in any region in the image without being affected by the diffusion of the binarized data and the texture in the contour portion and the non-contour region in the image, Furthermore, a gradation conversion processing device that performs image quality adjustment according to the target image can be realized.

Hereinafter, an area identifying apparatus and a gradation conversion processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a block diagram of a gradation conversion processing apparatus including an area identification apparatus A in the first embodiment of the present invention.
In FIG. 1, the gradation conversion circuit 1 converts N-value gradation image data 100 into M-value gradation image data 200. (However, N <M)
The enhancement circuit 5 enhances the N-value gradation image 100 or the estimated value NA (signal 300) output from the gradation conversion circuit 1, and generates an enhancement signal EF (signal 500).

The data conversion circuit 7 receives the estimated value NA (signal 300) output from the gradation conversion circuit 1, performs data conversion processing on a pixel basis, and outputs a signal 700. This data conversion process increases the sharpness of the estimated value NA (signal 300).
The identification circuit 4 of the area identification device A outputs an identification signal 400 (signal SE) for identifying the contour area and the non-contour area of the N-value gradation image.

The selection circuit 6 selects input A to input D based on the identification signal 400 and the control signal 61 (CONT1), and outputs a selection signal 600. By this selection, one of the signal 200 (Xout), the signal 300 (estimated value NA), the signal 500 (EF), or the signal 700 is output as the selection signal 600.
Regarding the gradation conversion processing apparatus including the area identification apparatus A configured as described above, the gradation conversion circuit 1, the identification circuit 4 of the area identification apparatus A, the data conversion circuit 7, the enhancement circuit 5, and the selection will be sequentially described below. The circuit 6 will be described.

First, FIG. 2 shows a block diagram of the gradation conversion circuit 1. The gradation conversion circuit 1 scans an N-value gradation image for each pixel and converts the N-value gradation image into an M-value gradation image (N <M). Hereinafter, components of the gradation conversion circuit 1 will be described.
The first multi-value conversion circuit 11 includes a first addition circuit 111 and a first normalization circuit 112. The first addition circuit 111 receives the N-value gradation image data 100 and performs an addition process for each pixel of interest and its surrounding pixels according to the set weighting coefficient. The first normalization circuit 112 converts the addition result signal SA obtained from the first addition circuit 111 into an estimated value NA based on the sum of the gradation number N and the weighting coefficient.

  The second multi-value conversion circuit 12 includes a second addition circuit 121 and a second normalization circuit 122. The second addition circuit 121 receives the N-value gradation image data 100 and performs an addition process for each pixel of interest and its surrounding pixels according to the set weighting coefficient. The second normalization circuit 122 converts the addition result signal SB obtained from the second addition circuit 121 into an estimated value NB based on the sum of the gradation number N and the weighting coefficient.

The edge extraction circuit 19 detects an edge component in the N-value gradation image.
The mixing circuit 13 mixes the estimated value NA and the estimated value NB obtained from the first normalization circuit 112 and the second normalization circuit 122 with the weighting coefficients Ka and Kb from the first weighting control circuit 134, and the mixed signal X Is calculated.
The quantization circuit 14 re-quantizes the mixed signal X and converts it into an M-value gradation image. Here, even when the estimated value NA and the estimated value NB are converted from 0 to 1 and are mixed and converted so that 0 ≦ mixed signal X ≦ 1, the quantization circuit 14 [X · (M− 1) By performing the calculation of +0.5], it can be re-quantized to the required number of gradations M. If the quantization circuit 14 is composed of a rewritable memory such as a RAM, the number of gradations M required for the display device and printer device can be accommodated by requantization. Further, when the estimated value NA and the estimated value NB are converted from 0 to an integer value of (M−1) and mixed and converted so that 0 ≦ mixed signal X ≦ (M−1), the quantization circuit 14 [X + 0.5] is calculated and requantized to the required number of gradations M, with the maximum value being M-1.

The operation of the gradation conversion circuit 1 configured as described above will be described below with reference to FIGS. 2, 3, 4, 5, and 24. FIG. In the first embodiment of the present invention, N and M are not specified, but the following description will be made assuming that N = 2 and M = 256, for example.
FIG. 3A shows a filter diagram used for the second adder circuit 121, and FIG. 3B shows a filter diagram used for the first adder circuit 111.

  Although the aperture size of the filter and the weighting factor of the filter are not specified, in the first embodiment of the present invention, the first addition circuit 111 has a 3 × 3 size and weighting factor shown in FIG. A signal SA is generated using a filter 1110 having The second adder circuit 121 generates a signal SB using a filter 1210 having a size of 5 × 5 and a weighting coefficient shown in FIG. When the value of the pixel of interest is P (i, j) and the weighting factor of the pixel of interest is W (i, j), the calculation of the signal SA = ΣΣW (i, j) · P (i, j) is performed in the scanning aperture region. The calculation is performed at all the pixel positions, and all the calculation results are added. The same applies to the signal SB. Therefore, the signal SA and the signal SB are calculated as (Equation 1) and (Equation 2), respectively. Here, · is an operator indicating multiplication.

第１加算回路１１１は、図３（ｂ）に図示する３×３のサイズと重み係数を有するフィルタ１１１０を用い、信号ＳＡを生成する場合、図２４に図示する回路で実現できる。入力したＮ値画像データ１００は、遅延回路１１３とラッチ回路１１７で主走査方向ｉと副走査方向ｊに展開される。３×３領域に展開された９画素の画像データは乗算器１１４によってそれぞれ重み係数レジスタ１１５からの重み係数が乗算され、乗算結果は加算回路１１６ですべて加算され、信号ＳＡを得る。加算結果は「０」から「１６」のＭ（＝１７）値画像データとなる。乗算器１１４は、重み係数レジスタ１１５からの重み係数が２n であれば、ビットシフトの演算によっても実現でき、回路を簡易化できる。 第１加算回路１１１、第２加算回路１２１において、入力される画像データの階調数をｎ、加算される領域の重み係数の和をＳｎとした場合、出力の最大値Ｍｘは（数３）のように演算される。

The first adder circuit 111 can be realized by the circuit shown in FIG. 24 when the signal SA is generated using the filter 1110 having the size of 3 × 3 and the weighting coefficient shown in FIG. 3B. The input N-value image data 100 is developed in the main scanning direction i and the sub-scanning direction j by the delay circuit 113 and the latch circuit 117. The image data of 9 pixels developed in the 3 × 3 area is multiplied by the weighting coefficient from the weighting coefficient register 115 by the multiplier 114, and all the multiplication results are added by the adding circuit 116 to obtain the signal SA. The addition result is M (= 17) value image data from “0” to “16”. If the weighting factor from the weighting factor register 115 is 2n, the multiplier 114 can be realized by a bit shift operation, and the circuit can be simplified. In the first addition circuit 111 and the second addition circuit 121, when the number of gradations of the input image data is n and the sum of the weighting factors of the added regions is Sn, the maximum output value Mx is (Expression 3). It is calculated as follows.

第１加算回路１１１において、重み係数の和をＳａとし、出力値ＳＡの最大値をＭａとすると、Ｍａ＝（ｎ−１）×Ｓａとなる。本発明の第１の実施例では、ｎ＝２であり、第１加算回路１１１は図３（ｂ）のフィルタ１１１０に基づいて加算処理を行うので、各画素の重み係数からＳａ＝１６、Ｍｂ＝１６となる。

In the first addition circuit 111, when the sum of the weighting factors is Sa and the maximum value of the output value SA is Ma, Ma = (n−1) × Sa. In the first embodiment of the present invention, n = 2, and the first adder circuit 111 performs addition processing based on the filter 1110 in FIG. 3B, and therefore Sa = 16, Mb from the weighting factor of each pixel. = 16.

Similarly, in the second adder circuit 121, if the sum of the weight coefficients is Sb and the maximum value of the output value SB is Mb, Mb = (n−1) × Sb. In the first embodiment of the present invention, n = 2, and the second adder circuit 121 performs addition processing based on the filter 1210 in FIG. 3A, so that Sb = 25, Mb from the weight coefficient of each pixel. = 25.
Next, the first normalization circuit 112 and the second normalization circuit 122 will be described. The first normalization circuit 112 and the second normalization circuit 122 assume that the input value is SGx, and that Mx obtained from (Equation 3) is the maximum value of the input value, the input value SGx is calculated based on (Equation 4). Normalize to output value SCx. [] Is an integerization process that cuts off the fractional part.

（数４）は演算回路としても良いし、ＣＰＵ、ＤＳＰなどによって、ＳＧｘからＳＣｘへの対応を予め（数４）に基づき計算し、計算された値をテーブル化したルック・アップ・テーブル（以下単にＬＵＴと記す。）を用いても良い。

(Equation 4) may be an arithmetic circuit, or a look-up table (hereinafter referred to as a table) that calculates the correspondence from SGx to SCx based on (Equation 4) in advance by a CPU, DSP, or the like. May be simply referred to as LUT).

  According to (Equation 3) and (Equation 4) described above, the input value SGx as an addition result is normalized to M-value gradation image data, respectively. Specifically, the input value SA of the first normalization circuit 112 is normalized to the estimated value NA by (Equation 5), and the input value SB of the second normalization circuit 122 is converted to the estimated value NB by (Equation 6). Normalized. Here, the maximum value of the input value SA is Ma, and the maximum value of the input value SB is Mb. In addition, [] is an integer process that rounds down the fractional part.

本発明の第１の実施例では、例えばＭａ＝１６、Ｍｂ＝２５あり、Ｍ＝２５６とすると、それぞれ入力ＳＡに対する出力ＮＡ、入力ＳＢに対する出力ＮＢが演算され、２５６階調の画像データとしてそれぞれ混合回路１３に出力される。

In the first embodiment of the present invention, for example, when Ma = 16 and Mb = 25 and M = 256, the output NA for the input SA and the output NB for the input SB are calculated, respectively, and image data of 256 gradations is obtained. It is output to the mixing circuit 13.

  In the first addition circuit 111 and the second addition circuit 121, the value of the weighting factor of the filter to be used may be not only a positive numerical value but also a negative numerical value or a zero value. Furthermore, it may be a real number as well as an integer. For pixels with zero coefficient, the input value is multiplied by “0” and the result is added as “0”. When the addition result is negative, it is processed as “0”, and the maximum value is processed into a numerical value based on (Equation 3).

  Further, the weighting factor and the area size (scanning aperture) to be added are a predetermined value and a predetermined size determined at the design stage, and an image required from the N-value gradation image data and the M-value gradation image data. It is taken into account by the quality, i.e. the characteristics of the required spatial filter. Accordingly, in the first embodiment of the present invention, different region sizes are used, but the same size may be used. By varying the weighting factor, the smoothness of the input image data (smooth characteristics of the spatial filter) can be changed.

Next, the mixing circuit 13 will be described with reference to FIGS. FIG. 5 is a diagram for explaining the operation of the mixing circuit 13.
The weighted mixing coefficients Ka and Kb indicate the weighting characteristics of a and c shown in FIG. 5 and are determined based on the signal Eout from the edge extraction circuit 19. The estimated value NA shown in FIG. 2 is multiplied by the coefficient Ka by the multiplier 131, and the estimated value NB is multiplied by the coefficient Kb by the multiplier 132. The multiplied results are added by an adder 133 to output a mixed signal X.

  When the estimated value NA (signal 300), estimated value NB, and edge amount Eout (signal 181) are input and the generated mixed signal is X, the mixed signal X is generated by the mixing circuit 13 based on (Equation 7). The Here, MAX is the maximum value output by Eout (signal 181).

（数７）に基づいて混合された混合信号Ｘは、量子化回路１４によって整数化処理され、最終的にＭ値階調画像データに変換される。例えば、Ｍ＝２５６とした場合は２５６階調の画像データＸｏｕｔ（信号２００）が生成される。

The mixed signal X mixed based on (Equation 7) is converted into an integer by the quantization circuit 14 and finally converted to M-value gradation image data. For example, when M = 256, image data Xout (signal 200) having 256 gradations is generated.

As described above, the mixing circuit 13 weights the input signals (estimated value NA and estimated value NB) based on the edge amount Eout (signal 181), and generates interpolated image data by performing the mixing process. .
As the edge amount Eout increases, the mixing circuit 13 increases the mixing ratio of the estimated value NA to the estimated value NB. This is an operation for reducing the smoothness, and the direction for maintaining the resolution. Conversely, as the edge amount Eout decreases, the mixing circuit 13 increases the mixing ratio of the estimated value NB to the estimated value NA. This is an operation for increasing the smoothness, and the input image data is processed to be smoother. Therefore, smoothness is improved in a region with a small edge change such as a photographic region.

  Further, as shown in FIG. 5, instead of using a and c having linear change characteristics as the coefficient Ka and coefficient Kb, coefficients such as b and d that show binary change characteristics at MAX / 2 may also be used. good. This is a selection operation and is optimal for processing characters and the like. If the first weighting control circuit 134 is configured by a LUT using RAM or ROM, a coefficient operation with an arbitrary change characteristic can be realized. However, Ka + Kb = 1.

  As described above, the output of a plurality of different addition circuits (spatial filters) can be continuously shifted by the edge amount Eout by the interpolation processing in the mixing circuit 13. As a result, according to the edge component of the input image data, the degree of smoothing can be continuously changed locally, and the input image data can be converted to a predetermined multilevel level. The multi-value conversion processing that adaptively preserves the edges can achieve both the resolution of the character / line drawing area and the smoothness of the photographic area. In particular, in a region where characters and photographs are mixed, since the binary switching process is not performed, image degradation due to erroneous identification can be suppressed to a very small level.

In the first embodiment of the present invention, the two inputs are mixed, but it is sufficient to perform at least two inputs, and the same effect can be obtained. Further, if the addition region size (scanning aperture) or the types of addition circuits having different weighting factors are increased and mixed, more continuous gradation image data can be generated.
Furthermore, it is possible to easily perform weighting operations on three or more inputs simultaneously (in parallel), and an accurate interpolation process can be performed. In the mixing circuit 13, linear weighting is performed, but non-linear weighting may be performed.

Next, the edge extraction circuit 19 will be described with reference to FIGS. FIG. 4 is a filter diagram used in the edge extraction circuit 19, and FIG. 8 is a spatial frequency characteristic diagram of the filter used in the first embodiment.
For the edge extraction circuit 19, primary differential filters such as a filter 1900 and a filter 1901 shown in FIG. 4 are used. The edge component in the main scanning direction i is detected by the filter 1901, and the edge component in the sub scanning direction j is detected by the filter 1900. Therefore, by combining the absolute value of the addition value obtained by each coefficient of the filter 1900 and the absolute value of the addition value obtained by each coefficient of the filter 1901, the main scanning direction i and the sub-scanning direction j in the N-value image are combined. Edge components can be extracted. As shown in FIG. 8, the filter 1900 and the filter 1901 have a spatial frequency characteristic having a peak at f0. Therefore, an edge component centered on a specific frequency in the N-value image is extracted. The extracted edge component is clipped to the maximum value MAX and output to the mixing circuit 13 as an edge amount Eout (signal 181).

  Here, since the target image is composed of various designs, photographs, and characters, it is usually difficult to specify the spatial frequency of the edge component. Therefore, extracting the edge component centered on a specific frequency can be expected when the characteristics of the image can be grasped or limited, and the edge component of the desired region to be detected as the contour can be obtained. Can be extracted.

  However, in general, FAX, document files, word processors, copiers, and the like handle arbitrary target images that are different on a plurality of pages, and symbols, photographs, and characters are mixed in an image on one page. In order to extract the edge components of the contour region expected in each symbol region, photo region, and character region of one page, it is necessary to prepare a plurality of edge detectors having different spatial frequencies. Furthermore, since it is difficult to specify the spatial frequency of the edge component, it is necessary to use a plurality of edge detectors adaptively.

An embodiment in which the edge extraction circuit 19 is improved so as to adaptively correspond to edge components having different spatial frequencies will be described below. FIG. 6 is an improved block diagram of the edge extraction circuit 19. In the improved block diagram of FIG. 6, the edge extraction circuit 19 includes a first edge detection circuit 15, a second edge detection circuit 16, a mixing circuit 17, and a clip circuit 18.
The first edge detection circuit 15 and the second edge detection circuit 16 detect an edge component at the target pixel position in the image.

  The mixing circuit 17 mixes the edge component signals Ea and Eb obtained from the first edge detection circuit 15 and the second edge detection circuit 16 with the weighting coefficients Kc and Kd from the second weighting control circuit 174 to obtain the edge amount. Eg is output. The edge component Ea of the first edge detection circuit 15 is multiplied by the coefficient Kc by the multiplication circuit 171, and the edge component Eb of the second edge detection circuit 16 is multiplied by the coefficient Kd by the multiplication circuit 172. The multiplied results are added by an adder 173, and an edge amount Eg is output. The mixing circuit 17 may be an LUT using RAM and ROM without using an arithmetic circuit.

The coefficients Kc and Kd are calculated from Kc = Ea / (Ea + Eb + Cn) and Kd = 1−Kc, and the edge amount Eg is calculated from Eg = Kc × Ea + Kd × Eb. The constant Cn may be a small value that allows the required accuracy compared to Ea and Eb. For example, C = 0.5.
The clip circuit 18 quantizes the edge amount Eg input from the mixing circuit 17, clips the maximum value to MAX, and outputs the clipped edge amount Eout to the mixing circuit 13.

FIG. 7A is a filter diagram used for the first edge detection circuit 15, FIG. 7B is a filter diagram used for the second edge detection circuit 16, and FIG. 23 is a circuit block diagram of the second-order differential filter 1500.
The edge component Ea is generated using the second-order differential filter 1500 shown in FIG. 7A, and the absolute value of the result obtained by adding the weighting coefficients shown in the figure is the edge amount Ea. The edge component Eb is generated by using the first-order differential filters 1601 and 1602 shown in FIG. 7B, and the absolute values of the respective results added by the weighting coefficients of the respective filters shown in FIG. The amount is Eb.

  FIG. 23 is a circuit block diagram of the second-order differential filter 1500. The delay circuit 150 delays the N-value image data 100 in the sub-scanning direction j with a line memory. The data delayed in the sub-scanning direction j is delayed in the main scanning direction i by the latch, and added by the adder circuit 152, the adder circuit 153, the adder circuit 159, and the adder circuit 160, respectively, depending on the coefficients of the filters used. The multiplier 154 multiplies the output of the adder circuit 153, and the multiplier 157 multiplies the output of the adder circuit 159 by -1. The adder 155 adds the outputs of the multiplier 157 and the multiplier 154 to output an edge component. The absolute value circuit 156 calculates the absolute value of the adder 155 and outputs the edge component Ea of the pixel of interest. FIG. 23 is a circuit that implements a secondary differential filter. By adjusting the delay latch in the main scanning direction i and the delay line memory in the sub-scanning direction j, the circuit can be adjusted to the coefficient of the secondary differential filter used. it can.

As shown in FIG. 8, the spatial frequency characteristics of the edge component Ea and the edge component Eb show spatial frequency characteristics having peaks at different f1 and f2, and the peak frequency has a relationship of f1> f2. Further, the relationship is f1>f0> f2 with respect to the peak frequencies of the filters 1900 and 1901 shown in FIG.
With respect to the outputs of the different edge component Ea and edge component Eb, the mixing circuit 17 performs control so as to adaptively increase the component ratio in which the output of the edge component increases. As a result, it is possible to extract edge components in a wider frequency range compared to detection centered on a specific frequency of f0, and to detect edge components in contour regions with different conditions such as photo contours, character contours, figure contours, etc. It can be detected adaptively. In FIG. 7A, a secondary differential filter is used to generate the edge component Ea, and in FIG. 7B, a primary differential filter is used to generate the edge component Eb, but a detector that detects the set spatial frequency. If it is good. The same effect can be obtained by mixing the outputs of three or more edge detectors.

  In this way, by mixing edge components having different characteristics, it is possible to eliminate binary processing switching and adaptively extract a wide range of edge components in the image in terms of spatial frequency. If this edge amount Eout is used in the mixing circuit 13, the scanning aperture mixing process can be performed in accordance with the local image edge characteristics, and the complete mixing process including the edge component can be executed. In other words, even if images with different characteristics such as characters, graphics, and photographs are mixed, the estimation process should completely eliminate the binary switching process and automatically adapt to the local image edge characteristics. Can do. Therefore, since the extraction of the optimum edge component for each region and the estimation process according to the edge component can be performed, the influence of local misidentification of the image can be suppressed, and the image degradation can be suppressed very small. Furthermore, an operation for specifying the image to be handled becomes unnecessary. Since the operation for specifying the image requires processing time, the processing speed can be increased by using the edge extraction circuit 19 shown in FIG. Further, optimum processing can be executed even for an image such as a received image such as a fax that cannot specify an image.

Next, the operation of the identification circuit 4 of the area identification device A will be described with reference to FIGS. 8, 9, 10, 11, and 12. FIG.
9 is a block diagram of the identification circuit 4, FIG. 10A is an arrangement diagram of detection positions of the edge detection filter 41 and the edge detection filter 42, FIG. 10B is a filter diagram of the edge detection filter 41, and FIG. ) Shows a filter diagram of the edge detection filter 42. In the first embodiment of the present invention, N and M are not specified, but the following description will be made assuming that N = 2 and M = 256, for example.

  In FIG. 9, the edge detection filter 41 includes nine detectors from the first detector A (41a) to the ninth detector A (41i) and an adder 410 for adding the outputs of the detectors (41a to 41i). The sum signal ESA is generated. As illustrated in FIG. 10A, the nine detectors (41 a to 41 i) define peripheral positions A to I including the position E, where the target pixel position processed by the gradation conversion circuit 1 is the position E. Edge amounts are detected as the respective detection positions. The same filter is used for the detectors (41a to 41i). For example, for the extraction of edge components, the first-order differential filters 4100 and 4101 shown in FIG. 10B are used, and the absolute values of the respective results added by the weighting coefficients of the respective filters shown in FIG. And

  FIG. 22 is a circuit block diagram that realizes one of the n-th detectors A (41 a to 41 i) of the edge detection filter 41. Here, n is 1-9. The delay circuit 418 delays the N-value image data 100 in the sub-scanning direction j by the line memory. The data delayed in the sub-scanning direction j is delayed in the main scanning direction i by the latch, and added by the adder circuits 412a to 412d, respectively, depending on the filter coefficient used. The adder 413 calculates the difference value in the sub-scanning direction j, and the absolute value circuit 415 calculates the absolute value of the adder 413 and outputs the edge component in the sub-scanning direction j (the edge component of the filter 4100). The adder 414 calculates the difference value in the main scanning direction i, and the absolute value circuit 416 calculates the absolute value of the adder 414 to output an edge component in the main scanning direction i (an edge component of the filter 4101). . The adder 417 adds the edge component in the main scanning direction i and the edge component in the sub-scanning direction j to output the edge component of the pixel of interest. FIG. 22 shows a circuit that implements a first-order differential filter. By adjusting the delay latch in the main scanning direction i and the delay line memory in the sub-scanning direction j, it can be adjusted to the coefficient of the first-order differential filter used. it can.

  Similarly, the edge detection filter 42 includes nine detectors of the first detector B (42a) to the ninth detector B (42i) and an adder 420 that adds the outputs of the detectors (42a to 42i). The addition signal ESB is generated. As illustrated in FIG. 10A, the nine detectors (42 a to 42 i) have peripheral positions A to I including the position E as the target pixel position processed by the gradation conversion circuit 1, respectively. The edge amount is detected as the detection position. The same filter is used for the detectors 42a to 42i. For example, the edge component extraction uses the first-order differential filters 4200 and 4201 shown in FIG. 10C, and adds the absolute values of the results obtained by adding the weighting coefficients of the respective filters to obtain the edge amount. .

  As illustrated in FIG. 8, the edge detection characteristic indicates a spatial frequency characteristic having different peaks. When the peak frequency of the filter 4100 and the filter 4101 is FSa, and the peak frequency of the filter 4200 and the filter 4201 is FSb, the relationship of FSa> FSb is established. Therefore, the edge detection filter 41 is suitable for detecting a contour of a pattern having a high frequency such as a character / graphic, and the edge detection filter 42 is suitable for detecting a contour of a low frequency such as a photograph without being affected by the texture and the halftone dot frequency. Further, by using the added value of a plurality of detectors as the edge amount, a large output is obtained when the detection values of the plurality of detectors are large and the correlation is high. Therefore, edge detection can be performed without being affected by data diffusion caused by the binarization process or a unique texture.

  In FIG. 9, the first comparison circuit 43 compares the signal ESA and the comparison level CPA (signal 64), and outputs “H” when ESA> CPA, and outputs “L” when ESA ≦ CPA. Similarly, the second comparison circuit 44 compares the signal ESB with the comparison level CPB (signal 65), and outputs “H” when ESB> CPB, and outputs “L” when ESB ≦ CPB. Here, “H” is determined to be a contour region, and “L” is determined to be a non-contour region.

The AND circuit 45 enables the output of the first comparison circuit 43 when the control signal 62 (signal CONT2) is “H”, disables it when it is “L”, and always sets the output to “L”. Similarly, the AND circuit 46 validates the output of the second comparison circuit 44 when the control signal 63 (signal CONT3) is “H”, is invalid when it is “L”, and always keeps the output “L”. .
The OR circuit 47 outputs an identification signal 400 of “H” when either of the outputs of the AND circuit 45 and the AND circuit 46 is “H”, and outputs “L” when both are “L”. Here, “H” is determined as a contour region, and “L” is a level determined as a non-contour region.

  As described above, the first comparison circuit 43 and the second comparison circuit 44 use the comparison levels CPA and CPB as parameters to determine the signal ESA and the detection signal of the signal ESB obtained by adding the edge signals detected at a plurality of positions. As shown in FIG. 8, the region of identification a is detected by the comparison level CPA, and the region of identification b is detected by the comparison level CPB. Therefore, it is possible to control the frequency region identified by the parameters of the comparison levels CPA and CPB.

The control signal 62 controls validity / invalidity of the determination result of the first comparison circuit 43, and the control signal 63 controls validity / invalidity of the determination result of the second comparison circuit 44. As a result, it can respond to the detection of contour areas of target images with different optimum conditions such as contours of photographic images, contours of character images, contours of graphic images, contours of halftone images, contours of mixed images of characters and photographs, and control of detection characteristics Can do.
Further, as shown in FIG. 11, the identification circuit 4 shown in FIG. 9 uses the outputs of the nine detectors (41a to 41i) and the value of the register 411 as nine comparators (41j to 41r). The values may be compared with each other in the register 411 and the adder 410 may add more than the value in the register 411. Similarly, the outputs of the nine detectors (42a to 42i) and the value of the register 421 are respectively compared by the nine comparators (42j to 42r), and the value of the register 421 or more is added by the adder 420. It may be improved as follows.

The effects improved by this improvement will be described below with reference to FIGS. 12 (a), 12 (b), 12 (c), and 12 (d).
FIG. 12A shows a pattern diagram of the binarized data 100. An area 2000 indicates a character / graphic area, and an area 2200 inside the area 2000 is an example in which data is diffused by binarization processing and character / graphic image data is moved. This movement of data does not occur with electronic data drawn by a computer. However, when an original is read by an input from a scanner or the like, it often occurs when the original density is low or blurred. Further, the region 2100 in the non-contour region is an isolated point frequently generated by the binarization process when the gray value of the K-value image data is small. Assuming that the gray value of the K-value image data is constant, the digital halftone technique such as the error diffusion method or the dither method performs binarization processing so that the gray value is averaged over a wide area. Because.

  FIG. 12B illustrates an output diagram when an edge of an image is detected using one fifth detector A (41e) that detects the target pixel position E in the edge detection filter 41. is there. The fifth detector A (41e) uses the filter 4100 and the filter 4101 to detect the edge of the image in the main scanning direction and the sub-scanning direction, and detects the edge at the target pixel position E by combining the respective outputs. To do. The implementation circuit is the same as in FIG. A region is identified using the output data of the edge detection. In the digital halftone technique such as the error diffusion method or the dither method, even if the data before binarization is a constant value, the data is diffused by the binarization process, so the edge output Eg does not become “0”. Therefore, in consideration of the influence (misidentification) of the isolated point region 200 in the non-contour region, when the determination level to be identified is “3” or more, the region 3000 surrounded by the dotted line in FIG. It can be detected. As shown in FIG. 12B, although there is no false detection of the isolated point area 2100, the character / graphic area 2000 is not detected and the outer area is detected. Further, the detection area 3000 is identified by the influence of the area 2200 in which data is moved by the binarization processing illustrated in FIG. If the determination level is “2” or higher, the identification area is expanded, but the state where the area 3000 is isolated cannot be solved. Further, the number of erroneous detection areas is further increased around the isolated point area 2100.

  FIG. 12C illustrates an output diagram of the edge output ESA of the edge detection filter 41. The edge detection filter 41 includes nine detectors from the first detector A (41a) to the ninth detector A (41i) and an adder 410 that adds the outputs of the detectors (41a to 41i). Since the ESA is generated, a larger edge component is output when the correlation between the detectors (41a to 41i) is large, and an output of the edge component does not increase when the correlation is small. Therefore, the influence of isolated points is suppressed in the non-contour region, and the region can be identified in the contour region without being influenced by data diffusion. Here, when the value of the determination level CPA of the first comparison circuit 43 illustrated in FIG. 9 is set to “8”, the region 3000 surrounded by the dotted line in FIG. 12C can be detected as the contour region. Although there is an erroneous detection of the isolated point region 100, a wide region including the periphery of the character / graphic region 2000 is detected in a single connected state. Further, the detection area 3000 is not affected at all by the area 2200 in which data is moved by the binarization processing shown in FIG. Here, by setting the value of the determination level CPA to “15”, only the character / graphic region 2000 can be extracted and identified. Thus, by changing the setting of the value of the determination level CPA, it is possible to change the area to be extracted and change the identification area.

  FIG. 12D illustrates an output diagram of the edge output ESA of the improved edge detection filter 41 illustrated in FIG. As a result of this improvement, since the edge component is added to a predetermined level or more, the influence of isolated points can be eliminated, and erroneous detection of isolated points in FIG. 12C is improved. Here, the comparison value (REG1) is set to “1”, the edge outputs Eg of the nine edge detectors (41a to 41i) illustrated in FIG. 11 are compared by the respective comparators (41j to 41r), and Eg When> 1, the adder 410 adds the edge output Eg. Furthermore, when the value of the determination level CPA of the first comparison circuit 43 shown in FIG. 9 is set to “8”, the region 3000 surrounded by the dotted line in FIG. 12D can be detected as the contour region. There is no false detection of the isolated point area 2100, and a wide area including the periphery of the character / graphic area 2000 is detected in a single connected state. Further, the detection area 3000 is not affected at all by the area 2200 in which data is moved by the binarization processing shown in FIG. Therefore, it can be seen that the detection accuracy of the edge detection filter 41 is improved as compared with FIG. By the same processing, the detection accuracy of the edge detection filter 42 can be improved. Here, by setting the value of the determination level CPA to “12”, only the character / graphic region 2000 can be extracted and identified. Thus, by changing the setting of the value of the determination level CPA, it is possible to change the area to be extracted and change the identification area.

  From the above, by adding the edge amounts detected by the plurality of edge detection filters from the peripheral position including the pixel position of interest and comparing it with a predetermined level, the character / graphic area that is the outline area can be detected with high accuracy. Furthermore, by adding a process of comparing the edge amount detected by the edge detection filter with a predetermined value and adding a value greater than or equal to the predetermined value, it is possible to eliminate the influence of data diffusion caused by the binarization process. Can eliminate false detection due to texture in the binarized image. As a result, since the erroneous detection amount in the non-contour region can be reduced and the edge amount in the contour region can be added, the edge detection accuracy can be further improved.

  Further, the identification circuit 4 shown in FIGS. 9 and 11 discriminates the contour region and the non-contour region in the N-value gradation image, so that different gradation conversion processing (N-value image is converted into M value in each identification region). Image [N <M]). Therefore, by using the optimum gradation conversion processing for each contour region and non-contour region, gradation conversion processing that can achieve both resolution and uniformity can be realized for the entire N-value gradation image.

  In the vicinity of the contour region, the n × m scanning aperture of the gradation conversion process outputs an estimated value NA of the intermediate state from the binarized data including the character / graphic region 2000 of the contour region and the non-contour region. . Since this intermediate region is a region where resolution is prioritized in terms of image quality, it needs to be identified as a contour region. In order to determine the position where the n × m scanning aperture includes the character / graphic region 2000 as the contour region, it is necessary to detect a wide region including the periphery of the character / graphic region 2000 in a single connected state. For this reason, the identification circuit 4 shown in FIG. 9 detects a wide area including the periphery of the character / graphic area 2000 in a single connected state, and thus is very compatible with the gradation conversion process.

Next, the data conversion circuit 7 will be described with reference to FIGS. 13, 14, and 15. FIG.
13 is a block diagram of the data conversion circuit 7, FIG. 14A is a filter diagram for explaining the coefficient setting of the data conversion circuit 7, FIG. 14B is a data conversion curve diagram, and FIG. The operation explanatory view of is shown. Here, it is assumed that N = 2 and M = 17, and that the normalization coefficient of the first normalization circuit 112 shown in FIG. 2 is 1 (SA = NA).

In FIG. 13, an input estimated value NA (signal 300) is a signal generated by the first multi-value conversion circuit 11 shown in FIG. A filter 1110 illustrated in FIG. 3B is used for the first adder circuit 111 of the first multi-value conversion circuit 11.
The coefficient setting circuit 71 of the data conversion circuit 7 sets the data conversion coefficient in the coefficient setting register 72. The data conversion coefficient is calculated based on the weight coefficient of the filter 1110 used in the first addition circuit 111 of the first multi-value conversion circuit 11. The calculation method will be described later.

  The estimated value NA (signal 300) output from the first multi-value conversion circuit 11 is subtracted from the value “4” of the register 72a by the subtractor 77, and the value “2” of the register 72c is further subtracted from the multiplier 78. To obtain a signal 780. The comparison circuit 73 sets the output signal 730 to “H” level when the input condition is A> B, and to “L” level when A ≦ B. The selection circuit 75 selects the value “16” of the register 72d when the output signal 730 of the comparison circuit 73 is “H” level, selects the output signal 780 when the output signal 730 is “L” level, and outputs the output signal 750 To do. The comparison circuit 74 sets the output signal 740 to “L” level when the input condition is A <B, and to “H” level when A ≧ B. The removal circuit 76 sets the output signal to “0” when the signal 740 is “L” level, and outputs the output signal 750 as the output signal 700 when it is “H” level.

Here, a method of calculating the values of the registers 72a to 72d set in the coefficient setting register 72 will be described with reference to FIG.
FIG. 14A illustrates the filter 1110 as an example. If the weighting coefficients at each pixel position are W11 to W33, W11, W13, W31, and W33 are “1”, W12, W21, W23, and W32 are “2”, and W22 is “4”. Although the weighting coefficient is not specified, the effect is greater as the weighting coefficient at the target pixel position is larger than the surrounding pixel positions. Furthermore, it is preferable in terms of image quality to arrange the coefficients so as to be the target in the main scanning direction i and the sub-scanning direction j because they do not depend on the direction.

  When the value of the register 72a is reg (a), the value of the register 72b is reg (b), the value of the register 72c is reg (c), and the value of the register 72d is reg (d), the value of each register is Is calculated as follows.

ｒｅｇ（ａ）は行ライン上端の重み係数を加算したが、行ライン上端、行ライン下端、列ライン左端、列ライン右端のいずれか１つのライン上の重み係数を加算すれば良い。ｒｅｇ（ｄ）は重み係数の総和が設定される。

In reg (a), the weighting coefficient at the upper end of the row line is added, but the weighting coefficient on any one of the upper end of the row line, the lower end of the row line, the left end of the column line, and the right end of the column line may be added. In reg (d), the sum of weighting coefficients is set.

  The calculation of (Equation 8) is performed by previously removing the estimated estimated value obtained from the pixel position located in the end row in the row direction or the end column in the column direction from the estimated value NA. Since the data conversion is performed in the direction of reducing the size equally, sharpness is improved. Even when the scanning aperture size is increased, the estimated amount obtained from the pixel located in the end row in the row direction of the scanning aperture or the pixel located in the end column in the column direction is deleted in advance from the estimated value, so that the same effect is obtained. .

By the above data conversion, the input estimated value NA (signal 300) is converted by the data conversion curve shown in FIG. 14B and output as an output signal 700.
FIG. 15 shows the estimated value NA (signal 300) and the estimated value NA (signal 300) when the binary image data is moved in the main scanning direction i by the filter 1110 of FIG. It is a drawing comparing the signal 700 processed in step 1, and it can be seen that the sharpness (resolution) is improved.

By using this converted signal 700 as the input D of the selection circuit 6 shown in FIG. 1, the sharpness (resolution) of the contour region identified by the identification circuit 4 can be improved. In addition, even if misidentification exists in the non-contour area, a rapid density change does not occur, and image quality deterioration can be suppressed to a small level.
When each value (72a to 72d) to be set in the register 72 of the data conversion circuit 7 is fixed, the data conversion circuit 7 is replaced with a ROM, and a data conversion table corresponding to the data conversion coefficient is stored therein. The same data conversion may be performed. Further, when each value (72a to 72d) set in the register 72 of the data conversion circuit 7 is variable, the data conversion circuit 7 is replaced with a RAM, and a coefficient corresponding to the weight coefficient of the filter 1110 is calculated and converted. The conversion table corresponding to the curve may be created again, and the created conversion table may be set again in the RAM.

Next, the enhancement circuit 5 will be described with reference to FIGS. FIG. 16 is a block diagram of the emphasis circuit 5.
In FIG. 16, the delay circuit 50 is composed of a three-line line memory, and delays the estimated value NA (signal 300) in the sub-scanning direction j. The delayed data is delayed in the main scanning direction i by the delay circuit 51. The delay circuit 51 is configured by a latch. The multiplication circuit 52 multiplies the value P (i, j) of the target pixel position to be emphasized five times. The adder circuit 54 has pixel values P (i−1, j−1), P (i + 1, j−1), P (i−1, j + 1), P (i + 1, j + 1) located around the target pixel position. Is added. The multiplier circuit 56 multiplies the output of the adder circuit 54 by -1. The adder circuit 53 adds the outputs of the multiplier circuit 52 and the multiplier circuit 56. The absolute value circuit 55 calculates the absolute value of the output from the adder circuit 53 and outputs an enhancement signal EF (signal 500).

  The enhancement circuit 5 enhances the image of the estimated value NA (signal 300) for each target pixel position, that is, for each pixel. Therefore, if the emphasized position of interest is P (i, j), the emphasized signal EF is calculated by (Equation 9). However, ABS [] is an operation that takes an absolute value.

また、同様の強調信号ＥＦ（信号５００）は、推定値ＮＡ（信号３００）を３ラインのラインメモリで遅延させずに生成することもできる。この場合は、強調する着目画素位置（ｉ，ｊ）を含む位置（ｉ，ｊ）、位置（ｉ−１，ｊ−１）、位置（ｉ＋１，ｊ−１）、位置（ｉ−１，ｊ＋１）、位置（ｉ＋１，ｊ＋１）の５点を、推定位置として、それぞれ図２の第１多値化変換回路１１を用いて推定値ＮＡを算出し、算出された各位置での推定値ＮＡ（ｉ，ｊ）、ＮＡ（ｉ−１，ｊ−１）、ＮＡ（ｉ＋１，ｊ−１）、ＮＡ（ｉ−１，ｊ＋１）、ＮＡ（ｉ＋１，ｊ＋１）を（数９）の各位置に対応する画素値として代入することで、Ｎ値階調画像１００から直接に強調信号ＥＦ（信号５００）を得ることができる。 このＮ値階調画像１００から直接に強調信号ＥＦを得ると、遅延回路５０の３ラインのラインメモリの容量が大幅に削減できる。本発明の第１の実施例ではＮ＝２、Ｍ＝２５６である為、信号３００の遅延は８ビット／画素を行なうのに対して、Ｎ値階調画像１００の遅延は１ビット／画素となる。遅延ライン数が同じ場合、ラインメモリ容量は１／８となる。Ｎ値階調画像１００から直接に強調信号ＥＦを得る方法は、５点を着目位置として推定するので第１多値化変換回路１１の規模は５倍になる。しかし、削減されるメモリ容量の７／８に相当するゲート換算数と、５倍の第１多値化変換回路１１の規模のゲート換算数では、Ｎ値階調画像１００から直接に強調信号ＥＦ（信号５００）を得る方がゲート換算数が小さい。これは、ＬＳＩ化する際に有利となり、高速化できるといった効果がある。

Further, the same enhancement signal EF (signal 500) can be generated without delaying the estimated value NA (signal 300) by a three-line line memory. In this case, the position (i, j), the position (i−1, j−1), the position (i + 1, j−1), the position (i−1, j + 1) including the pixel position of interest (i, j) to be emphasized. ) And 5 (5) at positions (i + 1, j + 1) as estimated positions, the estimated value NA is calculated using the first multi-value conversion circuit 11 of FIG. 2, and the estimated values NA ( i, j), NA (i-1, j-1), NA (i + 1, j-1), NA (i-1, j + 1), and NA (i + 1, j + 1) correspond to the respective positions of (Equation 9). By substituting as the pixel value to be applied, the enhancement signal EF (signal 500) can be obtained directly from the N-value gradation image 100. If the enhancement signal EF is obtained directly from the N-value gradation image 100, the capacity of the three-line line memory of the delay circuit 50 can be greatly reduced. In the first embodiment of the present invention, since N = 2 and M = 256, the delay of the signal 300 is 8 bits / pixel, whereas the delay of the N-value gradation image 100 is 1 bit / pixel. Become. When the number of delay lines is the same, the line memory capacity is 1/8. In the method of obtaining the enhancement signal EF directly from the N-value gradation image 100, since the five points are estimated as the target position, the scale of the first multi-value conversion circuit 11 is five times larger. However, the enhancement signal EF directly from the N-value gradation image 100 is obtained with the gate conversion number corresponding to 7/8 of the memory capacity to be reduced and the gate conversion number of the scale of the first multi-value conversion circuit 11 of 5 times. Obtaining (signal 500) has a smaller gate conversion number. This is advantageous when LSI is used, and has the effect of speeding up.

  By using the enhancement circuit 5 described above, it is possible to obtain an enhanced image of the estimated value NA with increased sharpness. By using this enhancement signal 500 (signal EF) for the contour region in the N-value gradation image, it is possible to suppress the deterioration of the sharpness of the edge. Further, by emphasizing only the contour region, an M-value gradation image can be obtained without deteriorating the smoothness of the non-contour region. As a result, an edge is preserved in the contour region, and an M-value gradation image (N <M) having good smoothness can be obtained in the non-contour region.

Next, the selection circuit 6 will be described with reference to FIG.
The selection circuit 6 receives an input A (signal 200), an input B (signal 300), an input C (signal 200), an input D (signal 500 or signal) according to a control signal 61 (signal CONT1) and an identification signal 400 (signal SE). 700) and the selection signal 600 is output.
The selection condition is as shown in (Table 1), for example. Here, the selection signal 600 is OUT. Further, the “H” level of the signal 400 (signal SE) represents the result of determination as a contour region, and the “L” level represents a result of determination as a non-contour region.

（表１）より、制御信号６１（信号ＣＯＮＴ１）は３ステップの信号レベルを有する。よって、選択回路６は制御信号６１によって以下の選択を行う。信号レベルが「０」のときは、非輪郭領域に入力Ａ、輪郭領域に入力Ｂを選択する。信号レベルが「１」のとき、非輪郭領域に入力Ｃ、輪郭領域に入力Ｄを選択する。信号レベルが「２」のとき、非輪郭領域に入力Ｂ、輪郭領域に入力Ｄを選択する。

From Table 1, the control signal 61 (signal CONT1) has a signal level of 3 steps. Therefore, the selection circuit 6 performs the following selection by the control signal 61. When the signal level is “0”, the input A is selected for the non-contour area and the input B is selected for the outline area. When the signal level is “1”, the input C is selected for the non-contour area and the input D is selected for the outline area. When the signal level is “2”, the input B is selected for the non-contour area and the input D is selected for the outline area.

  Therefore, in the “photo mode”, since gradation is emphasized, processing is performed using the inputs A and B, and the contour region is not emphasized. In the “character / photo mode”, since the resolution and gradation are important, processing is performed using the input C and input D, and the contour region is emphasized. Further, in the “character mode”, since the resolution is important, the processing is performed using the input B and the input D, and the contour region is emphasized.

As described above, the “processing mode” shown in (Table 1) is set by the setting operation from the operation panel 91 described later, and the control circuit 92 sets the corresponding control signal 61 (signal CONT1). Conversion processing from an N-value gradation image optimal for the target image to an M-value gradation image (N <M) can be executed.
Further, the output signal 500 of the enhancement circuit 5 that performs enhancement processing may be replaced with the output signal 700 of the data conversion circuit 7. The data conversion circuit 7 equalizes the aperture by removing in advance from the estimated value NA the estimated estimated value obtained from the pixel position located in the end row in the row direction or the end column in the column direction of the scanning aperture. Therefore, sharpness is improved because data conversion is performed in the direction of decreasing the size.

As described above, according to the first embodiment, it is possible to obtain an M-value gradation image (N <M) with little edge deterioration in the contour region and good smoothness in the non-contour region.
Hereinafter, a gradation conversion processing apparatus according to a second embodiment of the present invention will be described with reference to the drawings.
FIG. 17 shows a block diagram of a gradation conversion processing apparatus in the second embodiment of the present invention.

In FIG. 17, the first conversion circuit 2 is configured by a LUT such as a RAM, and converts K-value image data by a conversion table set from the control circuit 92 via a control signal 920 (signal TAB1).
The N-value conversion circuit 8 converts the K-value image data from the first conversion circuit 2 into N-value gradation image data (K> N).

The image memory 9 is composed of, for example, a semiconductor memory or a hard disk device, and stores the N-value gradation image data from the N-value conversion circuit 8.
The estimation circuit 93 is the gradation conversion processing apparatus of the first embodiment of the present invention shown in FIG. 1, and the N-value gradation image data 100 from the image memory 9 is converted into the M-value gradation image data 600 (N <M ).

The second conversion circuit 3 is configured by an LUT such as a RAM, and converts M-value gradation image data by a conversion table set from the control circuit 92 via a control signal 921 (signal TAB2).
The control circuit 92 outputs a control signal to the estimation circuit 93, the first conversion circuit 2, and the second conversion circuit 3 in accordance with the setting signal from the operation panel 91.

The operation panel 91 is composed of, for example, a plurality of keys, such as image resolution level setting, “photo mode”, “character / photo mode”, “character mode”, “character / graphic mode”, “halftone mode” values, etc. In accordance with the setting of the input switch, a setting signal is output according to the content set in the control circuit 92.
The operation of the gradation conversion processing apparatus configured as described above will be described below.

First, an embodiment in which the N-value conversion circuit 8 converts a K-value image into an N-value image (K> N) will be described with reference to FIG. The conversion method for performing the N-value processing includes a dither method and an error diffusion method. In the second embodiment of the present invention, for example, the K-value image data is converted into N-value image data by the error diffusion method shown in FIG. Convert to
In FIG. 21, the K-value image data fxy is added by the adder 81 with the integrated error value Err around the pixel of interest, and an output f′xy is output. This f′xy is quantized to an N value by being compared with a plurality of preset threshold values by the N-value conversion processing circuit 82, and an output gxy is output. The adder 83 performs an operation of xy = f′xy−gxy, and the quantization error xy is distributed around the pixel of interest with a certain weighting factor and stored in the error memory 86. The multiplier 84 multiplies the error value e distributed around the pixel of interest by the weight coefficient of the weight matrix Wij and outputs an integrated error value Err. The signal 801 is Err = ΣΣe (x + i, y + j) × Wij. For example, when N = 2, gxy outputs binary data “0” and “255”, and the normalization circuit 87 outputs binary data “0” and “255” to “0” and “1”. Normalize to binary data. As a result, the K-value image data is normalized to N-value image data.

  When a halftone image generated by the error diffusion method shown in FIG. 21 is used as the input image of the estimation circuit 93, estimation restoration is performed that has little degradation of the edge portion and has both a resolution and gradation without pseudo contour. be able to. Here, the error diffusion method is used as an N-value conversion process in which the K-value gradation is changed to the N-value gradation (K> N), but the N-value conversion circuit 8 is specified in the second embodiment of the present invention. Any processing may be used as long as the average data value in the image is stored. Therefore, the processing may be performed by a known N-value (K> N) means, and for example, a minimum average error method, a dither method, a multi-value dither method, or the like may be used.

Next, the first conversion circuit 2 and the second conversion circuit 3 will be described with reference to FIGS. 17, 18, 19, and 20. 18A is an explanatory diagram of the conversion operation of the first conversion circuit 2 and the second conversion circuit 3, FIG. 18B is a relationship diagram between the scanning aperture position and the black pixel position, and FIG. 19 is an explanatory diagram of data conversion. FIG. 20 is an explanatory diagram of a conversion table.
In the second embodiment of the present invention, N, M, and K are not specified, but N = 2, M = 256, and K = 256. For ease of explanation, the estimated value NA of the first multi-value conversion circuit 11 in the gradation conversion circuit 1 shown in FIG. 2 will be described as an example. The estimation operation will be described assuming that the scanning aperture of the filter 1110 used in the first addition circuit 111 is 2 × 2 and all the addition weight coefficients in the aperture are 1. Therefore, if the pixel value at the pixel position of interest is P (i, j) and the weighting coefficient is W (i, j), the first addition circuit 111 has a signal SA of SA = ΣΣW (i, j) · P (i, j), (Equation 3) becomes SA = P (i, j) + P (i + 1, j) + P (i, j + 1) + P (i + 1, j + 1). Here, · is an operator indicating multiplication. Further, Sa = 4 and Ma = 4. Accordingly, normalization of the first normalization circuit 112 is calculated by substituting Ma = 4 and M = 256 according to (Equation 5), and an estimated value NA is output. Since (M−1) / Ma is approximately 64, one black pixel counted in the area of the scanning aperture 2 × 2 has 64 data values in the estimated value NA.

First, the case where the conversion curve 3 illustrated in FIG. 18A is set in the first conversion circuit 2 and the second conversion circuit 3 will be described. The conversion curve 3 has a relationship in which the input signal Xin and the output signal Yout are Yout = Xin. This is a conversion table in which an input signal is directly used as an output signal.
The estimation circuit 93 estimates an M-value gradation image (N <M) from the N-value gradation image. If K = M, the K-value image input to the N-ary circuit 8 is estimated. The N-value conversion circuit 8 converts the grayscale data of the pixel of interest into binary data “0” and “255” and diffuses the generated error to surrounding pixels. The binary data “0” and “255” is normalized to “0” and “1” and stored in the image memory 9. By this binary quantization process, 8 bits / pixel is converted to 1 bit / pixel, and the data capacity is compressed to 1/8. This compressed image has a bitmap structure, and the compression rate is a fixed length. Therefore, it is suitable for real-time processing because the compression time is constant compared to compression by variable length coding. Furthermore, since the image data in the image memory 9 has a bitmap structure, it is not necessary to edit the image data once it has been decompressed as in the case of a compressed image by variable length coding, so that it is possible to execute overlapping editing at a high speed. . The binary data “0” is output as a white dot and “1” is expressed as a black dot, or the binary data “1” is output as a white dot and “0” is output as a black dot. In this way, a digital halftone image based on dot density can be obtained.

  From the binary data “0” and “1” stored in the image memory 9, an M-value gradation image is estimated by the first multi-value conversion circuit 11. For example, K value image data having a constant value “16” is converted into normalized data “0” and “1” by the N-ary circuit 8, and “0” is illustrated as a white pixel and “1” is illustrated as a black pixel. As shown in FIG. 18B, the data is converted into binary data “0” and “1” having a distance of Dx in the main scanning direction and Dy in the sub scanning direction. The first multi-value conversion circuit 11 adds the data values in the scanning aperture and performs normalization to estimate the M-value gradation image. If the scanning aperture is 2 × 2 and the weighting coefficients for addition are all 1, M = 256 and Ma = 4, and the black dot “1” is converted to approximately 64 as a data value by (Equation 5).

  In a small value of the K value data, that is, in the highlight area of the image, the scanning aperture size is smaller than the diffusion range of the black pixel (binary data “1”), and the estimated value NA varies depending on the scanning position. The estimated value is 64 at the scanning position A shown in FIG. 18B, 0 at the position B, and 64 at the position C. For the K value image data of the constant value “16”, the estimated value does not become constant but fluctuates. Also in the shadow area, the scanning aperture size becomes smaller than the diffusion range of white pixels (binary data “0”), and the estimated value NA also varies.

In order to improve the fluctuation of the estimated value NA of the highlight area and the shadow area, the conversion curve 1 shown in FIG. 18A is set in the first conversion circuit 2 and the conversion curve 2 is set in the second conversion circuit 3.
A conceptual description of the conversion process will be described with reference to FIGS. 18 (a), 18 (b), and 18 (c). Here, the conversion process of the K value image data at a constant value of 16, that is, the point H in FIG. 18A will be described. 18B and 18C, binary data “0” is illustrated as a white pixel and “1” is illustrated as a black pixel.

  As illustrated in FIG. 18A, the input data “16” is quadrupled by the conversion curve 1 of the first conversion circuit 2 by the conversion curve 1 and converted to “64” output data (point B). Is done. Further, the quadrupled K-value image data “64” is converted into “0” and “1” by the N-value conversion circuit 8. Conceptually, since the data is quadrupled, binary values of “0” and “1” having a distance of Dx / 2 in the main scanning direction and Dy / 2 in the sub scanning direction as shown in FIG. 18C. Converted to data. In the scanning position A illustrated in FIG. 18C, the estimated value NA is 64, 64 at the position B, and 64 at the position C. However, since the K-value image data is quadrupled by the conversion curve 1, it is multiplied by 1/4 using the conversion curve 2 (point E) to be 16 at position A, 16 at position B, and 16 at position C. To do. As a result, compared to FIG. 18A, it is possible to suppress the fluctuation of the estimated value NA and obtain an accurate estimated value.

  A point G in FIG. 18A is a median value of the signal range of the K-value image data, and is a point set at 128 when a signal range from 0 to 255 is input. The first conversion circuit 2 converts the K value image data so that the K value image data is larger than the straight line AG in the highlight area below the G point (for example, a curve passing through the point ABG), and the shadow area above the G point is from the straight line GD. Conversion (for example, a curve passing through the point GCD) is performed so as to decrease. This reduces the diffusion range of black pixels (binary data “1”) in the highlight region, or the diffusion range of white pixels (binary data “0”) in the shadow region. The second conversion circuit 3 performs an inverse conversion process of the conversion process performed in the first conversion circuit 2. That is, in the second conversion circuit 3, the conversion value by the curve ABG in the highlight region below the G point is inversely converted by the curve passing through the AEG point, and the conversion value by the curve GCD in the shadow region above the G point is converted. , Inversely transform using a curve passing through the GFD point.

As described above, when the K value image data is converted by the first conversion circuit 2 so as to be concentrated in the vicinity of the median value of the signal range, and the estimated value NA of the M value data is inversely converted by the second conversion circuit 3, a highlight region is obtained. Or in the shadow area, the fluctuation of the estimated value NA becomes small.
The outline of the conversion processing has been described above, and details are shown in FIGS. 19A, 19B, 19C, 19D, 19E, and 19F. I will explain.

FIG. 19A shows an example of K-value image data. In the description, the maximum value of K-value image data is 255, and the minimum value is 0. In the embodiment, a constant value “16” corresponding to approximately 1/16 of the maximum value 255 of the K-value image data is set as target data to be processed.
FIG. 19B shows an example of the binarized data 100 when the K-value image data of FIG. 19A is binarized by the N-value conversion circuit 8. As shown in FIG. 19B, in the average state, binarized data having one “1” in the region A (4 × 4) is obtained.

FIG. 19C shows the output of the estimated value NA when the binarized data 100 of FIG. 19B is estimated by the first multi-value conversion circuit 11. The average value in the area A is “16”, and the K value image data is certainly estimated for the average value in the area A as a unit. However, the fluctuation of the estimated value NA is 0 at each internal pixel position. It is big with 64.
On the other hand, in FIG. 19D, the K value image data “16” of FIG. 19A is converted to four times by the conversion curve 1 (conversion 1), and is almost ¼ of the maximum value 255 of the K value image data. An example of binarized data 100 in which “64” corresponding to the binarization is binarized by the N-valued circuit 8 is shown. As shown in FIG. 19D, in an average state, the data is converted into binarized data in which four “1” exist in the area A.

FIG. 19 (e) shows an output of the estimated value NA when the binarized data 100 of FIG. 19 (d) is estimated by the first multi-value conversion circuit 11.
Next, FIG. 19 (f) is an output obtained by inversely converting the estimated value NA of FIG. 19 (e) by a factor of 1/4 with the conversion curve 2 (conversion 2). Here, the reason for the 1/4 magnification is that the K-value image data input to the N-ary circuit 8 is converted to 4 times by the conversion curve 1 (conversion 1), and therefore, it is necessary to perform inverse conversion to return to the state before the conversion. It is to become. In FIG. 19 (f), within the region A, the estimated value NA does not vary at each pixel position, and the K-value image data “16” is estimated with high accuracy.

  Here, the effect of the conversion will be described. Compared to the estimated value NA of FIG. 19C in which no conversion is performed, the estimated value in FIG. 19F in which conversion is performed by the first conversion circuit 2 and the second conversion circuit 3. As for NA, the fluctuation | variation of an estimated value is suppressed clearly, Furthermore, the estimated value with sufficient precision is obtained. This conversion process is particularly effective in a highlight area or a shadow area where binary data is likely to diffuse.

  As described above, the K value image data is converted by the first conversion circuit 2 so as to be concentrated in the vicinity of the median value of the signal range, and the converted K value image data is converted into N value data (K> N). By converting, the data diffusion range of the black dot in the highlight area or the white dot in the shadow area can be suppressed. When the estimated value NA of the M-value data (N <M) obtained from the N-valued data (K> N) is inversely transformed by the second conversion circuit 3, the estimated value fluctuates in the highlight area or the shadow area. It is possible to obtain the estimated value NA with high accuracy. This is equivalent to controlling the data diffusion range caused by the binarization processing of the N-value conversion circuit 8, and the white dot “0” or the black dot “1” is placed in an area where the distance from the target pixel position is small. By suppressing the data diffusion range, it is possible to obtain an estimated value NA in which local fluctuations are suppressed.

  Also, the conversion operation of the first conversion circuit 2 and the second conversion circuit 3 is performed by changing the data diffusion range of the white dot “0” or the black dot “1” from the target pixel position in the highlight area or the shadow area. Since the distance is suppressed to be small, fluctuations in the estimated value can be suppressed even if the scanning aperture is set small. By reducing the scanning aperture, the circuit scale can be reduced and the resolution can be increased. If an estimated value NA (M-value image data) having a small variation is output to an output device or a display device, a high-quality image with little density unevenness can be obtained.

Further, although the estimation circuit 93 is the gradation conversion processing device shown in FIG. 1, the gradation conversion circuit 1, the first multi-value conversion circuit 11, or the multi-value conversion circuit 12 shown in FIG. . Any device that converts an N-value gradation image into an M-value gradation image (N <M) by estimating a multi-value level from pixel values within a predetermined scanning aperture is effective.
The fluctuation amount of the estimated value NA is determined by the conversion amount of the first conversion circuit 2 and the scanning aperture size of the filter 1110 used in the first addition circuit 111. When the aperture size is constant, the larger the conversion amount, the more effective, but the change amount of the straight line BC in FIG. 18A is also reduced, and the detection amount of the edge component is suppressed. This has a great influence on an apparatus that controls the opening size estimated based on the detected edge component. For example, it is preferable that the amount of change of the straight line BC is larger in characters / graphics.

  Therefore, an operation key for setting the “processing mode” is provided on the operation panel 91 so as to correspond to the image to be processed, and a setting signal is output to the control circuit 92 according to the setting of the operation key. The control circuit 92 has a built-in conversion memory and stores a plurality of types of conversion tables. In accordance with the “processing mode” set from the operation panel 91, the conversion tables of the first conversion circuit 2 and the second conversion circuit 3 are reset via the signal 920 and the signal 921. As shown in FIG. 20, the conversion table for adjusting image quality is stored in, for example, a conversion memory. When the “character / graphic mode” emphasizing the edge component is set, the table of the conversion curve 3 is read from the head address of the LUT 3 and is sent to the first conversion circuit 2 via the signal 920 via the signal 921. Then, the conversion table is reset in the second conversion circuit 3.

Similarly, when the “photo mode” that places importance on smoothness is set, the table of the conversion curve 1 is read from the head address of the LUT 1 and is sent to the first converter circuit 2 via the signal 920 from the head address of the LUT 2. The conversion curve 2 table is read out, and the conversion table is reset in the second conversion circuit 3 via the signal 921.
As shown in FIG. 20, by storing a plurality of types of conversion tables in the conversion memory, it is possible to deal with various images and to adjust image quality.

  Further, the estimation circuit 93 can cope with various images by controlling the control signals 61 to 65 from the control circuit 92 and can adjust the image quality. Hereinafter, the operation will be described with reference to FIG. 9, (Table 1), and (Table 2).

（表１）に示す動作により、制御信号６１（信号ＣＯＮＴ１）は、「処理モード」に応じて強調処理の有無（またはデータ変換の有無）など、各推定出力の選択をする。制御信号６２（信号ＣＯＮＴ２）、制御信号６３（信号ＣＯＮＴ３）は、図９に図示する識別信号４００を制御するものである。制御信号６２（信号ＣＯＮＴ２）は、図９に図示するＡＮＤ回路４５を制御し、第１比較回路４３で判定される結果の有効、無効を制御する。また、制御信号６３（信号ＣＯＮＴ３）は図９に図示するＡＮＤ回路６３を制御し、第２比較回路４４で判定される結果の有効、無効を制御する。「Ｈ」レベルで有効、「Ｌ」レベルで無効となる。比較レベルＣＰＡ、比較レベルＣＰＢは、識別レベルを操作する。比較レベル値（ＣＰＡ、ＣＰＢ）が大きいほど、大きなエッジ検出レベルが必要となり、識別領域が制限される。逆に、比較レベル値（ＣＰＡ、ＣＰＢ）が小さいほど、小さなエッジ検出レベルで識別するので、識別領域が広くなる。 以上の制御信号を用いて、「処理モード」に最適な制御値を設定する。

By the operation shown in (Table 1), the control signal 61 (signal CONT1) selects each estimated output, such as presence / absence of enhancement processing (or presence / absence of data conversion) according to the “processing mode”. The control signal 62 (signal CONT2) and the control signal 63 (signal CONT3) control the identification signal 400 shown in FIG. The control signal 62 (signal CONT2) controls the AND circuit 45 shown in FIG. 9, and controls the validity / invalidity of the result determined by the first comparison circuit 43. Further, the control signal 63 (signal CONT3) controls the AND circuit 63 shown in FIG. 9, and controls the validity / invalidity of the result determined by the second comparison circuit 44. Valid at “H” level and invalid at “L” level. The comparison level CPA and the comparison level CPB operate the identification level. The larger the comparison level value (CPA, CPB), the larger the edge detection level is required, and the identification area is limited. Conversely, the smaller the comparison level value (CPA, CPB), the smaller the edge detection level, the wider the identification area. Using the control signals described above, an optimal control value is set for the “processing mode”.

In the “photo mode”, since smoothness is important, identification processing is performed. Therefore, CONT2 is set to “L” and CONT3 is set to “L”. In this setting, the comparison level values CPA and CPB are invalid.
In the “character / photo mode”, since both the resolution of the character area and the smoothness of the photographic area are emphasized, the identification process is performed. However, in consideration of misidentification by a halftone image in which the spatial frequency is distributed over a wide range, the identification signal using the edge detection filter 41 having a high identification frequency is invalidated, the identification frequency is lower than the halftone frequency, and the halftone frequency. The identification signal using the edge detection filter 42 with small misidentification due to is enabled. Therefore, CONT2 is set to “L” and CONT3 is set to “H”. In this setting, the value of the comparison level CPA is invalid and the value of the comparison level CPB is valid.

  In the “character mode”, since the resolution of the character area is emphasized, identification processing is performed. Furthermore, in order to obtain an identification signal in which the spatial frequency is detected in a wide range, the result using both the edge detection filter 41 and the edge detection filter 42 is validated. Therefore, CONT2 is set to “H” and CONT3 is set to “H”. In this setting, the values of the comparison level CPA and the comparison level CPB function effectively. Further, in order to widen the edge detection area, the value of the comparison level CPB is changed from B1 to B2 (B1> B2).

Further, a plurality of image quality setting keys are provided on the operation panel 91, and the control circuit 92 sets the comparison level values CPA and CPB in a plurality of setting steps by performing a setting operation, and adjusts the image quality by controlling the identification area. .
As described above, according to the second embodiment, by controlling the control signals 61 to 65, the estimation circuit 93 can cope with various images and can adjust the image quality. Therefore, when converting an N-value gradation image into an M-value gradation image (N <M), optimum conversion processing corresponding to various images is performed, and desired image quality adjustment is also performed at the time of conversion. A high-quality M-value gradation image (N <M) can be generated.

As described above, according to the first embodiment and the second embodiment of the present invention, the K-value image is converted into the N-value image (with the identification means for detecting the contour region by adding a plurality of edge detections. The contour region and the non-contour region in the image can be accurately identified without being affected by the data fluctuation caused by the data diffusion when converted to K> N).
Further, since the contour region in the N-value image emphasizes sharpness and the non-contour region has a means for executing estimation processing that emphasizes gradation, any of the contour region and non-contour region in the N-value image is included. It is possible to estimate a high-quality M-value image (N <M) even in the region of.

  Further, there is provided means for performing conversion for concentrating the K-value image data in the vicinity of the median value of the signal range, and converting the converted K-value image data into N-valued data (K> N), thereby converting to N-value. Data diffusion range can be suppressed. By estimating the N-valued data by the estimation means, there is an effect that fluctuation of the estimated value can be suppressed even if the scanning aperture is reduced. Processing with a small scanning aperture can be realized at a low cost while ensuring the resolution.

  In addition, since it has means for generating an edge component amount in which outputs from a plurality of edge detection means having different characteristics are mixed in accordance with image characteristics and mixing a plurality of spatial filters according to the edge component amount, A wide range of edge components can be extracted with respect to the spatial frequency without changing the state. Therefore, gradation conversion adapted to various images or image regions can be performed.

In addition, when converting an N-value gradation image into an M-value gradation image (N <M), the image processing apparatus has a control unit that performs control so as to perform an optimal conversion process corresponding to various images. Since it also has means for executing at the time of conversion, it is possible to generate a high-quality M-value gradation image (N <M) with a desired image quality.
In addition, by applying the present invention to copying machines, printers, display devices, fax machines, document files, etc., it is possible to reduce the amount of image data to realize storage and data transfer, and to produce high-quality estimated images at the output and display stages. Obtainable. Furthermore, if applied to a color output device, a color display device, and a color FAX as well as a monochrome image, the image data capacity can be further reduced while maintaining the image quality. The color can be realized by performing the same processing as that for black and white on each color of the RGB image or the YMC image.

Further, the area identification device and the gradation conversion processing device in the first and second embodiments of the present invention may all be realized by arithmetic processing (software processing) using a CPU or DSP.
Further, when the gradation conversion processing apparatus of the present invention is used as compression / decompression processing for image data, it is possible to realize compression / decompression processing that maintains fixed-length encoding and a bitmap structure. The fixed-length encoding performs compression / decompression in a fixed time, and is optimal for an apparatus that performs real-time processing. Furthermore, the compression that maintains the bitmap structure enables overwriting editing at an arbitrary position in the image recording apparatus, and there is no need to re-develop and edit the compressed image once as in the variable-length encoding method. The editing process can be speeded up.

Summarizing the effects of the above embodiment, the data diffusion when the K-value image is converted into the N-value image (K> N) by having an identification means for detecting the contour region by adding a plurality of edge detections. Thus, there is an effect that the contour region and the non-contour region in the image can be accurately identified without being affected by the data fluctuation due to.
Further, since the contour region in the N-value image emphasizes sharpness and the non-contour region has a means for executing estimation processing that emphasizes gradation, any of the contour region and non-contour region in the N-value image is included. Even in this area, it is possible to estimate a high-quality M-value image (N <M).

  Further, there is provided means for performing conversion for concentrating the K-value image data in the vicinity of the median value of the signal range, and converting the converted K-value image data into N-valued data (K> N), thereby converting to N-value. Data diffusion range can be suppressed. By estimating the N-valued data by the estimation means, there is an effect that fluctuation of the estimated value can be suppressed even if the scanning aperture is reduced. Processing with a small scanning aperture has the effect that the resolution is ensured and can be realized at low cost.

  In addition, since it has means for generating an edge component amount in which outputs from a plurality of edge detection means having different characteristics are mixed in accordance with image characteristics and mixing a plurality of spatial filters according to the edge component amount, A wide range of edge components can be extracted with respect to the spatial frequency without changing the state. Therefore, there is an effect that gradation conversion adapted to various images or image regions can be performed.

In addition, when converting an N-value gradation image into an M-value gradation image (N <M), the image processing apparatus has a control unit that performs control so as to perform an optimal conversion process corresponding to various images. In addition, since it has means for executing at the time of conversion, there is an effect that a high-quality M-value gradation image (N <M) can be generated with a desired image quality.
As described above, according to the present invention, the data diffusion range of N-valued data can be suppressed by converting the K-value image data converted by the first conversion means into N-valued data (K> N). Since the M-value image data (N <M) is estimated from the N-value data, fluctuations in the estimated value can be suppressed even if the scanning aperture is reduced. Further, by using a small scanning aperture, the resolution can be secured and a circuit can be realized at low cost.

Further, the control unit can change the conversion table according to the processing mode from the setting unit or the set value of the image quality adjustment value, and can perform image quality adjustment corresponding to various images. Further, the control unit can change the conversion table according to the processing mode from the setting unit or the set value of the image quality adjustment value, and can perform image quality adjustment corresponding to various images.
Further, in a highlight region constituted by an image having a value smaller than a predetermined value, data conversion is performed so that the K value image data is increased from the original value, and the converted K value image data is converted into N-valued data ( K> N), M-value image data (N <M) is estimated from the generated N-value data, and the M-value image data (N <M) is an original value in the highlight region. Convert to reduce more.

Further, in a shadow area constituted by an image having a value greater than or equal to the predetermined value, data conversion is performed so that the K-value image data is reduced from the original value, and the M-value image data is restored in the shadow area. It is converted to increase from the value of.
Further, in a highlight region constituted by an image having a value smaller than a predetermined value, data conversion is performed so that the K value image data is increased from the original value, and the converted K value image data is converted into N-valued data ( K> N), M-value image data (N <M) is estimated from the generated N-valued data, and the M-value image data (N <M) is estimated in the highlight region. Inverse transformation can be performed.

    As described above, according to the present invention, the optimum gradation conversion is performed in any region in the image without being affected by the diffusion of the binarized data and the texture in the contour portion and the non-contour region in the image, Furthermore, a gradation conversion processing device that performs image quality adjustment according to the target image can be realized.

  The gradation conversion processing apparatus of the present invention is useful when converting an N-value gradation image into an M-value gradation image (N <M) in a facsimile, a still image file, a copying apparatus, or the like.

1 is a block diagram of a gradation conversion processing device including a region identification device A according to a first embodiment of the present invention. FIG. 2 is a block diagram of the gradation conversion circuit 1 in FIG. 1 according to the first embodiment of the present invention. (A) It is a filter figure (1210) used for the 2nd addition circuit 121. FIG.

FIG. 11B is a filter diagram (1110) used for the first adder circuit 111;
FIG. 6 is a filter diagram (1900, 1901) used for the edge extraction circuit 19; It is operation | movement explanatory drawing of the mixing circuit 13 used for a 1st Example. FIG. 6 is an improved block diagram of the edge extraction circuit 19. (A) It is a filter figure (1500) used for the 1st edge detection circuit 15. FIG.

(B) It is a filter figure (1600, 1601) used for the 2nd edge detection circuit 16. FIG.
It is a spatial frequency characteristic figure of the filter used in the 1st example. 3 is a block diagram of an identification circuit 4. FIG. (A) It is an arrangement diagram of detection positions of the edge detection filter 41 and the edge detection filter 42. FIG.

(B) It is a filter figure (4100, 4101) used for the edge detection filter 41. FIG.
(C) It is a filter figure (4200, 4201) used for the edge detection filter 42. FIG.
4 is an improved block diagram of an edge detection filter 41 and an edge detection filter 42. FIG. (A) It is a pattern diagram of the binarized data 100.

FIG. 6B is an edge output diagram of the fifth detector A (41e) of the edge detection filter 41.
FIG. 6C is an output diagram of the edge output ESA of the edge detection filter 41.
(D) It is an output figure of edge output ESA of the improved edge detection filter 41. FIG.
3 is a block diagram of a data conversion circuit 7. FIG. (A) is a filter diagram (1000) for explaining coefficient setting of the data conversion circuit 7;

(B) is a data conversion curve diagram.
6 is an operation explanatory diagram of the data conversion circuit 7. FIG. 3 is a block diagram of an emphasis circuit 5. FIG. It is a block diagram of the gradation conversion processing apparatus in 2nd Example of this invention. (A) It is explanatory drawing of the conversion operation | movement of the 1st conversion circuit 2 and the 2nd conversion circuit 3. FIG.

(B) It is a relationship figure of the scanning aperture position and pixel position before conversion.
(C) It is a relationship figure of the scanning aperture position and pixel position after conversion.
(A) It is a data figure of K value image data. FIG. 19B is a binarized data diagram when the K-value image data in FIG.

(C) It is an output data figure of estimated value NA at the time of estimating the binarized data 100 of FIG.19 (b).
FIG. 19D is a binarized data diagram when the K-value image data of FIG. 19A is converted by the conversion curve 1 and binarized.
(E) It is an output data figure of estimated value NA at the time of estimating the binarized data 100 of FIG.19 (d).

FIG. 20F is an output data diagram obtained by inversely transforming the estimated value NA of FIG.
It is explanatory drawing of a conversion table. 4 is a block diagram of an N-ary circuit 8. FIG. 3 is a circuit block diagram of an nth detector A of an edge detection filter 41. FIG. 2 is a circuit block diagram of a filter 1500. FIG. 3 is a circuit block diagram of a first addition circuit 111. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Gradation conversion circuit 2 1st conversion circuit 3 2nd conversion circuit 4 Identification circuit 5 Emphasis circuit 6 Selection circuit 7 Data conversion circuit 8 N-value conversion circuit 9 Image memory 11 1st multi-value conversion circuit 12 2nd multi-value conversion Conversion circuit 13 Mixing circuit 14 Quantization circuit 15 First edge detection circuit 16 Second edge detection circuit 17 Mixing circuit 19 Edge extraction circuit 41 Edge detection filter 42 Edge detection filter 91 Operation panel 92 Control circuit 93 Estimation circuit

Claims (12)

First conversion means for converting the K value image data so that the K value image data is concentrated in the vicinity of the median of the signal range of the K value image data;
N-value conversion processing means for converting the converted K-value image data into N-value data (K>N);
Estimation means for estimating M-value image data (N <M) from the N-value data generated by the N-value processing means;
A gradation conversion processing apparatus, comprising: second conversion means for performing inverse conversion on the M-value image data (N <M) in conjunction with data conversion of the first conversion means. 2. The gradation conversion processing apparatus according to claim 1, wherein the first conversion means minimizes the conversion amount by the median value of the signal range of the K-value image data. The first conversion means maximizes the amount of conversion in a region smaller than the median value of the signal range of K-value image data or a region larger than the median value of the signal range of K-value image data. 1. A gradation conversion processing apparatus according to 1. The estimation means is a gradation conversion processing device that converts an N-value gradation image into an M-value gradation image (N <M),
A first smoothing for converting the N-value gradation image into the M-value gradation image (N <M) by multiplying the pixel of interest in the N-value gradation image and its surrounding pixels by multiplication by a predetermined weighting coefficient. Filters,
A second value for converting the N-value gradation image into the M-value gradation image (N <M) by increasing the smoothness by making the scanning aperture size or the weighting factor to be added different from that of the first smoothing filter. A smoothing filter of
Edge detecting means for detecting an edge amount in the N-value gradation image;
A mixing ratio control means for calculating a mixing ratio from the edge amount;
Mixing processing means for mixing the first smoothing filter and the second smoothing filter based on the mixing ratio;
Identifying means for identifying a non-contour region and a contour region in the N-value gradation image;
A gradation conversion processing apparatus comprising: a non-contour region that selects an output of the mixing processing unit based on a control signal from the identification unit; and a selection unit that selects an output of the first smoothing filter in the contour region. The gradation conversion processing device according to claim 1. The estimation means is a gradation conversion processing device that converts an N-value gradation image into an M-value gradation image (N <M),
A first smoothing for converting the N-value gradation image into the M-value gradation image (N <M) by multiplying the pixel of interest in the N-value gradation image and its surrounding pixels by multiplication by a predetermined weighting coefficient. Filters,
A second value for converting the N-value gradation image into the M-value gradation image (N <M) by increasing the smoothness by making the scanning aperture size or the weighting factor to be added different from that of the first smoothing filter. A smoothing filter of
Edge detecting means for detecting an edge amount in the N-value gradation image;
A mixing ratio control means for calculating a mixing ratio from the edge amount;
Mixing processing means for mixing the first smoothing filter and the second smoothing filter based on the mixing ratio;
Enhancement means for enhancing the output of the first smoothing filter;
Identifying means for identifying a non-contour region and a contour region in the N-value gradation image;
A non-contour region is a gradation conversion processing device including a selection unit that selects an output of the mixing processing unit based on a control signal from the identification unit, and a selection unit that selects an output of the enhancement unit in the contour region. The gradation conversion processing device according to claim 1. The estimation means is a gradation conversion processing device that converts an N-value gradation image into an M-value gradation image (N <M),
A first smoothing for converting the N-value gradation image into the M-value gradation image (N <M) by multiplying the pixel of interest in the N-value gradation image and its surrounding pixels by multiplication by a predetermined weighting coefficient. Filters,
A second value for converting the N-value gradation image into the M-value gradation image (N <M) by increasing the smoothness by making the scanning aperture size or the weighting factor to be added different from that of the first smoothing filter. A smoothing filter of
Edge detecting means for detecting an edge amount in the N-value gradation image;
A mixing ratio control means for calculating a mixing ratio from the edge amount;
First processing means for mixing the first smoothing filter and the second smoothing filter based on the mixing ratio;
A sum of a predetermined weighting factor in one row direction or one column direction in the scanning aperture including the target pixel of the first smoothing filter and one row direction positioned at an end in the scanning aperture not including the target pixel; Second processing means for changing an output of the first smoothing filter based on a sum of predetermined weighting factors in one column direction;
Identification means for identifying a contour region and a non-contour region in the N-value gradation image;
The gradation conversion processing apparatus includes: a selection unit that selects the first processing unit for the non-contour region in response to a control signal from the identification unit, and selects the second processing unit for the contour region. The gradation conversion processing apparatus according to claim 1. The estimation means includes a plurality of edge detection means having different characteristics for detecting edge amounts in the input N-value image data;
Extraction means for mixing the outputs of the plurality of edge detection means to generate an edge extraction amount;
A plurality of spatial filters having different weighting factors or smoothing regions for smoothing the N-value image;
Mixing processing means for normalizing the outputs of the plurality of spatial filters to a predetermined level and selecting or mixing the outputs of the plurality of spatial filters normalized based on the output from the extraction means; The gradation conversion processing apparatus according to claim 1, wherein the gradation conversion processing apparatus converts to a value image (N <M). The gradation conversion processing apparatus further includes setting means for setting a plurality of processing modes or image quality adjustment values, and a plurality of types of conversion tables corresponding to the plurality of processing modes or image quality adjustment values. 2. The gradation conversion process according to claim 1, further comprising: a control unit that selects one of the conversion tables according to the contents and resets the conversion table in each of the first conversion unit and the second conversion unit. apparatus. The gradation conversion processing apparatus according to claim 1, wherein the N-value image is a binary image. First conversion means for performing data conversion so that the K-value image data is increased from the original value in a highlight region constituted by an image having a value smaller than a predetermined value;
N-value conversion processing means for converting the converted K-value image data into N-value data (K>N);
Estimation means for estimating M-value image data (N <M) from the N-value data generated by the N-value processing means;
Second conversion means for converting the M-value image data (N <M) to be less than the original value in the highlight region;
A gradation conversion processing apparatus comprising: The first conversion means performs data conversion so that the K value image data is reduced from the original value in a shadow region constituted by an image having a value greater than or equal to the predetermined value,
The gradation conversion processing device according to claim 10, wherein the second conversion unit converts the M-value image data so as to increase from the original value in the shadow region. First conversion means for performing data conversion so that the K-value image data is increased from the original value in a highlight region constituted by an image having a value smaller than a predetermined value;
N-value conversion processing means for converting the converted K-value image data into N-value data (K>N);
Estimation means for estimating M-value image data (N <M) from the N-value data generated by the N-value processing means;
Second conversion means for performing inverse conversion of the first conversion on the M-value image data (N <M) in the highlight region;
A gradation conversion processing apparatus comprising:

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