JP3767095B2 - Input interface device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an input interface device. More particularly, the present invention relates to an input interface device used when inputting an output signal of a Si logic circuit (CMOS) to a GaAs logic circuit (DCFL).
[0002]
[Prior art]
In high-frequency communication equipment such as mobile phones, Si (silicon) elements are used for low-frequency signal processing such as voice, and GaAs elements are used for high-frequency signal processing such as transmission / reception radio waves. In recent years, in a signal processing circuit using a GaAs element, an IC in which a front end portion such as a power amplifier, a low noise amplifier, and a switch is integrated on a single chip has been put into practical use. The circuit is also integrated in the same IC as the front end unit.
[0003]
On the other hand, the GaAs logic circuit is controlled by the Si logic circuit used on the low frequency signal processing side. For this purpose, it is necessary to input the output signal of the Si logic circuit to the GaAs logic circuit.
[0004]
However, the Si logic circuit is generally a CMOS composed of MOSFETs, and the output logic amplitude (hereinafter simply referred to as logic amplitude) is the power supply voltage V _DD (and ground potential). Also, since the Si logic circuit has a large output impedance, it cannot take a large drive current. On the other hand, when the GaAs logic circuit is a DCFL (Direct Coupled FET Logic) composed of MESFETs, the input logic amplitude (hereinafter simply referred to as logic amplitude) does not depend on the value of the power supply voltage V _DD , and the gate of the MESFET. A rising voltage (and ground potential) of diode characteristics (hereinafter referred to as a gate diode). Further, the GaAs logic circuit requires a drive current because a forward current flows into the gate diode when the rising voltage is input. Therefore, the output of the Si logic circuit and the input of the GaAs logic circuit cannot be directly connected, and an input interface circuit is required. In general, the rising voltage of the diode is 0.6 to 0.7V, but in the following description, it is assumed that the rising voltage of the gate diode is 0.7V.
[0005]
In order to solve such a problem, conventionally, as shown in FIG. 1, a source follower circuit generally used as an impedance conversion circuit is provided between the output stage of the Si logic circuit 1 and the input stage of the GaAs logic circuit 3. The input interface circuit 2 is inserted. FIG. 1 shows an inverter type CMOS in which pMOS 4 and nMOS 5 are connected in series as an output stage of the Si logic circuit 1, and a depletion type FET (hereinafter referred to as D-FET) 9 as an input stage of the GaAs logic circuit 3. A DCFL is shown in which enhancement type FETs (hereinafter referred to as E-FETs) 10 are connected in cascade, and the gate and source of a D-FET 9 are connected. Further, the Si logic circuit 1 is made of Si · IC, and the input interface circuit 2 and the GaAs logic circuit 3 are made into one chip as GaAs · IC.
[0006]
FIG. 2 shows only the input interface circuit 2 taken out from the circuit of FIG. 1. The power supply voltage V _DD is applied to the drain of the E-FET 6 and the source is grounded through the resistors 7 and 8. The input terminal 11 is taken out from the gate, and the output terminal 12 is taken out between the resistors 7 and 8 connected in series. Since the input interface circuit 2 is composed of the enhancement type FET 6, a high input impedance and a low output impedance can be realized by adopting a source follower configuration. Further, by dividing the source potential of the E-FET 6 by the resistors 7 and 8 and outputting it, the power supply voltage V _DD which is the logic amplitude of the Si logic circuit 1 is set to 0.7 V which is the logic amplitude of the GaAs logic circuit 3. It has been converted.
[0007]
FIG. 3 shows the characteristics of the input interface circuit 2 when the power supply voltage V _DD = 3V. As shown in FIG. 3, in this input interface circuit 2, when the input voltage Vin from the Si logic circuit 1 side is 0V or 3V, the output voltage Vout to the GaAs logic circuit 3 side is 0V, respectively. 0.7V, and the conversion of the logical amplitude as desired is realized. Moreover, the input current Iin is also almost 0 (0.3 μA when the input voltage is Vin = 3 V), and has a high input impedance (3 V / 0.3 μA = 10 MΩ).
[0008]
[Problems to be solved by the invention]
In recent years, Si logic circuits that are driven with a power supply voltage of 2 V have been put into practical use due to advances in microfabrication technology. For this reason, Si logic circuits that control GaAs front-end ICs are currently mixed with those driven by 2V and those driven by 3V.
[0009]
However, the conventional input interface circuit cannot simultaneously cope with both the 2V drive Si logic circuit and the 3V drive Si logic circuit. That is, when a 2 V drive Si logic circuit is connected to an input interface circuit designed for a 3 V drive Si logic circuit, the output voltage Vout of the input interface circuit only rises to about 0.4 V, as can be seen from FIG. . Therefore, the GaAs logic circuit does not operate normally.
[0010]
Conversely, when a 3V drive Si logic circuit is connected to an input interface circuit designed for a 2V drive Si logic circuit, as shown in FIG. 4, the open output voltage of the input interface circuit rises to about 1V. Therefore, a large current flows through the gate diode of the E-FET in the input stage of the GaAs logic circuit in order to clamp the output voltage of the input interface circuit to about 0.7V. Therefore, the reliability of the circuit is lowered, and in the worst case, the FET of the GaAs logic circuit is destroyed.
[0011]
The present invention has been made in view of the drawbacks of the above conventional example, and an object of the present invention is to provide an input interface device capable of dealing with a plurality of Si logic circuits having different logic amplitudes (drive voltages). It is in.
[0012]
DISCLOSURE OF THE INVENTION
Input interface device of the present invention, one of the two logic circuits having different logical amplitudes, a input interface device for connecting the output of one logic circuit to the input of the other logic circuit, the output of the source follower type circuit A constant voltage element is connected to the ground.
[0013]
In the input interface device of the present invention, the constant voltage value of the constant voltage element, for example, the breakdown voltage of the constant voltage diode, is set equal to the logic amplitude of the logic circuit connected to the next stage of the input interface device. Even when a logic circuit having the smallest logic amplitude is connected to the previous stage of the input interface device, the voltage output from the source follower type circuit of the input interface device is larger than the logic amplitude of the logic circuit of the next stage. By doing so, the voltage output from the input interface device to the next-stage logic circuit can be adapted to the logic amplitude of the next-stage logic circuit regardless of the logic amplitude of the previous-stage logic circuit.
[0014]
Therefore, according to the input interface device of the present invention, it is possible to share the input interface device for a plurality of preceding logic circuits having different logic amplitudes.
[0015]
In the input interface device, a diode is used as the constant voltage element, and an anode electrode of the diode is formed of the same material as that of the gate electrode of the field effect transistor used in the input portion of the logic circuit in the next stage. The area of the anode electrode is preferably larger than the area of the gate electrode.
[0016]
When the anode electrode area of the constant voltage diode is made larger than the gate electrode area of the field effect transistor in the next stage, the current flowing in the constant voltage diode can be increased and the current flowing in the logic circuit in the next stage can be reduced. Reliability can be improved.
[0017]
In the interface device, when a diode is used as the constant voltage element, the barrier height of the anode electrode of the diode is set to the barrier height of the gate electrode of the field effect transistor used in the input unit of the logic device in the next stage. Should be lower.
[0018]
If the barrier height of the constant voltage diode is lowered, the current flowing through the constant voltage diode can be increased without increasing the area of the constant voltage diode, and the current flowing through the logic circuit of the next stage can be reduced. Can be improved. In addition, since it is not necessary to increase the anode electrode of the constant voltage diode, the input interface device can be miniaturized and the cost can be reduced.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 5 is a circuit diagram showing a configuration of the input interface circuit 21 for connecting the Si logic circuit 1 and the GaAs logic circuit 3 according to the embodiment of the present invention. The same parts as those in the configuration of the conventional example are denoted by the same reference numerals, and the description will not be repeated.
[0020]
In this input interface circuit 21, the anode of the constant voltage diode (13) is connected to the output terminal 12 drawn out between the resistors 7 and 8 for voltage division of the source follower type E-FET (corresponding to the conventional input interface circuit 2). The cathode of the constant voltage diode (13) is connected to the ground (GND). Here, a GaAs MESFET is used as the E-FET 6 and a Schottky barrier diode (SBD) 13 is used as the constant voltage diode.
[0021]
Further, the output stage of the Si logic circuit 1 is constituted by CMOS, and the input stage of the GaAs logic circuit 3 is constituted by DCFL. Here, the Si logic circuit 1 and the input interface circuit 21 are separate chips, but the input interface circuit 21 and the GaAs logic circuit 3 are formed in one chip.
[0022]
The input interface circuit 21 is designed for the Si logic circuit 1 driven by 2V, and the source voltage of the E-FET 6 is divided by the resistors 7 and 8 when the output voltage from the Si logic circuit 1 is 2V. If the voltage is set to 0.7 V or more and the rising voltage of the Schottky barrier diode 13 is set to about 0.7 V, the open output voltage of the input interface circuit 21 is the input voltage as shown in FIG. When the voltage Vin is 2 V or higher, the voltage is clamped to the rising voltage (= about 0.7 V) of the Schottky barrier diode 13. Therefore, even when the Si logic circuit 1 driven by 2V is connected to the input interface circuit 21 or when the Si logic circuit 1 driven by 3V is connected to the input interface circuit 21, the input interface circuit 21 changes to the GaAs logic circuit. The voltage applied to 3 is about 0.7 V, and does not increase to about 1 V as in the prior art. Therefore, the input interface circuit 21 can be used for both the 2V-drive Si logic circuit 1 and the 3V-drive Si logic circuit 1, and the input interface circuit 21 can have general versatility.
[0023]
Therefore, if the input interface circuit 21 according to the present invention is designed for the Si logic circuit 1 driven by 2V, it can be applied to the Si logic circuit 1 having a higher driving voltage, so that it differs from the conventional one. For each Si logic circuit 1 having a logic amplitude, it is not necessary to make several types of GaAs ICs that are different only in the input interface circuit 21 from each other, and only one type is required. In the semiconductor industry, this is an advantage that leads to improvement in mass productivity, that is, cost reduction.
[0024]
In this embodiment, the same Schottky metal is used for the anode electrode of the Schottky barrier diode 13 used in the input interface circuit 21 and the gate electrode of the E-FET 10 used in the next stage GaAs logic circuit 3. Is formed by. That is, the barrier height (barrier barrier height) of the anode electrode of the Schottky barrier diode 13 and the barrier height of the gate electrode of the E-FET 10 used in the next stage GaAs logic circuit 3 are made equal. Moreover, the area of the anode electrode of the Schottky barrier diode 13 is made sufficiently larger than the area of the gate electrode of the E-FET 10 of the GaAs logic circuit 3 at the next stage. Therefore, the series resistance of the Schottky barrier diode 13 can be reduced, and if the same applied voltage V, the GaAs at the next stage than the current I flowing through the Schottky barrier diode (SBD) 13 as shown in FIG. The current I flowing into the E-FET 10 of the logic circuit 3 can be reduced to improve the reliability of the logic circuit.
[0025]
(Second Embodiment)
The circuit configuration of the input interface circuit 21 of this embodiment is the same as that of the first embodiment. In this embodiment, the area of the anode electrode of the Schottky barrier diode 13 used in the input interface circuit 21 and the next stage The area of the gate electrode of the E-FET 10 (GaAs MESFET) of the GaAs logic circuit 3 is made substantially equal. Further, the barrier height of the anode electrode of the Schottky barrier diode 13 is set lower than the barrier height of the gate electrode of the E-FET 10 of the GaAs logic circuit 3. For this purpose, the anode electrode of the Schottky barrier diode 13 and the gate electrode of the E-FET 10 may be formed of different Schottky metals, for example.
[0026]
Even in this embodiment, the open output voltage of the input interface circuit 21 is clamped to the rising voltage (= about 0.6 V) of the Schottky barrier diode 13 when the input voltage Vin is 2 V or more, as shown in FIG. The Therefore, even when the Si logic circuit 1 driven by 2V is connected to the input interface circuit 21 or when the Si logic circuit 1 driven by 3V is connected to the input interface circuit 21, the input interface circuit 21 changes to the GaAs logic circuit. The voltage applied to 3 is about 0.6 V, and is almost kept at its logical amplitude. Therefore, this input interface circuit 21 can also be used for both the 2V-driven Si logic circuit 1 and the 3V Si logic circuit 1, and the input interface circuit 21 can have general versatility.
[0027]
Further, in this embodiment, the barrier height of the anode electrode of the Schottky barrier diode 13 is set lower than the barrier height of the gate electrode of the E-FET 10 used in the GaAs logic circuit 3 in the next stage. As described above, at the rising voltage (for example, about 0.6 V) of the Schottky barrier diode 13, the gate diode of the E-FET 10 in the next stage is not completely raised, and the forward resistance is in a very high state. Therefore, even if the anode electrode area of the Schottky barrier diode 13 is not particularly larger than the gate electrode area of the E-FET 10 at the next stage as in the first embodiment, a large current is passed through the Schottky barrier diode 13 to The current I flowing into the E-FET 10 of the stage GaAs logic circuit 3 can be reduced. Therefore, the area of the Schottky barrier diode 13 can be reduced, leading to a reduction in size and cost of the IC.
[0028]
In the above embodiment, the case of a GaAs MESFET and a Schottky barrier diode has been described as an example. However, when another compound semiconductor is used instead of GaAs, a pn junction FET and a pn junction are used instead of the MESFET and the Schottky barrier diode. Even when a diode is used, all can be applied when the source follower type input interface circuit shown in the present invention is used.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a Si logic circuit and a GaAs logic circuit connected by a conventional input interface circuit.
FIG. 2 is a circuit diagram showing the input interface circuit of the above.
FIG. 3 is a diagram showing input / output characteristics of an input interface circuit intended for a 3 V drive Si logic circuit;
FIG. 4 is a diagram showing input / output characteristics of an input interface circuit intended for a Si logic circuit for 2V driving.
FIG. 5 is a circuit diagram showing a Si logic circuit and a GaAs logic circuit connected by an input interface circuit according to an embodiment of the present invention.
FIG. 6 is a diagram showing input / output characteristics of the input interface circuit of the above.
FIG. 7 is a diagram showing voltage-current characteristics of a Schottky barrier diode of the input interface circuit and the voltage-current characteristics of an E-FET (gate diode) of a GaAs logic circuit in the next stage.
FIG. 8 is a diagram showing input / output characteristics of an input interface circuit according to another embodiment of the present invention;
FIG. 9 is a diagram showing voltage-current characteristics of a Schottky barrier diode of the input interface circuit and the voltage-current characteristics of an E-FET (gate diode) of a GaAs logic circuit in the next stage.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Si logic circuit 3 GaAs logic circuit 6 Enhancement type FET (E-FET)
7,8 Resistance 10 E-FET of GaAs logic circuit
11 Input terminal 12 Output terminal 13 Schottky barrier diode 21 Input interface circuit

Claims (3)

An input interface device for connecting the output of one logic circuit to the input of the other logic circuit of two logic circuits having different logic amplitudes,
An input interface device comprising a constant voltage element connected between an output of a source follower type circuit and a ground .   The constant voltage element is a diode, and the anode electrode of the diode is formed of the same material as the gate electrode of the field effect transistor used in the input part of the next stage logic circuit, and the area of the anode electrode is The input interface device according to claim 1, wherein the input interface device is larger than an area of the gate electrode.   The constant voltage element is a diode, and the barrier height of the anode electrode of the diode is lower than the barrier height of the gate electrode of the field effect transistor used in the input part of the logic circuit in the next stage. The input interface device according to claim 1.

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