JP3756411B2 - データハザードを検出するシステム - Google Patents
データハザードを検出するシステム Download PDFInfo
- Publication number
- JP3756411B2 JP3756411B2 JP2001002040A JP2001002040A JP3756411B2 JP 3756411 B2 JP3756411 B2 JP 3756411B2 JP 2001002040 A JP2001002040 A JP 2001002040A JP 2001002040 A JP2001002040 A JP 2001002040A JP 3756411 B2 JP3756411 B2 JP 3756411B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- instruction
- stage
- data
- instructions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/490389 | 2000-01-24 | ||
| US09/490,389 US6604192B1 (en) | 2000-01-24 | 2000-01-24 | System and method for utilizing instruction attributes to detect data hazards |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001209538A JP2001209538A (ja) | 2001-08-03 |
| JP2001209538A5 JP2001209538A5 (enExample) | 2005-06-02 |
| JP3756411B2 true JP3756411B2 (ja) | 2006-03-15 |
Family
ID=23947830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001002040A Expired - Fee Related JP3756411B2 (ja) | 2000-01-24 | 2001-01-10 | データハザードを検出するシステム |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6604192B1 (enExample) |
| JP (1) | JP3756411B2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7555634B1 (en) * | 2004-04-22 | 2009-06-30 | Sun Microsystems, Inc. | Multiple data hazards detection and resolution unit |
| US20060200654A1 (en) * | 2005-03-04 | 2006-09-07 | Dieffenderfer James N | Stop waiting for source operand when conditional instruction will not execute |
| US7454598B2 (en) * | 2005-05-16 | 2008-11-18 | Infineon Technologies Ag | Controlling out of order execution pipelines issue tagging |
| US9710269B2 (en) * | 2006-01-20 | 2017-07-18 | Qualcomm Incorporated | Early conditional selection of an operand |
| US20090055636A1 (en) * | 2007-08-22 | 2009-02-26 | Heisig Stephen J | Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence |
| US8205057B2 (en) * | 2009-06-30 | 2012-06-19 | Texas Instruments Incorporated | Method and system for integrated pipeline write hazard handling using memory attributes |
| US9600280B2 (en) * | 2013-09-24 | 2017-03-21 | Apple Inc. | Hazard check instructions for enhanced predicate vector operations |
| US9928069B2 (en) | 2013-12-20 | 2018-03-27 | Apple Inc. | Predicated vector hazard check instruction |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE32493E (en) * | 1980-05-19 | 1987-09-01 | Hitachi, Ltd. | Data processing unit with pipelined operands |
| US6073231A (en) * | 1993-10-18 | 2000-06-06 | Via-Cyrix, Inc. | Pipelined processor with microcontrol of register translation hardware |
| US5471598A (en) * | 1993-10-18 | 1995-11-28 | Cyrix Corporation | Data dependency detection and handling in a microprocessor with write buffer |
| US5765035A (en) * | 1995-11-20 | 1998-06-09 | Advanced Micro Devices, Inc. | Recorder buffer capable of detecting dependencies between accesses to a pair of caches |
| US5860017A (en) | 1996-06-28 | 1999-01-12 | Intel Corporation | Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction |
| US5859999A (en) | 1996-10-03 | 1999-01-12 | Idea Corporation | System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers |
| US6304955B1 (en) * | 1998-12-30 | 2001-10-16 | Intel Corporation | Method and apparatus for performing latency based hazard detection |
| US6219781B1 (en) * | 1998-12-30 | 2001-04-17 | Intel Corporation | Method and apparatus for performing register hazard detection |
| US6115808A (en) * | 1998-12-30 | 2000-09-05 | Intel Corporation | Method and apparatus for performing predicate hazard detection |
| US6438681B1 (en) * | 2000-01-24 | 2002-08-20 | Hewlett-Packard Company | Detection of data hazards between instructions by decoding register indentifiers in each stage of processing system pipeline and comparing asserted bits in the decoded register indentifiers |
-
2000
- 2000-01-24 US US09/490,389 patent/US6604192B1/en not_active Expired - Fee Related
-
2001
- 2001-01-10 JP JP2001002040A patent/JP3756411B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6604192B1 (en) | 2003-08-05 |
| JP2001209538A (ja) | 2001-08-03 |
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Legal Events
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| A977 | Report on retrieval |
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| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
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| A61 | First payment of annual fees (during grant procedure) |
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| R150 | Certificate of patent or registration of utility model |
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| LAPS | Cancellation because of no payment of annual fees |