JP3737384B2 - LSI automatic design equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LSI automatic design method, and more particularly to an LSI automatic design method for applying a low power design technique in an ASIC (Application Specific IC).
[0002]
[Prior art]
Recently, the power consumption of LSIs has been steadily increasing with the increase in circuit scale due to the miniaturization of processes, and studies on methods for reducing this power consumption have been underway.
[0003]
Further, as represented by the application to portable devices and the like that are remarkably widespread, the future low power technology is a technology most regarded as important in LSI design, and it is expected that further reduction in power will be required.
[0004]
In the current ASIC low-power LSI design method, low-power design is performed by logic synthesis using a power optimization tool such as a power compiler, and power is reduced based on a low-power library. However, with current synthesis tools, when logic synthesis is performed with emphasis on low power consumption, the result of logic synthesis using a library element with low driving capability results in increased delay due to insufficient driving capability due to the influence of wiring load after back-end design. There are many cases where timing errors occur.
[0005]
In such a current low-power design, the reason for inducing timing errors is that the low-power library is preferentially synthesized at the time of logic synthesis, and the timing establishment considering low power and back-end It is considered that there are two types of points that cannot be considered simultaneously. In order to avoid such timing errors, the current situation is that the use of the low power library is stopped for the error path, the high drive library is applied, and the influence of the wiring load due to the buffer insertion is taken. Power synthesis has been returned to timing-oriented synthesis. Further, TAT (Turn Around Time: processing time) is increased due to the establishment of such timing, which also affects TAT of low power design.
[0006]
Against this background, the establishment of a more appropriate low-power LSI design technology with a short TAT and the establishment of a design flow that achieves both timing establishment and low power consumption are indispensable.
[0007]
Referring to FIG. 10 showing a flowchart of a conventional general first LSI automatic design method, this conventional first LSI automatic design method is based on the information on the function design result in the function design step S1. In the logic synthesis step S2, logic synthesis is performed using a low power library F101, which is a library of low power cells with small driving capability, using a power optimization tool such as a power compiler of Synopsys. In the timing verification step S3, the front end timing verification is performed on the synthesis result. For a path in which a timing error has occurred as a result of the determination in the determination step S4, a restriction at the time of logic synthesis (a large driving capability with an emphasis on timing, that is, application of a high power library cell) is provided in the error path weighting step P8. Then, synthesis is performed in the logic synthesis step S2. Steps S2 to P8 are repeated until the timing error converges.
[0008]
Next, when timing convergence is confirmed, layout design using the low-power library F102 is performed in the layout design step S5, and circuit connection information (RC net) F103 considering the wiring load and wiring resistance by the layout is extracted. To do. In this timing verification step S6, the RC network F103 is again checked for back-end timing to check the influence of the timing due to the wiring load. If it is determined in the determination step S7 that there is a timing error, the process returns to the layout design step S5 again or returns to the logic synthesis step S2. When it is determined that there is no timing error, the final power consumption verification is performed in the power verification step P9. If the determination result in the determination step P10 confirms the low power consumption, the design is completed, and the expected low power consumption is obtained. If not, the process returns to the logic synthesis step S2 and layout design step S5 again.
[0009]
In this way, in the conventional first LSI automatic design method, logic synthesis for lower power consumption and logic verification for timing fixing are performed individually, and low power design is performed while repeating error correction in each step. It is a flow to do.
[0010]
As described above, the first conventional LSI automatic design method performs low power design by logic synthesis using a power optimization tool such as a power compiler, but is driven as a result of synthesis by a library cell having a small drive capability. There are many cases where timing errors occur after layout because the capacity is insufficient and the wiring load due to the back-end (later stage) design cannot be driven sufficiently and the delay increases due to the influence.
[0011]
For this reason, conventionally, a method has been adopted in which a portion where timing errors frequently occur is replaced with a library cell having a large driving capability and the delay is reduced to establish timing within a predetermined timing standard. In addition, since these measures are performed by random processing using an automatic tool, there is a problem in that an increase in power more than necessary is caused, and appropriate low power design cannot be performed.
[0012]
Referring to FIG. 11 showing an example of this problem in a graph, this figure is a histogram of the data path delay distribution between flip-flops (F / F) in a macro product. The horizontal axis represents the data path delay value between F / Fs, and the vertical axis represents the number of F / F paths in the macro product. This histogram is a setup timing verification result, and shows a data path delay timing with respect to the F / F clock arrival time. FIG. 11A shows the timing verification result in the front end (previous stage) after synthesis by the low-power library cell having a small driving capability, and FIG. 11B shows the timing verification in the back end after layout with respect to the front end result. Results are shown. From this graph, it can be seen that when the transition from the front end to the back end occurs, a timing error (E portion) occurs due to the influence of the wiring load during actual wiring. Conventionally, it took time to converge this timing error, and also caused an increase in power due to automatic correction by a tool.
[0013]
Even if the optimum correction is made manually, it is difficult to reduce the power in consideration of the influence of delay variation due to the wiring load and the timing depending on the type of the library to be replaced (low power cell or high drive cell). However, it is not realistic in terms of TAT.
[0014]
As another countermeasure for timing convergence, there is a method using a TDL (Timing Drive Layout) tool that performs placement and routing in consideration of timing at the time of layout design in step S6 in FIG. Since only timing prediction can be performed at a temporary wiring load), an error from the actual wiring load occurs. For this reason, particularly when a large number of low power cells are used, there is a problem that a timing error is significantly induced by a redundant wiring or the like, so that it is difficult to apply the TDL to a low power design.
[0015]
In addition, in order to prevent such timing errors, when designing with a certain margin at the time of synthesis, synthesis is performed using a library having a large driving capability as a whole, so as a result, low power consumption is achieved. There arises a problem that an appropriate design cannot be performed.
[0016]
As described above, in low-power design using low-power library cells (libraries with low driving capability), timing error induction due to increased delay is a major problem. There is a problem that a low power design cannot be performed. Similarly, due to the influence of the return processing for establishing these timings, an increase in the design TAT is caused in combination with an increase in circuit scale due to high integration.
[0017]
The common cause of such problems is considered to be the inability to achieve both low power consumption and timing establishment. In other words, as in the current low-power design flow, logic synthesis for low power and logic verification for timing establishment are performed separately, and error correction is repeated at each step. Therefore, it is difficult to realize short TAT, and in the future, a mechanism for improving these design flows will be necessary.
[0018]
Furthermore, paying attention to the timing between F / F after design in the current low-power design flow, the design result is based on the balance with the timing error countermeasure (buffer replacement: drive capability improvement) by using the low-power library at the time of logic synthesis. In FIG. 4, there is a path with a margin in timing. Basically, all F / F paths cannot be critical paths in product data, and at least 40 to 50% of the paths should have sufficient timing. Considering such a situation, it can be said that the current design flow has a problem that an appropriate low power library for reducing power is not used.
[0019]
Referring to FIG. 12A showing a histogram of data path delay distribution between F / F after timing convergence in a macro product, the horizontal axis of this figure shows the data path delay value between F / F. The vertical axis represents the number of F / F paths in the macro product. From the graph, it can be seen that the data path delay is concentrated at 3.5 ns. That is, for a 10 ns clock, there are many paths with a timing margin of about 6.5 ns in terms of setup. That is, it can be seen that there are many paths that have a margin in the delay of the data path portion, with respect to the limit delay time = 10 ns in the 100 MHz clock operation.
[0020]
Therefore, it can be said from this graph that the optimum low-power library cell cannot be applied in the conventional low-power design flow. From these results, if it is possible to use an appropriate low-power library cell (shift the histogram to the right) to minimize the timing margin as shown in FIG. 12B, further reduction in power can be realized. .
[0021]
Next, although the first purpose is not to reduce power consumption, a conventional second LSI automatic design method that aims to reduce the timing margin to the limit is shared by the same components as in FIG. Referring to FIG. 13 with reference characters / numerals similarly shown in the flowchart, this conventional second LSI automatic design method is based on the tool of MAGMA, and information on the function design result in function design step S1. Based on the above, the timing margin optimization step P20 is performed using the Blast Fusion tool to optimize the timing margin.
[0022]
First, in step P21, logic synthesis is performed using a cell having the maximum driving capability, and front end timing verification is performed on the synthesis result in step P22. After timing convergence, the process proceeds to step P23 of the rough arrangement which is the back end. . At the time of the placement and routing process from step P23 to step P26, the timing verification of step P27 is always performed, and the design is performed in consideration of the timing.
[0023]
Further, in the flow of this timing margin optimization step P20, processing for reducing the capacity of the cell having the maximum driving capability used in the front end is also performed so as to reduce the timing margin to the limit. Yes. Thereafter, the layout is verified in steps P31 and P32, and the design is completed.
[0024]
As described above, in this design flow, the layout design is performed with the timing taken into consideration for the logic synthesis result, and the processing for reducing the timing margin to the limit is performed.
[0025]
However, since this conventional second LSI automatic design method can only reduce the timing margin by taking into account only the timing and lowering the cell driving capability, no factor relating to power is taken into consideration. Therefore, the following problems occur.
[0026]
For example, when the wiring load between cells is large, if the cell replacement (decrease in driving capability) is performed only in consideration of timing adjustment, the output waveform becomes dull, leading to an increase in the through current of the next cell, This can lead to an increase in power. In addition, as mentioned earlier, this tool uses the cell with the maximum driving capability in the initial design, that is, the cell with a large layout size, and further, the driving capability to reduce the timing margin during layout. If the cell size of the finally selected layout is small, the cell layout is not shrunk in terms of the LSI layout, and the LSI size is changed. There is also a concern that will increase.
[0027]
Referring to FIG. 14 showing an example of the layout correction result in the conventional second LSI automatic design method, AA1 to AA3 are cells having a large cell size applied at the initial design, and the wiring ( (Solid line). On the other hand, BB1 to BB3 are cells having a small cell size applied after the timing adjustment, the cells AA1 to AA3 are replaced, and the connections shown by dotted lines are additionally made. That is, in terms of layout, only the cells are replaced, and the arrangement between the cells BB is not reduced. In other words, since the cell layout is performed by securing the layout area of the original cell having a large layout size with high driving capability at the time of initial layout, the layout area does not change even if it is replaced with a cell having a small layout size with low driving capability. It is disadvantageous in terms of area.
[0028]
[Problems to be solved by the invention]
In the conventional first LSI automatic design method described above, in the low power design using a low power library cell with a small driving capability, the induction of a timing error due to an increase in delay is a big problem. Since the timing is established by replacing it with a high-power, high-drive capacity library cell, there is a disadvantage in that an unnecessarily high power is required and an appropriate low-power design cannot be performed.
[0029]
Further, due to the influence of the return processing for establishing the timing, there is a drawback that the design TAT increases in combination with the increase in circuit scale due to high integration.
[0030]
In addition, the conventional second LSI automatic design method that optimizes the timing margin can only reduce the timing margin by reducing the cell driving capability in consideration of only the timing. This is not considered, so if the wiring load between cells is large, if the cell replacement is performed so that the driving capability is reduced only by adjusting the timing, the output waveform will become dull. There is a drawback that it may lead to an increase in power.
[0031]
In the initial design, the cell is designed with the maximum driving capability, that is, a cell with a large layout size. If the driving capability is reduced to reduce the timing margin during layout, only the contents of the layout cell are used. Therefore, even if the cell size of the finally selected layout is small, the cell layout is not reduced in the layout of the LSI, and the LSI size increases.
[0032]
An object of the present invention is to provide an LSI automatic design method that eliminates the above-mentioned drawbacks, realizes both timing convergence and low power consumption, and achieves low power consumption with a short TAT.
[0033]
[Means for Solving the Problems]
  The LSI automatic design apparatus according to the present invention performs logic synthesis so as to satisfy a predetermined timing standard from information on a functional design that is an initial design of the LSI, and automatically designs an LSI that performs layout on the result of the logic synthesis. In the device
Logic synthesis means for generating a net list by performing logic synthesis on the functional design information using the first cell having a large driving capability and high power so as to satisfy the timing standard, and using the net list The first wiring resistance and capacitor-equipped circuit connection information and the cell instance coordinate information are respectively stored in the first wiring resistance and capacitor-equipped circuit connection information storage means and the first cell instance coordinate information storage means. Layout execution means for storing the timing information, timing verification is performed on the information stored in the circuit connection information storage means with the first wiring resistance and capacitance, and inter-flip-flop delay information storage means is stored. The timing verification execution means stored in the first cell has a lower driving capability and lower power than the first cell, and the first cell has upper data and a cell. Low power library storage means storing second cells having the same size and different base data including gate widths of transistors constituting the cells, and information stored in the inter-flip-flop delay information storage means Check the timing margin, and if there is delay information between flip-flops with timing margin, the inter-flip-flop path delay information is extracted from the inter-flip-flop delay information, and the cells in the inter-flip-flop path delay information are extracted. Cell selection means for storing a cell as a replacement target cell in the replacement target cell information storage means, and circuit connection information storage with the first wiring resistance and capacitance based on the information stored in the replacement target cell information storage means The first cell in the circuit connection information with the first wiring resistance and capacitance stored in the means Replacing the second cell stored in the low-power library storage means with the second wiring resistance and capacitance, and replacing the replaced circuit information with the second wiring resistance and capacitance with the second wiring resistance and capacitance, respectively. Cell replacement execution means stored in the attached circuit connection information storage means and cell replacement information storage means, information stored in the cell replacement information storage means, and low power stored in the low power cell layout information storage means in advance. Layout correction means for correcting the layout based on the power cell layout information and the information stored in the first cell instance coordinate information storage means.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0045]
The LSI automatic design method of the present embodiment performs logic synthesis using the first cell so as to satisfy a predetermined timing standard based on the result of functional design, which is the initial design of the LSI, and results of this logic synthesis In the LSI automatic design method for executing the first layout as the placement and routing of the first cell after confirming the timing convergence performed so as to satisfy the timing standard for the first net as the generated circuit connection information, Logic synthesis is performed using the first cell having a large driving capability and thus high power with an emphasis on satisfaction of the timing standard, and the first layout is taken into consideration after the first layout is verified. From the first cell and the second net, which has a lower driving power than the cell, and thus the first net is replaced with the second cell having a lower power and the power is reduced. It is characterized in that it has a serial optimization cell replacement processing step of extracting the replacement information to the second cell.
[0046]
As a result, in the result after the timing convergence of the logic circuit designed with an emphasis on satisfying a predetermined timing standard, the circuit is modified so as to reduce the timing margin, and the front-stage and rear-stage flip-flops ( F / F) delay calculation to prevent timing errors and timing convergence and low power by providing appropriate cell replacement by selecting cells that are effective for power reduction during circuit correction It is characterized by realizing a design that achieves both reduction in power consumption and lower power consumption with a shorter TAT than in the past. In this embodiment, the power is reduced by replacing the cell selected at the time of circuit correction with a low-power cell. However, the low-power library used here uses conventional data, layout cell size, terminal position, etc. By making the data the same as the cell and reducing only the gate width (W) size (background data) of the transistor, the TAT of layout correction accompanying circuit correction can be greatly reduced. Furthermore, by having a plurality of variations of these low power cells, it is possible to perform cell replacement for lower power more effectively.
[0047]
Next, the first embodiment of the present invention will be described with reference to FIG. 1 in which the same reference characters / numerals are attached to the same components as in FIG. The LSI automatic design method has a function design step S1 for performing functional design, which is an initial design of an LSI common to the conventional one, and a large driving capability according to the result of the function design step S1, giving priority to satisfaction of the timing standard, and thus high Logic synthesis step S2 for performing logic synthesis using a power cell (hereinafter referred to as a high power cell), and timing verification at the front end for circuit connection information (net) generated as a result of logic synthesis, and delay between F / F The timing verification step S3 for generating the information F1, and the presence / absence of a timing error that is unsatisfactory of the timing standard for the inter-F / F delay information F1 are determined. If the timing convergence is confirmed, the logic synthesis step S2 is performed. If the timing convergence is confirmed, the determination step S4 proceeds to the next layout design step S5, and automatic placement and routing is performed using the net after timing convergence. The layout design step S5 for extracting the RC net F2 in consideration of the wiring resistance and capacitance, and the timing for generating the inter-F / F delay information F3 by performing the back end timing verification based on the RC net F2 extracted in the layout design step S5 In the verification step S6, the presence / absence of a timing error is determined for the inter-F / F delay information F3. If there is a timing error, the process returns to the logic synthesis step S2 or the layout design step S5 to confirm timing convergence. R is a product after LSI design and corresponding to RC net F2 In addition to the determination step S7 for extracting the library of the net F5 and proceeding to the next step, the timing margin value which is a margin for the timing standard of each inter-F / F delay is checked against the inter-F / F delay information F3 ( Margin value check step S8 to be extracted) and whether the margin value extracted in the margin value check step S8 needs to be subjected to a process for reducing power by determining the presence or absence of timing margins between all F / Fs. If there is no timing margin, the design is terminated. If there is a timing margin, the inter-F / F delay information F6 is extracted as it is from the inter-F / F delay information F3, and the optimized cell replacement is performed to perform the power saving process. The margin determination step S9 that proceeds to the processing step S10, and the step that characterizes the present embodiment, the R extracted earlier The C net F4, inter-F / F delay information F6, and cell delay information F5 are used to replace the high power cell with a smaller driving capacity and hence a low power cell (hereinafter referred to as a low power cell) than the above high power cell in consideration of the timing standard. Optimized cell replacement processing step S10 for extracting a low power version new RC net F7 and replacement information F8 for low power cells by modifying the net for power reduction, RC network F4 before low power processing and low power Using the new RC net F7 after processing and the power library (LIB) F9 for each cell, the power consumption extraction step S11 for extracting the power consumption of each net, and the net after the low power processing based on the result of step S11 is low. If it is confirmed that the power has been reduced from the net before the power processing, and it is determined to be OK, the comparison determination step S12 proceeds to the next layout correction step S14, and the comparison is made. If it is determined as NG in step S12, the replacement method for the low power cell is changed, and the replacement order step S13 for returning to the optimized cell replacement processing step S10 and performing the low power processing again is performed. Cell replacement information F8, low power cell layout information F10 obtained in processing step S10, cell instance coordinate information (DEF) F11 which is information of the high power cell before replacement and layout coordinate information extracted during layout design in step S5. Layout correction step S14 for correcting the layout using the layout correction step S15, and layout verification step S15 for verifying the layout after the layout correction step S14.
[0048]
Referring to FIG. 2 showing the details of the optimized cell replacement processing step S10 that characterizes the present embodiment in a flowchart, this optimized cell replacement processing step S10 is an F that can reduce timing margin from the inter-F / F delay information F6. F / F path extraction step S101 for extracting the / F path, and selection of a cell (high power cell) effective for power reduction with respect to the inter-F / F path extracted in the F / F path extraction step S101 Cell selection step S102 to be performed, net modification for power reduction using the RC net F4 and low power cell name information F13, that is, cell replacement that performs cell name replacement and outputs a new RC net F14 and cell replacement information F15 Step S103, new RC net F14, cell delay information F5, and low power cell delay information F12 which is delay information of the low power cell. The delay information re-extraction step S104 for re-extracting the new RC net delay information (SDF) F16 after the cell replacement, the SDFF 16 considering the delay variation due to the cell replacement extracted in the step S104, and the cell replacement extracted in the step S103. The inter-F / F delay calculation step S105 that calculates the new inter-F / F delay using the information F15 and the old inter-F / F delay information F6, and generates the new inter-F / F delay information F17, and the new F / F If the timing margin is determined to be optimal based on the inter-delay information F17 and the timing margin is determined to be the limit (and there is no timing error) in each F / F path, the final cell replacement is performed to reduce power consumption. If the version of the new RC net F7 and cell replacement information F8 are extracted and timing over is confirmed, the RC net correction step S107 is executed. The network is corrected for the new RC net F14 using the optimum margin determination step S106, cell replacement information F15, new F / F delay information F17, and old F / F delay information F6, and the process returns to step S104 again. RC network correction (re-replacement) step S107.
[0049]
The optimized cell replacement processing step S10 is repeated to extract a new RC net F7 and cell replacement information F8, which are low-power circuit connection information.
[0050]
Next, the overall operation of the present embodiment will be described with reference to FIG. 1. In the present embodiment, timing adjustment and power reduction (low power cell replacement) are not performed separately, but both are considered simultaneously. Thus, by selecting an appropriate low power cell, an LSI automatic design method capable of designing a low power LSI with a short TAT is realized.
[0051]
First, based on the function design information in the function design step S1, logic synthesis is performed in a logic synthesis step S2 using a power optimization tool such as a power compiler of Synopsys. However, in the logic synthesis in the present embodiment, unlike prior art, power priority is not weighted more than necessary. That is, in the initial design, logic synthesis is performed with priority given to timing. This eliminates the time and man-hours conventionally required for timing convergence due to the influence of the low-power library, and the processing from the logic synthesis step S2 to the back-end (later stage) timing convergence determination step S7 can be designed in a short TAT. It becomes.
[0052]
In timing verification step S3, timing verification at the front end (previous stage) is performed on the circuit connection information (net) that is the logic synthesis result of logic synthesis step S2, and the inter-F / F delay information F1 that is the timing verification result is obtained. On the other hand, in the determination step S4, it is determined whether or not there is a timing error that does not satisfy the predetermined timing standard. If there is a timing error, the process returns to the logic synthesis step S2, and if the timing convergence is confirmed, the process proceeds to the layout design step S5.
[0053]
In layout design step S5, automatic placement and routing using a TDL (Timing Drive Layout) tool or the like is performed using a net after timing convergence to perform layout in consideration of timing convergence in the back end. Further, after the layout verification, the RC net F2 is extracted in consideration of the wiring resistance and capacitance. Next, in the timing verification step S6, the back-end timing verification is performed based on the RC net F2 extracted in the layout design step S5. In the determination step S7, the inter-F / F delay information which is the timing verification result in the timing verification step S6. The presence / absence of a timing error is determined for F3. If there is a timing error, the process returns to the logic synthesis step S2 or the layout design step S5, and if the timing convergence is confirmed, the library of the RC net F4 which is a product after the LSI design is extracted and the next step is performed. move on.
[0054]
However, as described above, since the synthesis is performed with priority given to the timing at the synthesis of the logic synthesis step S2, the number of backward steps such as frequent occurrence of timing errors due to the influence of the wiring load after layout does not occur so much. That is, the design using the low-power library (low drive capability library) element from the beginning of the design is not performed as in the prior art, thereby realizing a design that suppresses the influence of the output waveform blunting due to the wiring load after the layout. The basic processing flow from step S1 to step S7 is the same as the processing flow of the conventional first LSI automatic design method.
[0055]
Using the design results described above, a process for reducing power described below is performed.
[0056]
As processing for reducing power consumption, an RC net F4 which is a circuit connection information library with timing resistance convergence extracted after layout, and an F / F which is a library of timing verification result summaries after timing convergence. Optimized cell replacement, which is a network correction process for reducing power, that characterizes this embodiment, using three types of libraries: inter-cell delay information F6 and cell delay information F5, which is a library of delay information for each cell. Processing step S10 is performed.
[0057]
Referring again to FIG. 1, first, in the margin value check step S8 and the margin determination step S9, it is determined whether or not there is a timing margin between all the F / Fs from the delay information F3 between the F / Fs that is the timing verification result summary. Then, it is determined whether or not it is necessary to perform processing for reducing power consumption. If there is a path with a margin in timing, the inter-F / F delay information F3 is extracted as it is as the inter-F / F delay information F6, and the process proceeds to the optimization cell replacement processing step S10. Design low power by the mechanism. If the timing margin does not exist in all the F / F paths, the design is finished.
[0058]
In the optimized cell replacement processing step S10, the timing is considered using the three types of information of the RC net F4, the inter-F / F delay information F6, and the cell delay information F5 extracted after the timing verification considering the wiring load. Cell replacement for power reduction is performed, and finally, a new RC net F7 of a low power version and replacement information F8 in which a cell in the RC net is replaced with a low power cell are extracted.
[0059]
Briefly describing the outline of the low power method in the optimized cell replacement processing step S10, first, the timing margin of each path is minimized while calculating the delay of each F / F path with respect to the RC net F4. Replace the cell with a low power library (small driving capability library) cell suitable for the above. However, at the time of cell replacement, there is a mechanism for selecting only cells effective for power reduction, thereby preventing an unexpected increase in power due to cell replacement. Also, at the time of cell replacement, it has a mechanism to calculate each wiring delay and cell delay variation due to cell driving capability change and recalculate the total delay value between F / F. There is no timing error.
[0060]
In this way, the concept of reducing the timing margin as much as possible, and by performing cell replacement optimal for power reduction while performing delay calculation between F / F, the driving capability of each cell can be reduced to the limit. Power reduction can be realized.
[0061]
Next, the processing operation of the optimized cell replacement processing step will be described in detail with reference to FIG. 2. First, from the information of the inter-F / F delay information F6, which is the timing verification result summary after timing convergence, between F / Fs. At the path extraction step S101, information on a path that can reduce the timing margin is extracted, and at the cell selection step S102, a cell is selected so as to minimize the timing margin for each extracted inter-F / F path. Then, a cell effective for power reduction is selected.
[0062]
Here, a cell selection technique effective for power reduction, which is a point of the present embodiment, will be described.
[0063]
An example of an F / F path is an equivalent circuit, and FIG. 3 shows an example of information on intra-cell delay and inter-cell wiring delay for each cell of the inter-F / F path in a tabular form. It is assumed that the information shown in FIG. 3B is information on intra-cell delay and inter-cell wiring delay for each cell of the inter-F / F path composed of cell A and cell B shown in FIG. In that case, when the cell replacement of the portion of the cell A having a large wiring delay is performed to reduce the driving capability, the input waveform of the cell B of the next stage may be extremely dull, and the through current of the cell B of the next stage May increase. Since an increase in the through current leads to an increase in power of the LSI, it is necessary to exclude a cell with a large wiring delay, such as the cell A, from the cell replacement target. That is, when the timing margin is reduced for the purpose of reducing power, it can be said that it is necessary to avoid performing cell replacement for all cells while ignoring the wiring delay.
[0064]
Therefore, at the time of low-power cell replacement in the present embodiment, there is a mechanism for excluding cells with a large wiring delay, and processing for selecting only cells effective for power reduction. For example, in the example of FIG. 3, only the cells other than the cell A are selected as replacement targets.
[0065]
Referring to FIG. 4 showing the details of the processing contents of this cell selection step S102, first, a cell with a predetermined wiring delay (high power cell) is set for the inter-F / F path delay information F21 capable of reducing the timing margin. For example, whether or not there is a cell whose wiring delay is 0.2 ns or less is checked in the determination step S1021, and if it exists, the cell is selected as a replacement target in the replacement cell selection step S1022. If the corresponding cell has a wiring delay of 0.2 ns or more, the process proceeds to the replacement target exclusion step S1023, and the corresponding cell is excluded from the replacement target. The processes from the determination step S1021 to the replacement target exclusion step S1023 are repeated for the inter-F / F path that can reduce the timing margin, and finally the replacement cell information F22 that can be replaced is extracted. In addition, regarding the wiring delay value to be replaced with a cell, it is possible to prevent an increase in not only power but also a delay value by providing an appropriate wiring delay limit value in advance (set in step S1021). .
[0066]
In the cell selection step S102, attention is paid to the wiring delay. As another cell selection method effective for power reduction, there is a restriction on the in-cell delay and the cell delay is small (power consumption). It is also effective to select and replace a cell with a higher priority). Furthermore, since it is expected that the path with a small number of cell stages in the F / F path has a margin in timing, the timing margin is reduced by excessive cell replacement (through the next stage by lowering the driving capacity more than necessary). For the purpose of preventing an increase in current), a technique of deliberately removing F / F paths having a predetermined number of cell stages or less from cell replacement targets is also effective.
[0067]
Returning to the description of the flow in FIG. 2, cell replacement processing of the RC net is performed in the cell replacement step S103 for the cells selected by the above-described method and effective for power reduction.
[0068]
In step S103, the RC network F4, the low power cell name information F13, and the cell information selected in step S102 are used to perform net correction for power reduction, that is, cell replacement, and the new RC net F14 and cell replacement information F15. Is output. At the time of this cell replacement, replacement is performed by selecting a low power cell that is one rank lower than the drive capability of the replacement target cell from the low power cell name information F13. The drive capability of the replacement target cell can be easily determined by adding a unique character such as X1, X2, or X3 indicating the drive capability rank at the end of the cell name used for the initial design in advance. is there. Here, one rank of drive capability is determined by one step when the W size is increased in order from a smaller one in a predetermined step (step) for convenience of explanation because the drive capability is determined by the gate width W of the transistor. . For example, it is assumed that the driving capability is reduced by one rank in the order of X1> X2> X3. That is, if the rank of the drive capability of the replacement target cell is X1 (hereinafter referred to as X1 capability), the replacement cell lowered by one rank has X2 capability.
[0069]
It is also possible to determine the driving capability based on the load impedance added to the output, the maximum output load capacity, and the like. The reason why the driving capability is reduced by one rank at the time of replacement is to prevent the output waveform from becoming dull due to the influence of the wiring load due to an excessive reduction in driving capability and inducing a through current of the next cell.
[0070]
Note that the low power library (low driving capability library) composed of the low power cell delay information and the low power cell name information F13 used in the present embodiment is a footprint cell library (FPLIB) that has been conventionally used for timing adjustment. For example, the replacement cell having the X2 capability is identical to the replacement target cell having the X1 capability in that the ground data such as wiring and the layout have the same cell size, and only the base data such as the transistor W size is different. It is a (small) library. Therefore, both the circuit and the layout have the advantage that they can be corrected only by replacing data (replacement of the logic name and re-arrangement and wiring are not required even if the cell name in the circuit is replaced). That is, by using this FPLIB for low power technology, simple circuit change (cell replacement) and layout correction are possible.
[0071]
Referring to FIG. 5 showing a layout example of the low power library (FPLIB), an inverter 51 (an equivalent circuit is shown in FIG. 5C) is a replacement target cell having a large driving capability with the W size of the transistor shown in FIG. In contrast, the inverter 52 (equivalent circuit) is a replacement cell having a small driving capability of W2 which is smaller than W1 only in the W size of the transistor and the layout cell size is the same as the layout data such as the wiring shown in FIG. Includes FIG. 5 (D)). Therefore, the power consumption can be reduced by replacing the inverter 51 with the inverter 52.
[0072]
Next, returning to the description of FIG. 2, in the delay information re-extraction step S104, the new RC net F14 that has undergone cell replacement using the new RC net F14, the cell delay information F5, and the low-power cell delay information F12. Delay information (SDF) F16 is re-extracted. A delay calculation step between F / Fs using the new delay information SDFF16 in consideration of the delay variation due to the cell replacement extracted in this way, the cell replacement information F15 extracted in the cell replacement step S103, and the old inter-F / F delay information F6. In S105, a new inter-F / F delay is calculated. Through the above processing, the new inter-F / F delay information F17 after the low power cell replacement considering the actual wiring resistance (R) and the actual wiring capacity (C) can be extracted, and the determination of the timing error considering the actual wiring can be performed. It becomes possible.
[0073]
Referring to FIG. 6 showing an example of recalculation of the inter-F / F delay in the inter-F / F delay calculation step S105, the delay of the new RC net that has undergone cell replacement with respect to inter-F / F delay information F6 before cell replacement. The result of recalculating the inter-F / F delay using each instance of information and the SDFF 16 which is delay value information becomes the new inter-F / F delay information F17 after cell replacement.
[0074]
In this example, the numerical values of the INTERCON and IOPATH terms of the SDFF 16 are substituted into the INTERCON and IOPATH terms (parts indicated by A) of the new inter-F / F delay information F17 by the replacement process with the low power cell, and F As a result, the value of the timing margin B is changed from 2.862 ns in the inter-F / F delay information F6 to 0. 0 in the new inter-F / F delay information F17. It can be confirmed that the time is reduced to 094 ns (driving capacity reduction → power reduction).
[0075]
Returning to FIG. 2 again, in the determination step S106, it is determined whether or not the timing margin is optimum based on the new inter-F / F delay information F17. If it is determined that there is no error, the final new RC net F7 and cell replacement information F8 that have undergone cell replacement for power reduction are extracted. If timing over is confirmed, the cell replacement information F15, the new inter-F / F delay information F17, and the old inter-F / F delay information F6 are used for the new RC net F14 in the RC net modification step S107. The correction is made and the process returns to the delay information re-extraction step S104 again.
[0076]
In the RC net correction step S107, for example, based on the delay value that is over timing, a process for reducing the over delay value by performing reverse calculation is performed. Specifically, the network is corrected by determining which cell should be restored from the new F / F delay information F17, cell replacement information F15, and old F / F delay information F6. As a result, only the cells corresponding to the over timing can be replaced, so that it is not necessary to restore the low power cells more than necessary. When TAT is emphasized, the top three cells having the largest cell delay among the F / F paths with timing errors are selected using the new inter-F / F delay information F17 and the cell replacement information F15, and are uniform. It is possible to converge timing to a short TAT by correcting the net.
[0077]
The above is the optimized cell replacement processing step S10 that characterizes this embodiment. This optimized cell replacement processing step S10 is repeated, and finally, the new RC net F7 and the replacement information F8 to the low power cell, which are low power version circuit connection information without timing errors, are extracted.
[0078]
In other words, the timing adjustment and the low power (low power cell replacement) can be considered at the same time by including the processing of this optimized cell replacement processing step S10.
[0079]
Finally, referring again to the overall flow of FIG. 1, the processing after the power consumption extraction step S11 will be described. First, at the power consumption extraction step S11, the RC net F4 before the low power processing and the optimized cell replacement processing step S10 are performed. Then, using the new RC net F7 and the cell unit power library F9 after low power processing, each power consumption is extracted before and after power reduction. Thereafter, in comparison determination step S12, it is confirmed based on the result of power consumption extraction step S11 that the power after the low power processing is reduced compared to the net before the low power processing. If it is determined as NG in the comparison determination step S12, the process proceeds to the replacement order change step S13, the replacement method is changed to the low power cell, the limit value of the wiring delay to be replaced is changed, and the optimization is performed again. The power replacement process of the cell replacement process step S10 is performed. If it is determined OK in the comparison determination step S12, the process proceeds to the layout correction step S14, and is extracted at the time of layout design in the cell replacement information F8, the low power cell layout information F10 obtained in the optimized cell replacement processing step S10, and the layout design step S5. The layout is corrected using DEF11 which is the information of the cell instance and the layout coordinates.
[0080]
As described above, in this design flow, since FPLIB is used as the low-power library, the layout correction is only a simple replacement work and can be corrected with a short TAT. Specifically, the layout coordinates after the cell replacement are specified from the instance information described in the cell replacement information F8 and the instance and layout coordinate information described in DEF11, and the cell replacement processing of the specified coordinates is performed. Automatically by the shell. Alternatively, the corresponding cell name in DEF11 may be converted based on the instance information described in the cell replacement information F8, and the layout data may be re-extracted from DEF11 again.
[0081]
Thereafter, in layout verification step S15, layout verification, crosstalk verification, and the like are performed, and the LSI design is completed. Note that in the cell replacement process of the optimized cell replacement process step S10, the timing calculation taking into account the wiring resistance and capacitance of the layout after replacement is performed in advance, so that the timing error is regenerated by this layout correction. (In this layout correction method, only cell replacement is performed, and the wiring pattern and the like are not changed.)
[0082]
With the above mechanism, appropriate low power design can be performed while simultaneously considering timing adjustment and low power (low power cell replacement), and a low TAT and low power LSI can be designed.
[0083]
The LSI automatic design method according to the present embodiment induces a timing error by having an optimized cell replacement processing step which is a mechanism for replacing only cells effective for power reduction with a low power library in consideration of timing. Low power design is possible without any problems.
[0084]
For example, in the case where the present embodiment is applied to a macro product designed by the first conventional low power technology, the design method of the present embodiment is used for the power consumption of 53.7 mW of the macro product according to the conventional technology. The power consumption of macro products with the same functional performance was 46.4 mW, confirming the effect of reducing power consumption by approximately 13%.
[0085]
Similarly, the power reduction effect of the present embodiment over the second conventional low power technology is about 3% power reduction.
[0086]
In addition, by using the footprint library, simple circuit change and layout conversion are possible by changing the cell name (cell replacement), and TAT due to re-synthesis and rearrangement wiring does not occur. It becomes feasible.
[0087]
Conventionally, synthesis using a low power library has been difficult due to problems such as timing error induction, but in this embodiment, the low power library can be effectively used after synthesis.
[0088]
In addition, there has been a concern about the increase in design TAT due to the deterioration of timing convergence due to the conventional low power consumption, but this embodiment makes it possible to design considering both timing convergence considering actual wiring load and low power consumption. Therefore, the design TAT can be improved.
[0089]
Further, the timing margin can be easily reduced without distinguishing between the critical path and the other paths, and low power can be realized.
[0090]
Next, the details of the optimized cell replacement processing step S10A that characterizes the second embodiment of the present invention are shown in the same flow chart with the same reference characters / numbers attached to the same components as in FIG. , The difference between the optimized cell replacement processing step S10A of the present embodiment shown in this figure and the optimized cell replacement processing step S10 of the first embodiment described above is that the cell for reducing power consumption is shown in FIG. In addition to the low-power cell delay information F12 and the low-power cell name information F13, which are low-power libraries used for the replacement, in addition to the low-power cell delay information F12 and the low-power cell name information F13, The low-power cell delay information F12A and the low-power cell name information F13A are set so that the gate width W of the stage transistor is the same size as the replacement target cell before cell replacement.
[0091]
In the first embodiment, when performing cell name replacement for lower power consumption, for example, all the base data such as the W size of the transistor is set to the minimum size as a replacement cell for the X1 capability cell to be replaced. A low power library (hereinafter referred to as the minimum size library) was used. For this reason, the library was able to demonstrate sufficient effects by cell replacement for the purpose of reducing power consumption. However, the cell load wiring state at the time of net correction, that is, the cell delay value was not taken into consideration. When the replacement is performed, the output waveform becomes dull due to the influence of the wiring load due to an excessive decrease in driving capability, and there is a problem that a through current of the next cell is induced. Therefore, the first embodiment has a mechanism for excluding cells with a large wiring delay at the time of low-power cell replacement, and performs processing for replacing only cells effective for power reduction. However, in the case of the first embodiment, the cell replacement cannot be performed for all cells ignoring the wiring delay, and the power reduction cannot be performed to the limit.
[0092]
In this embodiment, as a low power library used at the time of cell replacement, in addition to the low power library used in the first embodiment, W of the final stage transistor Q1 in the low power cell as shown in FIG. By setting W1 of the same size as W of all the transistors in the replacement target cell (high power cell) before replacement, and having a low power library in which the W size is reduced only for other transistors, wiring delays are ignored when replacing cells. Cell replacement for all cells.
[0093]
If the W size of the final stage transistor is equal to the size of the replacement target cell, the output waveform will not become dull after the cell replacement due to the influence of the wiring load, and the through current of the next stage will not increase. Therefore, cell replacement for reducing power can be performed for all cells in the net, and the effect of reducing power consumption to the limit as compared with the first embodiment can be obtained.
[0094]
Note that the low-power library used in this embodiment is the same FPLIB as in the first embodiment, and the upper cell data such as wiring and the cell size of the layout are the same as those of the conventional cell, so that the circuit Both layouts can be modified simply by replacing data.
[0095]
Furthermore, by preparing such a low power library for each variety of conventional cell driving capabilities, it is possible to efficiently perform cell replacement for lowering power, and the effect of further reducing power can be obtained.
[0096]
This embodiment is effective in the case where further reduction in power is required even if the number of low-power libraries increases to some extent as the process evolves in the future.
[0097]
The entire design flow using the optimized cell replacement processing step S10A of the present embodiment is the same as that of the first embodiment shown in FIG.
[0098]
Next, details of the optimized cell replacement processing step S10B that characterizes the third embodiment of the present invention are shown in the same flow chart with the same reference characters / numbers attached to the same components as in FIG. , The difference between the optimized cell replacement processing step S10B of the present embodiment shown in this figure and the optimized cell replacement processing step S10 of the first embodiment described above is the F / F considering the timing. In addition to the inter-step delay calculation processing step S105, there is a power fluctuation value calculation step S108 for calculating a power fluctuation value in consideration of power increase / decrease due to cell replacement.
[0099]
In the first embodiment, when performing cell name replacement for reducing power, each wiring delay and cell delay variation due to a change in cell driving capability is extracted, and further, the total delay between F / Fs is extracted. Recalculated values to prevent unexpected timing errors due to cell replacement. The reason for the timing is that the purpose is to check the fluctuation of the cell delay due to the cell replacement, and at the same time, to reduce the timing margin to the limit and to realize the power reduction as the propagation. That is, it can be said that only the timing of the path between the F / Fs has been taken into account in the power consumption reduction method by reducing the timing margin, which is the point of the present invention. Accordingly, in the flow of the optimized cell replacement processing step S10, the content is focused on the timing, and the check regarding the power consumption is only performed as the final check after the process of reducing the power consumption.
[0100]
On the other hand, in the present embodiment, in addition to performing the delay calculation between F / Fs considering the timing at the time of cell replacement, the power fluctuation value calculating step S108 considering the power increase / decrease due to the cell replacement is performed, and the viewpoint of power consumption But I try to check at the same time.
[0101]
Actually, in the power fluctuation value calculation step S108, cell replacement information F15 extracted at the time of cell replacement in the cell replacement step S103 of the optimized cell replacement processing step S10B, and cell unit power information F18 which is power information for each cell are obtained. Using this, the fluctuation of the power in the cell due to the cell replacement is calculated, and the power increase / decrease value F19, which is the power increase / decrease value data for each F / F path, is extracted. In determination step S109, the power increase / decrease value F19 is used to determine whether or not the total power value of the F / F path after cell replacement has decreased. As a result, if the power consumption has increased, the net correction is performed in the RC net correction step S107 as in the first embodiment. If the power consumption is reduced and there is no timing error even in the timing determination at the determination step S106, the low-power version of the new RC net information F7 and the replacement information F8 for the low-power cell are obtained as in the first embodiment. Extract.
[0102]
Other processes are the same as those in the optimized cell replacement processing step S10 of the first embodiment shown in FIG.
[0103]
By providing the above processing, it becomes possible to check the cell delay variation and the intra-cell power variation at the same time when replacing with a low power cell, and check the power reduction effect at the final stage of the design flow. The low power design can be performed more efficiently than the first embodiment, and the effect of reducing the return TAT when the power is increased by cell replacement can be obtained.
[0104]
The entire design flow using the optimized cell replacement processing step S10B of this embodiment is the same as that of the first embodiment shown in FIG.
[0105]
【The invention's effect】
As described above, according to the LSI automatic design method of the present invention, logic synthesis is performed using the first cell having a large driving capability and high power with an emphasis on satisfaction of the timing standard, and the first layout. The second net and the first cell reduced in power by correcting the first net to be replaced with the second cell having a smaller driving capability and thus lower power than the first cell while considering the timing standard after the verification of By having an optimized cell replacement processing step for extracting replacement information from the first cell to the second cell, there is an effect that a low power design is possible without inducing a timing error.
[0106]
In addition, by using the footprint library, simple circuit change and layout conversion are possible by changing the cell name (cell replacement), and TAT due to re-synthesis and rearrangement wiring does not occur. There is an effect that it becomes feasible.
[0107]
Conventionally, synthesis using a low power library has been difficult due to problems such as timing error induction, but in this embodiment, there is an effect that the low power library can be effectively used after synthesis.
[0108]
In addition, there has been a concern about the increase in design TAT due to the deterioration of timing convergence due to the conventional low power consumption, but this embodiment makes it possible to design considering both timing convergence considering actual wiring load and low power consumption. Therefore, there is an effect that the design TAT can be improved.
[0109]
Furthermore, the timing margin can be easily reduced without distinguishing between the critical path and the other paths, and there is an effect that low power can be realized.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a first embodiment of an LSI automatic design method according to the present invention;
FIG. 2 is a flowchart showing details of an optimal cell replacement processing step in FIG. 1;
FIG. 3 is an explanatory diagram showing an example of an inter-F / F path in an equivalent circuit, and an example of information on intra-cell delay and inter-cell wiring delay for each cell of the inter-F / F path in a tabular format. .
4 is a flowchart showing details of a cell selection step in FIG. 2;
5 is a layout diagram showing an example of the layout of the low power library of FIG. 2. FIG.
6 is an explanatory diagram showing an example of recalculation of the inter-F / F delay in the inter-F / F delay calculation step of FIG. 2. FIG.
FIG. 7 is a flowchart showing details of an optimum cell replacement processing step that characterizes the second embodiment of the LSI automatic design method of the present invention;
8 is a layout diagram showing an example of the layout of the low-power library of FIG. 7. FIG.
FIG. 9 is a flowchart showing details of an optimum cell replacement processing step characterizing the third embodiment of the LSI automatic design method of the present invention;
FIG. 10 is a flowchart showing an example of a conventional first LSI automatic design method;
FIG. 11 is a graph showing a first example of a problem in a conventional first LSI automatic design method;
FIG. 12 is a graph showing a second example of a problem in the conventional first LSI automatic design method;
FIG. 13 is a flowchart showing an example of a conventional second LSI automatic design method;
FIG. 14 is a layout diagram showing an example of a problem in a conventional second LSI automatic design method;
[Explanation of symbols]
51, 52 Inverter
F1, F3, F6 F / F delay information
F2, F4, F103 RC net
F5 cell delay information
F7, F14 New RC Net
F8 replacement information
F9 Power Library (LIB)
F10 Low power cell layout information
F11 DEF
F12, F12A Low power cell delay information
F13, F13A Low power cell name information
F15 Cell replacement information
F16 SDF
F17 New F / F delay information
F18 Cell unit power information
F19 Electric power increase / decrease value
F21 F / F path delay information
F22 Replacement cell information
F101, F102 Low power library
Q1 transistor

Claims (5)

In an LSI automatic design apparatus that performs logic synthesis so as to satisfy a predetermined timing standard from information on functional design that is an initial design of LSI, and executes layout on the result of logic synthesis,
Logic synthesis means for generating a netlist by performing logic synthesis on the functional design information using the first cell having a large driving capability so as to satisfy the timing standard;
The placement and routing process is performed using the net list, and the first wiring resistance and capacitor-equipped circuit connection information and cell instance coordinate information are respectively stored in the first wiring resistance and capacitor-equipped circuit connection information storage means and the first cell instance. Layout execution means for storing in the coordinate information storage means;
Timing verification execution means for performing timing verification on information stored in the circuit connection information storage means with the first wiring resistance and capacitance, and storing delay information between flip-flops in the delay information storage means between flip-flops; ,
The second cell has a smaller driving capability than the first cell, and the first cell has the same cell size as that of the first cell, but stores a second cell having different base data including the gate width of the transistors constituting the cell. Low power library storage means,
The timing margin is checked for the information stored in the inter-flip flop delay information storage means, and if there is inter-flip flop delay information with a timing margin, the inter-flip flop path is determined from the inter-flip flop delay information. Cell selection means for extracting delay information and storing cells in the inter-flip-flop path delay information as replacement target cells in replacement target cell information storage means;
Based on the information stored in the replacement target cell information storage means, the first wiring resistance and capacity-added circuit connection information stored in the first wiring resistance and capacity-added circuit connection information storage means The first cell is replaced with the second cell stored in the low-power library storage means, and the replaced second wiring resistance and capacitor-attached circuit connection information and the replaced cell information are respectively stored in the second cell. Cell replacement execution means for storing the circuit connection information storage means and the cell replacement information storage means with wiring resistance and capacitance of
Information stored in the cell replacement information storage means, low power cell layout information stored in advance in the low power cell layout information storage means, and information stored in the first cell instance coordinate information storage means An LSI automatic design apparatus, comprising: a layout correction means for correcting the layout based on Delay calculation is performed on the second wiring resistance and capacitor-attached circuit connection information stored in the second wiring resistance and capacitor-attached circuit connection information storage means, and delay information between flip-flops is obtained as a result of delay recalculation. A delay recalculation means for storing in the storage means;
If there is a timing error in the information stored in the delay recalculation result storage means, a cell among the cells in the inter-flip-flop path having the timing error in the circuit connection information with the second wiring resistance and capacitance The wiring connection resistance and capacity-equipped circuit connection information correcting means for returning a cell having a large delay to the cell before replacement based on information stored in the cell replacement information storing means is further provided. The LSI automatic design apparatus described. The cell selection means checks the timing margin for the information stored in the inter-flip-flop delay information storage means, and if there is inter-flip-flop delay information with a timing margin, the inter-flip-flop delay Inter-flip-flop path delay information is extracted from the information, and a cell whose wiring delay value is equal to or smaller than a predetermined value is stored in the replacement-target cell information storage means from among the cells in the inter-flip-flop path delay information. The LSI automatic design apparatus according to claim 1 or 2, wherein The cell selection means checks the timing margin for the information stored in the inter-flip-flop delay information storage means, and if there is inter-flip-flop delay information having a timing margin, the inter-flip-flop delay When inter-flip-flop path delay information is extracted from the information, and the number of cells in the inter-flip-flop path delay information is equal to or greater than a predetermined value, the cell in the inter-flip-flop path delay information is used as a replacement target cell. 2. The information is stored in a replacement target cell information storage means. Or the LSI automatic design apparatus described in 2. The cell selection means checks the timing margin for the information stored in the inter-flip-flop delay information storage means, and if there is inter-flip-flop delay information having a timing margin, the inter-flip-flop delay Inter-flip-flop path delay information is extracted from the information, and a cell whose cell delay value is equal to or less than a predetermined value is stored in the replacement-target cell information storage means from among the cells in the inter-flip-flop path delay information. The LSI automatic design apparatus according to claim 1 or 2, wherein

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