JP3733627B2 - Digital signal arithmetic unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital signal arithmetic apparatus capable of reducing the circuit scale without reducing the arithmetic accuracy in the product-sum operation of digitized pixel data or audio data.
[0002]
[Prior art]
Conventionally, in an apparatus that performs a product-sum operation on digitized pixel data or audio data, the accumulator, adder, and peripheral elements are all worst-cased (when the word length is the longest) in order not to reduce the calculation accuracy. Since the number of bits can be handled, the circuit scale tends to increase as the number of taps increases.
[0003]
FIG. 4 shows a block diagram of a coefficient time-varying product-sum operation circuit connected to such a conventional cascade. Pixel data digitized to 8 bits is supplied from an input terminal 41, and the pixel data is supplied to an n-tap blocking circuit 42. In the n-tap blocking circuit 42, the input pixel data is blocked according to the tap of the filter operation. The blocked signal is supplied to the address signal generation circuit 43 and the register 45.
[0004]
In the address signal generating circuit 43 generates an address signal corresponding to the pixels included in the supply block, the address signals are supplied to the prediction coefficient memory circuit 44 _1. Prediction coefficient memory circuit 44 ₁ is comprised of registers 51 and 54, the address decoder circuit 52 and the memory cell 53. The address signal from the address signal generation circuit 43 is supplied to the register 51 and held. Holding address signal, based on the system clock of the device, supplied from the register 51 to the prediction coefficient memory circuit 44 ₂ and the address decoder circuit 52.
[0005]
As described above, the address signal is supplied to the prediction coefficient memory circuit 44 _n based on the system clock, and the following processing is performed in the prediction coefficient memory circuit. The address decoder circuit 52 converts an address signal supplied so as to correspond to the memory cell 53. In the address decoder circuit 52, the converted address signal is supplied to the memory cell 53, and the corresponding prediction coefficient is read out. Prediction coefficients read out from the memory cell 53 via the register 54, it is supplied to the product-sum operation circuit 47 _1.
[0006]
The product-sum operation circuit 47 ₁ includes an integrator 55, registers 56 and 58, and an adder 57. The product-sum operation circuit 47 ₁ is supplied with pixel data that has been blocked from the register 45 and 8-tap data consisting of 25 bits and a prediction coefficient from the rounding processing circuit 46. The supplied 8-bit pixel data and 10-bit prediction coefficient are integrated in the integrator 55 and supplied to the adder 57 via the register 56 as an 18-bit integration result. The adder 57 is a result of integration and data from rounding circuit 46 multiplier 55 adder is supplied to the product-sum operation circuit 47 ₂ via the register 58.
[0007]
Thus, similar processing to the product-sum operation circuit 47 _n is performed, the output from the product-sum operation circuit 47 _n is supplied to the limiter circuit 48. In the limiter circuit 48, the supplied 25-bit data is limited to 8 bits. The circuit shown in FIG. 4 has a sufficient width (25 bits) so that overflow or underflow does not occur in the bit width direction, in particular, in order not to reduce the calculation accuracy in the middle.
[0008]
Here, as an example of simple filtering in an image on the condition that the prediction coefficient is time-varying, there is, for example, sampling rate conversion, which converts a data sequence using a 4 fsc clock to a data sequence using a 3 fsc clock. Assuming that In this case, as shown in FIG. 5, pixel data between 4 fsc data series must be calculated by a filter. Therefore, three types of filter coefficients (B0, B1, B2) need to be prepared in advance according to the pixel position, and in order to convert to a 3 fsc data series, it is necessary to switch these according to the timing. is there.
[0009]
As described above, when the sampling rate conversion is performed by the pipeline method as shown in FIG. 4, the n-tap blocking circuit 42 can be deleted, and the input pixel data is sequentially supplied to each product-sum operation circuit 47 _1. It is sufficient that it is supplied to ˜47 _n . The address signal onset raw circuit 43, an address signal corresponding to a pixel position is generated as described above, it is supplied via sequentially latched to each prediction coefficient memory circuit 44 ₁ ~ 44 _n. In each of the prediction coefficient memory circuits 44 _{1 to} 44 _n , a corresponding portion of the memory cell 53 is selected by the address decoder circuit 52, and a prediction coefficient is read from the memory cell 53 and supplied to each of the product-sum operation circuits 47 _{1 to} 47 _n . Is done. In the product-sum operation circuits 47 _{1 to} 47 _n , the product of the sequentially supplied pixel data and the prediction coefficient is calculated and added to the results of the previous product-sum operation circuits 47 _{1 to} 47 _n−1 . As described above, the result of the product for each tap is sequentially added, and finally, the limiter circuit 48 outputs the result limited to 8 bits.
[0010]
[Problems to be solved by the invention]
However, the circuit scale is considerably large because the number of bits for calculation (25 bits) is too large and the address decoder circuit of the prediction coefficient memory circuit is individual due to the adverse effect of pipeline processing. There was a problem.
[0011]
Therefore, an object of the present invention is to make it possible to increase the use efficiency of memory cells by parallelizing the pipeline processing of the prediction coefficient memory circuit, thereby reducing the scale of the entire circuit. It is to provide an arithmetic device.
[0012]
[Means for Solving the Problems]
According to the first aspect of the present invention, in the digital signal arithmetic unit for multiplying and summing digital signals, n types of predictions are made from the memory in accordance with address signals corresponding to n digital signals extracted from the input digital signals. and prediction coefficient reading means to read out coefficients, and prediction coefficients for n type read, and n digital signals extracted from the input digital signal are respectively supplied, n taps product-sum operation is performed Product-sum operation means and limiter means for limiting the data on which the product-sum operation has been performed. The product-sum operation means integrates at least n types of prediction coefficients and n digital signals, respectively. n accumulators, a first hierarchy adder that adds at least a part of the accumulation results of the n accumulators , and clips and outputs the addition results ; A second layer adder that adds at least a part of the addition result by the adder, clips and outputs the addition result, and a register provided between the first and second layer adders This is a digital signal arithmetic device characterized by being configured as described above.
[0014]
Considering that the input pixel data is 8 bits and the final result of the filter operation is 8 bits, it is not necessary to leave a sufficient number of bits so far. Can be deleted.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, a block diagram of an embodiment of a digital signal arithmetic unit is shown in FIG. Pixel data digitized to 8 bits is supplied from an input terminal indicated by 1, and the pixel data is supplied to an n-tap blocking circuit 2. In the n-tap blocking circuit 2, the input pixel data is blocked corresponding to n-tap of the filter operation. That is, in this n-tap blocking circuit 2, blocking is performed for every n pixels, and each of the blocked pixels is supplied to _n product-sum operation circuits (MPY) 9 _{1 to} 9 _n and addresses The signal is supplied to the signal generation circuit 3.
[0016]
The address signal generation circuit 3 generates an address signal corresponding to a pixel included in the supplied block, and the address signal is supplied to the prediction coefficient memory circuit 4. The prediction coefficient memory circuit 4 includes registers 5 and 8 ₁ to 8 _n , an address decoder circuit 6 and a memory cell 7. The address signal from the address signal generation circuit 3 is supplied to the register 5 and held. The held address signal is supplied from the register 5 to the address decoder circuit 6 based on the system clock of this apparatus.
[0017]
The address decoder circuit 6 converts an address signal supplied so as to correspond to the memory cell 7. In the address decoder circuit 6, the converted address signal is supplied to the memory cell 7, and the prediction coefficient (CM) corresponding to each of the subsequent product-sum operation circuits 9 _{1 to} 9 _n is read. The read prediction coefficient consists of 10 bits and is supplied from the memory cell 7 to the product-sum operation circuits 9 _{1 to} 9 _n via the registers 8 ₁ to 8 _n .
[0018]
The product-sum operation circuit 9 ₁ includes registers 10 and 12 and an integrator 11. As described above, the 8-bit pixel data supplied from the n-tap blocking circuit 2 is supplied to the register 10. The 8-bit pixel data and the 10-bit prediction coefficient are integrated in the integrator 11. The multiplication result as 18-bit data, via the register 12, is supplied to the adder 13 as an output of the product-sum operation circuit 9 _1. The product-sum operation circuits 9 _{2 to} 9 _n perform the same processing as the product-sum operation circuit 9 _1, and each product-sum operation circuit 9 _{2 to} 9 _n outputs 18-bit data to the corresponding adder. .
[0019]
That is, the adder 13 is supplied with 18-bit data from the product-sum operation circuits 9 ₁ and 9 ₂ . Then, the addition result is supplied to the adder 15 as the next layer through the register 14 without increasing the bit width by truncating the lower one bit, that is, as 18-bit data. In the adder 15, the sum of the product-sum operation circuit 9 ₄ (not shown) and product-sum operation circuit 9 ₃ supplied via the register 17, the addition of the addition result supplied via the register 14 is performed . The addition result is output to the next layer as 18-bit data by truncating the lower 1 bit as in the adder 13.
[0020]
Similarly, the adder 19 adds the output of the product _- sum operation circuit 9 _{n-1 (} not shown) and the output of the product-sum operation circuit 9 _n . The addition result is output to the next hierarchy through the register 20. In this manner, the adder 21 in the final hierarchy adds two 18-bit data. Similarly to the adder described above, the addition result of the adder 21 is supplied to the limiter circuit 23 via the register 22 as 18-bit data by truncating the lower 1 bit. In the limiter circuit 23, the supplied 18-bit data is limited to 8-bit data and transmitted from the output terminal 24.
[0021]
FIG. 2 shows the above-described product-sum operation circuit as an example of 25 taps. Further, in FIG. 2, bits are reduced more actively in the middle layer than in the above embodiment. This example is to be added in 25 to become a tap, from the inability to clean hierarchy, near the accumulation result of the integrator 31 ₂₅ as a tap at the bottom in the final stage hierarchy. The integrator 31 _25, the general arithmetic operation of data that is central to the tap arranged to be performed, an advantage that accuracy calculation is performed occurs.
[0022]
The input pixel data consisting of 9 bits including the sign in the expression using the two's complement and the prediction coefficient consisting of 10 bits including the sign in the expression using the fixed point are supplied to the integrator 31 and integrated. As shown in FIG. 3, in the accumulator 31, the result of the first calculation is 18 bits in the full bit width, but the lower 3 bits are rounded down and output as 15 bits. In this way, the output of the integrator 31 ₁ is supplied to the adder 32 ₁ via the register. Similarly, the output of the integrator 31 _{2-31 24} even through the register is supplied to the adder 321 _to 323 _12.
[0023]
The adder 32 ₁ , that is, the first layer adder, in the addition result, as shown in FIG. 3, extends by 1 bit in the upper bit direction, but the same bit width is obtained by truncating the lower 1 bit. It is said. In the first layer of the adder 32 ₂ to 32 ₁₂ Similarly, the integrator 31 _3-31 are subject to 15-bit data supplied from the _24, each of the addition result, 15 as bit data, the second layer It is supplied to the adders 33 _{1 to} 33 ₆ .
[0024]
The 15-bit data output from the adders 32 ₁ and 32 ₂ is supplied to the adder 33 ₁ in the second hierarchy. Its adder 33 ₁ of the addition result, as shown in FIG. 3, to suppress the elongation of the upper bit direction, truncating a bit lower, is supplied to the adder 34 ₁ via the register as 14-bit data . Similarly, in the second layer adders 33 _{2 to} 33 ₆ , the 15-bit data supplied from the first layer adders 32 _{3 to} 32 ₁₂ are added, and each addition result is expressed as 14-bit data. is supplied to the adder 34 ₁ to 34 ₃ of the third layer.
[0025]
The 14-bit data output from the adders 33 ₁ and 33 ₂ is supplied to the adder 34 ₁ in the third hierarchy. Addition result of the adder 34 _1, as shown in FIG. 3, to suppress the elongation of the upper bit direction, truncating a bit lower, is supplied to the adder 35 ₁ through the register as the 13-bit data . Similarly in the third hierarchical adder 34 ₂ and 34 ₃ are added 14-bit data supplied from the adder 33 ₃ to 33 ₆ of the second hierarchy, each addition result as 13-bit data, It is supplied to the adders 35 ₁ and 35 _{2 in} the fourth layer.
[0026]
The 13-bit data output from the adders 34 ₁ and 34 ₂ is supplied to the adder 35 ₁ in the fourth layer. Addition result of the adder 35 _1, as shown in FIG. 3, to suppress the elongation of the upper bit direction, truncating a bit lower, is supplied to the adder 36 via the register as 12 bits of data. The adder 35 ₂ of the fourth hierarchy as well, 13-bit data supplied from the adder 34 ₃ and integrator 31 ₂₅ in the third layer is added, the addition result as 12-bit data, the fifth It is supplied to the adder 36 of the hierarchy.
[0027]
The integrator 31 ₂₅ supplied to the adder 35 _2, the center to become data (9 bits) and the prediction coefficient of the tap, as described above (10 bits) is accumulated. Data output from the integrator 31 ₂₅ is the same as the 18-bit and the integrator 31 _{1-31 24} described above. However, the output of the integrator 31 ₂₅ to be supplied to the adder 35 ₂ of the fourth hierarchy, as 13 bit by stretching 1 bit to the upper bit direction, to remove the 6 bits of the lower adder 35 ₂ Supplied to.
[0028]
The fifth layer adder 36 is supplied with 12-bit data output from the adders 35 ₁ and 35 ₂ . As shown in FIG. 3, the addition result of the adder 36 suppresses the expansion in the upper bit direction, truncates the lower one bit, that is, 11-bit data from which all the bits after the decimal point are deleted, to the limiter circuit 37. Supplied. In the limiter circuit 37, the supplied 11-bit data is limited to 8 bits, and the predicted value is output from the output terminal 24.
[0029]
The address signal generator 3 used in this embodiment generates an address signal corresponding to the pixel data included in the supplied block. For example, ADRC (Dynamic Range Adaptation) is applied to the pixel data included in the block. Coding), DPCM (predictive coding), DCT (discrete cosine transform), VQ (vector quantization), BTC (block truncation coding), etc. to compress the compressed value into the block It is also possible to use a class classification method for generating an address signal as the class.
[0030]
That is, a prediction coefficient is read out by class classification, and a prediction value is generated by linear linear combination using the read prediction coefficient and pixel data. Thus, by generating the prediction value, for example, prediction of pixels thinned out by up-conversion from an SD (Standard Definition) signal to an HD (High Definition) signal or sub-sampling is performed.
[0031]
Further, in this embodiment, in the case of a filter having a coefficient gain close to 1, it has a structure that can sufficiently withstand overflow or underflow. Even when the calculation result is rounded to 8 bits, only an error of about ± 1 to ± 2 occurs, and it is evaluated that the difference cannot be identified even when the image is displayed on the monitor. .
[0032]
In this embodiment, the pixel data is used for the explanation, but the same result can be obtained even if the audio data is used.
[0033]
【The invention's effect】
According to the present invention, in the case of handling an image, when pixel data input in 8 bits is rounded to 8 bits and output in the final stage, it is not necessary to take precision so accurately, and a stage in the middle of an operation Even if the rounding process is optimally repeated, that is, the lower bit of the result of the adder for each layer that adds the integration results is rounded down and reduced so that the bit width does not increase with each addition, the accuracy is so much. Does not deteriorate.
[0034]
Furthermore, according to the present invention, the product-sum operation circuit is parallelized, the address signal supplied to the prediction coefficient memory circuit is one, the address decoder circuit is shared, and the utilization efficiency of the memory cell is further increased. Therefore, the circuit scale of the product-sum operation circuit that performs the filter operation of the image can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a digital signal arithmetic device according to the present invention.
FIG. 2 is a block diagram showing an example of an integration operation circuit according to the present invention.
FIG. 3 is a schematic diagram showing an example of a bit width corresponding to a hierarchy of an integration arithmetic circuit according to the present invention.
FIG. 4 is a block diagram of a conventional digital signal arithmetic device.
FIG. 5 is a diagram used for explaining signal conversion;
[Explanation of symbols]
2 n-tap blocking circuit 3 address signal generation circuit 4 prediction coefficient memory circuit 6 address decoder circuit 7 memory cell 9 product-sum operation circuit 11 accumulator 13, 16, 19, 15, 21 adder 23 limiter circuit

Claims (6)

In a digital signal arithmetic unit that multiplies and sums digital signals,
According to the corresponding address signal into n digital signals extracted from the input digital signal, a prediction coefficient reading means for to read out the prediction coefficients of n type from the memory,
N-tap sum-of-products operation means for supplying the n-type prediction coefficients read out and n number of digital signals extracted from the input digital signal, respectively, and performing a sum-of-products operation;
Limiter means for limiting the data on which the product-sum operation has been performed,
The product-sum operation means is at least
And prediction coefficient of the n type, and the n integrators for integrating said n digital signals and respectively,
A first layer adder for adding at least a part of the integration results by the n integrators and clipping and outputting the addition results ;
A second layer adder that adds at least a part of the addition result by the first layer adder and clips and outputs the addition result;
A digital signal arithmetic apparatus comprising a register provided between the first and second layer adders . A plurality of adders configured in a hierarchical structure including the first and second hierarchy adders ,
2. The digital signal according to claim 1, wherein the data to be output is clipped as a rounding process for the lower bits without increasing in the higher bit direction as the number of operation stages is increased. Arithmetic unit. The prediction coefficient reading means is
The n kinds of prediction coefficients are read from the memory in accordance with an address signal generated according to a class determined based on n digital signals extracted from the input digital signal. 2. The digital signal arithmetic device according to 1. The prediction coefficient reading means is
And characterized in that in response to the address signal generated in accordance with the class that is determined based on the value generated by compressing a digital signal which is the input, and to read out the prediction coefficients of n type from the memory The digital signal arithmetic device according to claim 3 . The limiter means is
2. The digital signal arithmetic apparatus according to claim 1, wherein the data is limited so as to have the same number of bits as the input digital signal. The product-sum operation means is
The summation result of the digital signal corresponding to the center tap among the n taps is added to the layer close to the final stage among the plurality of adders configured in a hierarchical structure including the first and second layer adders. 2. The digital signal arithmetic apparatus according to claim 1, wherein the addition is performed by a calculator.

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