JP3728098B2 - Semiconductor device, logic rewrite prevention method, logic rewrite method, code processing method, and storage medium - Google Patents

Description

【０１９２】
この符号で、１、２、４桁目は検査ビットであり、（１、３、５、７）、（２、３、６、７）及び（４、５、６、７）の各桁の組で偶数パリティになるように検査ビットが決められている。例えば、１０進数「１２」に対応する符号“０１１１１００”を書き込んでおいたところ、誤りが発生して、“０１０１１００”と読み出された場合、表１に示したように、誤りがある桁を２進数（この場合は０１１）で得ることができるので、誤りが発生しても容易に、かつ確実に訂正することができる。
【０１９３】
尚、この符号は、情報ビット数がさらに多い場合にまで拡張することができ、ｎ個の情報ビットに対して必要な検査ビット数ｍは次式で表される。
２m ＝ｎ＋ｍ＋１ ・・・（１式）
【０１９４】
以上の説明では、本発明を浮遊ゲート型のメモリセルを有する不揮発性記憶装置に実施した場合を例に挙げて説明をしたが、多値記憶を行わせるメモリセルとしては、浮遊ゲート型のものに限らず、ＭＮＯＳ型のものでも良い。また、本発明は、ＥＥＰＲＯＭ以外にも、ＥＰＲＯＭやＰＲＯＭ、更には、例えば、電界効果トランジスタのチャネル領域にイオン注入する不純物の量を制御することによりしきい値を変化させて記憶状態を得るマスクＲＯＭにも適用することが可能である。また、４値と８値の場合を例に挙げたが、決してこの値に限定されるものでもない。
【０１９５】
さらに、本発明の書き込み方法はＤＲＡＭにも適用できる。この場合、書き込み時にプリチャージを行うことは言うまでもない。
【０１９６】
また、誤り訂正符号を得る方法として交錯法を例に説明をしたが、メモリセルに記憶する情報量に応じたバースト長の誤りを訂正できる誤り訂正符号であれば、交錯法以外の方法、例えば、巡回符号または短縮化巡回符号でもよい。
【０１９７】
一方、上述のようにして、メモリセルへ書き込まれたデータを暗号鍵として図５のステップＳ４００、図６のステップＳ４０２で読み出すには、図３のセンス回路４０４を図１３に示すような回路で構成すれば良い。
以下に図１３に示すセンス回路４０４によりメモリセルに書き込まれたデータを暗号鍵として読み出す動作を説明する。
【０１９８】
多値メモリとして構成されたメモリセル２０２に設定された下位ビットに相当する閾値電圧Ｖｔｈ１が、インバータ４０、トランジスタ４１、４２からなる出力バッファを介して、センスアンプ４３の反転入力端子に与えられる。センスアンプ４３の非反転入力端子には、トランジスタ４７に設定された判定電圧Ｖ４７が、インバータ４６、トランジスタ４４、４５からなる出力バッファを介して与えられる。
【０１９９】
閾値電圧Ｖｔｈ１が判定電圧Ｖ４７より小さい場合、センスアンプ４３の出力は、Ｈｉｇｈｔになるので、メモリセル２０２に記憶された下位ビットＤ０は”１”と判定される。センスアンプ４３の出力がＨｉｇｈｔなので、トランジスタ５２がオンする一方、インバータ５３によりトランジスタ５４がオフする。したがって、トランジスタ５２に設定された判定電圧Ｖ５２が、インバータ５１、トランジスタ４９、５０からなる出力バッファを介して、センスアンプ４８の非反転入力端子に与えられる。そして、メモリセル２０２に設定された上位ビットに相当する閾値電圧Ｖｔｈ２が、出力バッファ１を介して、センスアンプ４８の反転入力端子に与えられる。
【０２００】
閾値電圧Ｖｔｈ２が判定電圧Ｖ５２より小さい場合、センスアンプ４８の出力はＨｉｇｈｔになるので、メモリセル２０２に記憶された上位ビットＤ１は”１”と判定される。一方、閾値電圧Ｖｔｈ２が判定電圧Ｖ５２より大きい場合、センスアンプ４８の出力はＬｏｗになるので、メモリセル２０２に記憶された上位ビットＤ１は”０”として読み出される。
【０２０１】
また、閾値電圧Ｖｔｈ１が判定電圧Ｖ４７より大きい場合、センスアンプ４３の出力は、Ｌｏｗになるので、メモリセル２０２に記憶された下位ビットＤ０は”０”と判定される。センスアンプ４３の出力がＬｏｗなので、トランジスタ５２がオフする一方、インバータ５３によりトランジスタ５４がオンする。したがって、トランジスタ５２に設定された判定電圧Ｖ５４が、出力バッファを介して、センスアンプ４８の非反転入力端子に与えられる。そして、メモリセル２０２に設定された上位ビットに相当する閾値電圧Ｖｔｈ２が、出力バッファを介して、センスアンプ４８の反転入力端子に与えられる。
【０２０２】
閾値電圧Ｖｔｈ２が判定電圧Ｖ５４より小さい場合、センスアンプ４８の出力はＨｉｇｈｔになるので、メモリセル２０２に記憶された上位ビットＤ１は”１”として読み出される。一方、閾値電圧Ｖｔｈ２が判定電圧Ｖ５４より大きい場合、センスアンプ４８の出力はＬｏｗになるので、メモリセル２０２に記憶された上位ビットＤ１は”０”として読み出される。
【０２０３】
このようにして、図５のステップＳ４００、図６のステップＳ４０２で読み出された値が暗号鍵として図４に示すメモリ３０４に記憶される。
【０２０４】
尚、上記第１、第２の実施の形態では、メモリセル２００としてＥＥＰＲＯＭメモリセルを用いた場合について説明したが、例えば、特開平８ー１２４３７８に開示されているＦＲＡＭ（強誘電体）多値メモリセルを用いても良い。
具体的には、ゲート絶縁膜に強誘電体膜を用いた電解効果型トランジスタ（ＦＥＭＦＥＴ）で図２の各メモリセル２００を構成し、強誘電体膜の分極状態が変わることにより各メモリセルのしきい値電圧の変化を利用して、各１メモリセルに３値”Ｈ”、”Ｌ”、”ーＨ”を記憶させる。ＦＲＡＭ（強誘電体）メモリセルをメモリセル２００として用いることにより、ＥＥＰＲＯＭメモリセルよりさらに複雑な暗号鍵を構成することができ、第３者による不正な書き換えに対する安全性が一層高まる。
さらにメモリセル２００として、ＭＮＯＳ、マスクＲＯＭ、ＥＰＲＯＭ、ＰＲＯＭ、フラッシュ不揮発性メモリによる多値メモリセルを用いてもよい。
【０２０５】
（３）第３の実施の形態
本実施の形態において、上述した第１、２の実施の形態と異なる点は、書換制御回路１０３の構成を、例えば、図１４に示すような構成としたことである。
尚、ここでは、第１の実施の形態と異なる点についてのみ具体的に説明する。
【０２０６】
すなわち、本実施の形態においては、書換制御回路１０３は、信号線１０５からの命令信号が供給される制御回路３１１と、制御回路３１１の制御プログラムが格納されるプログラム用メモリ３１２と、論理集積回路１００の論理の破壊を目的とした命令信号のパターンデータ（基準信号）を複数種類記憶されるパターンメモリ３１３とを具備している。
そして、プログラム用メモリ３１２には、例えば、図１５に示すようなフローチャートに従った制御プログラムが予め設定されており、この制御プログラムが制御回路３１１により読み出され実行されることで、書換制御回路１０３は、以下のように動作する。
【０２０７】
先ず、制御回路３１１は、信号線１０５を介して外部から書換命令信号が入力されたか否かを判別し（ステップＳ４１１）、該書換命令信号が入力された場合には、次のステップＳ４１２に進み、入力されていない場合には、書換命令信号入力待ち状態となる。
【０２０８】
ステップＳ４１２では、制御回路３１１は、入力された書換命令信号を受け取る。
【０２０９】
そして、制御回路３１１は、パターンメモリ３１３に記憶されている複数種類のパターンデータの中に、ステップＳ４１２で受け取った書換命令信号に対応したパターンデータが存在するか否かを判別する（ステップＳ４１３）。
具体的には、パターンメモリ３１３には、論理集積回路１００の論理の破壊を目的とした書換命令信号（ウィルス）として考えられる信号に対応した複数種類のパターンデータが予め記憶されている。このパターンメモリ３１３のパターンデータと、受け取った書換命令信号のパターンデータとを比較することで、該書換命令信号が書換命令信号（ウィルス）であるか否かを知ることができる。
【０２１０】
このようなステップＳ４１３の判別の結果、受け取った書換命令信号に対応したパターンデータが存在した場合、制御回路３１１は、論理集積回路１００の論理の破壊を目的とした書換命令信号（ウィルス）が入力されたと認識し、該書換命令信号（ウィルス）を無効として、何も行わずに前述したステップＳ４１１に戻り、それ以降のステップ処理を繰り返し実行する。
【０２１１】
一方、ステップＳ４１３の判別の結果、受け取った書換命令信号に対応したパターンデータが存在しない場合、制御回路３１１は、その受け取った書換命令信号を有効とし、該書換命令信号に従って、複数のＥＥＰＲＯＭメモリセル２０２を書き換え（ステップＳ４１５）、前述したステップＳ４１１に戻り、それ以降のステップ処理を繰り返し実行する。
【０２１２】
前述のように、本実施の形態では、外部より書換命令信号を受け取ると、この書換命令信号が、論理集積回路１００の論理の破壊を目的とした書換命令信号（ウィルス）であるか否かを判別し、その判別の結果、書換命令信号（ウィルス）でなかった場合のみ、複数のＥＥＰＲＯＭメモリセル２０２の書き換えを行うようにする。
このように構成することで、論理集積回路１００の論理の破壊を目的とした書換命令信号（ウィルス）が論理集積回路１００に入力されたとしても、その書換命令信号は、書換命令信号（ウィルス）であると判別され、複数のＥＥＰＲＯＭメモリセル２０２の書き換えは行われないため、論理集積回路１００の論理の不正な書換えは不可能となる。
したがって、本実施の形態においても、論理集積回路１００の不正な書換えによる論理の破壊を確実に防ぐことができるので、書換可能な論理集積回路１００は論理の破壊に対して耐久性のあるものとして提供することができる。尚、パターンメモリ３１３に記憶するパターンデータは新しいウイルスパターンが発見され次第、パターンメモリ３１３に追加記憶することにより論理の破壊に対する耐久性がさらに高まる。
【０２１３】
尚、前述した第１、２及び第３の実施の形態では、論理集積回路１００をＥＥＰＲＯＭ型のものとしたが、これに限らず、例えば、ＳＲＡＭ型のものとしてもよい。
【０２１４】
（４）第４の実施の形態
本発明に係るの機密保持機能を備えた半導体装置は、例えば、図１６に示すような半導体装置５００に適用される。
【０２１５】
この半導体装置５００は、前記図１６に示すように、マスクＲＯＭ５０１ａとＥＥＰＲＯＭ５０１ｂと含む記憶装置５０１を具備し、情報を記憶するために必要な面積の小型化を図ることと、記憶内容を書き換え可能にすることの両方をバランス良く可能にしている。そして、マスクＲＯＭ５０１ａに暗号化された機密内容のデータを記憶している。このマスクＲＯＭ５０１ａに記憶した内容は暗号化してあるため、顕微鏡等を用いて構造解析しても、記憶内容を解読することはほとんど不可能である。
【０２１６】
また、半導体装置５００は、ＳＲＡＭ型のＦＰＧＡ（Field Programmable Gate Array ）５０２と、演算装置であるＣＰＵ（中央演算装置）５０３とを具備している。
【０２１７】
ここで、ＦＰＧＡとは、汎用論理集積回路として広く使われるようになってきた大規模ＰＬＤ（Programmable Logic Device ）のことであり、入力データを演算して出力データを得るための論理をユーザが電気的にプログラムすることができる回路、すなわち論理を電気的に書換可能な論理集積回路であり、しかもハード的に演算を行うため高速な回路である。
そこで、ＦＰＧＡ５０２は、第１、第２及び第３の実施の形態における論理集積回路１００と同様の構成としており、前述したような論理防衛機能を有している。
尚、ＦＰＧＡ５０２の構成及びその機能については、第１、第２及び第３の実施の形態における論理集積回路１００と同様であるため、その詳細な説明は省略する。
【０２１８】
さらに、記憶されたデータの外部出力先である外部装置６００が、出力端子５０９を介して接続されている。
外部装置６００には、記憶再生装置６０１及び記憶媒体６０２が設けられている。
【０２１９】
マスクＲＯＭ５０１ａに記憶された機密内容のデータの復号化の方法は、ＦＰＧＡ５０２が、ＣＰＵ５０３で用いる論理上のアドレスＡＤ−１からマスクＲＯＭ５０１ａの構造上のアドレス（暗号化されてばらばらの位置に記憶された一群のデータを復号化して読み出すためのアドレス）ＡＤ−２に変換することによって行う。すなわち、ＦＰＧＡ５０２は、後述するように、ＣＰＵ５０３から出力された論理上のアドレスＡＤ−１の入力を受け、それをマスクＲＯＭ５０１ａの構造上のアドレスＡＤ−２に変換してマスクＲＯＭ５０１ａに出力する。
【０２２０】
以下に、半導体装置５００の動作の一例を、図１７のフローチャートに基づいて説明する。
【０２２１】
前記図１７において、ステップＳ７０１で電源が投入され、半導体装置５００が記憶内容の外部出力先と接続されると、ステップＳ７０２でＣＰＵ５０３が動作し、記憶内容の外部出力先に対してＦＰＧＡ５０２に設定する論理演算のプログラムＰを指定するように要求する。
【０２２２】
この要求に応答して、記憶再生装置６０１は、記憶媒体６０２から読み出したプログラムのデータを再生し、半導体装置５００に送信する。
次に、そのプログラムをステップＳ７０３でデータＩ／Ｏ部５０４により受信すると、ＣＰＵ５０３は、ステップＳ５０４で受信したデータを解釈しながらＦＰＧＡ５０２をプログラムする論理演算のプログラムＰを出力する。
【０２２３】
尚、ＦＰＧＡ５０２は、前述した論理防衛機能により、ＦＰＧＡ５０２をプログラムする論理演算のプログラムＰ（例えば、ウィルスプログラムであったの場合）によりＦＰＧＡ５０２の論理が破壊されたか否か、或いは、該プログラムＰがウィルスプログラムのようなＦＰＧＡ５０２の論理の破壊を目的としたプログラムであるか否かを判別することで、ＦＰＧＡ５０２の論理の破壊を確実に防ぐようになされている。これにより、不正なデータが入力された場合は、半導体装置５００に記憶されたデータを正しく出力できる状態にはならないようになっている。ＦＰＧＡ２のプログラムは、前述した命令信号に対応したものであり、予め多数配置されているトランジスタをＯＮにしたり、ＯＦＦにしたりすることで、ＡＮＤ回路やＯＲ回路を任意に組むことによって行う。
【０２２４】
ところで、予め固定のロジックを組んである論理回路では、顕微鏡等を用いてゲートアレイの配線を辿れば、ＡＮＤ回路やＯＲ回路を識別することができ、その論理回路に設定されている論理を容易に解読することができる。
【０２２５】
これに対して、本実施の形態のように論理防衛機能を有するＦＰＧＡ５０２を用いた場合は、トランジスタにチャージされる電荷の有無によって任意のロジックを後から組むので、顕微鏡等を用いて構造解析しても、設定された論理を解読することはほとんど不可能であると共に、その論理を破壊することもほとんど不可能である。
【０２２６】
このプログラムが終了すると、次に、ＣＰＵ５０３は、ステップＳ７０５でデータの出力が可能になったことを示す信号をデータＩ／Ｏ部５０４を介して外部出力先に送信する。これに対応して、外部出力先からあるアドレスのデータの出力が要求され、ステップＳ６でそのアドレスをデータＩ／Ｏ部５０４で受信すると、ＣＰＵ５０３は、この受信したアドレスＡＤ−１をＦＰＧＡ５０２に出力する。
【０２２７】
すると、ＦＰＧＡ５０２は、ステップＳ７で、ステップＳ７０４にて設定されたプログラムに基づいて、論理上のアドレスＡＤ−１を基にマスクＲＯＭ５０１ａの構造上のアドレスＡＤ−２を演算し、それをマスクＲＯＭ５０１ａに出力する。
そして、次のステップＳ７０８で、マスクＲＯＭ５０１ａは、ＦＰＧＡ５０２により演算された構造上のアドレスＡＤ−２に従ってデータＤをＣＰＵ３に出力する。ＣＰＵ５０３は、入力されたデータＤを、データＩ／Ｏ部５０４を介して外部出力先に出力する。
【０２２８】
このように、第４の実施の形態では、暗号化された記憶内容を復号化するのにＦＰＧＡ５０２を使っているため、ＦＰＧＡ５０２のプログラムが終了した後はデータの出力を高速に行うことができる。しかも、そのデータ出力の間はＣＰＵ５０３はデータの出力のみを行っているので、ＣＰＵ５０３は他の演算を行うことができる。この場合、マスクＲＯＭ５０１ａに記憶されたデータ等を用いて、ＣＰＵ５０３が独自のデータ処理を行うことができることは言うまでもない。さらに、ＦＰＧＡ５０２は、ＥＥＰＲＯＭに比べて回路規模が小さく集積化が容易なので、半導体装置５００は安価に提供することができる。
【０２２９】
また、ＦＰＧＡ５０２に論理防衛機能を持たせることで、ＦＰＧＡ５０２に設定された論理の破壊を確実に防ぐようになされているため、半導体装置５００での正確な動作を常に保証することができ、半導体装置５００はより高性能に提供することができる。
【０２３０】
尚、本実施の形態では、ＦＰＧＡ５０２としてＳＲＡＭ型のものを用いた。この場合、電源を切るとＦＰＧＡ５０２の記憶データが破壊されるため、電源を再び入れたときにはＦＰＧＡ５０２のプログラムをやり直さなければならない。しかし、この問題はＳＲＡＭ型のＦＰＧＡの代わりに、ＥＥＰＲＯＭ型のＦＰＧＡを使用することによって回避することができる。
【０２３１】
以下に、前記図１６に示したＥＥＰＲＯＭ５０１ｂに暗号化されたデータを記憶するための暗号化動作の一例を、図１８のフローチャートに基づいて説明する。
【０２３２】
前記図１８において、ステップＳ７１０で電源が投入され、半導体装置５００が記憶すべきデータの外部入力元に備えられる、例えば、記憶再生装置６０１及び記憶媒体６０２と接続されると、ステップＳ７１１でＣＰＵ５０３が動作し、外部入力先に対してＦＰＧＡ５０２に設定する論理演算のプログラムを指定するように要求する。
【０２３３】
この要求に応答して、記憶再生装置６０１が記憶媒体６０２からプログラムデータを再生し、半導体装置に送信する。次に、ステップＳ７１２で、そのプログラムをデータＩ／Ｏ部５０４により受信すると、ＣＰＵ５０３は、ステップＳ７１３で受信したデータを解釈しながらＦＰＧＡ５０２をプログラムする。
尚、上述したように、ＦＰＧＡ５０２は、前述した論理防衛機能を有するため、不正なデータが入力された場合は、半導体装置５００へデータを正しく入力できる状態にはならないようになっている。
【０２３４】
このプログラムが終了すると、次にＣＰＵ５０３は、ステップＳ７１４で、データの出力が可能になったことを示す信号をデータＩ／Ｏ部５０４を介して外部出力先に送信する。これに応答して、外部入力元からあるアドレスのデータの入力が要求され、ステップＳ７１５でその論理上のアドレスＡＤ−１をデータＩ／Ｏ部５０４で受信すると、ＣＰＵ５０３は、この受信した論理上のアドレスＡＤ−１をＦＰＧＡ５０２に出力する。
【０２３５】
すると、ＦＰＧＡ５０２は、ステップＳ７１６で、ステップＳ７０４（前記図２０）にて設定されたプログラムに基づいて、論理上のアドレスＡＤ−１からＥＥＰＲＯＭ５０１ｂの構造上のアドレスＡＤ−２を演算し、それをＥＥＰＲＯＭ５０１ｂに出力する。そして、次のステップＳ７１７で外部入力元からデータをデータＩ／Ｏ部５０４を介してＣＰＵ５０３に入力し、これを構造上のアドレスＡＤ−２としてＥＥＰＲＯＭ５０１ｂに記憶する。
尚、ユーザが外部から暗号化キーを変える場合には、ＦＰＧＡ５０２に記憶させておいてもよい。
【０２３６】
このように、半導体装置５００では、記憶すべきデータを暗号化するのにも論理防衛機能を有するＦＰＧＡ５０２を使っているため、ＦＰＧＡ５０２のプログラムが終了した後はデータの入力を高速に行うことができ、正確なその動作を常に保証することができる。しかも、そのデータ入力の間はＣＰＵ５０３を使っていないので、ＣＰＵ５０３は他の演算を行うことができる。
【０２３７】
ここで、ステップＳ７１６でＦＰＧＡ５０２による構造上のアドレスＡＤ−２の演算方法の一例を説明する。
【０２３８】
例えば、ＥＥＰＲＯＭ５０１ｂのアドレスが００００ｈからＦＦＦＦｈまであるとする。この場合、ＥＥＰＲＯＭ５０１ｂの容量に応じて記憶すべきデータの順列が００００ｈ番からＦＦＦＦｈ番まで存在する。そして、記憶すべきデータの順列を一定の法則に基づいて並べ直し、ＥＥＰＲＯＭ５０１ｂに記憶する。
【０２３９】
具体的なデータの並べ直しの方法として、下記の表１に示すように、例えば、ＡＢＡＢｈのデータにつき、ＡＢＡＢｈを２進表示して（１０１０ １０１１
１０１０ １０１１）2 とし、さらにこの値を左シフトして（０１０１ ０１１１ ０１０１ ０１１１）2 とする。つまり、５７５７ｈ番目に並べなおす。
【０２４０】
【表１】

【０２４１】
並べ直されて生成された新しい順列で、外部から与えられたデータがデータＩ／Ｏ部５０４、ＣＰＵ５０３を介してＥＥＰＲＯＭ５０１ｂの各番地に記憶される。したがって、ＥＥＰＲＯＭ５０１ｂに記憶されるデータの順列は元のデータの順列とは異なる暗号化されたものとなり、元のデータを解読するのは困難となる。
【０２４２】
前記暗号化処理されて記憶装置６００に記憶されたデータを復号化（前記図８のステップＳ７０７）するには、ＣＰＵ５０３からＦＰＧＡ５０２に入力された論理上のアドレスＡＤ−１から左シフトした構造上のアドレスＡＤ−２を算出し、そのアドレスをデコードするプログラムをＦＰＧＡ５０２に書き込んでおけば、このプログラムにより復号化されたデータを読み出すことができる。
【０２４３】
具体的なデータの並べ直しのさらなる方法としては、前述した表１において、例えば、ＡＢＡＢｈ番地のデータにつき、ＡＢＡＢｈ番地を２進表示して（１０１０ １０１１ １０１０ １０１１）2 とし、この値と適当に決めた乱数（１１００ ０１１０ １１１１ ０１１１）2 との排他的論理和をとって得た値（０１１０ １１０１ ０１０１ １１００）2 、つまり６Ｂ５Ａｈ番目に並べ直す。
【０２４４】
そして、並べ直され生成された新しい順列で、外部から与えられたデータをデータＩ／Ｏ部５０４、ＣＰＵ５０３を介してＥＥＰＲＯＭ５０１ｂの各番地に記憶する。
【０２４５】
例えば、個人情報を記憶する場合において、新たな個人情報を追加したり、既存の個人情報を修正したりしたいという要求が多くある場合には、マスクＲＯＭ５０１ａの容量を小さくするとともに、ＥＥＰＲＯＭ５０１ｂの記憶容量を大きくすることで、書換え可能なメモリ領域を大きくすることが可能である。なお、ＥＥＰＲＯＭ５０１ｂの代わりにＤＲＡＭ等の揮発性メモリを用いることも可能である。
【０２４６】
尚、前述した暗号化、復号化処理において、ＥＥＰＲＯＭ５０１ｂを用いた場合には、ＦＰＧＡ５０２にアドレッシングのプログラムを書き込んでおけばよい。
【０２４７】
ＦＰＧＡを利用した情報処理装置としては、例えば特開平７−１６８７５０号公報に開示されている。この装置では、プログラムデータが記憶されたメモリにＦＰＧＡが接続され、ＣＰＵの制御の下で、メモリに記憶されたプログラムデータに従ってＦＰＧＡの論理回路を制御するようにしている。
【０２４８】
しかし、前記公報の図１に示されたように、この装置ではメモリに記憶されたＦＰＧＡによりＣＰＵと周辺機器との間でデータ通信を行うに過ぎないものであり、本実施の形態のように、ＦＰＧＡに暗号化・復号化プログラムを保持しておく。そして、ＣＰＵから与えられたデータによりプログラムされたＦＰＧＡで暗号化されたデータをメモリに記憶し、前記記憶された暗号化データを復号することは開示されていない。
また、ＦＰＧＡに論理防衛機能を持たせることで、装置での正確な動作を常に保証することも開示されていない。
【０２４９】
（５）第５の実施の形態
本発明に係る機密保持機能を備えた半導体装置は、例えば、図１９に示すような半導体装置５１０に適用される。
【０２５０】
この半導体装置５１０は、前記図１９に示すように、前述した第４の実施の形態における半導体装置５００と同様に、マスクＲＯＭ５１１ａ及びＥＥＰＲＯＭ５１１ｂよりなる記憶装置５１１と、ＦＰＧＡ５１２と、ＣＰＵ５１３とを具備しており、ＦＰＧＡ５１２をデータの暗号化あるいは復号化を行うインタフェース回路として用いている。
また、ＦＰＧＡ５１２は、第４の実施の形態におけるＦＰＧＡ５０２と同様に、論理防衛機能を有している。
【０２５１】
本実施の形態において、第４の実施の形態と異なる点は、外部出力先により指定されたアドレスがＣＰＵ５１３から記憶装置５１１に直接入力されるとともに、そのアドレスに従って記憶装置５１１より出力される構造上のデータＤ−２がＦＰＧＡ５１２によって論理上のデータＤ−１に変換され、ＣＰＵ５１３に入力されていることである。
【０２５２】
すなわち、本実施の形態においては、記憶装置５１１に記憶されている機密データの復号化の方法は、ＦＰＧＡ５１２が、マスクＲＯＭ５１１ａより読み出された構造上のデータ（暗号化されたままのデータ）Ｄ−２からＣＰＵ５１３で用いる論理上のデータＤ−１に変換することによって行う。
【０２５３】
換言すれば、ＦＰＧＡ５１２は、マスクＲＯＭ５１１ａからの構造上のデータＤ−２の入力を受け、それをＣＰＵ５１３の論理上のデータＤ−１に変換してＣＰＵ５１３に出力する。
【０２５４】
半導体装置５１０の動作は、電源が投入され、データの出力が可能な状態となるまでは、前記図１２のステップＳ７０１〜Ｓ７０５と同様である。しかし、この第４の実施の形態では、その後の動作が第３の実施の形態と異なる。
【０２５５】
すなわち、図２０に示すように、外部出力先からあるアドレスのデータの出力が要求され、ステップＳ７０６ａでそのアドレスをデータＩ／Ｏ部５１４で受信すると、ＣＰＵ５１３は、この受信したアドレスをＦＰＧＡ５１２に出力する。
【０２５６】
すると、ＦＰＧＡ５１２は、ステップＳ７０７ａにおいて、ステップＳ７０４で設定されたプログラムに基づいて論理上のデータを演算する。そして、次のステップＳ７０８で前記演算した論理上のデータを、ＣＰＵ５１３から与えられたＥＥＰＲＯＭ５１１ｂのアドレスに記憶する。
【０２５７】
一方、図２１に示すように、ＦＰＧＡ５１２からあるアドレスのデータの出力が要求され、ステップＳ７１５ａでそのアドレスをデータＩ／Ｏ部５１４で受信すると、ＣＰＵ５１３は、この受信したアドレスＡＤを記憶装置５１１に出力する。
【０２５８】
すると、ＦＰＧＡ５１２は、ステップＳ７１３で設定されたプログラムに基づいて、ステップＳ７１６ａで構造上のデータＤ−２を演算する。そして、次のステップＳ７１７で構造上のデータＤ−２をＥＥＰＲＯＭ５１１ｂのＣＰＵ５１３から与えられたアドレスに記憶する。
【０２５９】
このように、第５の実施の形態では、記憶すべきデータを暗号化するのにも論理防衛機能を有するＦＰＧＡ５１２を使っているため、ＦＰＧＡ５１２のプログラムが終了した後はデータの入力を高速に行うことができ、その正確な動作を常に保証することができる。しかも、そのデータを出力する間はＣＰＵ５１３はデータ入力しか行っていないので、ＣＰＵ５１３は他の演算を行うことができる。
【０２６０】
ここで、前記図２１のステップＳ７１６ａで行うＦＰＧＡ５１２による構造上のデータの演算方法の一例を説明する。
【０２６１】
ＥＥＰＲＯＭ５１１ｂの一つのアドレスにつき一つのワード（語長）が取り出され、一つのワード当たり１６ビットのデータが含まれているとする。この１６ビットのデータを一定の法則に基づいて並べ直し、ＥＥＰＲＯＭ５１１ｂに記憶する。
【０２６２】
例えば、ＡＢＡＢｈという１６ビットのデータについて、ＡＢＡＢｈを２進表示して（１０１０ １０１１ １０１０ １０１１）2 とし、さらにこの値を左シフトして（０１０１ ０１１１ ０１０１ ０１１１）2 とする。つまり、データ５７５７ｈをＥＥＰＲＯＭ５１１ｂに記憶する。
【０２６３】
この結果、ＥＥＰＲＯＭ５１１ｂに記憶されたデータは、元のデータとは異なる暗号化されたものとなり、元のデータを解読するのは困難となる。前記暗号化処理されてＥＥＰＲＯＭ５１１ｂに記憶されたデータを復号化（前記図１５のステップＳ７０７ａ）するには、得られた１６ビットのデータを左シフトするプログラムをＦＰＧＡ５１２に書き込んでおけば、このプログラムにより復号化されたデータを読み出すことができる。
【０２６４】
尚、この第５の実施の形態でも第４の実施の形態と同様に、ユーザ側で記憶内容を電気的に自由に書き換えたいとのニーズに対応するために、書換え可能なＥＥＰＲＯＭ５１１ｂの記憶容量を大きくすることも可能である。この場合は、ＦＰＧＡ５１２に暗号化のためのプログラムを設定し、ＣＰＵ５１３から供給されるデータをＦＰＧＡ５１２で暗号化してＥＥＰＲＯＭ５１１ｂに供給するようにすれば良い。
【０２６５】
また、前記暗号化、復号化処理において、前記図１９のＥＥＰＲＯＭ５１１ｂにデータを書き込んだ場合には、ＦＰＧＡ５１２にアドレッシングのプログラムを書き込んでおけばよい。
【０２６６】
また、第５の実施の形態でもＦＰＧＡ５１２として、ＳＲＡＭ型のものを用いる形態を示しているが、この場合は、電源を切るとＦＰＧＡ５１２の記憶データが破壊されるため、電源を再び入れたときにはＦＰＧＡ５１２のプログラムをやり直さなければならない。しかし、この問題はＳＲＡＭ型のＦＰＧＡの代わりにＥＥＰＲＯＭ型のＦＰＧＡを使用することによって回避することができる。
【０２６７】
この場合には、ＦＰＧＡ５１２にプログラムする複数のプログラムにそれぞれコードを割り当て、ＦＰＧＡ５１２にプログラムする時にはこの複数のプログラムから選択された１つのプログラムに従ってＦＰＧＡ５１２をプログラムする。このとき、プログラムのコードも記憶しておく。
【０２６８】
一旦プログラムされたＦＰＧＡ５１２にアクセスするときには、まず記憶されたプログラムコードがＣＰＵ５１３を通じて外部機器に出力され、外部機器はこのプログラムコードを元に、この半導体装置５１０に対するアクセスの仕方を変更してアクセスする。すなわち、半導体装置５１０と外部機器は、プログラムコードを共通の鍵として使用し、秘密情報の解読を協調して行うことができる。
【０２６９】
例えば、外部機器の方で１バイトずつのアドレスに対して所定ビットずつビットシフトを施してこの半導体装置５１０に供給する。そして、ＦＰＧＡ５１２では、それを逆方向にビットシフトして記憶装置５１１に対するアドレスとすることで暗号化する場合に利用できる。
【０２７０】
この場合、ＥＥＰＲＯＭ５１１ｂに記憶する内容自体は共通でも、ビットシフト量をＦＰＧＡ５１２の書き込み時に変更することで複数の暗号化が達成でき、頻繁にＦＰＧＡ５１２を書き換えることにより、機密性をより高めることができる。なお、実際の暗号化では、ビットシフトと逆シフトといったような単純な変換ではなく、周辺機器側でより複雑な変換が行われる。
【０２７１】
また、前記図１６及び図１９に示した半導体装置５００及び５１０において、記憶装置５０１及び５１１には暗号化していないデータを記憶しておき、それをＦＰＧＡ５０２及びＦＰＧＡ５１２で暗号化して出力するようにすることも可能である。例えば、半導体装置と外部出力先との間で行われる通信が傍受され機密内容が漏れることを防止するため、通信内容を暗号化する必要がある場合にこの方法を応用することができる。
【０２７２】
この場合は、例えば、第４の実施の形態において、ＣＰＵ５０３よりデータＩ／Ｏ部５０４を介して外部出力先に出力する機密データの暗号化は、次のように行う。
例えば、ＣＰＵ５０３は、外部出力先から受信したデータを解釈しながら、暗号化を行うためのプログラムをＦＰＧＡ５０２にセットする。そして、ＦＰＧＡ５０２が、ＣＰＵ５０３から供給される論理上のアドレスＡＤ−１を構造上のアドレスＡＤ−２に変換することによって行うようにしても良い。
【０２７３】
さらに、例えば、第５の実施の形態において、ＣＰＵ５１３よりデータＩ／Ｏ部５１４を介して外部出力先に出力する機密データの暗号化は、次のように行う。
例えば、ＣＰＵ５１３は、外部出力先から受信したデータを解釈しながら、暗号化を行うためのプログラムをＦＰＧＡ２０にセットする。そして、ＦＰＧＡ５１２が、その後マスクＲＯＭ５１１ａから読み出される構造上のデータ（暗号化されていない）Ｄ−２からＣＰＵ５１３で用いる論理上のデータ（暗号化されたデータ）Ｄ−１に変換することによって暗号化を行う。
【０２７４】
（６）第６の実施の形態
第６の実施の形態として、前記した第４の実施の形態と第５の実施の形態とを組み合わせることにより、アドレスとデータとの両者をＦＰＧＡで暗号化・復号化する演算を行い、その演算を常に正確に行うことを保証した装置を考えることができる。
この場合は、前記図１６に示したアドレス変換用のＦＰＧＡ５０２２と、前記図１４に示したデータ変換用のＦＰＧＡ５１２とを設け、それぞれに対して適当なプログラムをセットすることで実現することができる。
【０２７５】
（７）第７の実施の形態
本発明に係る機密保持機能を備えた半導体装置は、例えば、図２２に示すような半導体装置８００に適用される。
【０２７６】
この半導体装置８００は、前記図２２に示すように、前記図１９に示した半導体装置５１０にＲＦ部８１０及びアンテナ回路８２０を設けたものである。
尚、本実施の形態においては、記憶装置５１１としてマスクＲＯＭ５１１ａの他に、可変データを格納するＥＥＰＲＯＭ５１１ｂを設けている。また、本実施の形態でも、ＦＰＧＡ５１２に論理防衛機能を持たせた構成としている。
【０２７７】
アンテナ回路８２０は、コイル８２１とコンデンサ８２２からなる並列共振回路からなり、半導体装置の電源電力を図示しない端末機から受け取る機能と、端末機との間でデータ信号の送受信を行う機能とを兼ねたものであり、例えば、１ＭＨｚ以上の高周波のキャリア信号による無線の信号伝送を行うことができるようにしている。
【０２７８】
このような構成により、コイル８２１を通じて端末機からの電波を受信すると、その受信電力がＲＦ部８１０に供給される。ＲＦ部８１０は高周波処理を行うために設けられた回路であり、供給された受信電力から内部で使用する電源電圧を発生するとともに、受信電力中に含まれる信号成分を復調し、この復調した信号をＩ／Ｏ部５１４に出力する。Ｉ／Ｏ部５１４から先の動作は、前述した動作と同様である。
【０２７９】
一方、半導体装置８００から信号を出力する場合には、前述した動作と逆の動作となる。すなわち、ＲＦ部８１０は、Ｉ／Ｏ部５１４から与えられた信号成分をキャリアに重畳して高周波電流を生成する。そして、生成した高周波電流をアンテナ回路８２０に供給し、端末機に向けて送信する。
尚、端末機との間で信号の送受信を行うときには、端末機から動作電力が送られているので、半導体装置８００は送信電力を得ることができる。
【０２８０】
前述したように、本実施の形態における半導体装置８００は、端末機と非接触でデータの送受信を行うことができるので、非接触型のＩＣカードに内蔵する半導体装置として好適に使用することができる。
また、ＦＰＧＡ５１２に論理防衛機能を持たせているので、外部からの不正なデータによる記憶内容の破壊を確実に防ぎ、正確な動作を常に保証した半導体装置として好適に使用することができる。
【０２８１】
例えば、交通手段における定期券として使用した場合、端末機である改札口を非接触で通過することができるので、通行がスムースとなり、ラッシュアワー時における改札口の混雑を大幅に緩和することができるようになる。このように、定期券として使用した場合、定期券の有効期限等のように、内部に格納するデータを書き換える必要が生じる。
また、この場合には、定期券の記憶内容の破壊に対しても確実に防ぐことができる。例えば、第３者によりその記憶内容が書き換えられ不正に使用されるということも防ぐことができる。
【０２８２】
前記図１７に示したように、本実施の形態の半導体装置８００は、マスクＲＯＭ５１１ａの他にＥＥＰＲＯＭ５１１ｂを有しているので、ＥＥＰＲＯＭ５１１ｂに可変データを格納するようにしておくことにより、何回でも繰り返し使用することができる。
尚、データを書き換える場合にも、非接触で行うことができるので、金属の接点を介してデータの送受を行う場合と比較して、内蔵しているデータの秘密を保持し易い利点もある。
【０２８３】
また、本実施の形態の場合には、端子８３０を設けているので、端末機と接触して使用するＩＣカードとしても良好に使用することができる。
尚、前記図１７においては、アンテナ回路８２０が装置本体から突出して示しているが、アンテナ回路８２０は、実際には装置本体の表面上に配置される。
【０２８４】
尚、前述した実施の形態を実現するために、前記図３、図１６、図１９、及び図２２の各デバイスを動作させるように、各デバイスと接続された装置或いはシステム内のコンピュータ（ＣＰＵ或いはＭＰＵ）に対し、前述した実施の形態を実現するためのソフトウェアのプログラムコードを供給し、そのコンピュータに格納されたプログラムに従って前記各デバイスを動作させることによって実施したものも本発明の範疇に入る。
【０２８５】
この場合、前記ソフトウェアのプログラムコード自体が前述した実施の形態を実現することになり、そのプログラムコード自体及びそのプログラムコードをコンピュータに供給するための手段、例えば、そのプログラムコードを格納した記憶媒体は本発明を構成する。
【０２８６】
例えば、図３において、制御回路３０１には記憶再生装置３０４及び記憶媒体３０５が接続される。記憶再生装置３０４により、記憶媒体３０５に格納されているプログラムコードが読み出され制御回路３０１を動作させる。
さらに、図１６において、外部出力先（外部入力先）に設けられる記憶再生装置６０１及び記憶媒体６０２がデータＩ／Ｏ部５０４を介してＣＰＵ５０３に接続される。記憶再生装置６０１により、記憶媒体６０２に格納されているプログラムコードが読み出されデータＩ／Ｏ部５０４を介してＣＰＵ５０３を動作させる。
【０２８７】
前記プログラムコードを記憶する記憶媒体としては、例えば、フロッピーディスク、ハードディスク、光ディスク、ＣＤ−ＲＯＭ、磁気テープ、不揮発性のメモリカード、ＲＯＭ等を用いることができる。
【０２８８】
【発明の効果】
以上説明したように本発明によれば、論理防衛機能を有し、論理の破壊に対する耐久性のある電気的に書換可能な論理集積回路を提供することができる。また、書換可能な論理集積回路を備える装置に対して、正確な動作を常に保証する機能を持たせることができる。
【０２８９】
また、記憶手段と、制御手段（中央演算装置等）と、電気的に書き換え可能な論理手段とを備え、前記論理手段は、論理防衛機能を有し、論理の破壊に対する耐久性のあるものである。そして、暗号化、復号化の際には、前記制御手段により設定される暗号化、復号化プログラムに従って論理手段を書き換えるるようにするとともに、前記論理が書き換えられた論理手段により記憶手段へ入力するデータの暗号化、及び前記暗号化されたデータの復号を行うようにしたので、構造解析によって論理が解読されないようにする構成を従来よりも小規模に実現することができると共に、そのときの正確な動作を常に保証することができる。しかも、前記論理手段に設定された論理がハードウェア的に実行されるので処理を速くすることができ、その処理の間に制御手段で他の処理を行うようにすることもできる。これにより、記憶内容の機密保持機能、及び正確な動作を常に保証する機能を備え、高速な動作が可能でかつ安価な半導体装置を提供することができる。
【０２９０】
さらに、端末機に対して非接触でデータの送受信を行うことができるので、内部に記憶しているデータを不測に読み取られたり、破壊されたりする危険を無くすことができる。これにより、例えば、ＩＣカードに内蔵して使用するのに好適な半導体装置を提供することができる。
【図面の簡単な説明】
【図１】第１の実施の形態において、本発明を適用した論理集積回路の構成を示すブロック図である。
【図２】前記論理集積回路のＰＩＡの構成を示す回路図である。
【図３】前記ＰＩＡの各メモリセルの構成を示す回路図である。
【図４】前記論理集積回路の書換制御回路の構成を示すブロック図である。
【図５】第１の実施の形態において、前記書換制御回路により実行される処理プログラムの一例を説明するためのフローチャートである。
【図６】第２の実施の形態において、前記書換制御回路により実行される処理プログラムの一例を説明するためのフローチャートである。
【図７】ＥＥＰＲＯＭメモリセルの構造を示す断面図である。
【図８】本発明を適用した書き込み方法の一例（例２）を説明するための図である。
【図９】本発明を適用した書き込み方法の一例（例３）を説明するための図である。
【図１０】前記書き込み方法（例３）の変形例１、２を説明するための図である。
【図１１】本発明を適用した書き込み方法の一例（例４）を説明するための図である。
【図１２】本発明を適用した書き込み方法の一例（例４）の変形例１、２を説明するための図である。
【図１３】センス回路の構成を示す回路図である。
【図１４】第３の実施の形態における前記書換制御回路の構成を示すブロック図である。
【図１５】第３の実施の形態において、前記書換制御回路により実行される処理プログラムの一例を説明するためのフローチャートである。
【図１６】第４の実施の形態において、本発明を適用した半導体装置の構成を示すブロック図である。
【図１７】第４の実施の形態において、前記半導体装置の復号化動作の一例を示すフローチャートである。
【図１８】第４の実施の形態において、前記半導体装置の暗号化動作の一例を示すフローチャートである。
【図１９】第５の実施の形態において、本発明を適用した半導体装置の構成を示すブロック図である。
【図２０】第５の実施の形態において、前記半導体装置の復号化動作の一例を示すフローチャートである。
【図２１】前記半導体装置の暗号化動作の一例を示すフローチャートである。
【図２２】第７の実施の形態において、本発明を適用した半導体装置の構成を示すブロック図である。
【符号の説明】
１００ 論理集積回路
１０１ ＰＩＡ
１０２_X マクロセル
１０４_X Ｉ／Ｏ回路
１０５ 入力用信号線
１０６ 出力用信号線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic integrated circuit capable of electrically changing logic, a semiconductor device having a security function, a logic rewriting prevention method, a logic rewriting method, a code processing method for preventing logic destruction of the logic integrated circuit, And a storage medium storing the software.
[0002]
[Prior art]
In recent years, there has been an increasing demand for logic integrated circuits that can change (rewrite) logic for the purpose of shortening the development period of logic integrated circuits, updating after shipment to consumers, and the like. This rewritable logic integrated circuit can freely rewrite the logic, and can thereby realize a circuit having a completely different logic function. Such logic integrated circuits are widely used in communication devices such as mobile phones, computer add-on boards, video game devices, karaoke devices, and the like.
[0003]
On the other hand, in recent years, a program for illegally rewriting a computer rewritable storage device, for example, a hard disk device, a floppy disk device, or a BIOS storage flash memory, has become a problem.
Such a program is also referred to as a virus program, and is spread by infecting other computers one after another via a communication medium or a replaceable storage medium such as a floppy disk. Some virus programs make the operation impossible by destroying the stored contents of the computer, causing a great deal of damage to the computer user.
Therefore, a means for preventing or curing the infection of a virus program such as a vaccine program has been developed and widely used for a computer rewritable storage device.
For example, Japanese Patent Laid-Open No. 8-179742 discloses a computer system adapted to detect the presence of a virus program. Japanese Patent Laid-Open No. 8-22390 discloses a system for detecting whether data software in a computer has been rewritten by a virus program.
[0004]
Conventionally, a semiconductor device having a security function has been proposed.
For example, the device disclosed in Japanese Patent Laid-Open No. 4-232588 is particularly concerned with security maintenance when using an IC card, and includes a ROM storing basic software, encryption software, and an encryption key. An EEPROM for storing, a RAM for storing the manufacturer's identification number, and the like, and a CPU for controlling the encryption operation are provided.
Japanese Laid-Open Patent Publication No. 4-11420 discloses a one-chip microcomputer including a nonvolatile memory for storing ID data to be encrypted, an encryption circuit for encrypting ID data, a control circuit, and the like. Yes. JP-A-63-293637 discloses a nonvolatile memory (ROM) for storing encrypted programs and data, a volatile memory (RAM) for storing keys for encryption and decryption, A microcomputer having a rewritable memory (EEPROM) for storing data encrypted using an encryption key is disclosed.
In such a semiconductor device, since the EEPROM holds information depending on whether or not charge is accumulated, it is impossible to decode a program stored by structural analysis. For this reason, the logic for encrypting / decrypting confidential data cannot be decrypted. Therefore, it is extremely difficult to decrypt the encrypted confidential data in the mask ROM, and it is hardly decrypted.
[0005]
[Problems to be solved by the invention]
By the way, since the rewritable logic integrated circuit as described above has been used for an application in which the demand is increased and safety is more demanded, the countermeasure against the virus program ( It has become necessary to have an (immunity) function, that is, a logic defense function against logic destruction by a virus program.
However, there has been no countermeasure method (logic defense method) against a virus program in a rewritable logic integrated circuit.
That is, conventional countermeasures against virus programs such as those disclosed in Japanese Patent Application Laid-Open Nos. 8-17942 and 8-22390 provide data for controlling the operation of the entire computer system used by the CPU. The logic of the rewritable logic integrated circuit, which is the target, cannot be prevented from being rewritten by a virus program.
Therefore, the conventional rewritable logic integrated circuit cannot avoid the problem of logic destruction caused by a virus that the logic is illegally rewritten by a virus program.
[0006]
On the other hand, in the semiconductor device having the security function as described above, the EEPROM included in this device has a large area necessary for storing 1-bit information, and thus there is a problem that high integration is difficult. It was. In this device, since the CPU must process the program to encrypt / decrypt the confidential data, it takes time to output the data and the CPU does There was a problem that could not be processed. Furthermore, this apparatus has a possibility of being infected with a virus program, and there has been a problem that the stored contents of the apparatus are destroyed due to the infection of the virus program and become inoperable.
Therefore, the conventional nonvolatile semiconductor device having a security function has a problem that it is difficult to achieve high integration and cannot be provided at low cost. In addition, the stored data cannot be output at high speed, and the arithmetic unit cannot perform other processing while the data is being output. In addition, there is a problem of destruction of stored contents due to a virus, and accurate operation cannot always be guaranteed.
[0007]
Therefore, the present invention has been made to eliminate the above-mentioned drawbacks, and a first object of the present invention is to make it possible to reliably prevent logic destruction of a rewritable logic integrated circuit.
It is a second object of the present invention to provide a logic defense method for providing a rewritable logic integrated circuit with a function for reliably preventing logic destruction.
It is a third object of the present invention to provide a storage medium storing software for providing a rewritable logic integrated circuit with a function for reliably preventing logic destruction.
It is a fourth object of the present invention to enable high-speed operation of a semiconductor device having a function for maintaining the confidentiality of stored contents, to manufacture the semiconductor device at a low cost, and to assure accurate operation at all times. And
It is a fifth object of the present invention to provide an encryption / decryption method for providing a semiconductor device with a function for maintaining confidentiality of stored contents and a function for always guaranteeing an accurate operation.
It is a sixth object of the present invention to provide a storage medium storing software for providing a semiconductor device with a function for maintaining confidentiality of stored contents and a function for always ensuring accurate operation.
It is a seventh object of the present invention to provide a semiconductor device having a security function capable of transmitting / receiving data without contact with a terminal and a function for always guaranteeing an accurate operation. .
[0008]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a logic integrated circuit whose logic can be rewritten by an external command signal, first information relating to a current first logic state of the logic integrated circuit, and the logic included in the command signal. The second information related to the second logic state of the integrated circuit is compared, and when the first and second information do not match, the logic of the logic integrated circuit is changed from the first logic state to the second logic state. Means for prohibiting rewriting to a state, wherein the first information and the second information are information on a plurality of logic elements included in the logic integrated circuit, and the first information among the plurality of logic elements. A signal indicating the number of first elements used to configure the first logic state, the number of second elements not used to configure the first logic state, and the number of first or second elements. Code obtained by compression or the logic integrated circuit A semiconductor device, characterized in that at least one of said first logic state to a rewritten date further comprising storage means for storing as said first information.
In one aspect of the first invention, the logic integrated circuit includes a plurality of multi-value memory cells that hold one of three or more different storage states, and the semiconductor device further includes the first and second memory cells. When the information matches, at least a first code and a second code encoded by an arbitrary encoding method are given, and a plurality of first bit information constituting the first code and the second code Among the plurality of second bit information constituting the code, the plurality of first and second bit information are stored in one of the plurality of multilevel memory cells as a set of bit information having the same digit. Means for rearranging bit information; means for generating a plurality of voltages corresponding to the rearranged bit information; and receiving address information to convert the voltages into the plurality of multi-value memories. Corresponds to the address information in the cell And means for rewriting the logic is applied to the memory cell that.
According to a second aspect of the present invention, a logic integrated circuit whose logic is rewritable by a command signal from the outside, and first information relating to a current first logic state of the logic integrated circuit are detected according to the command signal. Comparing the second information related to the second logic state of the logic integrated circuit prior to the current time, and if the first and second information do not match, the logic of the logic integrated circuit is Determination means for determining that the logic state has been rewritten to the first logic state, wherein the first information and the second information are information relating to a plurality of logic elements included in the logic integrated circuit, The first number of elements used to configure the first logic state among a plurality of logic elements, the second number of elements not used to configure the first logic state, the first or Compress the signal indicating the number of second elements A semiconductor device further comprising storage means for storing at least one of the obtained code or the date when the logic integrated circuit is rewritten to the first logic state as the first information. It is.
In one aspect of the second invention, the determination means outputs a determination signal when it is determined that the logic of the logic integrated circuit has been rewritten.
In one aspect of the second invention, the determination means periodically performs the determination operation.
According to a third aspect of the present invention, a logic integrated circuit whose logic can be rewritten by an external command signal is compared with the command signal and at least one reference signal, and the command signal and the reference signal are the same signal. Prohibiting means for prohibiting rewriting of logic of the logic integrated circuit, wherein the logic integrated circuit includes a plurality of multi-value memory cells holding one of three or more different storage states, and the command signal is the reference When different from the signal, at least a first code and a second code encoded by an arbitrary encoding method are provided, and a plurality of first bit information constituting the first code and the second code Among the plurality of second bit information constituting the code, the plurality of first and second bit information are stored in one of the plurality of multilevel memory cells as a set of bit information having the same digit. Sort bit information Means for receiving the rearranged bit information and generating a plurality of voltages corresponding to the information; receiving the address information; and supplying the voltage to the plurality of multi-level memory cells. And a means for rewriting the logic by applying it to a memory cell corresponding to address information.
In one aspect of the third aspect of the present invention, the apparatus further comprises storage means for previously storing a plurality of types of signals as the reference signal, and the prohibiting means compares the command signal with the plurality of types of signals.
In one aspect of the third invention, the logic integrated circuit includes a plurality of arithmetic units each having a predetermined arithmetic function, and a wiring for rewriting the logic by changing the mutual wiring of the plurality of arithmetic units according to the command signal Means.
In one aspect of the third invention, the logic integrated circuit includes an FPGA (Field Programmable Gate Array).
In one aspect of the third invention, the multilevel memory cell has a control gate and a floating gate.
In one aspect of the third invention, the multi-value memory cell is at least one of MNOS, mask ROM, EEPROM, EPROM, PROM, FRAM, and flash nonvolatile memory.
In one aspect of the third invention, rewriting means for rewriting the logic of the logic integrated circuit in accordance with the command signal is further provided.
In one aspect of the third invention, there is further provided a reading means for reading the logic of the logic integrated circuit.
In one aspect of the third invention, the bit information rearranging means controls the number of bits in the same code stored in one of the plurality of multilevel memory cells according to the error correction capability of the one code. To do.
In one aspect of the third invention, the bit information rearranging means converts m pieces of bit information into the one multi-value when the number of bits stored in one of the plurality of multi-value memory cells is m. The m codes having the code length n are rearranged as each row of the m × n array so as to be stored in the memory cell.
According to a fourth aspect of the present invention, there is provided first information relating to a current first logic state of a logic integrated circuit whose logic can be rewritten by an external command signal, and a second information of the logic integrated circuit included in the command signal. The second information related to the logic state is compared, and when the first and second information do not match, the logic of the logic integrated circuit is rewritten from the first logic state to the second logic state. Including the step of prohibiting, wherein the first information and the second information are information relating to a plurality of logic elements included in the logic integrated circuit, and constitute the first logic state in the plurality of logic elements. Obtained by compressing a signal indicating the number of first elements used for the purpose, the number of second elements not used for configuring the first logic state, and the number of the first or second elements. The code or the logic integrated circuit is the first argument. A logic rewriting prevention method characterized by at least one of the date rewritten to the state and the first information.
A fifth invention is a semiconductor device having a security function, wherein at least temporarily a code processing program is held, a control means for outputting a command signal corresponding to the code processing program, and the command signal is provided. Logic means that changes logic in accordance with the program and performs code processing on at least one of the data and an address related to the data, a first storage means for storing the data, and the logic means And comparing the first information relating to the current first logic state with the second information relating to the second logic state of the logic means included in the command signal, and the first and second information Means for prohibiting rewriting of the logic of the logic means from the first logic state to the second logic state, the first information and the second information are: Information on a plurality of logic elements included in the logic means, for configuring the first logic state, the first number of elements used to configure the first logic state among the plurality of logic elements. The second element number not used for the code, the code obtained by compressing the signal indicating the first or second element number, or the date when the logic means is rewritten to the first logic state. The semiconductor device further comprises storage means for storing at least one of them as the first information.
A sixth aspect of the invention is a semiconductor device having a security function, which is provided with control means for holding a code processing program at least temporarily and outputting a command signal corresponding to the code processing program, and the command signal. Logic means that changes the logic in accordance with the program and performs code processing on at least one of the data and an address related to the data, a first storage means for storing the data, and the command signal And at least one reference signal, and when the command signal and the reference signal are the same signal, the logic means includes a prohibiting means for prohibiting rewriting of logic, and the logic means is different in three or more values. A plurality of multi-level memory cells that hold one of the storage states, and when the command signal is different from the reference signal, encoding is performed by an arbitrary encoding method At least a first code and a second code, and a plurality of first bit information constituting the first code and a plurality of second bit information constituting the second code. Means for rearranging the plurality of first and second bit information so that bit information having the same digit is stored in one of the plurality of multi-value memory cells as a set, and the rearranged bits Means for generating a plurality of voltages corresponding to the information and receiving the address information, and applying the voltage to a memory cell corresponding to the address information among the plurality of multi-level memory cells. And a means for rewriting the logic.
In one aspect of the sixth aspect of the present invention, the apparatus further comprises second storage means for previously storing a plurality of types of signals as the reference signal, and the prohibiting section compares the command signal with the plurality of types of signals.
In one aspect of the sixth invention, the logic means includes a plurality of arithmetic means each having a predetermined arithmetic function, and a wiring means for rewriting the logic by changing the mutual wiring of the plurality of arithmetic means according to the command signal. With.
In one aspect of the sixth invention, the logic means includes a field programmable gate array (FPGA).
In one aspect of the sixth invention, the multilevel memory cell has a control gate and a floating gate.
In an aspect of the sixth aspect of the present invention, rewrite means for rewriting the logic of the logic means in response to the command signal is further provided.
In an aspect of the sixth aspect of the invention, there is further provided a reading unit that reads out the logic of the logic unit.
In an aspect of the sixth invention, the logic means performs the encoding process including at least one of an encryption process and a decryption process.
In one aspect of the sixth invention, the logic means performs the encoding process for encrypting at least one of the data and the address before the data is stored in the first storage means.
In one aspect of the sixth invention, the logic means performs the encoding process for encrypting at least one of the data and an address related to the data when the data is output from the first storage means. Do.
In one aspect of the sixth invention, the logic means performs the encoding process for decoding at least one of the data and an address related to the data when the data is output from the first storage means. Do.
In one aspect of the sixth invention, the first storage means includes at least one of a mask ROM and an electrically rewritable nonvolatile storage device.
In one aspect of the sixth invention, the semiconductor device generates antenna power for transmitting and receiving the data in a contactless manner with a terminal, a power supply voltage from a reception output of the antenna means, and the terminal And a high-frequency processing means for generating a high-frequency current superimposed with the data to be transmitted to the terminal and outputting the high-frequency current to the antenna means.
A seventh invention is a code processing method of a semiconductor device comprising a logic circuit having a security function and a logic changeable, and a control device for controlling the logic circuit, wherein the control device performs code processing. A supplying step of supplying a program; an output step of outputting a command signal corresponding to the program from the control device; and a logic changing step of changing the logic of the logic circuit according to the program by supplying the command signal to the logic circuit And a code processing step of performing a code process on at least one of data and an address related to the data by the changed logic, and a step of storing the data in a storage device, wherein the logic changing step includes: First information relating to a current first logic state of the circuit and a second logic of the logic circuit included in the command signal; When the first and second information do not match, rewriting the logic of the logic circuit from the first logic state to the second logic state is prohibited. The first information and the second information are information relating to a plurality of logic elements included in the logic integrated circuit, and for configuring the first logic state in the plurality of logic elements. The number of first elements used, the number of second elements not used to configure the first logic state, the code obtained by compressing the signal indicating the number of first or second elements, Alternatively, at least one of dates when the logic integrated circuit is rewritten to the first logic state is used as the first information.
According to an eighth aspect of the invention, the logic is changeable, and either one of an encryption program and a decryption program is given, the logic is changed by an instruction signal corresponding to the program, and the signal is changed by the changed logic. A semiconductor device having a security function including logic means for processing the logic means, wherein the logic means compares a logic integrated circuit whose logic is rewritable by the command signal with the command signal and at least one reference signal. And a prohibiting means for prohibiting rewriting of the logic of the logic integrated circuit when the command signal and the reference signal are the same signal, and the logic integrated circuit holds one of three or more different storage states And at least a first code encoded by an arbitrary encoding method when the command signal is different from the reference signal A pair of bit information having the same digit among a plurality of first bit information constituting the first code and a plurality of second bit information constituting the second code is provided. Means for rearranging the plurality of first and second bit information so as to be stored in one of the plurality of multi-value memory cells, and the rearranged bit information is provided. Means for generating a plurality of corresponding voltages; and means for receiving the address information and applying the voltage to the memory cells corresponding to the address information among the plurality of multi-level memory cells to rewrite the logic. This is a semiconductor device.
According to a ninth aspect of the present invention, in the logic integrated circuit of the logic integrated circuit, the logic can be rewritten by an instruction signal from the outside, and the logic integrated circuit includes a plurality of multilevel memory cells that hold one of three or more different storage states. A signal is compared with at least one reference signal, and when the command signal is the same signal as the reference signal, rewriting of logic of the logic integrated circuit is prohibited, and the command signal is different from the reference signal In this case, among the plurality of first bit information constituting the first code and the plurality of second bit information constituting the second code, the plurality of bit information having the same digit as one set The plurality of first and second bit information are rearranged so as to be stored in one of the multivalued memory cells, a plurality of voltages corresponding to the rearranged bit information are generated, and address information is received. The above The pressure, the plurality of to applied to the memory cell corresponding to the address information of the multilevel memory cell, a logic rewriting method, which comprises a step of rewriting the logic.
According to a tenth aspect of the present invention, there is provided a program for preventing logic rewriting of a logic integrated circuit having a plurality of multi-valued memory cells that can rewrite logic by an external command signal and hold one of three or more different storage states. The Memorized computer readable A storage medium, wherein the program is On the computer, A procedure for comparing the command signal in the logic integrated circuit with at least one reference signal; and a procedure for prohibiting rewriting of logic in the logic integrated circuit when the command signal is the same signal as the reference signal; A step of inputting at least a first code and a second code encoded by an arbitrary encoding method when the command signal is different from the reference signal; and a plurality of second codes constituting the first code Among the plurality of second bit information constituting one bit information and the plurality of second bit information, the plurality of bit information having the same digit are stored in one of the plurality of multilevel memory cells as a set. The first bit information and the second bit information are rearranged, the plurality of voltages corresponding to the rearranged bit information are generated, the address information is received, and the voltages are converted into the plurality of multi-valued memos. It is applied to the memory cell corresponding to the address information of the cell, the logic of The procedure for rewriting What to do It is.
[0112]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0113]
(1) First embodiment
The semiconductor device according to the present invention is implemented by a logic integrated circuit 100 as shown in FIG.
[0114]
That is, the logic integrated circuit 100 is an EEPROM-type rewritable logic integrated circuit having a logic defense function, and includes a wiring matrix (PIA: Programmable Interconnect Array) 101 and a plurality of macro cells 1021 to 102n connected to the PIA 101. And a plurality of I / O circuits 1041 to 104n connected to the plurality of macrocells 1021 to 102n and a rewrite control circuit 103 of the PIA 101.
[0115]
First, the macro cells 1021 to 102n are each composed of a standard library of arithmetic logic such as a counter function, an AND function, a latch function, and the like, and can be connected to each other at a high speed with a certain delay by the PIA 101.
[0116]
The PIA 101 is formed of a global bus, and the rewrite control circuit 103 controls the connection of the macro cells 102 1 to 102 n by the PIA 101.
[0117]
Specifically, for example, as illustrated in FIG. 2, the PIA 101 includes a bus line 201 including m signal lines 0 to m, and an input unit 200 xin and an output unit 200 xout connected to the bus line 201. ing.
The input unit 200xin and the output unit 200xout correspond to an arbitrary macrocell 102x among the plurality of macrocells 1021 to 102n, and other macrocells also have an output unit having the same configuration as the output unit 200xout and the input unit 200xin And input units are provided correspondingly.
In FIG. 2, an input unit 200xin and an output unit 200xout corresponding to the macro cell 102x are shown for the sake of simplicity. Since the input unit and the output unit corresponding to other macro cells are the same as the input unit 200xin and the output unit 200xout corresponding to the macro cell 102x, the details thereof will be omitted.
[0118]
The input unit 200xin is connected to the EEPROM memory cells 202x0 to 202xm connected corresponding to the signal lines 0 to m, and connected to the EEPROM memory cells 202x0 to 202xm and corresponding to the signal lines 0 to m. AND circuits 203x0 to 203xm and an OR circuit 204x connected to the AND circuits 203x0 to 203xm, and the OR circuit 204x outputs to the macro cell 102x.
The output unit 200xout includes EEPROM memory cells 205x0, 205x1,..., AND circuits 203x0, 203x1,... Connected to the macrocell 102x and EEPROM memory cells 205x0, 205x1,. 203x0, 203x1,... Are connected to the OR circuit 207x, and the OR circuit 204x outputs to the signal line 0.
[0119]
Further, as shown in FIG. 3, each memory cell 202 is connected to a multiplexer 401 and a selection circuit 402, and a write circuit 403 and a sense circuit 404 are connected to the multiplexer 401. Further, these circuits 401, 402, 403, 404 are connected to a control circuit 301 included in the rewrite control circuit 103. 2 shows only the connection relationship between the memory cells 202xo, 202x1,..., 202xm and the above circuits, but the memory cells 205xo, 205x1,. It is connected.
[0120]
In such a PIA 101, in particular, the EEPROM memory cells 202x0 to 202xm control one input of the two-input AND circuits 203x0 to 203xm according to the storage state thereof, thereby connecting the macro cell 102x and the other macro cell. Is controlled.
Specifically, for example, when the threshold value of the EEPROM memory cell 202x0 is “L”, “L” is input to the AND circuit 203x0, so that the bus line data is not output to the macro cell 102x. On the other hand, if “H”, it is output.
In this way, by rewriting the values set in the EEPROM memory cells 2020 to 202m, the connection between the macro cell 102x and other macro cells can be controlled.
[0121]
Therefore, the mutual connection of the macro cells 1021 to 102n is controlled by the storage state of the EEPROM memory cells (hereinafter collectively referred to as "a plurality of EEPROM memory cells 202") corresponding to the macro cells of the PIA 101. That is, by rewriting the storage state of the plurality of EEPROM memory cells 202, the mutual connection of the macro cells 1021 to 102n can be changed. As a result, it is possible to obtain the logic integrated circuit 100 having completely different logic (logic function).
[0122]
Such rewriting of the storage states of the plurality of EEPROM memory cells 202 (hereinafter also referred to as “rewriting of PIA 101”) is performed by the rewrite control circuit 103.
[0123]
For example, a command signal from an external circuit (not shown) is given to the rewrite control circuit 103 via an input signal line 105.
When the command signal is a rewrite command signal, the rewrite control circuit 103 rewrites the PIA 101 according to the rewrite command signal.
[0124]
Here, for example, the case where the external rewrite command signal given to the rewrite control circuit 103 is a rewrite command signal (virus) for the purpose of destroying the logic of the logic integrated circuit 100 can be considered.
Therefore, the rewrite control circuit 103 realizes a function (logic defense function) that prevents the logic of the logic integrated circuit 100 from being destroyed from a rewrite command signal (virus) by the following configuration.
[0125]
For example, as illustrated in FIG. 4, the rewrite control circuit 103 includes a control circuit 301 to which a command signal from the signal line 105 is supplied, a program memory 302 in which a control program for the control circuit 301 is stored, and a memory in the PIA 101. A memory 304 for storing the status and a timer 303 for setting a predetermined timer value are provided.
In the program memory 302, for example, control programs according to flowcharts as shown in FIGS. 5 and 6 are set in advance, and any one of these control programs is read and executed by the control circuit 301. Thus, the rewrite control circuit 103 operates as follows.
In the first embodiment, the control program according to the flowchart shown in FIG. 5 is read and executed by the control circuit 301.
[0126]
First, the control circuit 301 detects the current storage state of the PIA 101, for example, the “H” value among the plurality of EEPROM memory cells 202 via the multiplexer 401 and the sense circuit 404, and the “H” value is detected. The set number of EEPROM memory cells (number of gates) is stored as a first encryption key (first information) in the memory 304 such as an EEPROM (step S400).
[0127]
Next, the control circuit 301 determines whether or not a rewrite command signal is input from the outside via the signal line 105 (step S410). If the rewrite command signal is input, the control circuit 301 proceeds to the next step S420. If it has not been input, the process returns to step S410 to repeat the command signal determination operation.
[0128]
In step S420, the control circuit 301 receives the input rewrite command signal.
Then, the control circuit 301 counts the number of EEPROM memory cells (gates) that are second encryption keys (second information) set by the user or a third party included in the rewrite command signal received in step S420. Number) and the number of EEPROM memory cells (number of gates) in which the value of “H” as the first encryption key stored in the memory 304 is set (step S430).
[0129]
If the result of the determination in step S430 is that the first encryption key and the second encryption key are different, the control circuit 301 disables the rewrite command signal received in step S420 and disables the rewrite (step S450). Return.
[0130]
On the other hand, as a result of the determination in step S430, if the first encryption key and the second encryption key match, the control circuit 301 validates the rewrite command signal received in step S420 and selects the selection circuit 402 according to the rewrite command signal. The memory cell to be rewritten is specified via the, and the EEPROM memory cell 202 is rewritten by the write circuit 403 (step S440), and the process returns to step S410.
[0131]
As described above, in the present embodiment, in the PIA 101, the number of EEPROM memory cells for which the value of “H” is currently set is set as the first encryption key by the user or a third party at the time of rewriting. There is no difference between the number indicated by the first encryption key and the number indicated by the second encryption key by the rewrite instruction as compared with the number of EEPROM memory cells (number of gates) which is the second encryption key included in the instruction. If the result of the inspection is “difference”, rewriting of the logic of the logic integrated circuit 100 is prohibited.
With this configuration, in order to rewrite the PIA 101, that is, to change the logic of the logic integrated circuit 100, it is necessary to accurately know the number of EEPROM memory cells that are currently set to a value of “H”. Rewriting is prohibited. Since the current number is known only to those who know the current logic of the rewritable logic integrated circuit 100 accurately, there is no possibility that the logic of the logic integrated circuit 100 can be changed.
[0132]
(2) Second embodiment
In the present embodiment, the difference from the first embodiment described above is that, in the first embodiment, when the check result by the encryption key is “not different” as described above, the logic of the logic integrated circuit 100 is rewritten. In the case of “there is a difference”, rewriting is prohibited to allow rewriting by the user, while, for example, unauthorized rewriting by a third party is prevented, whereas the second embodiment In the case where the user does not rewrite for the time being, the inspection using the encryption key is performed after the rewriting, and when the inspection result is “difference”, the logic integrated circuit 100 is used. And configured to issue a warning.
In the embodiment, the rewrite control circuit 103 is read by the control circuit 301 according to the flowchart shown in FIG. 6 preset in the program memory 302 of FIG. It operates as follows.
[0133]
First, the control circuit 301 sets a predetermined timer value in the timer 303 (step S401).
[0134]
Next, the control circuit 301 detects the storage state of the PIA 101, for example, the “H” value among the plurality of EEPROM memory cells 202 via the multiplexer 401 and the sense circuit 404, and the “H” value is detected. The set number of EEPROM memory cells (number of gates) is stored as an encryption key (second information) in the memory 304 such as an EEPROM (step S402).
[0135]
Next, the control circuit 301 determines whether or not a rewrite command signal is input from the outside via the signal line 105 (step S403). If the rewrite command signal is input, the control circuit 301 proceeds to the next step S404. If it has not been input, the process proceeds to step S406 to be described later.
[0136]
In step S404, the control circuit 301 receives the input rewrite command signal.
Then, the control circuit 301 specifies a memory cell to be rewritten via the selection circuit 402 in accordance with the rewrite command signal received in step S404, rewrites the EEPROM memory cell 202 by the write circuit 403 (step S405), and next step S406. Proceed to
[0137]
In step S406, the control circuit 301 determines whether or not the timer 303 has timed up. If the time has not expired, the control circuit 301 returns to step S403 described above and repeats the subsequent step processing.
[0138]
As a result of the determination in step S406, if the timer 303 times out, the control circuit 301 determines that the storage state of the PIA 101 that is the encryption key stored in the memory 304 in step S402 and the current storage state of the PIA 101, that is, “H”. The current number of EEPROM memory cells (first information) for which values are set is compared (step S407).
[0139]
As a result of the determination in step S407, when the storage state of the PIA 101 in the memory 304 is different from the current storage state of the PIA 101, the control circuit 301 recognizes that the logic of the logic integrated circuit 100 has been rewritten “illegally”. A warning (determination) signal indicating recognition is output to the outside, and this processing ends. This warning signal allows the user to recognize that the logic of the rewritable logic integrated circuit 100 has been “illegally” rewritten.
[0140]
On the other hand, as a result of the determination in step S407, if the storage state of the PIA 101 in the memory 304 matches the storage state of the current PIA 101, the control circuit 301 recognizes that rewriting has not been performed and sets the timer 303 again to the predetermined value. (Step S408), the process returns to the above-described step S403, and the subsequent step processing is repeatedly executed.
[0141]
As described above, in the present embodiment, in the PIA 101, the number of EEPROM memory cells in which the value of “H” is set is used as an encryption key, and there is a difference between the set number and the current number. If the result of the inspection is “difference”, it is recognized that the logic of the logic integrated circuit 100 has been rewritten, and the logic integrated circuit 100 is continuously used. It was configured to issue a warning for this.
As described above, by periodically checking the logic of the logic integrated circuit 100, for example, it is possible to prevent the user from inadvertently using the logic integrated circuit 100 that has been illegally rewritten by a third party.
When the user wants to rewrite the logic of the logic integrated circuit 100, as described in the first embodiment, the control program according to the flowchart shown in FIG. 5 preset in the program memory 302 in FIG. May be read and executed by the control circuit 301.
[0142]
In the first and second embodiments described above, the number of EEPROM memory cells in which the value of “H” is set is used as the encryption key. The number may be used as the encryption key, or a code obtained by compressing a signal indicating the number of EEPROM memory cells in which the value of “H” or “L” is set may be used as the encryption key. . Alternatively, information such as the date when the logic was last rewritten and the number of unused macro cells when the logic was last rewritten may be used as the encryption key.
[0143]
Furthermore, in the second embodiment, the address of the EEPROM memory cell 200 in which the value of “H” or “L” is set is stored in the lookup table of the memory 304 as an encryption key, and FIG. In step S405 of the flowchart shown in FIG. 4, the address of the memory cell 200 in which the value of “H” or “L” is rewritten is read into the control circuit 301 of FIG. 4 via the sense circuit 404 of FIG. The key address is compared with the current address after rewriting. If the addresses are different, it is recognized that the “H” or “L” value of the memory cell 200 has been rewritten, and a warning signal is output in step S409. May be.
[0144]
As described above, if the address of the EEPROM memory cell 200 in which the value of “H” or “L” is set is stored in the lookup table of the memory 304 as the encryption key, the value of the memory cell 200 is rewritten. In this case, referring to the address of the lookup table, the memory cell can be selected by the selection circuit 402 in FIG. 3 and returned to the logic state before being rewritten by the write circuit 403. Furthermore, a code obtained by compressing the signal indicating the address may be used as an encryption key. It is to be noted that these encryption key history tables are stored in an internal or external lookup table of the logic integrated circuit 100 that cannot be understood by a third party, and the encryption keys are periodically changed by referring to the history table. Increases safety against rewriting.
[0145]
Further, when the memory cell 200 described in the first and second embodiments is composed of a multi-value memory, the combination of “H” or “L” values written in the memory cell becomes complicated, and this complicated “H” By using the combination of “L” or “L” as an encryption key, the security against unauthorized rewriting is further increased.
Hereinafter, an example of a method of writing and reading “H” or “L” when the memory cell 200 in the figure is configured by a multi-level memory will be described.
[0146]
(Write method: Example 1)
The multilevel memory here has a control gate and a charge storage layer capable of having at least three different storage states, and stores a storage state among at least three storage states. This is a multi-valued memory cell. As such a multilevel memory, for example, an EEPROM (flash EEPROM) is used.
[0147]
First, the EEPROM will be described. The EEPROM has a configuration in which a plurality of memory cells 900 (corresponding to the memory cell 200 in FIG. 2) as shown in FIG. 7 are arranged.
As shown in FIG. 7, the memory cell 900 has a drain (a pair of impurity diffusion layers) 902 and a source 903 each formed of an n-type impurity diffusion layer formed on the surface region of the p-type silicon substrate 901. The channel region 904 is configured. Then, on the channel region 904, about 10 nm thick SiO. ₂ A tunnel insulating film 905 made of a film is formed, and a floating gate (charge storage layer) 913 made of low-resistance polysilicon, an interlayer insulating film 906, and a control gate 910 made of low-resistance polysilicon are sequentially formed thereon. Yes. A bit line 911 is connected to the drain 902, and a source line 912 is connected to the source 903.
[0148]
For example, a case where four-value data “00” to “11” is written in the EEPROM having the memory cell 900 having such a configuration will be described.
Note that “1” and “0” correspond to “H” and “L” in the first and second embodiments described above.
[0149]
When “11” is written in the target memory cell, the bit line 911 selected by the selection circuit 402 in FIG. 3 is grounded, the source line 912 is opened, and about 10 to 15 V is applied to the selected control gate (word line) 910. Is applied by the writing circuit 403 via the multiplexer 401 in FIG. As a result, a voltage is induced in the floating gate 913 of the target memory cell, and a predetermined amount of charge is injected into the floating gate 913 by Fowler-Nordheim tunneling according to the voltage difference between the floating gate 913 and the drain 902. Become. Then, the threshold value of the target memory cell rises to about 7V. This state is assumed to be “11”.
At this time, by applying a voltage of about 3 V to the bit lines of other memory cells other than the target memory cell, Fowler-Nordheim tunneling does not occur in the other memory cells, and therefore data is written. Absent.
[0150]
Similarly, when “10” is written to the target memory cell, the selected bit line 911 is grounded, the source line 912 is opened, and a pulse voltage of about 1 V is applied to the selected control gate (word line) 910. Apply. As a result, the threshold value of the target memory cell rises to about 5V. This state is assumed to be “10”.
Similarly, when “01” is written to the target memory cell, the selected bit line 911 is grounded, the source line 912 is opened, and a pulse voltage of about 2 V is applied to the selected control gate (word line) 910. Apply. As a result, the threshold value of the target memory cell rises to about 3V. This state is set to “01”.
Similarly, when “00” is written to the target memory cell, the selected bit line 911 is grounded, the source line 912 is opened, and a pulse voltage of about 3 V is applied to the selected control gate (word line) 910. Apply. As a result, the threshold value of the target memory cell rises to about 1V. This state is set to “00”.
[0151]
In order to perform the above-described write operation by the write circuit 403 in FIG. 3, the write circuit 403 may be configured as a program circuit disclosed in, for example, Japanese Patent Laid-Open No. 6-195987.
[0152]
(Write method: Example 2)
Hereinafter, the second embodiment of the writing method of the present invention will be specifically described with reference to FIG.
[0153]
In the multi-value storage EEPROM which is the object of this embodiment, the threshold voltage of each memory cell corresponds to 4-bit information (00, 01, 10, 11) to be stored (four values (0, 2, 2)). 4 and 6V), a cross error method is used in which a code C having a code length n and a burst error correction capability L is crossed m times as a burst error correction code.
[0154]
In the rewriting of this apparatus, every time 8 bits of stored contents are input from the control circuit 301 of FIG. 4, the writing circuit 403 of FIG. 3 converts this into 4 × 2 information bits (m11, m21, m31, m41) (m12, m22, m32, m42), and 3 × 2 check bits (p11, p21, p31) (p12, p22, p32) are generated from this information bit.
From these information bits (m11, m21, m31, m41) (m12, m22, m32, m42) and check bits (p11, p21, p31) (p12, p22, p32), two code words (m11, m21, m31, m41, p11, p21, p31) and (m12, m22, m32, m42, p12, p22, p32) are generated.
[0155]
The two code words generated in this way are given to the bit information distribution means provided in the writing circuit 403, and are arranged in a row in a 2 × 7 array as shown in FIG. Then, each of the seven memory cells is sequentially stored in a combination of m11 and m12, m21 and m22, m31 and m32, m41 and m42, p11 and p12, p21 and p22, and p31 and p32.
[0156]
The input information on which the information bits are rearranged is given to a voltage generation and voltage control circuit provided in the writing circuit 403, and a voltage corresponding to the information bits is generated. The generated voltage is applied to the memory cell 202 via the multiplexer 401 in FIG. 3, and a predetermined threshold voltage is set for each memory cell.
That is, in FIG. 8, the upper bit of the memory cell 1 is m11 and the lower bit is m12. Similarly, the memory cell 2 has m21 and m22, the memory cell 3 has m31 and m32, the memory cell 4 has m41 and m42, and the memory cell 5 M51 and m52, p21 and p22 in the memory cell 6, and p31 and p32 in the memory cell 7, respectively.
[0157]
As will be described later in detail, each code word can be corrected even if one error occurs. For example, the threshold voltage of the memory cell 3 changes as shown in FIG. Even if a burst error of 2 occurs, there is one error for each codeword, so correction is possible. That is, even if a burst error occurs in which the threshold voltage of one memory cell among the seven memory cells changes and, for example, the stored content of “01” changes to “10”, one code word Since the error is 1 bit, it can be corrected.
[0158]
(Write method: Example 3)
In the target device, the threshold voltage of each memory cell corresponds to three bits of information (000, 001, 010, 011, 100, 101, 110, 111) to be stored. , 1, 2, 3, 4, 5, 6, 7V).
[0159]
In the rewriting of the apparatus, every time 12 bits of stored contents are received, 4 × 3 information bits (m11, m21, m31, m41) (m12, m22, m32, m42) (m13, m23) are received. , M33, m43), and 3 × 3 check bits (p11, p21, p31) (p12, p22, p32) (p13, p23, p33) are obtained from this information bit.
[0160]
From these information bits and check bits, three code words (m11, m21, m31, m41, p11, p21, p31) (m12, m22, m32, m42, p12, p22, p32) (m13, m23, m33, m43, p13, p23, p33) are arranged in each row of a 3 × 7 array, and m11, m12, and m13, m21, m22, and m23, m31, m32, and m33, and m41, m42, and m43 are arranged in seven memory cells, respectively. , P11 and p12 and p13, p21 and p22 and p23, and p31 and p32 and p33 are stored.
[0161]
9, the upper bit of the memory cell 1 is m11 and the lower bit is m12. Similarly, the memory cell 2 has m21 and m22, the memory cell 3 has m31 and m32, the memory cell 4 has m41 and m42, and the memory cell 5 M51 and m52, p61 and p62 in the memory cell 6, and p71 and p72 in the memory cell 7, respectively.
[0162]
Each codeword can be corrected even if one error occurs. Therefore, as shown in FIG. 9, even if a burst error of length 3 occurs, one codeword is used for each codeword. Since it becomes an error, it can be corrected. That is, even if a burst error occurs in which the memory voltage of “100” changes to “011”, for example, when the threshold voltage of one memory cell changes among the seven memory cells, correction is possible. It is.
[0163]
(Modification 1 of “Write Method: Example 3”)
In the target device, the threshold voltage of each memory cell corresponds to the stored 3-bit information (000, 001, 010, 011, 100, 101, 110, 111) in eight values (0, 1, 2, 3, 4, 5, 6, 7V). In the first modification, a case where a predetermined linear coding rule capable of error correction up to two errors in each bit constituting a code word is illustrated.
[0164]
In rewriting by this apparatus, first, every time a stored content is inputted with a predetermined bit, for example, k bits, it is divided into three (k / 3) information bits. Then, a redundant bit is obtained from each information bit, a 14-bit code word (m11, m21, m31, m41, m51, m61, m71, m12, m22, m32, m42, m52, m62, m72) and 7 bits Are generated (m13, m23, m33, m43, m53, m63, m73).
That is, of the 14-bit and 7-bit codewords, a predetermined number of bits are information bits, and the rest are redundant bits for error correction.
[0165]
Next, a 14-bit code word (m11, m21, m31, m41, m51, m61, m71, m12, m22, m32, m42, m52, m62, m72) is converted into a 7-bit code string (m11, m21, m31, m41, m51, m61, m71) (m12, m22, m32, m42, m52, m62, m72). The code sequence a (m11, m21, m31, m41, m51, m61, m71) and the code sequence b (m12, m22, m32, m42, m52, m62, m72) and one code sequence c (m13, m23, m33, m43, m53, m63, m73) are arranged in each row of a 3 × 7 array, and as shown in FIG. 10 (A), m11, m12, m13, m21, m22 and m23, m31 and m32 and m33, m41 and m42 and m43, m51 and m52 and m53, m61 and m62 and m63, m71 and m72 and m73 are stored.
[0166]
That is, in FIG. 10A, the upper bit of the memory cell 1 is m11, the middle bit is m12, and the lower bit is m13. Similarly, the memory cell 2 has m21, m22, and m23, and the memory cell 3 has m31 and m32. m33, m41, m42, and m43 in the memory cell 4, m51, m52, and m53 in the memory cell 5, m61, m62, and m63 in the memory cell 6, and m71, m72, and m73 in the memory cell 7, respectively.
[0167]
The code strings a and b and the code word c can be corrected even if one error occurs. Therefore, as shown in FIG. 10A, for example, a burst of length 3 of the third memory cell Even if an error occurs, there is one error for each of the code strings a and b and the code word c. At this time, two errors are generated for the code word composed of the code strings a and b. Therefore, correction becomes possible.
That is, even if a burst error occurs in which the memory voltage of “100” changes to “011” due to a change in the threshold voltage of one of the seven memory cells, correction is possible. Become.
[0168]
(Modification 2 of “Write Method: Example 3”)
In the target device here, the threshold voltage of each memory cell corresponds to three bits of information (000, 001, 010, 011, 100, 101, 110, 111) to be stored. 1, 2, 3, 4, 5, 6, 7V). In the second modification, an example is shown in which, according to an encoding rule that can correct an error up to one error and can detect an error up to two errors in each bit constituting a code word. To do.
[0169]
In rewriting by the present apparatus, first, every time 12 bits of stored contents are received, this is converted into 4 × 3 bits of information bits (m11, m21, m31, m41) (m12, m22, m32, m42) (m13). , M23, m33, m43) and 3 × 3 redundant bits (p11, p21, p31) (p12, p22, p32) (p13, p23, p33) are obtained from this information bit by Hamming coding. .
[0170]
Subsequently, three code strings (m11, m21, m31, m41, p11, p21, p31) (m12, m22, m32, m42, p12, p22, p32) (m13, m23, m33, m43, p13, p23) , P33), EX-OR of all the bits is calculated, and the redundant bits q1, q2, q3 obtained as a result are added to each code string, and three code words (m11, m21) are obtained. , M31, m41, p11, p21, p31, q1) (m12, m22, m32, m42, p12, p22, p32, q2) (m13, m23, m33, m43, p13, p23, p33, q3) .
[0171]
These three code words are arranged in each row of a 3 × 8 array, and as shown in FIG. 10B, each of eight memory cells has m11, m12, m13, m21, m22, m23, m31, and m31, respectively. m32 and m33, m41 and m42 and m43, p11 and p12 and p13, p21 and p22 and p23, p31 and p32 and p33, q1 and q2 and q3 are stored.
[0172]
That is, in FIG. 10B, the upper bit of the memory cell 1 is m11, the middle bit is m12, and the lower bit is m13. Similarly, the memory cell 2 has m21, m22, and m23, and the memory cell 3 has m31 and m32. m33, m41, m42 and m43 in memory cell 4, p11, p12 and p13 in memory cell 5, p21, p22 and p23 in memory cell 6, p31, p32 and p33 in memory cell 7, q1 and q2 in memory cell 8 q3 is stored.
[0173]
Each codeword can be corrected even if one error occurs. Therefore, as shown in FIG. 10B, for example, even if a burst error of length 3 occurs in the third memory cell, Since each code word has one error, it can be corrected.
That is, even if a burst error occurs in which the memory voltage of “100” changes to “011” due to a change in threshold voltage of one memory cell among the eight memory cells, correction is possible. Become. Furthermore, although it seems to be extremely rare, for example, if 1 to 3 burst errors occur in another memory cell, there will be 2 errors for at least one codeword. At this time, the two errors can be detected, and one of them can be corrected.
[0174]
(Write method: Example 4)
In this apparatus, the threshold voltage of each memory cell is stored as 4-bit information (0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 110, 1110, 1111), 16 values (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15V) are set. It is a 16-value memory.
[0175]
In rewriting by this apparatus, each time 16 bits of stored contents are received, this is converted to 4 × 4 information bits (m11, m21, m31, m41) (m12, m22, m32, m42) (m13, m23, m33, m43) (m14, m24, m34, m44) and 3 × 4 redundant bits (p11, p21, p31) (p12, p22, p32) (p13, p23, p33) from this information bit ) (P14, p24, p34).
[0176]
And four code words (m11, m21, m31, m41, p11, p21, p31) (m12, m22, m32, m42, p12, p22, p32) (m13, m23, m33, m43, p13, p23, p33) (m14, m24, m34, m44, p14, p24, p34) are arranged in each row of a 4 × 7 array, and as shown in FIG. 11, m11, m12, m13, and m14 are arranged in seven memory cells, respectively. , M21, m22, m23, m24, m31, m32, m33, m34, m41, m42, m43, m44, p11, p12, p13, p14, p21, p22, p23, p24, p31, p32, p33, p34 To do.
[0177]
That is, in FIG. 11, the first bit of the memory cell 1 is m11, the second bit is m12, the third bit is m13, and the fourth bit is m14. Similarly, the memory cell 2 includes m21, m22, m23 and m24, memory M31, m32, m33, and m34 in cell 3, m41, m42, m43, and m44 in memory cell 4, p11, p12, p13, and p14 in memory cell 5, p21, p22, p23, and p24 in memory cell 6, memory cell 7 P31, p32, p33 and p34 are stored in
[0178]
Each code string can be corrected even if one error occurs. Therefore, as shown in FIG. 11, for example, even if a burst error of length 4 of the third memory cell occurs, each code string Since each column has one error, it can be corrected.
That is, even if a burst error occurs in which the memory voltage of “1000” changes to “0011” when the threshold voltage of one memory cell changes among the seven memory cells, for example, correction is possible. Become.
[0179]
(Modification 1 of “Write Method: Example 4”)
In this apparatus, the threshold voltage of each memory cell is stored as 4-bit information (0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 110, 1110, 1111), 16 values (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15V) are set. It is a 16-value memory. In the third modification, a case where a predetermined linear coding rule capable of error correction up to two errors in each bit constituting a code word is exemplified.
[0180]
In rewriting by this apparatus, first, every time a stored content receives a predetermined bit, for example, p bits, it is divided into four (p / 3) information bits. Then, redundant bits are obtained from each information bit, and two 14-bit code words (m11, m21, m31, m41, m51, m61, m71, m12, m22, m32, m42, m52, m62, m72) (m13) , M23, m33, m43, m53, m63, m73, m14, m24, m34, m44, m54, m64, m74).
That is, of each 14-bit code word, a predetermined number of bits are information bits, and the rest are redundant bits for error correction.
[0181]
Next, each 14-bit codeword (m11, m21, m31, m41, m51, m61, m71, m12, m22, m32, m42, m52, m62, m72) (m13, m23, m33, m43, m53, m63) , M73, m14, m24, m34, m44, m54, m64, m74) are each converted into a 7-bit code string (m11, m21, m31, m41, m51, m61, m71) (m12, m22, m32, m42, m52, m62, m72) and (m13, m23, m33, m43, m53, m63, m73) (m14, m24, m34, m44, m54, m64, m74). Then, the respective code strings are arranged in each row of a 4 × 7 array, and as shown in FIG. 12 (A), m11, m12, m13 and m14, m21, m22, m23 and m24, m31, m32, m33, m34, m41, m42, m43, m44, m51, m52, m53, m54, m61, m62, m63, m64, m71, m72, m73, and m74 are stored.
[0182]
That is, in FIG. 12A, the first bit of the memory cell 1 is m11, the second bit is m12, the third bit is m13, and the fourth bit is m14. Similarly, the memory cell 2 has m21, m22, and m23. m24, m31, m32, m33, and m34 in memory cell 3, m41, m42, m43, and m44 in memory cell 4, m51, m52, m53, and m54 in memory cell 5, m61, m62, m63, and m64 in memory cell 6, M71, m72, m73, and m74 are stored in the memory cell 7.
[0183]
Each code string can be corrected even if one error occurs. Therefore, as shown in FIG. 12A, for example, even if a burst error of length 4 of the third memory cell occurs. Each code string has one error, and at this time, each code word composed of two code strings has two errors, which can be corrected.
That is, even if a burst error occurs in which the memory voltage of “1000” changes to “0011” when the threshold voltage of one memory cell changes among the seven memory cells, for example, correction is possible. Become.
[0184]
(Modification 2 of “Write Method: Example 4”)
In this apparatus, the threshold voltage of each memory cell is stored as 4-bit information (0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 110, 1110, 1111), 16 values (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15V) are set. It is a 16-value memory. In the fourth modification, an example is shown in which, according to an encoding rule that can correct an error up to one error and can detect an error up to two errors in each bit constituting a code word. To do.
[0185]
In rewriting by the present apparatus, first, every time the stored content receives 16 bits, this is converted to 4 × 4 information bits (m11, m21, m31, m41) (m12, m22, m32, m42) (m13). , M23, m33, m43) (m14, m24, m34, m44), and 3 × 4 redundant bits (p11, p21, p31) (p12, p22, p32) from this information bit by Hamming coding. (P13, p23, p33) (p14, p24, p34) is obtained.
[0186]
Subsequently, four code strings (m11, m21, m31, m41, p11, p21, p31) (m12, m22, m32, m42, p12, p22, p32) (m13, m23, m33, m43, p13, p23) , P33) (m14, m24, m34, m44, p14, p24, p34), the EX-OR of all the bits is calculated, and the redundant bits q1, q2, q3, q4 obtained as a result are calculated. In addition to each code string, four code words (m11, m21, m31, m41, p11, p21, p31, q1) (m12, m22, m32, m42, p12, p22, p32, q2) (m13, m23, m33, m43, p13, p23, p33, q3) (m14, m24, m34, m44, p14, p24, p34, q4) are created.
[0187]
These four code words are arranged in each row of a 4 × 8 array, and as shown in FIG. 12 (B), m11, m12, m13, m14, m21, m22, m23, m24, m31, m32, m33, m34, m41, m42, m43, m44, p11, p12, p13, p14, p21, p22, p23, p24, p31, p32, p33, p34, q1, q2, q3, and q4. Remember.
[0188]
That is, in FIG. 12B, the first bit of the memory cell 1 is m11, the second bit is m12, the third bit is m13, and the fourth bit is m14. Similarly, the memory cell 2 has m21, m22, and m23. m24, m31, m32, m33, and m34 in the memory cell 3, m41, m42, m43, and m44 in the memory cell 4, p11, p12, p13, and p14 in the memory cell 5, p21, p22, p23, and p24 in the memory cell 6, The memory cell 7 stores p31, p32, p33, and p34, and the memory cell 8 stores q1, q2, q3, and q4.
[0189]
Each code word can be corrected even if one error occurs. Therefore, as shown in FIG. 12B, for example, even if a burst error of length 4 occurs in the third memory cell, Since each code word has one error, it can be corrected.
That is, even if a burst error occurs in which the memory voltage of “1000” changes to “0111” due to a change in threshold voltage of one of the eight memory cells, for example, correction is possible. Become. Furthermore, although it seems to be extremely rare, for example, if one to four burst errors occur in another memory cell, there will be two errors for at least one codeword. At this time, the two errors can be detected, and one of them can be corrected.
[0190]
In addition to the encoding methods shown in the third and fourth modifications, there are methods that are considered useful.
For example, 56 bits of “0” data are first added to 64 original data to obtain information bits having a total length of 120 bits. Subsequently, a 127-bit Hamming code is created from 120 information bits. Subsequently, EX-OR of all 127 bits is calculated, and an additional 128-bit code is obtained from the result. Thereafter, the previously added 56-bit “0” is removed to obtain a 72-bit codeword.
In such an encoding method, error correction is possible for up to one error in each bit constituting a code word, and error detection is possible for up to two errors. / DED code (single-error-correcting / double-error-detecting code) is frequently used.
[0191]
Here, a specific example will be described in which one codeword can be corrected even if one error occurs. Table 1 below shows a Hamming code in which 3 check bits are added to 4 information bits.

[0192]
In this code, the 1st, 2nd, and 4th digits are check bits, and each digit of (1, 3, 5, 7), (2, 3, 6, 7) and (4, 5, 6, 7) The check bits are determined so that the parity becomes even parity. For example, when the code “0111100” corresponding to the decimal number “12” is written and an error occurs and “0101100” is read, as shown in Table 1, the digit with the error is displayed. Since it can be obtained as a binary number (in this case, 011), it can be easily and reliably corrected even if an error occurs.
[0193]
This code can be extended to a case where the number of information bits is larger, and the required number m of check bits for n information bits is expressed by the following equation.
2m = n + m + 1 (1 formula)
[0194]
In the above description, the case where the present invention is applied to a nonvolatile memory device having a floating gate type memory cell has been described as an example. However, as a memory cell for performing multi-value storage, a floating gate type memory cell is used. However, the MNOS type may be used. In addition to the EEPROM, the present invention also provides a mask for obtaining a memory state by changing the threshold value by controlling the amount of impurities ion-implanted into the channel region of the field effect transistor, in addition to the EEPROM and PROM. It can also be applied to ROM. Moreover, although the case of 4-value and 8-value was mentioned as an example, it is not limited to this value by any means.
[0195]
Furthermore, the writing method of the present invention can also be applied to a DRAM. In this case, needless to say, precharge is performed at the time of writing.
[0196]
In addition, the crossing method has been described as an example of a method for obtaining an error correction code, but any method other than the crossing method may be used as long as the error correction code can correct a burst length error according to the amount of information stored in the memory cell. It may be a cyclic code or a shortened cyclic code.
[0197]
On the other hand, in order to read the data written in the memory cell as described above in step S400 of FIG. 5 and step S402 of FIG. 6 as described above, the sense circuit 404 of FIG. What is necessary is just to comprise.
Hereinafter, an operation of reading data written in the memory cell by the sense circuit 404 shown in FIG. 13 as an encryption key will be described.
[0198]
A threshold voltage Vth1 corresponding to the lower bit set in the memory cell 202 configured as a multi-level memory is applied to the inverting input terminal of the sense amplifier 43 through an output buffer including the inverter 40 and the transistors 41 and. A determination voltage V47 set in the transistor 47 is applied to the non-inverting input terminal of the sense amplifier 43 via an output buffer including an inverter 46 and transistors 44 and 45.
[0199]
When the threshold voltage Vth1 is smaller than the determination voltage V47, the output of the sense amplifier 43 becomes High, so that the lower bit D0 stored in the memory cell 202 is determined to be “1”. Since the output of the sense amplifier 43 is High, the transistor 52 is turned on, while the transistor 54 is turned off by the inverter 53. Therefore, the determination voltage V52 set in the transistor 52 is applied to the non-inverting input terminal of the sense amplifier 48 through the output buffer including the inverter 51 and the transistors 49 and 50. A threshold voltage Vth 2 corresponding to the upper bit set in the memory cell 202 is applied to the inverting input terminal of the sense amplifier 48 via the output buffer 1.
[0200]
When the threshold voltage Vth2 is smaller than the determination voltage V52, the output of the sense amplifier 48 becomes High, so that the upper bit D1 stored in the memory cell 202 is determined to be “1”. On the other hand, when the threshold voltage Vth2 is larger than the determination voltage V52, the output of the sense amplifier 48 becomes Low, so the upper bit D1 stored in the memory cell 202 is read as “0”.
[0201]
Further, when the threshold voltage Vth1 is larger than the determination voltage V47, the output of the sense amplifier 43 becomes Low, so the lower bit D0 stored in the memory cell 202 is determined to be “0”. Since the output of the sense amplifier 43 is Low, the transistor 52 is turned off, while the transistor 54 is turned on by the inverter 53. Therefore, the determination voltage V54 set in the transistor 52 is applied to the non-inverting input terminal of the sense amplifier 48 via the output buffer. Then, a threshold voltage Vth2 corresponding to the upper bit set in the memory cell 202 is applied to the inverting input terminal of the sense amplifier 48 via the output buffer.
[0202]
When the threshold voltage Vth2 is smaller than the determination voltage V54, the output of the sense amplifier 48 becomes High, so that the upper bit D1 stored in the memory cell 202 is read as “1”. On the other hand, when the threshold voltage Vth2 is larger than the determination voltage V54, the output of the sense amplifier 48 becomes Low, so that the upper bit D1 stored in the memory cell 202 is read as “0”.
[0203]
In this way, the values read out in step S400 in FIG. 5 and step S402 in FIG. 6 are stored as encryption keys in the memory 304 shown in FIG.
[0204]
In the first and second embodiments, the case where an EEPROM memory cell is used as the memory cell 200 has been described. For example, an FRAM (ferroelectric) multivalue disclosed in JP-A-8-124378 is described. Memory cells may be used.
Specifically, each of the memory cells 200 of FIG. 2 is configured by a field effect transistor (FEMFET) using a ferroelectric film as a gate insulating film, and the polarization state of the ferroelectric film changes to change the memory cell. By utilizing the change in threshold voltage, three values “H”, “L”, and “−H” are stored in each memory cell. By using an FRAM (ferroelectric) memory cell as the memory cell 200, a more complicated encryption key than that of the EEPROM memory cell can be formed, and the security against unauthorized rewriting by a third party is further increased.
Further, as the memory cell 200, a multi-value memory cell using MNOS, mask ROM, EPROM, PROM, or flash nonvolatile memory may be used.
[0205]
(3) Third embodiment
The present embodiment is different from the first and second embodiments described above in that the rewrite control circuit 103 is configured as shown in FIG. 14, for example.
Here, only the points different from the first embodiment will be specifically described.
[0206]
In other words, in this embodiment, the rewrite control circuit 103 includes a control circuit 311 to which a command signal from the signal line 105 is supplied, a program memory 312 in which a control program for the control circuit 311 is stored, and a logic integrated circuit. And a pattern memory 313 for storing a plurality of types of pattern data (reference signals) of command signals for the purpose of destroying the logic of 100.
In the program memory 312, for example, a control program according to a flowchart shown in FIG. 15 is set in advance, and the control program 311 is read and executed by the control circuit 311, whereby the rewrite control circuit 103 operates as follows.
[0207]
First, the control circuit 311 determines whether or not a rewrite command signal is input from the outside via the signal line 105 (step S411). If the rewrite command signal is input, the control circuit 311 proceeds to the next step S412. If not input, a rewrite command signal input wait state is entered.
[0208]
In step S412, the control circuit 311 receives the input rewrite command signal.
[0209]
Then, the control circuit 311 determines whether or not there is pattern data corresponding to the rewrite command signal received in step S412 among a plurality of types of pattern data stored in the pattern memory 313 (step S413). .
Specifically, the pattern memory 313 stores in advance a plurality of types of pattern data corresponding to signals considered as rewrite command signals (viruses) for the purpose of destroying the logic of the logic integrated circuit 100. By comparing the pattern data of the pattern memory 313 and the pattern data of the received rewrite command signal, it can be determined whether or not the rewrite command signal is a rewrite command signal (virus).
[0210]
If there is pattern data corresponding to the received rewrite command signal as a result of the determination in step S413, the control circuit 311 receives a rewrite command signal (virus) for the purpose of destroying the logic of the logic integrated circuit 100. It recognizes that it has been performed, invalidates the rewrite command signal (virus), returns to the above-described step S411 without performing anything, and repeats the subsequent step processing.
[0211]
On the other hand, if the result of determination in step S413 is that there is no pattern data corresponding to the received rewrite command signal, the control circuit 311 validates the received rewrite command signal and, according to the rewrite command signal, a plurality of EEPROM memory cells. 202 is rewritten (step S415), the process returns to the above-described step S411, and the subsequent step processing is repeatedly executed.
[0212]
As described above, in this embodiment, when a rewrite command signal is received from the outside, it is determined whether or not this rewrite command signal is a rewrite command signal (virus) for the purpose of destroying the logic of the logic integrated circuit 100. Only when the result of the determination is not a rewrite command signal (virus), the plurality of EEPROM memory cells 202 are rewritten.
With this configuration, even if a rewrite command signal (virus) for the purpose of destroying the logic of the logic integrated circuit 100 is input to the logic integrated circuit 100, the rewrite command signal is a rewrite command signal (virus). Since the plurality of EEPROM memory cells 202 are not rewritten, the logic of the logic integrated circuit 100 cannot be illegally rewritten.
Therefore, in the present embodiment as well, it is possible to reliably prevent logic destruction due to unauthorized rewriting of the logic integrated circuit 100, so that the rewritable logic integrated circuit 100 is durable against logic destruction. Can be provided. The pattern data stored in the pattern memory 313 is further stored in the pattern memory 313 as soon as a new virus pattern is found, thereby further enhancing the durability against logic destruction.
[0213]
In the first, second, and third embodiments described above, the logic integrated circuit 100 is an EEPROM type. However, the present invention is not limited to this. For example, an SRAM type may be used.
[0214]
(4) Fourth embodiment
The semiconductor device having a security function according to the present invention is applied to a semiconductor device 500 as shown in FIG. 16, for example.
[0215]
As shown in FIG. 16, the semiconductor device 500 includes a storage device 501 including a mask ROM 501a and an EEPROM 501b, so that the area required for storing information can be reduced and the stored contents can be rewritten. Both are possible in a well-balanced manner. The encrypted confidential data is stored in the mask ROM 501a. Since the contents stored in the mask ROM 501a are encrypted, it is almost impossible to decrypt the stored contents even if the structure is analyzed using a microscope or the like.
[0216]
In addition, the semiconductor device 500 includes an SRAM type FPGA (Field Programmable Gate Array) 502 and a CPU (Central Processing Unit) 503 which is a processing unit.
[0217]
Here, the FPGA is a large-scale PLD (Programmable Logic Device) that has come to be widely used as a general-purpose logic integrated circuit, and the user has the logic to calculate the input data and obtain the output data. This is a circuit that can be programmed automatically, that is, a logic integrated circuit that can electrically rewrite logic, and is a high-speed circuit that performs hardware operations.
Therefore, the FPGA 502 has the same configuration as that of the logic integrated circuit 100 in the first, second, and third embodiments, and has a logic defense function as described above.
Note that the configuration and function of the FPGA 502 are the same as those of the logic integrated circuit 100 in the first, second, and third embodiments, and thus detailed description thereof is omitted.
[0218]
Further, an external device 600 that is an external output destination of stored data is connected via an output terminal 509.
The external device 600 is provided with a storage / reproduction device 601 and a storage medium 602.
[0219]
The method of decrypting the confidential content data stored in the mask ROM 501a is that the FPGA 502 uses the logical address AD-1 used by the CPU 503 to the structural address of the mask ROM 501a (encrypted and stored at different positions). An address for decoding and reading a group of data) is converted into AD-2. That is, as will be described later, the FPGA 502 receives the logical address AD-1 output from the CPU 503, converts it to the address AD-2 in the structure of the mask ROM 501a, and outputs it to the mask ROM 501a.
[0220]
Below, an example of operation | movement of the semiconductor device 500 is demonstrated based on the flowchart of FIG.
[0221]
In FIG. 17, when the power is turned on in step S701 and the semiconductor device 500 is connected to the external output destination of the stored content, the CPU 503 operates in step S702 and sets the external output destination of the stored content in the FPGA 502. Requests to specify a program P for logical operation.
[0222]
In response to this request, the storage / reproduction device 601 reproduces the program data read from the storage medium 602 and transmits it to the semiconductor device 500.
Next, when the data I / O unit 504 receives the program in step S703, the CPU 503 outputs a logical operation program P for programming the FPGA 502 while interpreting the data received in step S504.
[0223]
The FPGA 502 determines whether or not the logic of the FPGA 502 has been destroyed by the logic operation program P (for example, if it was a virus program) that programs the FPGA 502, or the program P By determining whether or not the program is intended to destroy the logic of the FPGA 502 such as a program, the logic of the FPGA 502 is surely prevented from being destroyed. As a result, when illegal data is input, the data stored in the semiconductor device 500 cannot be output correctly. The program of the FPGA 2 corresponds to the above-described command signal, and is performed by arbitrarily assembling an AND circuit or an OR circuit by turning on or off a number of previously arranged transistors.
[0224]
By the way, in a logic circuit in which a fixed logic is assembled in advance, an AND circuit and an OR circuit can be identified by tracing the wiring of the gate array using a microscope or the like, and the logic set in the logic circuit can be easily determined. Can be deciphered.
[0225]
On the other hand, when the FPGA 502 having a logic defense function is used as in this embodiment, since arbitrary logic is assembled later depending on the presence or absence of the charge charged in the transistor, the structure is analyzed using a microscope or the like. However, it is almost impossible to decipher the set logic, and it is almost impossible to destroy the logic.
[0226]
When this program ends, the CPU 503 transmits a signal indicating that data output is enabled in step S705 to the external output destination via the data I / O unit 504. Correspondingly, output of data at a certain address is requested from the external output destination, and when the data I / O unit 504 receives the address in step S6, the CPU 503 outputs the received address AD-1 to the FPGA 502. To do.
[0227]
Then, in step S7, the FPGA 502 calculates the structural address AD-2 of the mask ROM 501a based on the logical address AD-1 based on the program set in step S704, and stores it in the mask ROM 501a. Output.
In the next step S708, the mask ROM 501a outputs the data D to the CPU 3 in accordance with the structural address AD-2 calculated by the FPGA 502. The CPU 503 outputs the input data D to an external output destination via the data I / O unit 504.
[0228]
As described above, in the fourth embodiment, since the FPGA 502 is used to decrypt the encrypted storage content, data can be output at high speed after the program of the FPGA 502 is completed. Moreover, since the CPU 503 only outputs data during the data output, the CPU 503 can perform other calculations. In this case, it goes without saying that the CPU 503 can perform unique data processing using the data stored in the mask ROM 501a. Further, since the FPGA 502 has a smaller circuit scale and can be easily integrated than an EEPROM, the semiconductor device 500 can be provided at a low cost.
[0229]
In addition, since the FPGA 502 is provided with a logic defense function, the logic set in the FPGA 502 is surely prevented from being destroyed. Therefore, an accurate operation in the semiconductor device 500 can always be ensured. 500 can be provided with higher performance.
[0230]
In this embodiment, an SRAM type FPGA 502 is used. In this case, since the stored data of the FPGA 502 is destroyed when the power is turned off, the program of the FPGA 502 must be restarted when the power is turned on again. However, this problem can be avoided by using an EEPROM type FPGA instead of an SRAM type FPGA.
[0231]
Hereinafter, an example of the encryption operation for storing the encrypted data in the EEPROM 501b shown in FIG. 16 will be described based on the flowchart of FIG.
[0232]
In FIG. 18, when the power is turned on in step S710 and the semiconductor device 500 is connected to an external input source of data to be stored, for example, connected to the storage / playback device 601 and the storage medium 602, the CPU 503 in step S711. Operates and requests the external input destination to specify a logic operation program to be set in the FPGA 502.
[0233]
In response to this request, the storage / reproduction device 601 reproduces program data from the storage medium 602 and transmits it to the semiconductor device. Next, when the program is received by the data I / O unit 504 in step S712, the CPU 503 programs the FPGA 502 while interpreting the data received in step S713.
Note that, as described above, the FPGA 502 has the above-described logic defense function. Therefore, when invalid data is input, the FPGA 502 is not in a state where data can be correctly input to the semiconductor device 500.
[0234]
When this program ends, the CPU 503 transmits a signal indicating that data output is possible to the external output destination via the data I / O unit 504 in step S714. In response to this, input of data at an address from the external input source is requested, and when the logical address AD-1 is received by the data I / O unit 504 in step S715, the CPU 503 receives the received logical address. The address AD-1 is output to the FPGA 502.
[0235]
Then, in step S716, the FPGA 502 calculates the address AD-2 in the structure of the EEPROM 501b from the logical address AD-1 based on the program set in step S704 (FIG. 20), and calculates it as the EEPROM 501b. Output to. In the next step S717, data is input from the external input source to the CPU 503 via the data I / O unit 504, and stored in the EEPROM 501b as a structural address AD-2.
If the user changes the encryption key from the outside, it may be stored in the FPGA 502.
[0236]
As described above, since the semiconductor device 500 uses the FPGA 502 having the logic defense function to encrypt data to be stored, the data can be input at high speed after the program of the FPGA 502 is completed. Can always guarantee its correct operation. In addition, since the CPU 503 is not used during the data input, the CPU 503 can perform other calculations.
[0237]
Here, an example of a method for calculating the structural address AD-2 by the FPGA 502 in step S716 will be described.
[0238]
For example, it is assumed that the addresses of the EEPROM 501b are from 0000h to FFFFh. In this case, there are permutations of data to be stored according to the capacity of the EEPROM 501b, from 0000h to FFFFh. Then, the permutation of data to be stored is rearranged based on a certain rule and stored in the EEPROM 501b.
[0239]
As a specific data rearrangement method, as shown in Table 1 below, for example, ABABh is displayed in binary for the data of ABABh (1010 1011
1010 1011) 2, and this value is further left shifted to (0101 0111 0101 0111) 2. That is, they are rearranged to the 5757hth.
[0240]
[Table 1]

[0241]
With a new permutation generated by rearrangement, data given from the outside is stored in each address of the EEPROM 501b via the data I / O unit 504 and the CPU 503. Therefore, the permutation of data stored in the EEPROM 501b is encrypted differently from the permutation of the original data, and it is difficult to decrypt the original data.
[0242]
In order to decrypt the encrypted data stored in the storage device 600 (step S707 in FIG. 8), the data is shifted left from the logical address AD-1 input from the CPU 503 to the FPGA 502. If the address AD-2 is calculated and a program for decoding the address is written in the FPGA 502, the data decoded by this program can be read out.
[0243]
As a further method of rearranging the specific data, for example, in the above-mentioned Table 1, for the data of the address ABABh, the address ABABh is displayed in binary (1010 1011 1010 1011) 2 and this value is determined appropriately. The value (0110 1101 0101 1100) 2 obtained by exclusive OR with the random number (1100 0110 1111 0111) 2, that is, rearranged to the 6B5Ahth.
[0244]
Then, the data given from the outside is stored in each address of the EEPROM 501b via the data I / O unit 504 and the CPU 503 in a new permutation generated by rearrangement.
[0245]
For example, when storing personal information, if there are many requests for adding new personal information or modifying existing personal information, the capacity of the mask ROM 501a is reduced and the storage capacity of the EEPROM 501b By increasing the size, it is possible to increase the rewritable memory area. Note that a volatile memory such as a DRAM can be used instead of the EEPROM 501b.
[0246]
In the above-described encryption / decryption process, when the EEPROM 501b is used, an addressing program may be written in the FPGA 502.
[0247]
An information processing apparatus using an FPGA is disclosed in, for example, Japanese Patent Laid-Open No. 7-168750. In this apparatus, an FPGA is connected to a memory in which program data is stored, and the logic circuit of the FPGA is controlled according to the program data stored in the memory under the control of the CPU.
[0248]
However, as shown in FIG. 1 of the above publication, this apparatus merely performs data communication between the CPU and peripheral devices using an FPGA stored in the memory, as in this embodiment. The encryption / decryption program is held in the FPGA. And it is not disclosed that the data encrypted by the FPGA programmed with the data given from the CPU is stored in the memory and the stored encrypted data is decrypted.
Also, it is not disclosed that an FPGA always has a logical defense function to always guarantee an accurate operation in the apparatus.
[0249]
(5) Fifth embodiment
The semiconductor device having a security function according to the present invention is applied to a semiconductor device 510 as shown in FIG. 19, for example.
[0250]
As shown in FIG. 19, the semiconductor device 510 includes a storage device 511 composed of a mask ROM 511a and an EEPROM 511b, an FPGA 512, and a CPU 513, like the semiconductor device 500 in the fourth embodiment described above. The FPGA 512 is used as an interface circuit for encrypting or decrypting data.
Further, the FPGA 512 has a logical defense function, like the FPGA 502 in the fourth embodiment.
[0251]
The present embodiment is different from the fourth embodiment in that the address specified by the external output destination is directly input from the CPU 513 to the storage device 511 and is output from the storage device 511 according to the address. Data D-2 is converted to logical data D-1 by the FPGA 512 and input to the CPU 513.
[0252]
That is, in the present embodiment, the method for decrypting confidential data stored in the storage device 511 is the structural data (data that remains encrypted) D that the FPGA 512 has read from the mask ROM 511a. -2 to the logical data D-1 used by the CPU 513.
[0253]
In other words, the FPGA 512 receives the structural data D-2 from the mask ROM 511a, converts it into logical data D-1 of the CPU 513, and outputs it to the CPU 513.
[0254]
The operation of the semiconductor device 510 is the same as that in steps S701 to S705 of FIG. 12 until the power is turned on and data output is possible. However, in the fourth embodiment, the subsequent operation is different from that of the third embodiment.
[0255]
That is, as shown in FIG. 20, when an output of data at an address is requested from an external output destination, and the address is received by the data I / O unit 514 in step S706a, the CPU 513 outputs the received address to the FPGA 512. To do.
[0256]
Then, the FPGA 512 calculates logical data in step S707a based on the program set in step S704. In the next step S708, the calculated logical data is stored in the address of the EEPROM 511b given from the CPU 513.
[0257]
On the other hand, as shown in FIG. 21, when an output of data at a certain address is requested from the FPGA 512 and the address is received by the data I / O unit 514 in step S715a, the CPU 513 stores the received address AD in the storage device 511. Output.
[0258]
Then, the FPGA 512 calculates the structural data D-2 in step S716a based on the program set in step S713. In the next step S717, the structural data D-2 is stored at the address given from the CPU 513 of the EEPROM 511b.
[0259]
As described above, in the fifth embodiment, since the FPGA 512 having the logic defense function is used to encrypt the data to be stored, the data is input at high speed after the program of the FPGA 512 is completed. And its precise operation can always be guaranteed. Moreover, since the CPU 513 only inputs data while outputting the data, the CPU 513 can perform other calculations.
[0260]
Here, an example of a structural data calculation method by the FPGA 512 performed in step S716a of FIG. 21 will be described.
[0261]
It is assumed that one word (word length) is taken out for one address of the EEPROM 511b, and 16-bit data is included in one word. The 16-bit data is rearranged based on a certain rule and stored in the EEPROM 511b.
[0262]
For example, with respect to 16-bit data ABABh, ABABh is binary-displayed to be (1010 1011 1010 1011) 2, and this value is further left-shifted to (0101 0111 0101 0111) 2. That is, the data 5757h is stored in the EEPROM 511b.
[0263]
As a result, the data stored in the EEPROM 511b is encrypted differently from the original data, and it is difficult to decrypt the original data. In order to decrypt the encrypted data stored in the EEPROM 511b (step S707a in FIG. 15), a program for shifting the obtained 16-bit data to the left is written in the FPGA 512. The decrypted data can be read out.
[0264]
In the fifth embodiment, similarly to the fourth embodiment, the rewritable EEPROM 511b has a storage capacity that is rewritable in order to meet the needs of the user to electrically rewrite the stored contents. It is also possible to enlarge it. In this case, an encryption program may be set in the FPGA 512, and the data supplied from the CPU 513 may be encrypted by the FPGA 512 and supplied to the EEPROM 511b.
[0265]
Further, when data is written in the EEPROM 511b of FIG. 19 in the encryption / decryption processing, an addressing program may be written in the FPGA 512.
[0266]
Also, in the fifth embodiment, an SRAM type is used as the FPGA 512. However, in this case, the stored data of the FPGA 512 is destroyed when the power is turned off, so that the FPGA 512 is turned on when the power is turned on again. The program must be redone. However, this problem can be avoided by using an EEPROM type FPGA instead of an SRAM type FPGA.
[0267]
In this case, a code is assigned to each of a plurality of programs to be programmed into the FPGA 512, and when programming into the FPGA 512, the FPGA 512 is programmed according to one program selected from the plurality of programs. At this time, the program code is also stored.
[0268]
When accessing the once programmed FPGA 512, the stored program code is first output to the external device through the CPU 513, and the external device accesses the semiconductor device 510 by changing the access method based on the program code. In other words, the semiconductor device 510 and the external device can use the program code as a common key, and can decrypt the secret information in cooperation.
[0269]
For example, the external device applies a bit shift by a predetermined bit to the address of 1 byte and supplies it to the semiconductor device 510. The FPGA 512 can be used for encryption by bit-shifting it in the reverse direction to obtain an address for the storage device 511.
[0270]
In this case, even if the content itself stored in the EEPROM 511b is common, a plurality of encryptions can be achieved by changing the bit shift amount at the time of writing the FPGA 512, and the confidentiality can be further improved by frequently rewriting the FPGA 512. In actual encryption, more complicated conversion is performed on the peripheral device side, not simple conversion such as bit shift and reverse shift.
[0271]
Further, in the semiconductor devices 500 and 510 shown in FIGS. 16 and 19, unencrypted data is stored in the storage devices 501 and 511, and is encrypted and output by the FPGA 502 and the FPGA 512. It is also possible. For example, this method can be applied when it is necessary to encrypt the communication content in order to prevent the communication performed between the semiconductor device and the external output destination from being intercepted and leaking the confidential content.
[0272]
In this case, for example, in the fourth embodiment, encryption of confidential data output from the CPU 503 to the external output destination via the data I / O unit 504 is performed as follows.
For example, the CPU 503 sets a program for performing encryption in the FPGA 502 while interpreting data received from an external output destination. Then, the FPGA 502 may perform the conversion by converting the logical address AD-1 supplied from the CPU 503 into the structural address AD-2.
[0273]
Further, for example, in the fifth embodiment, encryption of confidential data output from the CPU 513 to the external output destination via the data I / O unit 514 is performed as follows.
For example, the CPU 513 sets a program for encryption in the FPGA 20 while interpreting data received from an external output destination. Then, the FPGA 512 performs encryption by converting the structural data (not encrypted) D-2 read from the mask ROM 511a into the logical data (encrypted data) D-1 used by the CPU 513. I do.
[0274]
(6) Sixth embodiment
As the sixth embodiment, by combining the fourth embodiment and the fifth embodiment described above, an operation for encrypting and decrypting both an address and data with an FPGA is performed, and the operation is performed. Can be thought of as a device that guarantees that it always performs accurately.
This case can be realized by providing the address conversion FPGA 5022 shown in FIG. 16 and the data conversion FPGA 512 shown in FIG. 14, and setting an appropriate program for each of them.
[0275]
(7) Seventh embodiment
A semiconductor device having a security function according to the present invention is applied to a semiconductor device 800 as shown in FIG. 22, for example.
[0276]
In the semiconductor device 800, as shown in FIG. 22, an RF unit 810 and an antenna circuit 820 are provided in the semiconductor device 510 shown in FIG.
In this embodiment, an EEPROM 511b for storing variable data is provided as the storage device 511 in addition to the mask ROM 511a. Also in this embodiment, the FPGA 512 has a logic defense function.
[0277]
The antenna circuit 820 includes a parallel resonance circuit including a coil 821 and a capacitor 822, and has a function of receiving power from a semiconductor device (not shown) from a terminal device and a function of transmitting / receiving a data signal to / from the terminal device. For example, wireless signal transmission is possible using a carrier signal having a high frequency of 1 MHz or higher.
[0278]
With such a configuration, when a radio wave is received from the terminal through the coil 821, the received power is supplied to the RF unit 810. The RF unit 810 is a circuit provided for performing high frequency processing, generates a power supply voltage to be used internally from the supplied received power, demodulates a signal component included in the received power, and demodulates the demodulated signal. Is output to the I / O unit 514. The operation after the I / O unit 514 is the same as the operation described above.
[0279]
On the other hand, when a signal is output from the semiconductor device 800, the operation is the reverse of the above-described operation. That is, the RF unit 810 generates a high-frequency current by superimposing the signal component supplied from the I / O unit 514 on the carrier. The generated high-frequency current is supplied to the antenna circuit 820 and transmitted to the terminal.
When transmitting / receiving a signal to / from the terminal, the semiconductor device 800 can obtain transmission power because operating power is transmitted from the terminal.
[0280]
As described above, the semiconductor device 800 in this embodiment can transmit and receive data without contact with a terminal, and thus can be suitably used as a semiconductor device incorporated in a contactless IC card. .
Further, since the FPGA 512 is provided with a logic defense function, it can be suitably used as a semiconductor device that reliably prevents destruction of stored contents due to illegal data from the outside and always guarantees an accurate operation.
[0281]
For example, when it is used as a commuter pass for transportation, it can pass through the ticket gate, which is a terminal, in a non-contact manner, making the traffic smoother and greatly reducing the congestion at the ticket gate during rush hours. It becomes like this. As described above, when used as a commuter pass, it is necessary to rewrite data stored therein, such as the expiry date of the commuter pass.
In this case, destruction of the stored contents of the commuter pass can be surely prevented. For example, it is possible to prevent a third party from rewriting the stored content and using it illegally.
[0282]
As shown in FIG. 17, the semiconductor device 800 of this embodiment has an EEPROM 511b in addition to the mask ROM 511a. Therefore, by storing variable data in the EEPROM 511b, the semiconductor device 800 can be repeated any number of times. Can be used.
In addition, since rewriting data can be performed in a non-contact manner, there is an advantage that it is easy to maintain the secret of the built-in data as compared with the case where data is transmitted and received through a metal contact.
[0283]
In the case of this embodiment, since the terminal 830 is provided, it can be used well as an IC card used in contact with the terminal.
In FIG. 17, the antenna circuit 820 is shown protruding from the apparatus body, but the antenna circuit 820 is actually disposed on the surface of the apparatus body.
[0284]
In order to realize the above-described embodiment, a device (CPU or computer) in an apparatus or system connected to each device is operated so that each device shown in FIGS. 3, 16, 19, and 22 is operated. MPU), which is implemented by supplying software program codes for implementing the above-described embodiments and operating the devices in accordance with the programs stored in the computer, also falls within the scope of the present invention.
[0285]
In this case, the program code of the software itself realizes the above-described embodiment, and the program code itself and means for supplying the program code to a computer, for example, a storage medium storing the program code is provided. This constitutes the present invention.
[0286]
For example, in FIG. 3, a storage / reproduction device 304 and a storage medium 305 are connected to the control circuit 301. The program code stored in the storage medium 305 is read out by the storage / reproduction device 304 and the control circuit 301 is operated.
Further, in FIG. 16, a storage / reproduction device 601 and a storage medium 602 provided at an external output destination (external input destination) are connected to the CPU 503 via a data I / O unit 504. The program code stored in the storage medium 602 is read out by the storage / playback device 601 and the CPU 503 is operated via the data I / O unit 504.
[0287]
As the storage medium for storing the program code, for example, a floppy disk, a hard disk, an optical disk, a CD-ROM, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.
[0288]
【The invention's effect】
As described above, according to the present invention, it is possible to provide an electrically rewritable logic integrated circuit having a logic defense function and having durability against logic destruction. In addition, a device including a rewritable logic integrated circuit can be provided with a function of always guaranteeing an accurate operation.
[0289]
In addition, it comprises storage means, control means (central processing unit, etc.), and electrically rewritable logic means, and the logic means has a logic defense function and is durable against logic destruction. is there. Then, at the time of encryption / decryption, the logic means is rewritten in accordance with the encryption / decryption program set by the control means, and the logic is rewritten and input to the storage means. Since the encryption of data and the decryption of the encrypted data are performed, the configuration that prevents the logic from being decrypted by the structural analysis can be realized on a smaller scale than before, and the accuracy at that time Can always be guaranteed. In addition, since the logic set in the logic means is executed by hardware, the processing can be speeded up, and other processing can be performed by the control means during the processing. As a result, it is possible to provide a low-cost semiconductor device that has a function for maintaining confidentiality of stored contents and a function that always guarantees an accurate operation, and that can operate at high speed.
[0290]
Furthermore, since data can be transmitted / received to / from the terminal without contact, it is possible to eliminate the risk of unexpectedly reading or destroying data stored therein. Thereby, for example, a semiconductor device suitable for use in an IC card can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a logic integrated circuit to which the present invention is applied in a first embodiment.
FIG. 2 is a circuit diagram showing a configuration of a PIA of the logic integrated circuit.
FIG. 3 is a circuit diagram showing a configuration of each memory cell of the PIA.
FIG. 4 is a block diagram showing a configuration of a rewrite control circuit of the logic integrated circuit.
FIG. 5 is a flowchart for explaining an example of a processing program executed by the rewrite control circuit in the first embodiment;
FIG. 6 is a flowchart for explaining an example of a processing program executed by the rewrite control circuit in the second embodiment;
FIG. 7 is a cross-sectional view showing the structure of an EEPROM memory cell.
FIG. 8 is a diagram for explaining an example (Example 2) of a writing method to which the present invention is applied;
FIG. 9 is a diagram for explaining an example (Example 3) of a writing method to which the present invention is applied;
FIG. 10 is a diagram for explaining Modifications 1 and 2 of the writing method (Example 3);
FIG. 11 is a diagram for explaining an example (Example 4) of a writing method to which the present invention is applied;
FIG. 12 is a diagram for explaining modifications 1 and 2 of an example (Example 4) of a writing method to which the present invention is applied;
FIG. 13 is a circuit diagram showing a configuration of a sense circuit.
FIG. 14 is a block diagram illustrating a configuration of the rewrite control circuit according to a third embodiment.
FIG. 15 is a flowchart for explaining an example of a processing program executed by the rewrite control circuit in the third embodiment;
FIG. 16 is a block diagram showing a configuration of a semiconductor device to which the present invention is applied in a fourth embodiment;
FIG. 17 is a flowchart showing an example of a decoding operation of the semiconductor device in the fourth embodiment.
FIG. 18 is a flowchart showing an example of the encryption operation of the semiconductor device in the fourth embodiment.
FIG. 19 is a block diagram showing a configuration of a semiconductor device to which the present invention is applied in a fifth embodiment.
FIG. 20 is a flowchart showing an example of a decoding operation of the semiconductor device in the fifth embodiment.
FIG. 21 is a flowchart showing an example of an encryption operation of the semiconductor device.
FIG. 22 is a block diagram showing a configuration of a semiconductor device to which the present invention is applied in a seventh embodiment;
[Explanation of symbols]
100 logic integrated circuit
101 PIA
102 _X Macro cell
104 _X I / O circuit
105 Input signal line
106 Output signal line

Claims (34)

A logic integrated circuit whose logic can be rewritten by an external command signal;
The first information relating to the current first logic state of the logic integrated circuit is compared with the second information relating to the second logic state of the logic integrated circuit included in the command signal, and the first information is compared. And means for prohibiting rewriting of the logic of the logic integrated circuit from the first logic state to the second logic state when the second information does not match ,
The first information and the second information are information on a plurality of logic elements included in the logic integrated circuit,
Among the plurality of logic elements, a first number of elements used for configuring the first logic state, a second number of elements not used for configuring the first logic state, the first Alternatively, at least one of a code obtained by compressing a signal indicating the number of second elements and a date when the logic integrated circuit is rewritten to the first logic state is stored as the first information. A semiconductor device characterized by further comprising a storage means . The logic integrated circuit includes a plurality of multi-value memory cells that hold one of three or more different storage states.
The semiconductor device further includes
When the first and second information match, at least a first code and a second code encoded by an arbitrary encoding method are provided, and a plurality of first codes constituting the first code are provided. The plurality of bit information and the plurality of second bit information constituting the second code are stored in one of the plurality of multi-valued memory cells as a set of bit information having the same digit. Means for rearranging the first and second bit information of
Means for generating a plurality of voltages corresponding to the rearranged bit information and corresponding to the information;
2. The circuit according to claim 1, further comprising means for receiving the address information and applying the voltage to a memory cell corresponding to the address information among the plurality of multi-level memory cells to rewrite the logic. Semiconductor device. A logic integrated circuit whose logic can be rewritten by an external command signal;
In response to the command signal, first information related to the current first logic state of the logic integrated circuit is detected, and second information related to the second logic state of the logic integrated circuit prior to the current time. And determining means for determining that the logic of the logic integrated circuit has been rewritten from the second logic state to the first logic state when the first and second information do not match ,
The first information and the second information are information on a plurality of logic elements included in the logic integrated circuit,
Among the plurality of logic elements, a first number of elements used for configuring the first logic state, a second number of elements not used for configuring the first logic state, the first Alternatively, at least one of a code obtained by compressing a signal indicating the number of second elements and a date when the logic integrated circuit is rewritten to the first logic state is stored as the first information. A semiconductor device characterized by further comprising a storage means .   4. The semiconductor device according to claim 3, wherein the determination unit outputs a determination signal when it is determined that the logic of the logic integrated circuit has been rewritten.   The semiconductor device according to claim 3, wherein the determination unit periodically performs the determination operation. A logic integrated circuit whose logic can be rewritten by an external command signal;
A means for comparing the command signal with at least one reference signal, and prohibiting rewriting of logic of the logic integrated circuit when the command signal and the reference signal are the same signal ,
The logic integrated circuit includes a plurality of multi-value memory cells that hold one of three or more different storage states,
When the command signal is different from the reference signal, at least a first code and a second code encoded by an arbitrary encoding method are provided, and a plurality of first codes constituting the first code are provided. Among the plurality of second bit information constituting the second code and the bit information, the plurality of bit information having the same digit are stored in one of the plurality of multilevel memory cells as a set. Means for rearranging the first and second bit information, and means for generating a plurality of voltages corresponding to these information given the rearranged bit information;
Means for receiving address information and applying the voltage to a memory cell corresponding to the address information among the plurality of multi-level memory cells to rewrite the logic . It further comprises storage means for previously storing a plurality of types of signals as the reference signal,
The semiconductor device according to claim 6, wherein the prohibiting unit compares the command signal with the plurality of types of signals. The logic integrated circuit includes a plurality of arithmetic units each having a predetermined arithmetic function;
7. The semiconductor device according to claim 6, further comprising wiring means for rewriting the logic by changing mutual wiring of the plurality of arithmetic means according to the command signal.   7. The semiconductor device according to claim 6, wherein the logic integrated circuit includes an FPGA (Field Programmable Gate Array). The semiconductor device according to claim 6 , wherein the multi-level memory cell includes a control gate and a floating gate . 7. The semiconductor device according to claim 6 , wherein the multi-value memory cell is at least one of MNOS, mask ROM, EEPROM, EPROM, PROM, FRAM, and flash nonvolatile memory .   7. The semiconductor device according to claim 6, further comprising rewriting means for rewriting the logic of the logic integrated circuit in response to the command signal.   7. The semiconductor device according to claim 6, further comprising reading means for reading the logic of the logic integrated circuit. The bit information reordering means in response to the one code error correction capability, claim 6, characterized in that to control the number of bits in the same code to be stored in one of said plurality of multilevel memory cells The semiconductor device described. The bit information rearranging means encodes the bit information so that m bit information is stored in the one multilevel memory cell when the number of bits stored in one of the plurality of multilevel memory cells is m. 7. The semiconductor device according to claim 6 , wherein m codes having a length of n are rearranged as rows of an mxn array. First information related to the current first logic state of the logic integrated circuit whose logic can be rewritten by an external command signal, and second information related to the second logic state of the logic integrated circuit included in the command signal Compared with the information
The first, when the second information does not match viewing including the step of prohibiting rewriting to the second logic state from the logic of the first logic state of the logic integrated circuit,
The first information and the second information are information on a plurality of logic elements included in the logic integrated circuit,
Among the plurality of logic elements, a first number of elements used for configuring the first logic state, a second number of elements not used for configuring the first logic state, the first Alternatively, at least one of a code obtained by compressing a signal indicating the number of second elements or a date when the logic integrated circuit is rewritten to the first logic state is used as the first information. A logical rewrite prevention method characterized by that. A semiconductor device having a security function,
Control means for holding a code processing program at least temporarily and outputting a command signal corresponding to the code processing program;
A logic means that is provided with the command signal and changes logic according to the program, and at least one of data and an address related to the data is subjected to code processing;
First storage means for storing the data;
The first information relating to the current first logic state of the logic means is compared with the second information relating to the second logic state of the logic means included in the command signal, and the first, And means for prohibiting rewriting of the logic of the logic means from the first logic state to the second logic state when the two information do not match ,
The first information and the second information are information relating to a plurality of logic elements included in the logic means,
Among the plurality of logic elements, a first number of elements used for configuring the first logic state, a second number of elements not used for configuring the first logic state, the first Alternatively, at least one of a code obtained by compressing a signal indicating the number of second elements or a date when the logic means is rewritten to the first logic state is stored as the first information. A semiconductor device further comprising storage means . A semiconductor device having a security function,
Control means for holding a code processing program at least temporarily and outputting a command signal corresponding to the code processing program;
A logic means that is provided with the command signal and changes logic according to the program, and at least one of data and an address related to the data is subjected to code processing;
First storage means for storing the data;
Comparing the command signal with at least one reference signal, and comprising a prohibiting means for prohibiting rewriting of logic of the logic means when the command signal and the reference signal are the same signal ,
The logic means comprises a plurality of multi-valued memory cells holding one of three or more different storage states;
When the command signal is different from the reference signal, at least a first code and a second code encoded by an arbitrary encoding method are provided, and a plurality of first codes constituting the first code are provided. Among the plurality of second bit information constituting the second code and the bit information, the plurality of bit information having the same digit are stored in one of the plurality of multilevel memory cells as a set. Means for rearranging the first and second bit information; means for generating a plurality of voltages corresponding to these information given the rearranged bit information;
Means for receiving address information and applying the voltage to a memory cell corresponding to the address information among the plurality of multi-level memory cells to rewrite the logic . A second storage means for storing a plurality of types of signals in advance as the reference signal;
19. The semiconductor device according to claim 18 , wherein the prohibiting unit compares the command signal with the plurality of types of signals. The logic means includes a plurality of arithmetic means each having a predetermined arithmetic function;
19. The semiconductor device according to claim 18, further comprising wiring means for rewriting the logic by changing mutual wiring of the plurality of arithmetic means according to the command signal. 19. The semiconductor device according to claim 18 , wherein the logic means includes a field programmable gate array (FPGA). The semiconductor device according to claim 18, wherein the multi-level memory cell includes a control gate and a floating gate. 19. The semiconductor device according to claim 18 , further comprising rewriting means for rewriting the logic of the logic means in response to the command signal. 19. The semiconductor device according to claim 18 , further comprising reading means for reading the logic of the logic means. 19. The semiconductor device according to claim 18 , wherein the logic means performs the code processing including at least one of encryption and decryption processing. 19. The semiconductor according to claim 18 , wherein the logic means performs the code processing for encrypting at least one of the data and the address before the data is stored in the first storage means. apparatus. Said logic means, according to claim 18, wherein the data and performing the encoding processing of encrypting either one of the addresses relating to at least the data and the data in output from said first storage means The semiconductor device described. Said logic means, according to claim 18, wherein the data and performing the encoding processing for decoding the one of the addresses relating to at least the data and the data in output from said first storage means The semiconductor device described. 19. The semiconductor device according to claim 18, wherein the first memory means includes at least one of a mask ROM and an electrically rewritable nonvolatile memory device. The semiconductor device includes:
Antenna means for transmitting and receiving the data in a contactless manner with a terminal;
A power supply voltage is generated from the reception output of the antenna means, and a signal transmitted from the terminal is demodulated, and a high-frequency current superimposed with the data to be transmitted to the terminal is generated and output to the antenna means. 19. The semiconductor device according to claim 18, further comprising high frequency processing means. A code processing method for a semiconductor device comprising a logic circuit having a security function and a logic changeable, and a control device for controlling the logic circuit,
A supplying step of supplying a code processing program to the control device;
An output step of outputting a command signal corresponding to the program from the control device;
A logic change step of changing the logic of the logic circuit according to the program by applying the command signal to the logic circuit;
A code processing step of performing code processing on at least one of data and an address related to the data by the changed logic;
Storing the data in a storage device,
The logic change step includes:
Comparing first information relating to a current first logic state of the logic circuit with second information relating to a second logic state of the logic circuit included in the command signal;
The first, when the second information does not match viewing including the step of prohibiting rewriting to the second logic state from the logic of the first logic state of said logic circuit,
The first information and the second information are information on a plurality of logic elements included in the logic integrated circuit,
Among the plurality of logic elements, a first number of elements used for configuring the first logic state, a second number of elements not used for configuring the first logic state, the first Alternatively, at least one of a code obtained by compressing a signal indicating the number of second elements or a date when the logic integrated circuit is rewritten to the first logic state is used as the first information. The code processing method characterized by the above-mentioned. Logic means that can change logic, is provided with any one of an encryption program and a decryption program, the logic is changed by an instruction signal corresponding to the program, and a logic means for processing the signal by the changed logic A semiconductor device having a confidentiality maintaining function, wherein the logic means includes:
A logic integrated circuit whose logic can be rewritten by the command signal;
A means for comparing the command signal with at least one reference signal, and prohibiting rewriting of logic of the logic integrated circuit when the command signal and the reference signal are the same signal ,
The logic integrated circuit includes a plurality of multi-value memory cells that hold one of three or more different storage states,
When the command signal is different from the reference signal, at least a first code and a second code encoded by an arbitrary encoding method are provided, and a plurality of first codes constituting the first code are provided . Among the plurality of second bit information constituting the second code and the bit information, the plurality of bit information having the same digit are stored in one of the plurality of multi-level memory cells as one set. Means for rearranging the first and second bit information, and means for generating a plurality of voltages corresponding to these information given the rearranged bit information;
Means for receiving address information and applying the voltage to a memory cell corresponding to the address information among the plurality of multi-level memory cells to rewrite the logic . The instruction signal and at least one reference in a logic integrated circuit of a logic integrated circuit having a plurality of multi-valued memory cells that can rewrite logic by a command signal from the outside and hold one of three or more different storage states Compare with the signal,
When the command signal is the same signal as the reference signal, rewriting the logic of the logic integrated circuit is prohibited,
When the command signal is a signal different from the reference signal, the digit of the plurality of first bit information constituting the first code and the plurality of second bit information constituting the second code Reordering the plurality of first and second bit information so that the same bit information is stored in one of the plurality of multilevel memory cells as a set,
Generating a plurality of voltages corresponding to the sorted bit information;
Receiving the address information, and applying the voltage to the memory cell corresponding to the address information among the plurality of multi-level memory cells, and rewriting the logic. . A computer-readable program storing a program for preventing logic rewriting of a logic integrated circuit having a plurality of multi-valued memory cells that hold one of three or more different memory states and can be rewritten by an external command signal. a Do not storage medium,
The program is stored on a computer .
Comparing the command signal and at least one reference signal in the logic integrated circuit;
A procedure for prohibiting rewriting of logic of the logic integrated circuit when the command signal is the same signal as the reference signal;
A step of inputting at least a first code and a second code encoded by an arbitrary encoding method when the command signal is different from the reference signal;
Among the plurality of first bit information constituting the first code and the plurality of second bit information constituting the second code, the bit information having the same digit is set as a set, and the plurality of multilevel memory cells Reordering the plurality of first and second bit information to be stored in one of
Generating a plurality of voltages corresponding to the sorted bit information;
Receiving the address information, applying the voltage to a memory cell corresponding to the address information among the plurality of multi-level memory cells, and executing a procedure of rewriting the logic. Medium.

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