JP3722202B2 - Semiconductor integrated circuit device, microcomputer and electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, a microcomputer, and an electronic apparatus.
[0002]
[Background Art and Problems to be Solved by the Invention]
Conventionally, a video memory for an LCD controller requires a memory that is physically separate from the main memory. Here, when integrating the microprocessor incorporating the DRAM controller and the LCD controller, the following methods can be considered.
[0003]
First, the LCD controller has a second DRAM controller different from the DRAM controller for the microprocessor, and a method of externally attaching a DRAM physically different from the main memory DRAM on the microprocessor side as a video memory is conceivable.
[0004]
In this case, a video memory DRAM different from the main memory DRAM is required, and there is a disadvantage that the number of parts increases and the cost increases. In particular, in an electronic device or the like that requires only a small-scale LCD display device, a video memory DRAM may be small in capacity. However, since the demand for such a small-capacity DRAM is small, the production volume is also small, so that the cost performance is poor and the cost is increased.
[0005]
Second, the LCD controller has a second DRAM controller that is different from the DRAM controller for the microprocessor, and there is a technique in which a DRAM that is physically different from the main memory DRAM on the microprocessor side is integrated as an on-chip memory for the video memory. Conceivable.
[0006]
In this case, there is a drawback that the area of the LSI chip is increased and the cost is increased as DRAM is integrated on-chip.
[0007]
Third, the LCD controller integrates a microprocessor memory DRAM controller and a video memory constituted by an SRAM different from the main memory DRAM connected thereto as an external or on-chip memory.
[0008]
When the SRAM is externally attached, it has the same drawbacks as in the first method, and when the SRAM is integrated as an on-chip memory, it has the same disadvantages as in the second method. In addition, the SRAM generally has a disadvantage that the cost per unit bit number is higher than that of the DRAM, resulting in an increase in cost.
[0009]
As described above, all of the first to third methods have a problem that the cost is high. Therefore, it is possible to prevent an increase in cost by adopting a method of allocating a part of DRAM used as main memory to video memory.
[0010]
However, in this method, there is a problem in that the processing speed is reduced due to contention between access from the CPU to the main memory and access from the LCDC controller to the video memory.
[0011]
The present invention has been made in view of the above problems, and an object thereof is a microprocessor capable of using a VRAM in which video memory is allocated to a part of main memory without reducing the processing speed. An object of the present invention is to provide a semiconductor integrated circuit device, a microcomputer and an electronic device in which an LCD controller is integrated.
[0012]
[Means for Solving the Problems]
The present invention is a semiconductor integrated circuit device that includes a CPU and an LCD controller and is connected to a DRAM that functions as a main memory and a video memory, and pre-reads display data in the video memory area required by the LCD controller. Means for holding in the prefetch buffer, means for determining the urgency of the access request to the video memory area based on the holding status of the display data required by the LCD controller in the prefetch buffer, and an access request to the DRAM Priority control means for controlling the video memory area to be executed in the priority order of the access request with a high degree of urgency> the access request from the CPU to the main storage area> the access request with a low degree of urgency to the video memory It is characterized by including these.
[0013]
The prefetch buffer is preferably composed of, for example, a FIFO.
[0014]
Here, the holding status of the display data required by the LCD controller in the prefetch buffer means, for example, whether or not the request data is held in the prefetch buffer when the LCD controller requests display data. Alternatively, the situation may be the amount of data held in the prefetch buffer.
[0015]
In general, a method of allocating a part of DRAM used as main memory to video memory can prevent an increase in cost. However, processing due to contention between access to main memory from CPU and access to video memory from LCDC controller. There was a problem that the speed was reduced.
[0016]
However, according to the present invention, the display data in the video memory area required by the LCD controller is prefetched and held in the prefetch buffer. Therefore, when the LCD controller prefetches the display data in the video memory, the prefetch buffer The stored display data can be passed.
[0017]
Therefore, when the display data is requested from the LCD controller, only the access request when the requested data is not in the buffer has a high degree of urgency, and this needs to be executed with priority over the CPU access request. .
[0018]
On the other hand, the access request for prefetching and holding in the buffer need not be given priority over the CPU access request, and may be made when the bus is free.
[0019]
According to the present invention, the urgency level of the access request to the video memory is determined, and if there is a conflict, the CPU requests the access request only when the urgency level is high.
[0020]
Therefore, in the case of contention, the access from the CPU is less likely to be waited than when the access request to the video memory is always executed by the CPU in preference to the access request. Therefore, a part of the DRAM used as the main memory can be allocated to the video memory without degrading the processing speed due to the competition between the access from the CPU to the main memory and the access from the LCDC controller to the video memory.
[0021]
As described above, according to the present invention, there is provided a semiconductor integrated circuit device in which a CPU (or a microprocessor) and an LCD controller are integrated, which can use a VRAM in which video memory is allocated to a part of main memory without reducing the processing speed. Can be provided.
[0022]
The semiconductor integrated circuit device of the present invention includes a prefetch control circuit that receives an access request for display data from the LCD controller to the video memory and returns the requested display data to the LCD controller. The prefetch control circuit includes the prefetch control circuit. When the display data required by the LCD controller is not held in the buffer, when the display data access request is received from the LCD controller, the urgency level of the video memory is accessed to access the display data. A display request accessed from the video memory area in response to the access request is passed to the LCD controller, and the display data required by the LCD controller is held in the prefetch buffer. Display data from LCD controller When an access request is received, the display data held in the prefetch buffer is passed to the LCD controller, a read address is generated at a predetermined timing based on the video memory read logic of the LCD controller, and the generated read address is set. Based on this, an access request with a low degree of urgency is made to the video memory, and control is performed to hold display data accessed from the video memory area in the prefetch buffer in response to the access request.
[0023]
The present invention pays attention to the fact that access requests from the LCD controller are made periodically and have high priority but can be prefetched, and the timing of access requests from the CPU is not regular and cannot be prefetched. Thus, the above-described prefetch control circuit is provided, and instead of the LCD controller, the display data of the video memory is prefetched and stored in the prefetch buffer, and passed to the LCD controller as necessary.
[0024]
Since the prefetching may be performed when the bus is free, the bus can be used efficiently, and the occurrence of contention for access to the external DRAM can be reduced.
[0025]
The semiconductor integrated circuit device according to the present invention includes a DRAM controller for controlling at least one of an access procedure to the DRAM and a refresh operation, and the priority control means includes a refresh request from the DRAM controller> an urgency to the video memory area. High access request> access request from the CPU to the main storage area> control to execute the request with the priority of the access request with low urgency to the video memory.
[0026]
A DRAM has a lower cost per unit bit than an SRAM or the like, but requires a DRAM controller for controlling these because the access procedure is complicated and a refresh operation is required.
[0027]
The semiconductor integrated circuit device of the present invention incorporates this DRAM controller, and internally adjusts access requests from the CPU, access requests to the video memory, and refresh requests from the DRAM controller.
[0028]
For this reason, various requirements for the DRAM can be adjusted efficiently, and a reduction in processing speed can be prevented.
[0029]
The priority control means of the semiconductor integrated circuit device according to the present invention is connected to an external bus release request signal line, and receives a refresh request from the DRAM controller> an urgent access request to the video memory area> an external bus Control is performed so that the request is released in order of priority of access requests with a low degree of urgency to the video memory.
[0030]
The semiconductor integrated circuit device of the present invention collectively adjusts access requests from the CPU, access requests to the video memory, refresh requests from the DRAM controller, and external bus release requests.
[0031]
For this reason, various requirements for the DRAM can be adjusted efficiently, and a reduction in processing speed can be prevented.
[0032]
The semiconductor integrated circuit device of the present invention is configured to be separately connectable to at least two buses, a first bus connected to the DRAM and a second bus connected to a device other than the DRAM, The priority control means determines whether the access target of the CPU is an area of the DRAM, and when the access area is the DRAM area, the access request to the DRAM is a highly urgent access request to the video memory area> It is characterized in that the first bus is controlled so that it is executed in the priority order of access requests from the CPU to the main storage area> access requests with a low degree of urgency to the video memory.
[0033]
In the present invention, the first bus and the second bus are configured to be separately connectable to at least two buses of the first bus connected to the DRAM and the second bus connected to other than the DRAM. Can operate in parallel.
[0034]
Therefore, it is only necessary to adjust the conflict between the CPU access request and the video memory access request for only the DRAM. For this reason, the phenomenon of waiting for the CPU access is reduced compared to the case where the contention adjustment is performed for all the access requests to the external device of the CPU, and the processing speed can be prevented from being lowered.
[0035]
The priority control means of the semiconductor integrated circuit device of the present invention includes a first bus operation procedure control circuit that is connected to an internal DRAM controller and controls the operation of the first bus to which the DRAM is connected, The first bus operation procedure control circuit includes a refresh request from the DRAM controller> a high urgency access request to the video memory area> a CPU access request to the main storage area> a low urgency to the video memory The bus operation of the first bus is controlled according to the priority order of the access requests.
[0036]
The semiconductor integrated circuit device of the present invention includes a second bus operation procedure control circuit that controls the operation of the second bus to which a device other than the DRAM is connected, and the second bus operation procedure control circuit includes: The bus operation of the second bus is controlled according to the priority order of the access request from the CPU to the device other than the DRAM.
[0037]
The priority control means of the semiconductor integrated circuit device of the present invention includes a memory map controller that determines a CPU access target based on an access address from the CPU, and the CPU access target is determined based on a determination result of the memory map controller. It is determined whether the area is the DRAM area or not.
[0038]
A microcomputer according to the present invention includes any one of the semiconductor integrated circuits described above.
[0039]
Since the microcomputer of the present invention can allocate a part of DRAM used as main memory to video memory without reducing the processing speed, it is possible to provide a microcomputer system using an LCD with good cost performance. I can do it.
[0040]
An electronic apparatus according to the present invention includes the microcomputer described above, input means for data to be processed by the microcomputer, and LCD output means for outputting data processed by the microcomputer. And
[0041]
By incorporating the microcomputer of the present invention into an electronic device, it is possible to provide an electronic device with low cost and high processing speed.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0043]
FIG. 1 is a diagram showing a conventional example of access timing from the LCD controller to the video memory and access timing from the CPU to the main memory.
[0044]
Reference numerals a1 to a7 indicate access timings 410 from the LCD controller to the video memory, and b1 to b9 indicate access timings 420 from the CPU to the main memory. In general, the LCD controller performs control to read, for example, display data for one screen from a video memory in a plurality of times and output it to the LCD. Therefore, as shown in a1 to a7 of FIG. On the other hand, the timing at which the CPU accesses the main memory generally has no regularity as indicated by b1 to b7 in FIG.
[0045]
Here, when both accesses compete as indicated by reference numerals 430 and 432, the access request from the LCD controller is given priority and the access request from the CPU is made to wait. The reason why priority is given to the access request from the LCD controller is to prevent a problem from occurring in the display on the LCD.
[0046]
Therefore, normally, when the competition between the two occurs, the processing of the CPU is awaited, which causes a reduction in processing speed.
[0047]
Therefore, the present inventor is that the access request from the LCD controller is made periodically and has a high priority but can be prefetched, and the timing of the access request from the CPU is not regular and cannot be prefetched. Paying attention, we succeeded in reducing the occurrence of contention for access to the external DRAM without delaying the processing of the CPU by prefetching the display data required by the LCD controller.
[0048]
FIG. 2 is a block diagram of the semiconductor integrated circuit device according to the first example of the present embodiment.
[0049]
The semiconductor integrated circuit device 10 of the first embodiment is a case where the external DRAM device 80 and the other devices 90 and 92 are connected to one bus (address bus 72, control bus 74, data bus 76).
[0050]
The semiconductor integrated circuit device 10 of this embodiment includes a microprocessor core 20 including a CPU 22, an LCD controller 30, a prefetch control circuit 40, an access priority control circuit 50, a bus operation procedure control circuit 60, and a bus interface circuit 70. An external DRAM device 80 and other external non-DRAM devices 90 and external I / O devices 92 are connected to one external bus (address bus 72, control bus 74, data bus 76).
[0051]
Here, the external non-DRAM device 90 is, for example, a ROM or an SRAM.
The external DRAM device 80 according to the present embodiment includes an area 82 used as a main memory and an area 84 used as a video memory. The video memory 84 temporarily stores display data necessary for the LCD controller 30 to display on the external LCD 96.
[0052]
The LCD controller 30 reads the display data in the video memory 84 via the prefetch circuit 40 and performs control for displaying on the external LCD 96.
[0053]
The prefetch control circuit 40 prefetches display data in the video memory 84 required by the LCD controller 30 and performs a process of passing the display data to the LCD controller 30 in response to a request from the LCD controller 30.
[0054]
The access priority control circuit 50 is a circuit for controlling the access to the external DRAM device 80 from the CPU 22 and the access to the external DRAM device 80 from the prefetch control circuit 40 to be processed with a predetermined priority.
[0055]
The bus operation procedure circuit 60 includes a DRAM controller 62 and a memory map control circuit 64, and controls the operation of the external bus (address bus 72, control bus 74, data bus 76) based on control signals from the priority control circuit 50.
[0056]
The DMA controller 62 performs processing for controlling at least one of an access procedure to the external DRAM device 80 and a refresh operation.
[0057]
The memory map control circuit 64 has a register and a determination logic (comparator) for determining whether or not the access address of the CPU is the external DRAM device 80, and the access address of the CPU 22 is the external DRAM device 80. Processing for determining whether or not there is present is performed.
[0058]
As described above, the semiconductor integrated circuit device 10 of the first embodiment is connected to the external DRAM device 80 functioning as the main memory 82 and the video memory 84, and includes the CPU 22, the LCD controller 30, and the DRAM controller 62.
[0059]
Here, a configuration for preventing a decrease in processing speed due to contention of access to the external DRAM device 80 due to one external DRAM device 80 including the main memory area 82 and the video memory area 84 will be described in detail.
[0060]
FIG. 3 is an example of a block diagram of the prefetch control circuit 40.
[0061]
The prefetch control circuit 40 includes a prefetch VRAM pointer 42, a control circuit 44, and a prefetch frame buffer (FIFO) 40. The prefetch control circuit 40 is connected to the LCD controller 30 and makes an access request to the video memory of the external DRAM device on behalf of the LCD controller 30.
[0062]
The LCD controller 30 issues an access request by outputting the display data address and the access request signal to the LCDC address signal line 32 and the LCD memory control signal line 36 at a predetermined timing, and receives the display data via the LCDC data signal line 34. .
[0063]
The prefetch control circuit 40 accesses the video memory of the external DRAM device in place of the LCD controller, and upon receiving a display data access request from the LCD controller via the LCDC address signal line 32 and the LCD memory control signal line 36, the LCDC. Processing for passing the requested display data to the LCD controller via the data signal line 34 is performed.
[0064]
Based on the address (previous access address) stored in the prefetch VRAM pointer 42 and the logic by which the LCD controller 30 reads the video memory, the control circuit 44 generates a read address 43 for the video memory and sets it in the prefetch VRAM pointer 42. . The read address 43 is output to the internal address bus 24 at a predetermined timing to make an access request to the video memory of the external DRAM device.
[0065]
Here, the control circuit 44 determines the urgency level of the access request and generates a high priority request (high urgency level) 48 and a low priority request (low urgency level) 49 which are signals indicating the level of urgency level. Output to the access priority control circuit 50 in synchronization with the access request.
[0066]
In general, an access request for prefetching is performed at a predetermined timing so that display data required before the LCD controller 30 requests display data can be prefetched and held in the prefetch frame buffer (FIFO) 46 in principle. Is called.
[0067]
In this case, the display data requested by the LCD controller 30 already exists in the prefetch frame buffer (FIFO) 46, or even if there is no display data, an access request from the LCD controller 30 for the read address is not generated again. Because there is, urgency can be lowered. Therefore, in the case of a normal look-ahead purpose, the control circuit 44 generates and outputs a low priority request (low urgency).
[0068]
Data read in response to the access request is stored in a prefetch frame buffer (FIFO) 46.
[0069]
On the other hand, when the prefetch frame buffer (FIFO) 46 is empty, the control circuit 44 generates a high priority request (high urgency) when an access request is made when a display data access request is received from the LCD controller. Output.
[0070]
The display data 47 read in response to the access request is input to the prefetch frame buffer (FIFO) 46 via the internal data bus 26, and is passed through the LCDC data line 34 without being held. Return to 30.
[0071]
FIG. 4 is a flowchart for explaining an operation example of the prefetch control circuit.
[0072]
When there is a display data read request from the LCD controller 30, if the requested display data is stored in the prefetch frame buffer (FIFO) 46, the control circuit 44 reads the prefetch frame buffer (FIFO) 46. The corresponding display data is returned to the LCD controller 30 (steps S10, S20, S30).
[0073]
When there is a display data read request from the LCD controller 30, if the requested display data is not stored in the prefetch frame buffer (FIFO) 46, the requested display data is highly urgent. An access request is made with a request (steps S10, S20, S40).
[0074]
Specifically, the control circuit 44 sets the access address prefetch VRAM pointer 42 sent from the LCD controller 30 via the LCDC address signal line 32 and outputs the address as a read address to the internal address bus 22 to request access. I do. Synchronously with this, a high priority request 48 is output to the access priority control circuit 50 in order to increase the urgency of the access request.
[0075]
In response to the access request, the display data read from the video memory of the external DRAM device is returned to the LCD controller 30 through (step S50).
[0076]
In addition, except when there is a display data read request from the LCD controller 30, a read address is generated at a predetermined timing based on the video memory read logic of the LCD controller, and an access request is made with a less urgent request ( Step S60).
[0077]
Specifically, the control circuit 44 generates the next access address based on the address stored in the prefetch VRAM pointer and sets it in the prefetch VRAM pointer 42 and outputs the address to the internal address bus 24 as the read address. Make an access request. In synchronism with this, a low priority request 49 is output to the access priority control circuit 50 in order to reduce the urgency of the access request.
[0078]
The display data read from the video memory of the external DRAM device in response to the access request is stored in the prefetch frame buffer (FIFO) 46 (step S70).
[0079]
In the present embodiment, the prefetch control circuit 40 prefetches display data required by the LCD controller 30 to the video memory 84 of the external DRAM device 80, holds it in a buffer, and passes it to the LCD controller 30 as necessary. Since the configuration is adopted, display data normally requested by the LCD controller is held in a buffer. Accordingly, when the data is requested from the LCD controller 30, only the access request when the requested data is not in the buffer has a high degree of urgency, and this needs to be executed with priority over the access request of the CPU.
[0080]
However, the access request for prefetching and holding in the buffer need not be given priority over the CPU access request, and may be made when the bus is free.
[0081]
As described above, in this embodiment, the urgency of an access request to the video memory can be determined and the bus can be used efficiently.
[0082]
Next, a configuration in which the access priority control circuit 50 controls the priority of access to the external VRAM device based on the high priority request and the low priority request will be described with reference to FIG.
[0083]
The access priority control circuit 50 is a signal line for a READ / WRITE request 28 from the CPU 22, a high priority request 48 and a low priority request 49 from the prefetch control circuit 40, a refresh request 66 from the DRAM controller 62, and an external release request 72. It is connected to the.
[0084]
When accessing the external device, the CPU 22 outputs an access address to the internal address bus 24 and outputs a READ / WRITE request 28 to the access priority control circuit 50.
[0085]
When the prefetch control circuit 40 accesses the external DRAM device 80, the read address is output to the internal address bus 24, and a high priority request is sent to the access priority control circuit 50 according to the degree of urgency. 48 or low priority request 49 is output.
[0086]
The DRAM controller 62 outputs a refresh request 66 to the access priority control circuit 50 at a timing when the external DRAM device 80 needs to be refreshed.
[0087]
When there is an external bus release request, an external bus release request 72 is input to the access priority control circuit 50.
[0088]
When the access priority control circuit 50 receives a request signal from each of these signal lines, it determines the priority of the request and outputs a priority signal 52 to the bus operation procedure control circuit 60.
[0089]
Here, the refresh request from the DRAM controller> the request for accessing the video memory area with high urgency> the request for opening the bus from the outside> the request for accessing the main memory area from the CPU> the access with low urgency to the video memory The priority increases in order of request.
[0090]
The access priority control circuit 50 outputs a priority signal 52 to the bus operation procedure control circuit 60 so that it is executed with higher priority.
[0091]
FIG. 5 is a flowchart for explaining an output example of the priority signal 52 of the access priority circuit.
[0092]
When a request signal from any one of the signal lines is received (step S10), if it is a refresh request from the DRAM controller, a priority signal of priority 5 is output to the bus operation procedure circuit (steps S20 and S30). .
[0093]
If the access request is a high quality request from the prefetch control circuit, a priority 4 priority signal is output to the bus operation procedure circuit (steps S40 and S50).
[0094]
If it is an external bus release request, a priority 3 priority signal is output to the bus operation procedure circuit (steps S60 and S70).
[0095]
If it is a READ / WRITE request from the CPU, a priority level 2 priority signal is output to the bus operation procedure circuit (steps S80 and S90).
[0096]
If the access request is a low priority request from the prefetch control circuit, a priority signal of priority 1 is output to the bus operation procedure circuit (steps S100 and S110).
[0097]
It is assumed that the higher the priority value, the higher the priority order.
[0098]
In addition, the prefetch control circuit prefetches display data in the video memory area required by the LCD controller and holds it in the prefetch buffer, and holds the display data required by the LCD controller in the prefetch buffer. This functions as a means for determining the urgency of the access request to the video memory area.
[0099]
The bus operation procedure circuit 60 controls the operation of the bus so that it is executed in the priority order according to the priority indicated by the priority signal. When a plurality of accesses with different priorities compete, an access with a higher priority is executed first, and an access with a lower priority is awaited.
[0100]
As shown in FIG. 2, the bus operation procedure circuit 60 includes a DRAM controller 62 for controlling the access procedure to the external DRAM device 80, and a general circuit (not shown) for controlling the access procedure to the other external devices 90 and 92. It is determined by looking at the address to determine which of the external bus terminals is actually controlled.
[0101]
The memory map control circuit 64 built in the bus operation procedure control circuit 60 includes a register storing an address for specifying a DRAM area, and a logic circuit for determining whether the received address is in the DRAM area. Viewing the received address, control is passed to the DRAM controller 62 or a general circuit (not shown).
[0102]
As described above, in the present embodiment, only the access request to the video memory 84 of the external DRAM device 80 with high urgency is executed with priority over the access request from the CPU to the main storage area. For this reason, the phenomenon in which the CPU access is waited due to contention is reduced as compared with the case where the access request to the video memory 84 of the external DRAM device 80 is always executed in preference to the access request from the CPU to the main storage area, and the processing speed is reduced. Decrease can be prevented.
[0103]
Note that the access priority control circuit 50 and the bus operation procedure control circuit 60 make an access request to the DRAM when the urgent access request to the video memory area> the access request from the CPU to the main storage area> the emergency to the video memory It functions as a priority control means for performing control so that it is executed with a low priority access request priority.
[0104]
Next, when the semiconductor integrated circuit is separately connected to a first external bus connected to an external DRAM device and a second external bus connected to a device other than the external DRAM device (second embodiment). Will be described.
[0105]
FIG. 6 is a block diagram of the semiconductor integrated circuit device 100 of the second example of the present embodiment.
[0106]
In the semiconductor integrated circuit device according to the second embodiment, a microprocessor core 20 including a CPU 22 and an LCD controller 30, a prefetch control circuit 40, an access priority control circuit 50 ', a first bus operation procedure control circuit 110 and a connection thereto are connected. DRAM bus terminal group 130, second bus operation procedure control circuit 120 and other bus interface / terminal group 140 connected thereto, and external DRAM device 80 is connected to first external bus (DRAM dedicated address bus 132). The DRAM dedicated data bus 134 and the DRAM dedicated control bus 136 are connected to the DRAM bus terminal group 130. The other external non-DRAM device 90 and the external I / O device 92 are connected to the second external bus (address bus 142). , Control bus 134, data bus 136) other bus in It is connected to the interface / terminal group 140.
[0107]
Here, the portions denoted by the same reference numerals as those in FIG. 2 have the same functions, and thus the description thereof is omitted.
[0108]
In the first embodiment, since the same signal terminal is shared by the external DRAM device 80 and the other external devices 90 and 92 except for the terminal of the DRAM dedicated control signal 78, only one of them can operate.
[0109]
On the other hand, in the second embodiment, the DRAM bus terminal group 130 and the other bus interface / terminal group 140 are assigned completely different terminals, so that parallel operation is possible.
[0110]
Here, data and addresses when the CPU 22 and the prefetch control circuit 40 exchange with the external DRAM device 80 are exchanged with the first external bus via the DRAM bus terminal group 130, and the external device 90 other than the external DRAM device 80 is exchanged with the CPU 22. , 92 are exchanged on the second external bus via the other bus interface / terminal group 140.
[0111]
As described above, since the request for the first external bus and the request for the second external bus are received separately, the first bus operation control procedure circuit 110 and the second bus operation control procedure circuit 110 are separately provided in the first bus operation control procedure circuit 110 and the second bus operation control procedure circuit 110, respectively. The operation procedure of the external bus and the second external bus is controlled.
[0112]
The second bus operation control procedure circuit 120 includes a memory map control circuit 122. The memory map control circuit 122 determines whether the access address received from the CPU indicates an area other than the external DARAM device 80. If it indicates an area other than the external DARAM device 80, the second bus operation control procedure circuit 120 outputs the access address to the other bus interface / terminal group 140.
[0113]
Here, there may be an external bus release request for the second external bus connected to the other bus interface / terminal group 140. In this case, the external bus rather than the access request from the CPU. The operation procedure of the second external bus is controlled so that the release request has priority.
[0114]
The access priority control circuit 50 ′ includes a memory map control circuit 52 and determines whether the access address from the CPU 22 is an area of the external DRAM device 80. When this is the area of the external DRAM device 80, the operation is performed in the same manner as in the first embodiment, and the priority signal is output to the first bus operation procedure control circuit 110.
[0115]
Similarly to the case of the first embodiment, a priority signal for the access request from the prefetch control circuit and the refresh request from the DRAM controller 112 is output. However, since the first external bus is connected only to the external DARAM device 80, unlike the first embodiment, no external bus release request for the first external bus is generated.
[0116]
Therefore, the access priority control circuit 50 ′ determines the refresh request from the DRAM controller> the access request with high urgency to the video memory area> the access request from the CPU to the main storage area> the access with low urgency to the video memory. The priority signal 52 is output to the first bus operation procedure control circuit 110 so that the priority is executed in the order of request.
[0117]
The first bus operation procedure circuit 110 includes a DRAM controller 112, and a first external bus (DRAM dedicated address bus 132, DRAM dedicated data bus 134, DRAM dedicated control bus 136 based on a control signal from the priority control circuit 50 '. ) Control the operation.
[0118]
In FIG. 6, the memory map control circuits are described at two locations 52 and 122, but it is sufficient if only one is physically referred to by 52 and 122.
[0119]
As described above, the semiconductor integrated circuit of the second embodiment is configured to be connectable to the first bus connected to the external DRAM device and the second bus connected to a device other than the external DRAM device. It is only necessary to adjust the conflict between the CPU access request and the video memory access request only for the external DRAM device.
[0120]
For this reason, the phenomenon of waiting for the CPU access is reduced compared to the case of adjusting the contention for all the access requests to the external device of the CPU, and the delay of the processing speed can be prevented.
[0121]
2. Microcomputer
FIG. 7 is an example of a hardware block diagram of the microcomputer of this embodiment.
[0122]
The microcomputer 700 includes a CPU 510, a cache memory 520, an LCD controller 530, a reset circuit 540, a programmable timer 550, a real time clock (RTC) 560, a DRAM controller / bus I / F 570, an interrupt controller 580, a serial interface 590, and a bus controller 600. , A / D converter 610, D / A converter 620, input port 630, output port 640, I / O port 650, clock generator 560, prescaler 570, and various buses 680 connecting them, various pins 690 Etc.
[0123]
The DRAM controller / bus I / F 570 includes the prefetch control circuit 40, the access priority circuit 50, the bus operation control procedure circuit 60, and the like described in FIG.
[0124]
The RAM 720 includes a DRAM that functions as a main memory and a video memory.
[0125]
Since the microcomputer of this embodiment can allocate a part of DRAM used as main memory to video memory without lowering the processing speed, it provides a microcomputer system using an LCD with good cost performance. I can do it.
[0126]
3. Electronics
FIG. 8 illustrates an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (or ASIC) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, and a sound output unit 860.
[0127]
Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device.
[0128]
The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.
[0129]
FIG. 9A illustrates an example of an external view of a cellular phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.
[0130]
FIG. 9B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.
[0131]
FIG. 9C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.
[0132]
By incorporating the microcomputer of this embodiment into the electronic devices in FIGS. 9A to 9C, an electronic device with low cost and high processing speed can be provided.
[0133]
As electronic devices that can use this embodiment, in addition to those shown in FIGS. 9A, 9B, and 9C, portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, Various electronic devices using an LCD such as a projector, a word processor, a viewfinder type or a monitor direct view type video tape recorder, and a car navigation device can be considered.
[0134]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[Brief description of the drawings]
FIG. 1 is a diagram showing a conventional example of access timing from an LCD controller to a video memory and access timing from a CPU to a main memory.
FIG. 2 is a block diagram of a semiconductor integrated circuit device according to a first example of the present embodiment;
FIG. 3 is an example of a block diagram of a prefetch control circuit according to the present embodiment.
FIG. 4 is a flowchart for explaining an operation example of a prefetch control circuit according to the present embodiment;
FIG. 5 is a flowchart for explaining an output example of a priority signal of an access priority circuit according to the present embodiment;
FIG. 6 is a block diagram of a semiconductor integrated circuit device 100 according to a second example of the present embodiment;
FIG. 7 is an example of a hardware block diagram of the microcomputer according to the present embodiment.
FIG. 8 illustrates an example of a block diagram of an electronic device including a microcomputer.
9A, 9B, and 9C are examples of external views of various electronic devices.
[Explanation of symbols]
10 Semiconductor integrated circuit device
20 Microprocessor core
22 CPU
30 LCD controller
40 Look-ahead control circuit
42 Look-ahead VRAM pointer
44 Control circuit
46 Prefetch frame buffer
48 High priority request
49 Low priority request
50 Access priority circuit
52 Memory map control circuit
60 Bus operation procedure control circuit
62 DRAM controller
64 Memory map control circuit
70 Bus interface circuit
72, 74, 76 External bus
80 External DRAM device
82 Main memory
84 Video memory
90 External non-DRAM devices
92 External I / O device 92
110 First bus operation procedure circuit
112 DRAM controller
120 Second bus operation procedure circuit
122 Memory Map Control Circuit
130 DRAM bus terminal group
132, 134, 136 First external bus
140 Other buses / interfaces / terminals
142, 144, 146 Second external bus
510 CPU
530 LCD controller
540 reset circuit
550 Programmable timer
560 Real Time Clock (RTC)
570 DRAM controller and bus I / F
580 interrupt controller
590 serial interface
600 Bus controller
610 A / D converter
620 D / A converter
630 input port
640 output port
650 I / O port
660 Clock generator (PLL)
670 prescaler
680 Various buses
690 various pins
700 Microcomputer
710 ROM
720 RAM
800 Electronic equipment

Claims (3)

A semiconductor integrated circuit device including a CPU and an LCD controller and connected to a DRAM functioning as a main memory and a video memory,
Means for prefetching display data in the video memory area required by the LCD controller and holding it in a prefetch buffer;
Means for determining an urgency of an access request to the video memory area based on a holding status of the display data required by the LCD controller in the prefetch buffer;
A DRAM controller for controlling at least one of an access procedure to the DRAM and a refresh operation;
Connected to the external bus release request signal line,
The access request to the DRAM is a refresh request from the DRAM controller> a highly urgent access request to the video memory area> a bus release request from the outside> an access request from the CPU to the main storage area> to the video memory Priority control means for controlling to be executed in the priority order of access requests with low urgency;
A semiconductor integrated circuit comprising: A semiconductor integrated circuit device including a CPU and an LCD controller and connected to a DRAM functioning as a main memory and a video memory,
Means for prefetching display data in the video memory area required by the LCD controller and holding it in a prefetch buffer;
Means for determining an urgency of an access request to the video memory area based on a holding status of the display data required by the LCD controller in the prefetch buffer;
The access request to the DRAM is executed in the priority order of the access request with high urgency to the video memory area> the access request from the CPU to the main storage area> the access request with low urgency to the video memory. Priority control means for controlling,
The CPU is configured to be separately connectable to at least two buses, a first bus connected to the DRAM and a second bus connected to a device other than the DRAM,
The priority control means includes
It is determined whether the access target of the CPU is the DRAM area. If the access area is the DRAM area, the access request to the DRAM is a highly urgent access request to the video memory area> from the CPU to the main storage area Request to access> control the first bus so that it is executed in the priority order of the less urgent access request to the video memory;
A second bus operation procedure control circuit for controlling the operation of the second bus to which a device other than the DRAM is connected;
The second bus operation procedure control circuit includes:
A bus integrated circuit which controls the bus operation of the second bus according to the priority order of the access request from the CPU to a device other than the DRAM. In any one of Claims 1 thru | or 2.
A prefetch control circuit that receives a display data access request from the LCD controller to the video memory and returns the requested display data to the LCD controller;
The prefetch control circuit includes:
When the display data required by the LCD controller is not held in the prefetch buffer, when the display data access request is received from the LCD controller, the video memory is accessed to access the display data. Make an urgent access request and pass the display data accessed from the video memory area in response to the access request to the LCD controller,
When the display data required by the LCD controller is held in the prefetch buffer, when the display data access request is received from the LCD controller, the display data held in the prefetch buffer is received by the LCD controller. To
A read address is generated at a predetermined timing based on the video memory read logic of the LCD controller, an access request with a low degree of urgency is made to the video memory based on the generated read address, and the video according to the access request A semiconductor integrated circuit which performs control to hold display data accessed from a memory area in the prefetch buffer.

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