JP3711350B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a sidewall made of an insulating material on a side wall of a gate electrode.
[0002]
[Prior art]
Along with the recent improvement in performance of semiconductor devices such as system LSIs and logic LSIs, field effect transistors (FETs) are formed on SOI (Silicon on Insulator) substrates instead of conventional bulk Si substrates. Technology is used. This method uses an insulating substrate (SiO 2 ₂ This is a method of forming an FET on the above thin film silicon, and is superior in that the junction capacity can be reduced as compared with a conventional bulk substrate, so that the operation speed can be increased and the element isolation can be facilitated. In particular, a fully depleted FET formed on a thin-film SOI layer is attracting attention as a low power consumption device because it has a small parasitic capacitance and a sub-threshold coefficient (sub-threshold swing) smaller than that of the bulk. Furthermore, since the channel depletion layer width is determined by the SOI film thickness, it is effective for suppressing the short channel effect.
[0003]
In order to realize a complete depletion operation of an SOI device having these merits, it is necessary to reduce the SOI film thickness as the device is miniaturized. For example, IEICE Transactions C-II vol. J81-C-II No. 3 pp. As shown in 313-319 (1998), as the gate length is scaled to 0.35 μm, 0.25 μm, and 0.18 μm, the SOI film thickness has been reduced to about 60 nm, 50 nm, and 40 nm. Yes. In the generation of the gate length of 0.1 μm, the SOI thin film is required to be less than 20 nm, and the thickness is further reduced.
[0004]
When the SOI layer is thinned, the parasitic resistance of the source / drain diffusion layer is increased, and the current driving capability is significantly reduced. In order to avoid this, the resistance is generally reduced by forming silicide such as TiSix or CoSix on the diffusion layer. Taking CoSix silicide as an example, CO ₂ Si, CoSi, CoSi ₂ CoSi has the lowest resistance among the three reaction forms ₂ In order to selectively form the phase on the SOI substrate, Co having a certain optimum film thickness is sputter deposited on the thin film SOI substrate, for example, (550 ° C., 30 seconds) → (700 ° C., 60 seconds). CoSi by two-step thermal reaction process (RTA treatment) ₂ It has been reported that silicide can be stably formed (IEEE Electron Device Letters, Vol. 15, No. 9 (1994)).
[0005]
However, when the SOI layer is thinned, the amount of Si consumed by the reaction with Co is reduced, and miniaturization is limited. Furthermore, since the thin SOI layer is gradually reduced through various processes before the formation of silicide, the influence of these effects cannot be ignored as the device becomes finer and the SOI layer becomes thinner.
Further, the thinning of the SOI layer due to the above process makes the formation of the silicide layer unstable and may cause defects in some cases. In the subsequent contact hole formation process, if the contact falls to the defect, the BOX (Buried Oxide) layer penetrates through the defect at the bottom of the hole, resulting in a significant decrease in yield. . Accordingly, it is an extremely important issue in the development of a fine SOI device to reduce the film thickness reduction of the SOI layer caused by the above process as much as possible. In the present specification, the yield related to the penetration of the BOX layer is referred to as “BOX yield”.
[0006]
As a cause of the film thickness reduction of the SOI layer, the influence of the film thickness reduction of the SOI layer at the time of side wall spacer formation etching particularly used in the single drain structure or the LDD transistor structure is serious, and the film thickness reduction can be made almost zero. A sidewall formation etching technique with a very high selectivity to Si is required for a thin film SOI device.
The present invention has been made in view of the above-mentioned problems of the conventional method for producing a field effect transistor, and a first object of the present invention is to form a sidewall under ultrahigh selectivity etching conditions in a thin film SOI device. The present invention is to provide a novel and improved method for manufacturing a field effect transistor and an etching method capable of reducing the thickness of an SOI layer as much as possible.
[0007]
In addition, the second object of the present invention is to provide a stable and high level even when a sidewall is formed under ultra-high selectivity etching conditions in a thin film SOI device and the amount of reduction in the SOI layer is reduced as much as possible. It is to provide a novel and improved field effect transistor manufacturing method and etching method capable of having a current driving capability.
The third object of the present invention is to achieve a high yield even in the case where the sidewall is formed under the ultra-high selectivity etching condition in the thin film SOI device and the amount of reduction of the SOI layer is reduced as much as possible. It is an object of the present invention to provide a novel and improved field effect transistor manufacturing method and etching method that can be realized.
[0008]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, according to a first aspect of the present invention, as described in claim 1, a step of forming a gate electrode on a semiconductor substrate containing silicon, and the semiconductor including the gate electrode A step of forming an insulating film on the substrate; and performing anisotropic etching on the insulating film, and etching and removing the insulating film by an amount corresponding to 70% to 90% of the film thickness of the insulating film. And a second etching step for etching the remaining silicon oxide film under a condition in which the selectivity to silicon is higher than that of the anisotropic etching, and a field effect transistor comprising: A manufacturing method is provided.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a method for manufacturing a field effect transistor and an etching method according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.
[0010]
(First embodiment)
In the present embodiment, sidewall formation with an extremely high selectivity to Si that can reduce the amount of reduction in the SOI layer as much as possible will be described. As a result of searching for sidewall formation etching conditions with a very high selectivity to Si that can reduce the amount of reduction of the SOI layer as much as possible (substantially to zero), the inventor has found it extremely difficult to date. We have found practical process conditions that can achieve the ultra-high selectivity of about 500 that has been achieved. The method will be described below.
[0011]
(Dipole ring type magnetron RIE system 1)
First, a dipole ring type magnetron RIE (Reactive Ion Etching) apparatus will be described with reference to FIG. 1 as an example of a processing apparatus used in the following embodiments.
[0012]
The dipole ring-type magnetron RIE apparatus 1 has a processing chamber 2 that is an electrically sealed airtight container in its interior. An exhaust pipe 4 communicating with the vacuum pump 3 is connected to the bottom of the processing chamber 2. The inside of the processing chamber 2 can be uniformly evacuated from the bottom peripheral portion, and the processing chamber 2 can be set and maintained at an arbitrary pressure.
In the center of the processing chamber 2, a lower electrode 5 and a support base 6 are provided. The lower electrode 5 is configured such that high frequency power from a high frequency power source 7 provided outside the processing chamber 2 is supplied via a matching circuit 8 and a blocking capacitor 9.
[0013]
An upper electrode 12 is provided in the upper part of the processing chamber 2. A number of gas diffusion holes 13 are formed on the surface of the upper electrode 12 facing the semiconductor wafer W. The processing gas (etching gas) supplied from the gas inlet 14 provided on the upper portion of the upper electrode 12 is configured to be discharged uniformly from the gas diffusion holes 13 toward the semiconductor wafer W. ing.
Permanent magnets 15 are arranged on the side surface of the processing chamber 2 in the vicinity thereof. The permanent magnet 15 is configured to rotate with the gas introduction port 14 as its rotation center axis at a desired rotation speed by a drive mechanism (not shown) such as a motor. The permanent magnet 15 can form a uniform parallel magnetic field on the surface of the semiconductor wafer W.
[0014]
The dipole ring type magnetron RIE apparatus 1 is used in FIG. _Three / CO mixed gas (mixing ratio = 15% / 85%) ₂ Etching rate of each film with respect to the total gas flow rate when etching the film and Si, SiO ₂ The change of / Si selectivity is shown. Here, the pressure and RF power conditions are fixed at 35 mTorr and 1600 W, respectively. Similarly, the change of the selection ratio with respect to the total pressure is shown in FIG. RF power, CHF _Three The / CO gas flow rate conditions are fixed at 1600 W and 45/255 (sccm), respectively.
[0015]
2 and 3, the higher the total gas flow rate, that is, the shorter the gas residence time (see FIG. 2), and the higher the total pressure (see FIG. 3), ₂ It can be seen that the / Si selectivity increases. In particular, as shown in the results of FIG. _Three Under a high flow rate of / CO = 45/255 (sccm) and a high pressure of 70 mTorr, an ultrahigh selectivity of about 500 was achieved. Note that a practically sufficient ultra-high selection ratio can be achieved under a high pressure condition of 60 mTorr or higher (for example, 65 mTorr).
[0016]
SiO at this time ₂ A practical value of 380 nm / min was ensured for the etching rate of the film, and the amount of abrasion during overetching of about 30% could be substantially zero. When this condition was applied to the sidewall formation etching process in an actual 0.15 μm SOI device (SOI film thickness = 35 nm), the amount of reduction of the SOI layer at the flat portion was almost zero.
As described above, according to the present embodiment, the amount of reduction in the SOI layer caused by the process can be substantially reduced to zero, which is extremely useful in the development of a fine SOI device.
The first embodiment described above can substantially reduce the amount of reduction in the SOI layer caused by the process, and is extremely useful in the development of a fine SOI device.
[0017]
(Second Embodiment)
In the second embodiment, a case will be described in which the etching conditions described in the first embodiment are applied to the formation of a sidewall of a MOS transistor.
When the etching conditions described in the first embodiment are applied as they are to the sidewalls of the MOS transistor, there is a case where the variation of current knowledge becomes large particularly in a single drain structure transistor.
The inventor first transmits the sidewall shape after etching in order to investigate the cause of the large variation in the current value in the single drain structure transistor when the above-described ultra-high selectivity SW etching condition of about 500 is used. It analyzed in detail using the electron microscope (TEM). FIG. 4 is an explanatory view showing a state in which the sidewall spacer 23 is formed on the side wall of the gate (gate electrode 21, gate oxide film 22) on the SOI substrate 25. As shown in FIG. As a result, as shown in FIG. 4, it was found that a part of the sidewall shape is tapered (tapered portion 24) (tail is pulled).
[0018]
This is because CHF is used as an etching gas for sidewall formation in order to achieve an ultra-high selectivity. _Three This is probably because a highly polymerized gas such as / CO was used, so that a CF-based polymer film was deposited thickly on the pattern side wall, and it acted as a mask on the side wall during etching. The deposition rate of the polymer film on the side wall is very sensitive to changes in process parameters such as pressure and temperature. For example, if these process parameters vary in the wafer surface, This will directly lead to variations in the taper angle of the tail part.
[0019]
The width of the side wall spacer is a very important parameter in determining the concentration profile at the time of impurity implantation by ion implantation from an oblique direction, particularly in the case of a single drain structure transistor. Therefore, the tail shape has a wider sidewall width than that of the vertical shape. Therefore, the impurity concentration profile easily changes with a slight change in the taper angle, resulting in the current value of the transistor. Cause fluctuations. In particular, when the taper width varies in the direction of increasing, the effective sidewall width may deviate significantly from the target value, impurity ions may not reach the vicinity of the gate, and the current value may be offset. I understood. Therefore, it was concluded that verticalization of the sidewall shape is essential for stabilizing the transistor operation.
[0020]
The inventor conducted an experiment of sidewall spacer formation etching using various fluorocarbon plasmas, and investigated in detail the relationship between the selectivity to Si and the sidewall shape. As a result, the high selectivity and the verticalization of the sidewall shape are in a trade-off relationship. For example, it is virtually impossible to achieve the ultra-high selectivity of about 500 and the vertical sidewall shape at the same time. I understood. This is considered to be mainly due to the use of a technique for selectively depositing a fluorocarbon polymer film on Si as a means for achieving a high selectivity. This is because a thick polymer film that causes a tail shape is also deposited on the side wall of the sidewall.
[0021]
However, by using a new method described below, it has become possible to simultaneously achieve a vertical sidewall shape without Si scraping. By using this method, a vertical side wall spacer 33 having no tail portion and no Si scraping as shown in FIG. 5 can be formed. When this process was applied to an actual SOI device, the instability of transistor operation, particularly the above-described problem of offset current, was dramatically improved.
[0022]
Hereinafter, an etching process capable of simultaneously achieving an ultra-high selectivity to Si and a vertical sidewall shape will be described.
As described above, within the scope of the experiments conducted by the inventors, no matter what kind of fluorocarbon gas plasma is used, the high selectivity to Si and the verticalization of the sidewall shape are in a trade-off relationship. It turns out that these cannot be achieved at the same time. In order to solve this problem, the conventional concept of single-step etching was stopped, and the etching process was divided into two steps. For each step, (1) vertical processing of the sidewall and (2) high Si selection I came up with the idea of having two different roles of securing the ratio independently.
[0023]
The inventor investigated the relationship between the ratio of the etching amount and the sidewall shape in each step (1) and (2) of the total thickness of the film to be etched, and within the range of the experiment, (2) It has been found that when the ratio of the etching amount in the high selectivity step exceeds 30% of the film thickness of the whole film to be etched, the shape has a tail. That is, the etching amount of step (1) is about 70% to 90% (preferably about 90%), and the etching amount of step (2) is about 30% to 10% (preferably about 10%). Thus, it was found that a vertical sidewall shape can be obtained while ensuring an ultrahigh selectivity. Hereinafter, the specific method will be described with reference to FIG.
[0024]
200nm high gate Electrode 21 On top, SiO is formed by CVD (Chemical Vapor Deposition). ₂ After depositing 1500 liters of the film 26 (FIG. 6A), first, as a step (1), a dipole ring type magnetron RIE apparatus is used. _Four F ₈ / Ar (= 20/500 (sccm)) mixed gas at 40 mTorr and 800 W with the above SiO ₂ The film is etched by 1350 mm corresponding to 70% to 90%, preferably 90% of the total film thickness (FIG. 6B). C _Four F ₈ / Ar = 20/500 (sccm) is merely an example, and the ratio of the Ar gas flow rate to the total gas flow rate may be 90% or more.
[0025]
Subsequently, as the step (2), the remaining SiO in the same chamber. ₂ 150 mm (10% of the total film thickness) of the film 26 'is etched under a high selection ratio condition (FIG. 6C). As a high selection ratio condition, for example, the above-mentioned CHF _Three A selection ratio of about 500 can be achieved by performing RF power at 1600 W under a high flow rate and high pressure condition of / CO = 45/255 (sccm), pressure of 70 mTorr. Since the etching amount in this step is as low as 150 mm or less, and the etching time is short (about several seconds), the effect of tail formation by polymer film deposition on the side wall is negligible.
[0026]
As described above, according to the present embodiment, the etching of the side wall spacer is divided into two steps, and for each step, (1) vertical processing of the side wall and (2) ensuring a high Si to selectivity ratio. Thus, it was possible to achieve both the high selectivity to Si and the vertical processing that were in a trade-off relationship at the same time. By applying this technique to a thin film SOI device, the operational stability of a single drain structure transistor has been dramatically improved.
[0027]
In addition, since the FET structure having the vertical sidewall spacers 33 is employed without the SOI layer (Si) under the FET being scraped, the single drain is particularly effective when the SOI layer (Si) scraping is reduced by the conventional sidewall etching. The instability of the operation, which has been a problem with the structure transistor, has been solved, and stable FET operation has become possible.
[0028]
(Third embodiment)
This embodiment is for solving the problem that the effect of the second embodiment cannot be obtained with respect to specific etching conditions, and is an indispensable condition for the first etching step. ₂ It is characterized by adding gas.
[0029]
In the second embodiment, it has been shown that a high selectivity to Si and vertical processing can be achieved simultaneously by dividing the etching of the sidewall spacer into two steps. However, experiments have shown that if certain etching conditions are used for the first step, the vertical shape may not be achieved even if the etching is divided into two steps. For example, CHF in the first step _Three / Ar and CHF _Three / CF _Four When / Ar or the like is used, the shape becomes a shape with a tail even if the above-described two-step process is used. This is considered to be caused by the fact that an unnecessary deposition effect on the side wall portion is promoted in the first step originally intended only for vertical machining.
[0030]
The inventor examined changes in the sidewall shape when various types of gases were used for the first etching step while the second etching step conditions were fixed. As a result, no matter what kind of gas is used for the first etching step, O gas is commonly used. ₂ It was found that the shape can be verticalized by adding gas. As the gas for the first etching step, for example, C in the second embodiment is used. _Four F ₈ / Ar to O ₂ Plus C _Four F ₈ / O ₂ / Ar (= 20/10/500 (sccm)), CHF _Three / O ₂ / Ar, CHF _Three / CF _Four / O ₂ / Ar, CF _Four / O ₂ Vertical processing becomes possible by using a mixed gas such as / Ar.
As described above, in the present embodiment, the etching of the sidewall spacer is divided into two steps, and the first step includes O ₂ Since the process of adding Si was used, it was possible to solve the problem that the sidewall shape was not vertical even if divided into two steps, and it was possible to achieve a high selectivity to Si and vertical processing at the same time. By applying this technology to a thin film SOI device, the operational stability of a single drain structure transistor has been dramatically improved.
[0031]
(Fourth embodiment)
The purpose of this embodiment is to improve the BOX yield.
In the second and third embodiments, the structure of the FET that solves the problem that the operation of the single drain structure transistor becomes unstable when the sidewall is formed under the ultra-high selectivity etching condition, and The manufacturing method has been described. In addition, it was shown that the amount of decrease in the SOI layer thickness can be reduced as much as possible by the sidewall formation process developed here, and the minimum remaining thickness of the SOI layer necessary for the subsequent process can be secured.
[0032]
The remaining film thickness of the SOI layer is secured by stable CoSi. ₂ Silicide was selectively formed to improve the current driving capability.
In the present embodiment, a method for manufacturing a semiconductor device that can drastically improve the yield reduction of the BOX layer at the hole bottom will be described in the subsequent contact hole formation process for the Co silicide layer.
[0033]
In order to investigate the cause of the decrease in the yield of the BOX layer at the hole bottom, the inventor uses the shape of the sidewall when the sidewall is formed by the two-step etching method described in the second and third embodiments as a transmission electron. Detailed analysis was performed using a microscope (TEM). As a result, as shown in FIG. 7, although the Si scraping at the flat portion is almost zero, the Si scraping of about 50 mm is called a sub-trench (also referred to as trenching) at the side wall end. 47 was found to occur locally.
[0034]
Although details of the sub-trench generation mechanism are unknown at this stage, (1) reflection of ions on the side wall of the sidewall, (2) change of trajectory of incident ions due to electric field distortion near the side wall, (3) A shielding effect of polymer film deposition (protection effect from ion bombardment) in the vicinity of the pattern can be considered.
[0035]
As a result of the analysis, since the SOI film thickness is effectively reduced in the sub-trench portion, stable CoSi is obtained thereafter. ₂ When silicide is formed, it has been found that since the amount of Si consumed by reaction with Co is small in the sub-trench portion, metal-rich CoSix with higher resistance is formed. This metal-rich CoSix layer is chemically unstable near the aforementioned second RTA temperature (usually 750 to 850 ° C.), and CoSi in the CoSix is liberated during the heat treatment so that the surface energy is stable. ₂ Try to become.
[0036]
The released Co is CoSi. ₂ Diffusion to the layer or diffusion to the Si layer under the sidewall to form an alloy with Si, but at this time, CoSix / CoSi ₂ Crystal grain growth occurs through the interface (that is, the sub-trenched portion), and cracks are generated at the interface. As this progresses, defects occur. When a contact hole is opened on this defect, the BOX layer penetrates through the defect at the bottom of the hole and reaches the Si substrate. In particular, it has been found that when a hole is opened in contact with a gate or a side wall as in a self-alignment contact, the possibility of penetration of the BOX layer is dramatically improved.
[0037]
Therefore, it was concluded that it is essential to eliminate the sub-trench (the local scraping of Si) at the end of the sidewall in order to improve the drop in BOX yield.
The inventor conducted experiments on sidewall spacer formation etching using various fluorocarbon plasmas, and as a result, no matter what conditions were used, SiO at the end of the sidewall was obtained. ₂ It was found that the etching rate of the film was increased, and the net to Si selectivity in this portion was also low. However, by using the method described in detail below, it is possible to achieve a vertical sidewall shape without sub-trench.
[0038]
By using this method, it is possible to form a vertical sidewall spacer having no tail portion and having no Si scraping as shown in FIG. When this process was applied to an actual 0.15 μm SOI device, the instability of transistor operation, particularly the above-described problem of offset current, was dramatically improved.
[0039]
Hereinafter, a sidewall formation etching method without a sub-trench will be described.
As described above, when sidewall etching is performed under a single condition, SiO at the edge of the sidewall ₂ It was found that the etching rate was high and the net to Si selectivity in this part was also low. The reason for the poor local selectivity at the side wall end is that the etching ends at the side wall end earlier than the flat part and Si appears, so that the SiO still remaining in the flat part at that time. ₂ It is thought that O, which is a reaction product from the above, attacks this portion and removes the fluorocarbon polymer film as an etching protective layer. Accordingly, it is considered that Si scraping locally occurs even when the selection ratio of the second step is as high as 500.
[0040]
In order to solve this problem, the inventor in the second step etching, from the time Si first appears at the sidewall end until the sidewall etching is completely completed, that is, Si at the sidewall end is O.sub.2. During the attack, a thick polymer film is deposited by exposing the Si to a plasma having a very high deposition property so that even if attacked from O during this time, it is not completely removed. did. The specific etching conditions will be described below.
[0041]
As described in the second embodiment, first, as a first step, a die ball ring type magnetron RIE apparatus is used. _Four F ₈ / O ₂ / Ar (= 20/10/500 (sccm)) mixed gas at 40 mTorr and 800 W with the above SiO ₂ The film is etched by 1350 mm corresponding to 90% of the total film thickness. Subsequently, the remaining 150 mm is etched in the same chamber under the condition of the above extremely high deposition property.
[0042]
As a condition of the second step, for example, CHF _Three / CO = 45/255 (sccm), under a high flow rate of 70 mTorr and high pressure, by performing RF power at 800 W, which is lower than 1600 W shown in the second embodiment, the selection ratio is increased. A very high ultra-high selectivity can be achieved. Thus, by making the selectivity ratio to Si extremely larger than 500, it is possible to form vertical sidewalls without subtrenching.
[0043]
As a result of evaluating various fluorocarbon plasmas, the inventor has found that there are very limited practical gas species that can obtain the above-mentioned ultra-high selectivity. That is, CHF is used as an etching gas. _Three / CO (= 45/255 (sccm)) or CH ₂ F ₂ / CO or CH ₂ F ₂ / CHF _Three It was found necessary to use a mixed gas of / CO.
[0044]
As described above, in this embodiment, the etching of the sidewall spacer is divided into two steps, and the second etching step is CHF. _Three / CO or CH ₂ F ₂ / CO or CH ₂ F ₂ / CHF _Three Because the selectivity ratio to Si is made extremely high by using a mixed gas of / CO, sub-trench which has been generated at the end of the side wall is suppressed, and a vertical side wall spacer without Si scraping is formed. Became possible. By applying this technology to thin film SOI devices, it has become possible to dramatically improve the reduction in the BOX yield of SOI devices.
[0045]
The preferred embodiments of the method for manufacturing a field effect transistor and the etching method according to the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to this example. It is obvious for those skilled in the art that various modifications or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.
[0046]
For example, in the above embodiment, SiO deposited on the gate electrode formed on the SOI substrate. ₂ Although the case where the film is etched has been described, the present invention is not limited to this. SiO deposited on the gate electrode formed on the Si substrate ₂ Even when the film is etched, the present invention can be applied, and damage to the surface of the Si substrate can be reduced.
[0047]
(Fifth embodiment)
In the fifth embodiment, a case where a silicon nitride film is used as a sidewall in the second embodiment will be described.
In recent years, with the miniaturization of semiconductor elements, a technique called SAC (Self-aligned Contact) has attracted attention.
In the SAC structure, a silicon nitride film is formed on the top and side walls of a gate electrode of a transistor, and when a contact hole reaching the source and drain of the transistor is formed, the contact hole is opened in a self-aligned manner by the silicon nitride film. Technology.
[0048]
This silicon nitride film plays a role as an ion implantation mask at the same time for controlling the impurity profile of the channel region in an LDD transistor, a single drain transistor, etc., and its width and shape control are extremely important for stable operation of the transistor. It becomes. Therefore, in the case of the above SAC structure, the sidewall formation etching by the silicon nitride film having an extremely high selectivity to Si, which can reduce the film thickness of the silicon layer in the SOI substrate to almost zero, and at the same time, the width and shape of the sidewall Is required to be controlled with high accuracy.
[0049]
In the present embodiment, as a result of searching for sidewall formation etching conditions for a silicon nitride film having a very high Si-to-Si selectivity so that the amount of SOI layer reduction can be made substantially zero, it has been extremely difficult to date. We have found a practical process condition in which an ultra-high selection ratio of about 500 is obtained and the uniformity within the wafer surface is within ± 5%. The method is described below.
[0050]
In order to construct a high selectivity process between the silicon nitride film and silicon during sidewall etching of the silicon nitride film, the inventors first applied the etching conditions in the first embodiment to the silicon nitride film.
In this case, the selectivity between the silicon nitride film and silicon could be achieved as high as 200 or higher, but the uniformity within the wafer surface was extremely deteriorated.
[0051]
As an example, a dipole ring type magnetron RIE apparatus is used in FIG. _Three / CO flow rate = 30/170 (sccm), RF power 800 W, electrode spacing 27 mm, Si under different pressure conditions from 15 to 70 mTorr _Three N _Four , Si etching rates and Si _Three N _Four The change of / Si selectivity is shown.
Also, Si at that time _Three N _Four The in-plane uniformity of the etching rate (6 inch wafer surface) is also shown in the same graph.
[0052]
As shown in FIG. _Three N _Four The etching rate of Si gradually increases, but on the contrary, the etching rate of Si decreases, resulting in Si _Three N _Four / Si selectivity is improved. This tendency is similar to the SiO shown in the first embodiment. ₂ This is consistent with the change in the / Si selectivity.
[0053]
FIG. 8 shows that a high selection ratio of 200 or more can be achieved under a high pressure condition of 70 mTorr. However, on the other hand, unlike in the case of the sidewall of the silicon oxide film, the in-plane uniformity gradually deteriorates as the pressure increases, and reaches ± 19% at 70 mTorr. This tendency is exactly the same for the gas flow rate. The higher the flow rate, the more Si _Three N _Four However, the in-plane uniformity deteriorated. Thus Si _Three N _Four / Si high selectivity and in-plane uniformity are in a trade-off relationship, and it was found that some technical improvement is necessary. It has been found that there is an optimum pressure condition for uniformity, and it is minimized at 20 to 30 mTorr as shown in FIG.
[0054]
Next, the inventor made Si in the above trade-off relationship. _Three N _Four As a result of searching for a new gas species that can overcome the problems of high Si / Si high selectivity and in-plane uniformity, _Three / CH gas under low pressure and low flow conditions where high uniformity can be obtained with CO gas system ₂ F ₂ It has been found that the selectivity can be made extremely high by adding gas without deteriorating the uniformity.
[0055]
FIG. 9 shows CO flow rate = 170 (sccm), CHF _Three + CH ₂ F ₂ = 30 (sccm), RF power 800W, electrode spacing 40mm _{3 /} CH ₂ F ₂ Si when changing the flow rate ratio of _Three N _Four Etching rate of Si film, Si film and Si _Three N _Four The change of / Si selectivity is shown. Si _Three N _Four The in-plane uniformity of the etching rate is also shown in the same graph.
[0056]
CH ₂ F ₂ As the flow rate ratio increases, Si _Three N _Four / Si etch rate increases slightly, but Si etch rate decreases, resulting in Si _Three N _Four / Si selectivity increases. On the other hand, it can be seen that the in-plane uniformity does not deteriorate extremely even when the selection ratio is high, and both are within ± 5%.
CHF _{3 /} CH ₂ F ₂ = 15/15 (sccm), Si _Three N _Four / Si selection ratio of about 500 and uniformity of ± 4.8% were achieved. Si at this time _Three N _Four A practical value of 160 nm / min was secured for the etching rate of the film, and the amount of Si scraped during overetching of about 30% could be substantially reduced to zero.
[0057]
As described above, the conditions for etching the silicon nitride film formed on the silicon are as follows.
(1) CHF as etching gas _Three + CH ₂ F ₂ Using a mixed gas of + CO,
(2) Hold the pressure condition at 20-30 mTorr,
(3) CHF _Three + CH ₂ F ₂ CH in gas ₂ F ₂ Since the mixing ratio was set to 30% or more, Si _Three N _Four / Si selection ratio and uniformity problem are both solved, while maintaining uniformity ± 5% _Three N _Four / Si selection ratio of 500 or more can be achieved.
[0058]
(Sixth embodiment)
In the sixth embodiment, an example will be described in which the etching conditions described in the fifth embodiment are applied to etching at the time of forming a sidewall of a MOS transistor.
Under the etching conditions described in the fifth embodiment, Si _Three N _Four Also in the case of etching, as described in the second embodiment, it has been found that a part of the sidewall is tapered (the tail is pulled).
[0059]
This is because CHF is used as an etching gas for sidewall formation in order to achieve an ultra-high selectivity. _Three + CH ₂ F ₂ This is probably because a highly polymerized gas of + CO was used, so that a CF-based polymer film was deposited thickly on the side wall of the pattern, and it acted as a mask on the side wall during etching. The deposition rate of the polymer film on the side wall is very sensitive to changes in process parameters such as pressure and temperature. For example, if these process parameters vary in the wafer surface, This will directly lead to variations in the taper angle of the tail part.
[0060]
The width of the side wall spacer is a very important parameter in determining the concentration profile at the time of impurity implantation by ion implantation from an oblique direction, particularly in the case of a single drain structure transistor. Therefore, since the tail shape has a wider sidewall width than that of the vertical shape, the impurity implantation concentration profile easily changes with a slight change in the taper angle. It causes fluctuations in value. In particular, when the width of the tapered portion varies, the effective sidewall width may deviate from the target value, impurity ions may not reach the vicinity of the gate, and the current value may be offset. all right. Therefore, it was concluded that verticalization of the sidewall shape is essential for stabilizing the transistor operation.
[0061]
The inventor conducted an experiment of side wall spacer formation etching using various fluorocarbon plasmas, and investigated in detail the relationship between the selectivity to Si and the side wall shape. As a result, the high selectivity and the verticalization of the sidewall shape are in a trade-off relationship, for example, it is practically impossible to achieve the ultra-high selectivity of about 500 and the vertical sidewall shape at the same time. I understood. This is considered to be mainly due to the use of a method of selectively depositing a thick fluorocarbon polymer film on Si as a means for achieving a high selectivity (the tail wall is also tailed at the same time). Because a thick polymer film that causes the shape is deposited).
[0062]
In the sixth embodiment, the etching process is performed in two etching steps, and (1) Si for each step. _Three N _Four He came up with the idea of having two different roles, vertical processing of the sidewalls and (2) ensuring a high selectivity to Si.
Of the total thickness of the film to be etched, the ratio of the etching amount in each step (1), (2) and Si _Three N _Four As a result of investigating the relationship between the sidewall shapes, the tail was pulled when the ratio of the etching amount at the high selectivity step (2) exceeded 30% of the entire film thickness to be etched within the range of the experiment. It turns out that it becomes a different shape.
That is, the etching amount of step (2) is set to Si. _Three N _Four 30% or less of the film thickness, (1) is Si _Three N _Four It was found that a vertical sidewall shape can be obtained while ensuring a very high selection ratio by setting the film thickness to 70% or more.
[0063]
The specific method will be described below with reference to FIG.
First, as shown in FIG. 10A, a gate insulating film 102 and a gate electrode film 103 are sequentially formed on a silicon film 101 of a semiconductor wafer, and then Si _Three N _Four The gate electrode film 103 and the gate insulating film 102 are etched using the hard mask 104 as a mask. The height of the gate electrode at this time is, for example, 200 nm.
The silicon film 101 is, for example, a silicon layer formed on an insulating film in an SOI substrate.
[0064]
Next, Si is formed on the entire surface of the semiconductor wafer by LP-CVD. _Three N _Four Deposit 500 liters of film 105.
Next, as shown in FIG. 10 (b), a dipole ring-type magnetron RIE apparatus is used and CHF is used. _Three / O ₂ / Ar (flow rate 30/5/150 (sccm)) mixed gas at 25 mTorr, RF power 300 W, Si _Three N _Four The film 105 is etched by 350 mm corresponding to 70% of the total film thickness. Under this condition, Si _Three N _Four The film 105 is etched substantially vertically.
Here, CHF _Three / O ₂ / Ar mixed gas was used, but CHF _Three / CF _Four / O ₂ / Ar mixed gas and CF _Four / O ₂ It is also possible to use a / Ar mixed gas. Thus, O ₂ By using the gas containing, it becomes possible to suppress unnecessary deposition effects on the side wall portion.
[0065]
Next, as shown in FIG. _Three N _Four The remaining 150 mm (30% of the total film thickness) of the film 105 is etched under the high selectivity condition described in the fifth embodiment. As a high selection ratio condition, for example, CHF _{3 /} CH ₂ F _{2 /} By using CO = 15/15/170 (sccm), RF power of 800 W, and electrode spacing of 40 mm, a selection ratio of about 500 can be achieved. Since the etching amount in this step is as low as 150 mm or less, and therefore the etching time is short (about several seconds), the effect of tailing by polymer film deposition on the side wall is negligible. Further, it is desirable that these two etching steps are continuously performed in the same chamber.
[0066]
Thus, in the sixth embodiment, Si _Three N _Four The sidewall spacer etching is divided into a plurality of steps, and (1) Si for each step. _Three N _Four Since the two different roles of vertical processing of the sidewall and (2) securing of the high selectivity to Si are independently performed, the high selectivity to Si and the vertical processing, which were in a conventional trade-off relationship, are simultaneously performed. It became possible to achieve.
[0067]
【The invention's effect】
As described above, according to the present invention, in a thin film SOI device, it is possible to form a sidewall under ultra-high selectivity etching conditions, and to reduce the amount of reduction in the SOI layer as much as possible. Furthermore, even when the amount of reduction of the SOI layer is reduced as much as possible, it is possible to provide a field effect transistor having a stable and high current driving capability. Furthermore, even when the amount of reduction of the SOI layer is reduced as much as possible, a high yield can be realized.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a dipole ring type magnetron RIE apparatus.
FIG. 2 CHF _Three / SiO for total gas flow rate ₂ Si etching rate and SiO ₂ It is explanatory drawing which shows the change of / Si selectivity.
FIG. 3 CHF _Three / SiO for the total pressure of CO gas ₂ Si etching rate and SiO ₂ It is explanatory drawing which shows the change of / Si selectivity.
FIG. 4 shows a high selectivity ratio against Si (CHF). _Three It is explanatory drawing which shows the shape at the time of forming a side wall spacer by / etching in a single step using / CO gas.
FIG. 5 is an explanatory diagram showing an FET structure according to a second embodiment.
6A and 6B are explanatory views showing an FET structure according to a second embodiment, in which FIG. 6A shows a shape before etching, FIG. 6B shows an etching shape in a first step, and FIG. This is the etching shape of the step.
FIG. 7 is an explanatory diagram showing local Si collapse (sub-trench or trenching) at the end of a sidewall spacer when vertical processing is performed with a high selectivity to Si.
FIG. 8 CHF _Three / Si for all gas pressure _Three N _Four , Si etching rate and Si _Three N _Four It is explanatory drawing which shows the change of / Si selectivity.
FIG. 9 CH ₂ F ₂ / CHF _Three Si against flow ratio _Three N _Four , Si etching rate and Si _Three N _Four It is explanatory drawing which shows the change of / Si selectivity.
10A and 10B are explanatory views showing an FET structure according to a sixth embodiment, wherein FIG. 10A shows a shape before etching, FIG. 10B shows an etching shape in the first step, and FIG. 10C shows a second shape. This is the etching shape of the step.
[Explanation of symbols]
21 Gate electrode
22 Gate oxide film
25 Si substrate
26 SiO ₂ film
33 Sidewall spacer

Claims (4)

Forming a gate electrode on a semiconductor substrate containing silicon;
Forming an insulating film on the semiconductor substrate including the gate electrode;
A first etching step in which anisotropic etching is performed on the insulating film, and the insulating film is etched away by an amount corresponding to 70% to 90% of the thickness of the insulating film;
A second etching step of etching the remaining insulating film under a condition where the selectivity to silicon is higher than that of the anisotropic etching and the selectivity to silicon is 500 or more;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the first etching step and the second etching step are performed using the same etching apparatus. .   2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is a semiconductor substrate having an insulating layer and a silicon layer formed on the insulating layer, and the gate electrode is formed on the silicon layer. A method of manufacturing a semiconductor device.

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