JP3698949B2 - Function allocation optimization apparatus for instruction cache, function allocation optimization method, and recording medium recording function allocation optimization procedure - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an instruction cache function allocation optimization device, a function allocation optimization method, and a recording medium storing a function allocation optimization procedure, and more particularly, to a function allocation optimization device to an instruction cache in a microprocessor system equipped with a cache, The present invention relates to a function allocation optimization method and a recording medium on which a function allocation optimization procedure is recorded.
[0002]
[Prior art]
In the processing speed of this type of microprocessor system, in addition to the CPU speed, the access to the external memory which is the main memory, that is, the memory access processing speed (hereinafter referred to as memory access speed) is greatly affected. However, the improvement in memory access speed is not so large with respect to the recent significant increase in CPU speed, and the difference between CPU speed and memory access speed is increasing year by year. For example, there is data that the improvement rate of DRAM access time is about 7% per year, while the improvement rate of CPU speed is 50-100% (David A. Patterson, John A. Patterson, David A. Patterson, (John L. Hennessy), translated by Mitsuaki Narita, “Computer Configuration and Design”, Nikkei Business Publications, April 19, 1996).
[0003]
Therefore, effective use of the cache has become a very important issue for improving the system processing speed. As is well known, the cache is a mechanism comprising a buffer that is a small-capacity high-speed memory for accessing an external memory at high speed. Generally, a program processes functions arranged in a memory in the order of addresses. However, since the memory access speed of the external memory is very slow compared with the processing speed of the CPU, there is a problem that the execution speed becomes slow as a result.
[0004]
In order to solve the above problems, high-speed program execution can be realized by copying the program stored in the external memory to the cache, which is a buffer that can be accessed at high speed, when executing the function. Is possible. This is because, generally, when a program is executed, a memory once accessed is likely to be accessed again soon.
[0005]
However, in general, a high-speed cache memory is expensive compared to an external memory, and its configuration is expensive, so its capacity (size) is very small compared to an external memory. For this reason, a processing system using a cache divides the external memory into areas divided by the size of the cache, and allocates the external memory to the cache for each divided area. In the first access to an address, the program at that address is copied to the cache allocation area, and when the same address in the external memory is accessed next, the cache is directly accessed. This realizes high-speed program execution.
[0006]
At this time, copying from the external memory to the cache memory is performed in units of a specific size, and an area obtained by dividing the cache by this size is called a cache line. Therefore, it is necessary to copy the program between the functions arranged at the addresses of the external memory allocated to the same cache line every time the functions are switched. This is called a cache conflict. If this cache conflict frequently occurs, there is a problem that the execution speed of the program becomes slow as a result. Therefore, in recent years, a method has been studied in which functions that are likely to move simultaneously are arranged so as not to be placed in the same cache line in order to solve this problem.
[0007]
The cache includes an instruction cache and a data cache. The present invention focuses on the instruction cache.
[0008]
External memory cache allocation methods include the simplest and cheapest direct map method and set associative / full associative methods, but the basic problems are the same. I will explain to you.
[0009]
In the conventional language processing system program, each processing unit (function) is appropriately arranged in the memory. For this reason, in a system equipped with a cache, it is not always optimally used.
[0010]
In the latest conventional technology, in order to reduce the number of cache conflicts stochastically, research on how to effectively use the cache by optimizing the function memory allocation based on the function call count information has been made. Several algorithms have been published.
[0011]
For example, AH Hassemi, D.R. Kaeli, B. Calda, “Efficient Mapping Procedure Using Cache Line Coloring” (AH Hashemi, DR Kaeli, B. Calder “Efficient Procedure”. “Mapping Using Cache Line Coloring”) ACM SIGPLAN, June 1997, (Reference 1) discloses a method for optimizing the memory allocation of functions so as to avoid cache conflicts in descending order of the number of calls. .
[0012]
Further, in the conventional function allocation optimization method for the first instruction cache described in Japanese Patent Application Laid-Open No. 11-232117 (Document 2), as an example of the function allocation method for efficiently using the cache memory, The method of literature 1 is adopted and explained in detail.
[0013]
In the algorithm of this prior art, a call graph of a function is created, and the number of calls is prioritized as a weight for that edge (function combination) and placed in a memory space. This avoids a cache conflict when the function is first placed. Furthermore, a set of “used color” (that is, used cache line) in which each function is arranged and “unavailable color” that the function cannot currently use is recorded, and the latter, that is, an unusable color. The function is arranged so that it is not used, and the function that has already been arranged is moved to another place under the condition that the unavailable color of the function is not used. This eliminates cache conflicts that occur with the direct “parent” or “child”.
[0014]
Next, the operation in the conventional example for the application program applied in the embodiment of the present invention to be described later is confirmed. Thus, problems in the conventional example will be described in more detail.
[0015]
Referring to FIG. 10 showing a block diagram of a conventional function allocation optimization apparatus for a first instruction cache, the conventional function allocation optimization apparatus for a first instruction cache reads function call information from an application program 110. The function call information output unit 1 outputs the function information of the caller and the callee and the number of calls to the function call combination information 111 when the function is called, and the function layout is optimized based on the function call combination information 111 to address space And a function memory arrangement optimizing unit 103 that outputs the function memory arrangement result 104.
[0016]
Referring to FIG. 10, FIG. 11 showing the processing flow of the function memory arrangement optimizing unit 103 in a flowchart, and FIG. 3 showing an example of the application program, the conventional function allocation optimization device for the first instruction cache The conventional function allocation optimization method for the first instruction cache, which is the operation, will be described. First, when the application program 110 shown in FIG. 3 is applied, the function call information output unit 1 calls the caller at the time of function call according to the profile. Each function information of the call destination and the number of calls are output to the function call combination information 111. In FIGS. 10 and 11, solid arrows indicate the flow of processing, and dotted arrows indicate the flow of data.
[0017]
Referring to FIG. 2 showing an example of the function call combination information 111, the function call combination information 111 includes columns of function call source, call destination, and number of calls.
[0018]
Next, the function memory arrangement optimizing unit 103 sorts the function call combination information 111 in descending order of the number of calls, arranges the function call combination information 111 in this order in the address space, and simultaneously uses the “unusable color” corresponding to the cache line in which the arranged function cannot be used. Recognizing a set of and avoiding this and placing subsequent functions.
[0019]
That is, in FIG. 9, in step P1, the function call graph 120 shown in FIG. 12 is created from the function call combination information 111, and in step P2, the created function function call graph 120 is divided into one with a large number of calls and one with a small number of calls. . Here, func-funcA, func-funcB, and func-funcC are the former “many”, and main-func, funcA-funcD, and funcB-funcD are the latter “small”.
[0020]
In the function call graph 120 created here, a combination of functions is an edge, and nodes at both ends thereof are two functions in the combination.
[0021]
Note that the number of cache lines, that is, the number of “colors” occupied by each function in FIG. 3 is two func and one each of funcA, funcB, funkC, and main.
[0022]
Next, in step P3, groups having a large number of calls are sorted in descending order of the number of calls, and the processes after step P4 are performed in that order. In step P4, it is confirmed whether a side with a large number of calls remains. Since it remains, the process proceeds to step P5, and it is confirmed whether nodes on both sides with respect to the side of func-funcA are not arranged. In this confirmation, since it is not arranged, the process proceeds to step P9, where func and funcA are arranged adjacent to arbitrary locations in the memory space, and in step P15 “unavailable” colors of func and funcA are recognized as unusable sets. After that, the process returns to Step P4 again. The sides of func-funcA arranged adjacent to each other will be treated as one node from now on as a composite node. At this point, the relationship between the functions already arranged and the cache line and the state of the unusable set of each function are as shown in FIG.
[0023]
Subsequently, since there are still sides with a large number of calls, the process proceeds to step P5 to check whether nodes on both sides of the side of func-funcC are not arranged. In this confirmation, since the func has already been arranged, the process proceeds to step P6, and it is confirmed whether or not it is an edge connecting nodes belonging to two different composite nodes. In this confirmation, since funcC does not belong to the composite node, the process proceeds to step P7. When one node belongs to the composite node and it is confirmed whether the other node is not arranged, the condition is met, so the process proceeds to step P11.
[0024]
In step P11, an unallocated funcC is arranged at a location close to func. In step P13, it is not checked if there is no gap due to the unusable set at the time of function arrangement. After recognizing “unusable color” that cannot use funcC as an unusable set, the process returns to step P4 again.
[0025]
At this time, the relationship between the functions already arranged and the cache line and the state of the unusable set of each function are as shown in FIG.
[0026]
In step P4, since there are still unallocated sides, the process proceeds to step P5, and it is confirmed whether the nodes on both sides are unallocated with respect to the side of func-funcB. In this confirmation, since the func has already been arranged, the process proceeds to step P6, and it is confirmed whether or not the edge connects nodes belonging to two different composite nodes. In this confirmation, since funcB does not belong to the composite node, the process proceeds to step P7, and it is confirmed whether one node belongs to the composite node and the other node has not been arranged. Since this condition is met in this confirmation, the process proceeds to Step P11.
[0027]
In step P11, since the distance from the center of the func paired with the unallocated funcB to both ends of the composite node is the same, it is arbitrarily arranged on the left side, and the influence of the unavailable set at the time of function arrangement in step P13 Confirm that there is no gap. Then, since it is not vacant, the process proceeds to step P15, and “unusable color” that cannot be used for func and funcB is recognized as an unusable set, and then the process returns to step P4 again.
[0028]
If it is confirmed in step P4 that there are no unallocated sides, the process proceeds to step P16, where the unallocated nodes main and funcD are allocated in an arbitrary cache line.
[0029]
FIG. 13C shows the relationship between the final function arrangement and the cache line, and the state of the unusable set of each function, that is, the function memory arrangement result 104, but funcA and funcB have the same cache line “blue”. Shared and each unavailable set does not contain "blue". Therefore, the cache conflict between the caller function and the callee function can be reduced.
[0030]
The purpose of the first conventional technique is to prevent collisions and cache misses in the cache memory when procedures, functions, or subroutines call each other. For this purpose, information indicating the number of times a procedure, function, or subroutine is actually called and information indicating a relationship in which procedures, functions, or subroutines call each other are used. As a result, it is possible to prevent collisions in the cache memory when procedures, functions, or subroutines call each other.
[0031]
As described above, in the first conventional technique, the cache conflict between the caller function and the callee function can be reduced, but (1) when a plurality of functions are called continuously in a certain function, Alternatively, (2) when called in a loop, etc., there is a first problem that cache conflicts among these functions cannot be reduced and a great number of cache conflicts occur.
[0032]
In other words, since funcA and funcB do not have a direct call relationship, in the conventional technique in which function arrangement is performed based on function call combination information, these functions may be on the same cache line. However, as is clear from the above application program example in FIG. 3, funcA and funcB are called continuously in the loop, and funcB has a program description that calls funcA via funcD, and funcA and funcB Frequently repeats the transition, so that a very large number of cache conflicts occur in this loop processing.
[0033]
In order to solve the above first problem, the conventional function allocation optimization method to the second instruction cache described in Japanese Patent Application No. 2000-027218 (Document 3) is a combination of direct function calls according to a profile. Instead of outputting information, function execution time series information is output, and from this time series information, combination execution patterns of functions that may cause cache conflicts other than direct function calls such as consecutive function calls are detected. Then, the function arrangement optimization of the prior art is applied to the detected inter-function cache conflict combination information. As a result, it has not been possible to reduce in the past, (1) when a plurality of functions are called continuously in a certain function, or (2) when they are called in a loop, between these functions. The present invention provides means for reducing the cache conflict and improving the execution speed of the application program.
[0034]
However, this conventional second technique can be realized by simple processing when the program transition is simple, and is an extremely effective means. However, as shown in this example, (3) in the loop When the function called in (2) calls another function, there is a second problem that pattern matching cannot be performed and optimization cannot be performed.
[0035]
[Problems to be solved by the invention]
In the above-described conventional function allocation optimization apparatus, function allocation optimization method, and function allocation optimization procedure for the first instruction cache, a plurality of functions are called continuously in a certain function. If this is the case, or if it is called in a loop, it is not always possible to reduce the cache conflict between these functions, and in the worst case, a very large number of cache conflicts will occur. was there.
[0036]
In addition, a conventional function allocation optimization apparatus, function allocation optimization method, and function allocation optimization procedure for recording a second instruction cache that solves the above-described drawbacks may be used when the program transition is simple. It can be realized with simple processing and is an extremely effective means. However, when a function called in a loop calls another function, pattern matching becomes impossible and optimization is impossible. There was a drawback of becoming.
[0037]
An object of the present invention is to optimize function allocation to an instruction cache that eliminates the disadvantages of the first and second prior arts described above, reduces cache conflicts between a plurality of functions, and improves the execution speed of an application program. An object is to provide a recording medium in which an apparatus, a function allocation optimization method, and a function allocation optimization procedure are recorded.
[0038]
[Means for Solving the Problems]
The function allocation optimization apparatus for an instruction cache according to the first aspect of the present invention inputs a predetermined application program for a microprocessor system equipped with an instruction cache and probabilistically reduces the number of cache conflicts related to the instruction cache. In a function allocation optimizing device for an instruction cache that optimizes the memory allocation of a function based on function call count information,
A function call information output unit that inputs the application program and outputs each function of the call source and the call destination and the number of calls to the function call combination information as a function call combination when the function is called by the profile;
A function that inputs the application program and outputs to the function basic block transition information in which a combination of the function ID and the basic block order of the function is arranged for each function transition with respect to the function transition according to the function call by the profile A basic block transition information output unit;
Call number replacement information composed of function call number replacement data in which the number of transitions that are the number of function transitions between the function call combinations is replaced with reference to the function call combination information is generated, and then the generated call number replacement is generated. After referring to the information and temporarily placing the function at an address in the memory space, the number of cache conflicts is detected by referring to the function basic block transition information, and the number of cache conflicts in the call count replacement data The function memory allocation optimizing unit that determines the memory allocation of the function and outputs the corresponding function memory allocation result is provided.
[0039]
In addition, each of the function call combination information and the call count replacement information is a caller field describing a function name of a function caller, and
A callee field describing the function name of the callee of the function;
Each may have a call count column for setting the call count of the function.
[0040]
4. The method for optimizing function allocation to an instruction cache according to claim 3, wherein an application program for a microprocessor system equipped with an instruction cache is input, and the number of function calls is reduced so as to reduce the number of cache conflicts with respect to the instruction cache. In the function allocation optimization method to the instruction cache that optimizes the memory allocation of the function based on the information,
The application program is input, and function call combination information is generated by using each function of the call source and call destination and the number of calls as a function call combination when the function is called by the profile,
After generating the function basic block transition information regarding the execution of the basic block unit of the function obtained by the profile by inputting the application program,
The function call combination information is referred to, and the function call number replacement information including the function call number replacement data in which the number of transitions as the number of function transitions is replaced between the function call combinations is generated, and the function basic block transition information is referred to And a function memory allocation optimization step of detecting the number of cache conflicts of each function and determining the memory allocation of the function to the smallest number of cache conflicts among the call count replacement data. To do.
[0041]
Further, the function memory arrangement optimizing step refers to the function call combination information, and generates the call number replacement information with reference to the function call combination information.
A function memory temporary placement step for temporarily placing a function at an address in the memory space with reference to the generated call count replacement information;
A cache conflict frequency calculation processing step for detecting the cache conflict frequency of each function temporarily placed with reference to the function basic block transition information;
A function memory allocation step for determining a memory allocation of a function in the function call count replacement data having the smallest number of cache conflicts.
[0042]
In the function memory arrangement optimizing step, the number-of-calls replacement step reads an argument that is the number of the function-call combinations whose number of calls is to be replaced with reference to the function-call combination information and sets a first variable A first step to:
A second step of determining whether the first variable is 0;
A third step of outputting call content replacement information of the current contents when the first variable is 0 in the second step;
A fourth step of performing a recursive call by performing a call frequency replacement process when the first variable is other than 0 in the second step and setting an argument corresponding to the first variable-1;
A fifth step of setting the second variable to 0;
A sixth step of ending the process if it is not determined whether or not the second variable is smaller than the first variable-1;
A seventh step of exchanging the number of calls for each of the second variable and the first index that is the first variable-1 in the case of consent in the sixth step;
An eighth step in which the argument is decremented by 1 and the call count replacement process is performed to set an argument corresponding to the first variable-1 and a recursive call is performed;
A ninth step of exchanging the number of calls for each of the second index being the second variable and the first variable-1;
And a tenth step in which the second variable is incremented by 1 and the sixth and subsequent steps are repeated.
[0043]
A first step of initializing a variable for counting the number of cache conflicts to zero, wherein the cache conflict number calculation processing step in the function memory arrangement optimization step;
A second step of sequentially reading the function basic block transition information and obtaining ID order information which is function ID and basic block order information;
A third step of determining whether or not the function basic block transition information has been completed,
In the case where the third step is negative, a fourth step for obtaining the arrangement of the ID order information on the cache;
A fifth step of determining whether the function basic block transition information at the head is acceptable and returning to the second step in the case of acceptance;
If not in the fifth step, a sixth step returns to the second step if it is not determined whether there is an overlap in address with the previous block;
In the case of consent in the sixth step, there may be provided a seventh step of incrementing a variable for counting the number of times of the cache conflict by 1 and returning to the second step.
[0044]
The recording medium recording the function allocation optimization procedure to the instruction cache according to claim 7 inputs an application program for a microprocessor system equipped with an instruction cache and probabilistically reduces the number of cache conflicts related to the instruction cache. In the recording medium in which the function allocation optimization procedure to the instruction cache for optimizing the memory allocation of the function based on the function call count information is recorded,
A procedure of inputting the application program and generating function call combination information using each function of the call source and the call destination and the number of calls as a function call combination when the function is called by the profile;
A procedure for generating function basic block transition information relating to execution of the basic block unit of the function obtained by inputting the application program and obtained by the profile;
The function call combination information is referred to, and the function call number replacement information including the function call number replacement data in which the number of transitions as the number of function transitions is replaced between the function call combinations is generated, and the function basic block transition information is referred to And a function memory allocation optimization procedure for detecting the number of cache conflicts of each function and determining the memory allocation of the function to the one with the smallest number of cache conflicts among the call count replacement data. It is characterized by recording.
[0045]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0046]
The present invention inputs an application program for a microprocessor system equipped with an instruction cache, and optimizes the function memory allocation based on the function call count information so as to reduce the number of cache conflicts with respect to the instruction cache. In the function allocation optimization method for the instruction cache to be generated, function call combination information is generated by using each function of the call source and call destination and the number of calls as a function call combination when the function is called by the profile, and the function obtained by the profile Function basic block transition information related to the execution of each basic block is generated, and the number of calls is composed of function call number replacement data obtained by replacing the number of function transitions between function call combinations by referring to the function call combination information. Generate information and refer to function basic block transition information By detecting the number of cache conflicts in the instruction cache and placing the function at an address in the memory space so that the number of cache conflicts is the smallest among the call count replacement data, the program execution speed is improved. is there.
[0047]
Referring to FIG. 1, in which the same reference characters / numbers are attached to the same components as in FIG. The function allocation optimizing device receives an application program 110 that is common to the conventional one and outputs each function of the call source and the call destination and the number of calls to the function call combination information 111 as a function call combination when the function is called by the profile. In addition to the call information output unit 1, the application program 110 is input, and the function ID (identification) and the combination of the order of the basic block of the function are set for each function transition in response to the function transition according to the function call by the profile. Refer to the function basic block transition information output unit 2 to be output to the function basic block transition information 112 arranged in the above and the function call combination information 111. Then, the number of transitions, which is the number of function transitions, is exchanged between the function call combinations to generate the call number replacement information 113 composed of the function call number replacement data, and the function is referenced with reference to the generated call number replacement information 113. Is temporarily allocated at an address in the memory space, the number of cache conflicts is detected by referring to the function basic block transition information 112, and the number of function calls is replaced, that is, in the function call number replacement data, A function memory arrangement optimizing unit 3 that determines the memory arrangement of the function with the least number of conflicts and outputs a corresponding function memory arrangement result 4;
[0048]
In FIG. 1, solid arrows indicate the flow of processing, and dotted arrows indicate the flow of data.
[0049]
Referring to FIG. 2 showing an example of the function call combination information 111, the function call combination information 111 includes a call source field describing a function name of a function call source and a call destination field describing a function name of a function call destination. , And the number-of-calls column for setting the number of calls.
[0050]
Also, the number-of-calls replacement information 113 has exactly the same structure as the function call combination information 111, and includes a caller field describing the function name of the function call source and a call destination field describing the function name of the function call destination. , And the number-of-calls column for setting the number of calls.
[0051]
Next, the operation of the present embodiment will be described with reference to FIG. 1, FIG. 2, FIG. 3 showing an example of the application program, and FIG. 5 showing the processing flow of the function memory arrangement optimization unit in a flowchart. The function call information output unit 1 receives the application program 110, and outputs the function information of the call source and the call destination and the number of calls to the function call combination information 111 when the function is called in the profile, as in the conventional case. Here, the term “profile” means that a code that outputs a function ID and the order of the basic blocks is inserted into the application program 110 and executed when returning from the top of the basic block of the function and the calling function.
[0052]
Next, the function basic block transition information output unit 2 inputs the application program 110 and outputs a profile, that is, a code that outputs the function ID and the order of the basic blocks when returning from the top of the basic block of the function and the calling function. The information is output to the function basic block transition information 112 by being inserted into the application program 110 and executed.
[0053]
Referring to FIG. 3 again, the application program 110 shown in this figure is an example of an application program in C language. The function ID of the function main is 0, the function ID of the function func is 1, the function ID of the function funcA is 2, and the function Assume that the function ID of funcB is 3, the function ID of function funcC is 4, and the function ID of function funcD is 5.
[0054]
Further, the function func is composed of two basic blocks, which are basic processing units of the function, and each basic block of the functions main, funcA, funcB, funcC, and funcD has one structure.
[0055]
First, 0, which is the ID of main, and 0-1, which is the first combination of basic blocks (hereinafter referred to as combination 0-1, etc.) are output at the time of calling the top function main. Next, the process shifts from the function main to the function func, and the func ID 1 and the first basic block combination 1-1 are output. Next, the process moves from the function func to funcA, and the function ID 2 of funcA and the first combination 2-1 of the basic block are output. Next, the process returns from the function funcA to func, and the func ID 1 and the first combination 1-1 of the basic block are output. Thereafter, similarly, the combination of the function ID and the order of the basic blocks is output until the end of the program.
[0056]
The application program 110 of this example calls the function func from the function main, and the function func repeats the process of calling the function funcA and the function funcB 20 times (repetition), followed by the function funcA and the function funcC. This is a program that performs a process of repeating the calling process 30 times, returns to the function main, and ends. Here, the function funcB calls the function funcD, and the function funcD calls the function funcA. When the profile is executed by this processing until the end of the program, function basic block transition information 112, which is an array of information on the function ID and the order of the basic blocks, as shown in FIG. 4 is created.
[0057]
Next, the function memory arrangement optimization unit 3 refers to the function call combination information 111 and replaces the number of calls to generate call number replacement information 113 including function call number replacement data. Next, with reference to the generated number-of-calls replacement information 113, the function is temporarily placed at an address in the memory space. Thereafter, the number of cache conflicts of each function temporarily arranged with reference to the function basic block transition information 112 is detected, and the number of call conflicts is replaced, that is, the number of cache conflicts most frequently among the function call count replacement data. Decide the memory allocation of the function to the few.
[0058]
That is, the details of the operation of the function memory arrangement optimizing unit 3 will be described with reference to FIG. 5. First, the call number replacement processing step S 1 is performed with reference to the function call combination information 111. In this process, the number of combinations with a large number of calls is given as an argument. These many and small criteria are the same as the function call graph division in the function memory arrangement optimizing unit which is the prior art. In this example, in the function call combination information 111, each combination of func-funcA, func-funcB, and func-funcC is determined to have a large number of function calls, and other combinations are determined to be small. Therefore, there are three types of combinations with a large number of calls, and these are passed as arguments. Thereafter, the number of calls to be replaced becomes these three sets.
[0059]
Here, the detailed operation of the call frequency replacement processing step S1 will be described with reference to FIG. 6 showing the details of the call frequency replacement processing step S1 in a flowchart and FIG. 7 showing an example of the call frequency replacement information 113. In step S101, argument 3 is read. Next, the argument 3 is set to the variable n in step S102. Next, the condition judgment “whether n is 0” in step S103 is performed, and the variable n is not 0. Therefore, the process branches to step S105, and the number of calls is changed to the variable n−1, and the argument corresponding to n−1 is executed. Recursive call is made as 2.
[0060]
Next, the argument 2 is read again in step S101, and 2 is set to the variable n in step S102. Next, the condition determination in step S103 is performed, and the variable n is not 0. Therefore, the process branches to step S105, the number of calls is replaced with the variable n-1, and the recursive call is performed again as the argument 1.
[0061]
Next, the argument 1 is read in step S101, and 1 is set to the variable n in step S102. The condition determination in step S103 is performed, and the variable n is not 0. Therefore, the process branches to step S105, the number of calls is changed to the variable n-1, and the recursive call is further performed as the argument 0.
[0062]
Next, the argument 0 is read in step S101, and the argument 0 is set to the variable n in step S102. The condition determination in step S103 is performed, and the variable n is 0. Therefore, the process proceeds to step S104, and the call frequency replacement information 113, which is the current content, is output. Since the number of calls has not been replaced so far, the same number as the function call combination information 111 shown in FIG. 7A is output as the number-of-calls replacement information 113, and the process for the argument 0 ends.
[0063]
Next, returning to the process for argument 1, in step S106, an initial value 0 is set to the variable i, and the condition determination “i <(n−1)” in step S107 is performed. Since n-1 is 0, and the variable i is not smaller than (n-1), the process for argument 1 ends.
[0064]
Next, returning to the processing for the argument 2, in step S106, an initial value 0 is set to the variable i, and the condition determination in step S107 is performed. Since n-1 is 1, therefore, the variable i is smaller than (n-1), the process proceeds to step S108. In step S108, the elements of indexes n-1 and i, that is, the number of calls is exchanged. In this example, the number of calls of func-funcA corresponding to index 0 (i) is exchanged with the number of calls of func-funcB corresponding to index 1 (n-1). Thereafter, the recursive call is performed again with the argument set to 1 in step S109.
[0065]
Next, the argument 1 is read in step S101, and 1 is set to the variable n in step S102. The condition determination in step S103 is performed, and the variable n is not 0. Therefore, the process branches to step S105, and a recursive call is further performed with the call count replacement process step S109 as an argument 0.
[0066]
Next, in step S101, the argument 0 is read, and in step S102, the argument 0 is set to the variable n. The condition determination in step S103 is performed, and the variable n is 0. Therefore, the process proceeds to step S104, the number-of-calls replacement information 113 shown in FIG. 7B is output, and the process for argument 0 ends.
[0067]
Next, returning to the process for argument 1, in step S106, an initial value 0 is set to the variable i, and the condition determination “i <(n−1)” in step S107 is performed. Since n-1 is 0, and the variable i is not smaller than (n-1), the process for argument 1 is terminated.
[0068]
Next, returning to the processing for argument 2, in step S110, the number of calls of func-funcA 20 corresponding to index 0 and the number of calls 50 of func-funcB corresponding to index 1 are exchanged and restored. Thereafter, in step S110, the variable i is changed from 0 to 1, and the condition is determined in step S107. Since n−1 is 0, and the variable i is not smaller than (n−1), the process for argument 2 is terminated.
[0069]
Thereafter, the same processing is repeated to output FIGS. 7C, 7D, 7E, and 7F, respectively, and the call frequency replacement processing step S1 is completed.
[0070]
Next, returning to FIG. 5, in step S2, the call number replacement information 113 is referred to, and it is recognized that six pieces of information from (A) to (F) are output. We will continue processing.
[0071]
Thereafter, the same processes as those in the conventional steps P1 to P16 are performed from step S4 to step S19.
[0072]
As described in the prior art, the algorithm of steps S4 to S19 creates a function call graph and places the number of calls as a weight for that edge (combination of functions) and places it in the memory space. Therefore, it is possible to avoid a cache conflict when the function is first arranged. Record the “used color” where each function is placed (ie, the used cache line) and the set of “unavailable colors” that the function cannot currently use, and use the latter, ie, the unavailable color. The function is arranged so that there is no function, and the function that has already been arranged is moved to another place under the condition that the unusable color that cannot be used for the function is not used. This eliminates cache conflicts that occur with the direct “parent” or “child”.
[0073]
First, in step S4, a function call graph 120 shown in FIG. 12 is created from the function call combination information 111, and in step S5, the created function function call graph 120 is divided into one having a large number of calls and one having a small number of calls. Here, each combination of func-funcA, func-funcB, and func-funcC has the “number of calls” “high”, and main-func, funcA-funcD, and funcB-funcD have the “number of calls” low.
[0074]
In the function call graph 120 created here, a combination of functions is an edge, and nodes at both ends thereof are two functions in the combination.
[0075]
It is assumed that the number of cache lines occupied by each function in FIG. 3, that is, the number of “colors” is two for func and one for funcA, funcB, funkC, and main.
[0076]
Next, in step S6, the groups with the highest number of calls are sorted in descending order of the number of calls, and the processing after step S7 is performed in that order. In step S7, it is confirmed whether a side with a large number of calls remains. Since it remains, the process proceeds to step S8, and it is confirmed whether nodes on both sides with respect to the side of func-funcA are not arranged. Since it is not allocated in this confirmation, the process proceeds to step S9, where func and funcA are arranged adjacent to any location in the memory space, and “color” in which func and funcA cannot be used is recognized as an unusable set in step S18. After that, the process returns to step S7 again. The sides of func-funcA arranged adjacent to each other will be treated as one node from now on as a composite node. At this point, the relationship between the functions already arranged and the cache line and the state of the unusable set of each function are as shown in FIG.
[0077]
Subsequently, since there are still sides with a large number of calls, the process proceeds to step S8, and it is confirmed whether nodes on both sides with respect to the side of func-funcC are not arranged. In this confirmation, since the func has already been arranged, the process proceeds to step S9, and it is confirmed whether or not it is an edge connecting nodes belonging to two different composite nodes. In this confirmation, since funcC does not belong to the composite node, the process proceeds to step S10. When one node belongs to the composite node and it is confirmed whether the other node is not arranged, the condition is met, and the process proceeds to step S14.
[0078]
In step S14, unplaced funcC is placed at a location close to func. In step S16, it is not checked if there is no gap due to the unusable set at the time of function placement. After recognizing “unusable color” that cannot use funcC as an unusable set, the process returns to step S7 again.
[0079]
At this time, the relationship between the functions already arranged and the cache line and the state of the unusable set of each function are as shown in FIG.
[0080]
In step S7, since there are still unallocated sides, the process proceeds to step S8, and it is confirmed whether the nodes on both sides are unallocated with respect to the side of func-funcB. In this confirmation, since the func has already been arranged, the process proceeds to step S9 to confirm whether the edge connects nodes belonging to two different composite nodes. In this confirmation, since funcB does not belong to the composite node, the process proceeds to step S10, and it is confirmed whether one node belongs to the composite node and the other node is not arranged. In this confirmation, since the condition is met, the process proceeds to step S14.
[0081]
In step S14, since the distance from the center of the func paired with the unallocated funcB to both ends of the composite node is the same, it is arbitrarily arranged on the left side and the influence of the unusable set at the time of function arrangement in step S16 Confirm that there is no gap. Then, since it is not vacant, the process proceeds to step S18, and “unusable color” that cannot be used for func and funcB is recognized as an unusable set, and then the process returns to step S7 again.
[0082]
When it is confirmed in step S7 that there are no unallocated edges, the process proceeds to step S46, where the unallocated nodes main and funcD are allocated in an arbitrary cache line.
[0083]
As for the processing results of the above steps S4 to S19, the function memory arrangement result 4 of the present embodiment, which is the same as the conventional FIG. 13C, is used for the call frequency replacement information 113 shown in FIG. 9A shown in FIG.
[0084]
Referring to FIG. 9 showing the relationship between the function arrangement and the cache line and the state of the unusable set of each function, that is, the function memory arrangement result 4 in this embodiment, the number-of-calls replacement information 113 (A) to 113A shown in FIG. 9A to 9F correspond to each of (F).
[0085]
In the example of the present embodiment, among the six functions main, func, funcA, funcB, funcC, and funcD to be processed, it is not used for the four functions func, funcA, funcB, and funcC that are to be replaced with the number of calls. Assign a color corresponding to the possible set, that is, an unavailable color. In this example, blue and yellow are assigned to the function func, and red and green are assigned to the functions funcA, funcB and funcC as unavailable colors.
[0086]
Next, the process proceeds to step S20, and cache conflict frequency calculation processing is performed with reference to the function basic block transition information 112.
[0087]
In the following description, it is assumed that the function IDs of the functions main, func, funcA, funcB, funcC, and funcD are set to 0, 1, 2, 3, 4, and 5 as described above.
[0088]
The detailed operation of the cache conflict count calculation process will be described with reference to FIG. 8 showing the details of the cache conflict count calculation step S20 in a flowchart. First, in step S201, a variable for counting the conflict count is initialized to zero. .
[0089]
Next, in function basic block transition information reading step S202, the function basic block transition information 112 is sequentially read to obtain function ID and basic block order information (hereinafter referred to as ID order information) 0-1, that is, main-1. Next, in the condition determination “function basic block transition information is completed” in step S203, it is determined that the function basic block transition information is not yet completed, and the process proceeds to step S204. In step S204, the arrangement of the ID order information 0-1 on the cache is obtained, and the color “yellow” of the cache line corresponding to the function “main” is obtained with reference to FIG. Next, since the ID order information 0-1 is the top function basic block transition information in the condition determination “whether it is the top function basic block transition information” in step S205, the process returns to step S202.
[0090]
Next, in step S202, the function basic block transition information 112 is sequentially read to obtain ID order information 1-1, that is, func-1. Next, in step S203, it is determined that the function basic block transition information is not yet finished, and the process proceeds to step S204. As the arrangement of the ID order information 1-1 on the cache, refer to FIG. The cache line color “red” corresponding to the function func is obtained. Next, since the ID order information 1-1 is not the first function basic block transition information in the condition determination in step S205, the process proceeds to step S206. Next, in step S206, the condition determination “whether there is an overlap in the address with the previous block” has not been placed in “red” before, so the process returns to step S202.
[0091]
Next, in step S202 again, the function basic block transition information 112 is sequentially read to obtain the next ID order information 2-1, that is, funcA-1. Thereafter, in the same manner as the above processing, it is determined in step S203 that the function basic block transition information is not yet finished, and in step S204, the arrangement of the ID order information 2-1 on the cache is referred to with reference to FIG. , The cache line “blue” corresponding to the function funcA is obtained. Next, in the condition determination in step S205, since this ID order information 2-1 is not the top function basic block transition information, the process proceeds to step S206. Next, in the condition determination in step S206, there has not been anything placed in “blue” before, so the process returns to step S202.
[0092]
Next, in step S202, the function basic block transition information 112 is sequentially read to obtain the next ID order information 1-1, that is, func-1. Next, in step S203, it is determined that the function basic block transition information is not yet finished, and in step S204, as the arrangement of the ID order information 1-1 on the cache, with reference to FIG. 9A, the function func is supported. Get the cash line "red". Next, in the condition determination in step S205, since the ID order information 1-1 is not the top function basic block transition information, the process proceeds to step S206. Next, in the condition determination in step S206, the previous block arranged in “red” is 1-1 as in this case, so the process returns to step S202.
[0093]
Next, in step S202, the function basic block transition information 112 is sequentially read to obtain ID order information 3-1, that is, funcB-1. Next, in step S203, it is determined that the function basic block transition information is not yet finished, and in step S204, the arrangement of the ID order information 3-1 on the cache is referred to FIG. 9A, and the function funcB is supported. Get the cash line "blue". Next, since the ID order information 3-1 is not the first function basic block transition information in the condition determination in step S205, the process proceeds to step S206. Next, in the condition determination in step S206, the previous block arranged in “blue” is the ID order information 2-1, unlike this time, so the process proceeds to step S207. In step S207, a variable for counting the number of conflicts (hereinafter, the number of conflicts) is incremented by 1, and the process returns to step S202.
[0094]
In step S202, the function basic block transition information 112 is sequentially read to obtain ID order information 5-1, that is, funcD-1. Next, in step S203, it is determined that the function basic block transition information is not yet finished, and in step S204, the arrangement of the ID order information 5-1 on the cache is referred to FIG. 9A, and the function funcD is supported. Get the cash line “green”. Next, since the ID order information 5-1 is not the first function basic block transition information in the condition determination in step S205, the process proceeds to step S206. Next, in the condition determination in step S206, since there has not been anything previously arranged in “green”, the process returns to step S202.
[0095]
Next, in step S202, the function basic block transition information 112 is sequentially read to obtain ID order information 2-1, that is, funcA-1. Next, in step S203, it is determined that the function basic block transition information is not yet finished, and in step S204, the arrangement on the cache 2-1 is referred to with reference to FIG. 9A, and the cache line corresponding to the function funcA. Get “blue”. Next, since the ID order information 2-1 is not the top function basic block transition information in the condition determination in step S205, the process proceeds to step S206. Next, in the condition determination in step S206, the previous block arranged in “blue” is the ID order information 3-1, which is different from this time, so the process proceeds to step S207. Next, in step S207, the number of conflicts is incremented by 1, and the process returns to step S202.
[0096]
In step S202, the function basic block transition information 112 is sequentially read to obtain ID order information 5-1, that is, funcD-1. Next, in step S203, it is determined that the function basic block transition information is not yet finished, and in step S204, the arrangement of the ID order information 5-1 on the cache is referred to FIG. 9A, and the function funcD is supported. Get the cash line “green”. Next, since the ID order information 5-1 is not the first function basic block transition information in the condition determination in step S205, the process proceeds to step S206. Next, since the previous block arranged in “green” in the condition determination in step S206 is the ID order information 5-1, as in this case, the process returns to step S202.
[0097]
Next, in step S202, the function basic block transition information 112 is sequentially read to obtain ID order information 3-1, that is, funcB-1. Next, in step S203, it is determined that the function basic block transition information is not yet finished, and in step S204, the arrangement of the ID order information 3-1 on the cache is referred to FIG. 9A, and the function funcB is supported. Get the cash line "blue". Next, since the ID order information 3-1 is not the first function basic block transition information in the condition determination in step S205, the process proceeds to step S206. Next, in the condition determination in step S206, since the previous block arranged in “blue” is the ID order information 2-1, unlike this time, the process proceeds to step S207. Next, in step S207, the number of conflicts is incremented by 1, and the process returns to step S202.
[0098]
Thereafter, when the same processing is repeated until the end of the function basic block transition information 112, the number of conflicts in the cache line “blue” (hereinafter abbreviated as “blue” etc.) is 79, and the number of conflicts in “yellow”. Is 2 times, the number of conflicts in “green” is 1 time, the number of conflicts in “red” is 0 times, and a total of 82 times of conflicts are calculated.
[0099]
Thus, the cache conflict frequency calculation processing step S20 is completed.
[0100]
Next, returning to step S2, the same processing is performed thereafter, and the relationship between the function arrangement and the cache line for each of the number-of-calls replacement information 113 (FIGS. 7A to 7F) shown in FIG. The states of the impossible set (hereinafter referred to as cache memory arrangement) are as shown in FIGS.
[0101]
For example, in the case of the cache memory arrangement of FIG. 9B, it is calculated that the same 82 times of conflicts as in the case of (A) occur.
[0102]
9C and 9F, the number of conflicts in “blue” is 1, the number of conflicts in “yellow” is 2, the number of conflicts in “green” is 1, The number of conflicts in “red” is zero, and it is calculated that a total of four conflicts will occur.
[0103]
9D and 9E, the number of conflicts in “blue” is 79 times, the number of conflicts in “yellow” is 2, the number of conflicts in “green” is 1, The number of conflicts in “red” is 0, and it is calculated that a total of 82 conflicts occur.
[0104]
Therefore, it can be seen that the number of occurrences of cache conflict is the smallest in the case of the cache memory arrangement of FIGS.
[0105]
In step S3, the cache memory layout of the function is finally determined to be the layout of FIG. 9C, which is one of them.
[0106]
In the first conventional technique, funcA and funcB share the same cache line “blue”, and each unavailable set does not include “blue”, so these funcA and funcB are directly Since there is no calling relationship, when function arrangement based on function call combination information is performed, these functions may be on the same cache line, and depending on the application program, a cache conflict between these two functions may not necessarily occur. It was not possible to reduce. On the other hand, in the present embodiment, as shown in FIG. 9C, funcA is arranged in “yellow” and funcB is arranged in “blue”. Therefore, even if funcA and funcB repeat transitions, a cache conflict occurs. The execution speed of the application program can be improved without happening.
[0107]
【The invention's effect】
As described above, the function allocation optimization apparatus, the function allocation optimization method, and the function allocation optimization procedure recorded on the instruction cache according to the present invention include a function call information output unit and a function corresponding to the function call. Refer to the function basic block transition information output unit that outputs the combination of the function ID and the order of the basic block order of the function to the function basic block transition information arranged for each function transition, and the function call combination information. Call number replacement information consisting of function call number replacement data with the number of transitions exchanged between the two function call combinations is generated, and the function is temporarily placed at an address in the memory space with reference to the generated call number replacement information. After that, the number of cache conflicts is detected by referring to the function basic block transition information, and the smallest number of cache conflicts among the call number replacement data. Since a function memory placement optimization unit that outputs to determine the memory configuration of the function corresponding function memory arrangement result to those, the following effects.
[0108]
First, the first effect is that (1) even when a plurality of functions are called continuously in a certain function, or (3) when they are called in a loop, etc. By allocating functions in the memory space so as to reduce conflicts, the execution speed of application programs can be improved.
[0109]
The reason is that the number of calls in the function call information is changed and the weight of each information is changed, focusing on the ones with a large number of calls such as when the functions are called continuously or in a loop. Then, the function allocation process similar to the conventional one is performed, and the temporary allocation is performed, and the one with the smallest number of cache conflicts among the changes is determined as the final memory allocation of the function. This is because the processing does not depend on the complexity of the application program such as when a plurality of functions are called continuously or when called in a loop.
[0110]
In addition, the second effect is that (3) even when a function called in a loop calls another function, the function is arranged in the memory space so as to reduce the cache conflict. The program execution speed can be improved.
[0111]
The reason is that the number of calls in the function call information is changed, the weighting of each information is changed, and then the conventional function placement processing is performed for temporary placement. This is because the process is independent of the complexity of the application program, such as when a function called in a loop calls another function to determine the final memory allocation of the function.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a function allocation optimizing device for an instruction cache and a processing procedure thereof according to the present invention.
FIG. 2 is a diagram illustrating an example of function call combination information according to the present embodiment.
FIG. 3 is a diagram illustrating an example of an application program.
FIG. 4 is a diagram illustrating an example of function basic block transition information according to the present embodiment.
FIG. 5 is a flowchart showing an example of a function allocation optimizing method that is an operation of the function allocation optimizing apparatus for instruction cache according to the present embodiment;
6 is a flowchart showing detailed processing of a call number replacement processing step in FIG. 5;
FIG. 7 is a diagram illustrating an example of call frequency replacement information according to the present embodiment;
8 is a flowchart showing detailed processing of a cache conflict frequency calculation processing step in FIG. 5;
FIG. 9 is a diagram illustrating a result of function memory arrangement according to the present embodiment.
FIG. 10 is a block diagram illustrating an example of a conventional function allocation optimization apparatus for an instruction cache and a processing procedure thereof.
FIG. 11 is a flowchart showing an example of a function allocation optimizing method that is an operation of a function allocation optimizing apparatus for a conventional instruction cache.
FIG. 12 is a diagram for explaining the configuration of a conventional function call graph.
FIG. 13 is a diagram illustrating an example of a relationship between a conventional function arrangement and a cache line, an unusable set state of each function, and a function memory arrangement result;
[Explanation of symbols]
1 Function call information output section
2 Function basic block transition information output part
3,103 Function memory allocation optimization unit
4,104 Function memory allocation result
110 Application program
111 Function call combination information
112 Function basic block transition information
113 Number of calls replacement information
120 Function call graph

Claims (7)

An instruction that inputs a predetermined application program for a microprocessor system equipped with an instruction cache and optimizes the memory arrangement of the function based on the function call count information so as to reduce the number of cache conflicts with respect to the instruction cache. In the function allocation optimization device to the cache,
A function call information output unit that inputs the application program and outputs each function of the call source and the call destination and the number of calls to the function call combination information as a function call combination when the function is called by the profile;
A function that inputs the application program and outputs to the function basic block transition information in which a combination of the function ID and the basic block order of the function is arranged for each function transition with respect to the function transition according to the function call by the profile A basic block transition information output unit;
The function call combination information is referred to, and the function call number replacement data including the function call number replacement data in which the number of calls is replaced between the function call combinations is generated, and the function is then referred to by referring to the generated call number replacement information. After tentatively arranging at an address in the memory space, the number of cache conflicts is detected by referring to the function basic block transition information, and the function number is changed to the one with the smallest number of cache conflicts among the call count replacement data. A function allocation optimization unit for an instruction cache, comprising: a function memory allocation optimization unit that determines a memory allocation and outputs a corresponding function memory allocation result. Each of the function call combination information and the call frequency replacement information is a caller field describing a function name of a function caller, and
A callee field describing the function name of the callee of the function;
2. The function allocation optimizing device for an instruction cache according to claim 1, further comprising a call count column for setting the number of call of the function. To an instruction cache that optimizes the memory allocation of a function based on function call count information so that an application program for a microprocessor system equipped with an instruction cache is input and the number of cache conflicts is stochastically reduced with respect to the instruction cache In the function allocation optimization method of
When the application program is input, function call combination information is generated by using the call source and call destination functions and the number of calls as a function call combination when the function is called by the profile, and the application program is input and obtained by the profile. After generating function basic block transition information regarding execution of the basic block unit of the function,
Call number replacement information consisting of function call number replacement data in which the call number is replaced between the function call combinations with reference to the function call combination information is generated, and a cache conflict of each function with reference to the function basic block transition information A function memory allocation optimization step for determining a memory allocation of a function to the one with the smallest number of cache conflicts among the number of call replacement data. Optimization method. The function memory arrangement optimizing step refers to the function call combination information, and generates the call number replacement information with reference to the function call combination information.
A function memory temporary placement step for temporarily placing a function at an address in the memory space with reference to the generated call count replacement information;
A cache conflict frequency calculation processing step for detecting the cache conflict frequency of each function temporarily placed with reference to the function basic block transition information;
4. The function allocation optimization to an instruction cache according to claim 3, further comprising a function memory allocation step for determining a memory allocation of a function in the function call count replacement data having the smallest number of cache conflicts. Method. A first step of setting a first variable by reading an argument which is the number of the function call combinations to be replaced with a call count by referring to the function call combination information;
A second step of determining whether the first variable is 0;
A third step of outputting call content replacement information of the current contents when the first variable is 0 in the second step;
A fourth step of performing a recursive call by performing a call frequency replacement process when the first variable is other than 0 in the second step and setting an argument corresponding to the first variable-1;
A fifth step of setting the second variable to 0;
A sixth step of ending the process if it is not determined whether or not the second variable is smaller than the first variable-1;
A seventh step of exchanging the number of calls for each of the second variable and the first index that is the first variable-1 in the case of consent in the sixth step;
An eighth step in which the argument is decremented by 1 and the call count replacement process is performed to set an argument corresponding to the first variable-1 and a recursive call is performed;
A ninth step of exchanging the number of calls for each of the second index being the second variable and the first variable-1;
5. The method according to claim 4, further comprising a tenth step of incrementing the second variable by 1 and repeating the sixth and subsequent steps. A first step of initializing a variable for counting the number of cache conflicts to 0, wherein the cache conflict number calculation processing step;
A second step of sequentially reading the function basic block transition information and obtaining ID order information which is function ID and basic block order information;
A third step of determining whether or not the function basic block transition information has been completed,
In the case where the third step is negative, a fourth step for obtaining the arrangement of the ID order information on the cache;
A fifth step of determining whether the function basic block transition information at the head is acceptable and returning to the second step in the case of acceptance;
If not in the fifth step, a sixth step returns to the second step if it is not determined whether there is an overlap in address with the previous block;
5. The instruction cache according to claim 4, further comprising a seventh step of incrementing a variable for counting the number of times of the cache conflict by 1 when the approval is obtained in the sixth step and returning to the second step. Function allocation optimization method. To an instruction cache that optimizes the memory allocation of a function based on function call count information so that an application program for a microprocessor system equipped with an instruction cache is input and the number of cache conflicts is stochastically reduced with respect to the instruction cache A computer-readable recording medium storing a program for causing a computer to execute the function allocation optimization process of
Inputting the application program and generating function call combination information using each function of the call source and call destination and the number of calls as a function call combination when the function is called by the profile;
Generating function basic block transition information related to execution of the basic block unit of the function obtained by inputting the application program and obtained by the profile;
Call number replacement information consisting of function call number replacement data in which the call number is replaced between the function call combinations with reference to the function call combination information is generated, and a cache conflict of each function with reference to the function basic block transition information Function allocation optimization step to the instruction cache, wherein the function memory allocation optimization step for determining the memory allocation of the function to the one with the smallest number of cache conflicts among the number of call replacement data is executed. A computer-readable recording medium in which a program for causing a computer to execute is recorded .

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