JP3698157B2 - Display device - Google Patents

Description

  The present invention relates to a display that displays image data such as a digital signal, or a video signal and a synchronization signal as input signals, and displays an image based on those input signals. The present invention relates to a display that can be used for various adjustments such as a keyboard and the like (without going through a computer main body) and has improved usability.

  Currently, in display devices such as computer terminals, the display position and display size of the screen and the deflection frequency of the video signal to be displayed are diverse. For this reason, as a display device such as a computer terminal, a display device capable of handling various video signals (video signals) has been used.

  As this type of display device, there is a device that attempts to provide an optimal screen display for each type of video signal using a microcomputer, a memory LSI, or the like. The thing etc. which are described in 1-321475 gazette can be mentioned.

  In this conventional example, the memory that stores the display position and display size information for each type of video signal is controlled by a microcomputer or the like, and the optimal display position and display for the input video signal are controlled. The size information is read from the memory, and the deflection circuit of the display device is controlled based on the read information. If the video signal input to the display device is not known, the corresponding information is not stored in the memory. Therefore, the adjustment switch arranged on the front surface of the display device or the like is operated to display the screen. Input the adjustment information such as display position and display size. Based on this input information, a control circuit such as the microcomputer creates control information such as deflection, and adjustment is performed.

  In the above conventional example, the display device side tries to obtain an optimal screen display according to the input video signal. However, as another conventional example, the display state is switched by controlling from the computer body side. Such conventional examples include those described in Japanese Examined Patent Publication No. 2-60193.

  In this conventional example, the computer body superimposes and outputs a discrimination pulse during the blanking interval of the video signal, and the display device switches the deflection frequency based on the discrimination pulse.

  Of the two conventional examples described above, in the former conventional example, the control of the display position and display size of the screen is all managed on the display device side. It is necessary to release the hand from the input device such as the connected keyboard and reach the adjustment switch of the display device for operation, which is troublesome in terms of usability.

  Further, in the latter conventional example, it can be operated from an input device such as a keyboard connected to the computer main body. However, since the deflection frequency can be switched only in binary, it is necessary for the computer user. There was a problem that the display state could not be obtained sufficiently.

Accordingly, the present invention has been made in view of the above-described problems of the prior art, and an object thereof is to improve usability when a computer and a display device are connected and used.

In order to achieve the above object, a display device according to the present invention can be connected to a computer, and in a display device capable of displaying video based on image information from the computer, an interface capable of bidirectional communication with the computer. An interface circuit connected via a cable; and a memory circuit for storing information relating to display of the display device. The interface circuit receives digital image data and the memory circuit from the computer as the image information. And receiving a control signal for accessing the computer via the interface cable, transmitting a reception confirmation signal indicating that the control signal has been received, and receiving image information from the computer. With a single interface cable It is characterized in that it has a capability.

The memory circuit may be an EEPROM, and the interface circuit may also receive a second control signal for controlling the display screen of the display device from the computer.

According to the present invention, since the information on the display screen is read from the memory circuit by the control signal from the computer, a suitable display state can be obtained based on this information. Further, since communication with the computer and reception of image information from the computer can be executed with a single interface cable, the connection between the computer and the display device can be simplified. Therefore, according to the present invention, usability can be improved .

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a first embodiment of the present invention. In the figure, 1a shows a computer main body, in which 11 is a CPU, 12 is a keyboard controller for processing various commands input from a keyboard (not shown) connected to the computer main body 1a, and 13 is a memory. Circuit, 14 is an input / output port for connection with peripheral devices, 15 is a display control circuit for generating a video signal and a synchronization signal for driving the display device, and 16 is a video signal output from the display control circuit 15 Alternatively, a control signal superimposing circuit for superimposing the control signal on the synchronization signal, and 17 is a floppy disk drive circuit. Reference numeral 1b denotes a display device, in which 18 is a control signal extraction circuit that extracts the control signal from the video signal or synchronization signal output from the control signal superimposing circuit 16, and 19 is a control signal extraction circuit 18. A display control circuit that generates an adjustment signal for a predetermined circuit based on the extracted control signal, 20 is a video circuit, 21 is a deflection circuit, and 22 is a cathode ray tube for displaying an image.

  The operation of FIG. 1 is as follows. In the computer main body 1a, the portions other than the control signal superimposing circuit 16 are the same as those of a general configuration such as a conventional personal computer or workstation.

  First, when a computer user inputs a control command for adjusting the display screen of the display device 1b from a keyboard connected to the computer main body 1a, the keyboard controller 12 digitally encodes the control command, and then the CPU 11 Recognizes the control command and controls the control signal superimposing circuit 16.

  The control signal superimposing circuit 16 creates a control signal corresponding to the control command and superimposes it on the vertical blanking period of the video signal or synchronization signal generated by the display control circuit 15 for driving the display device 1b. .

  Next, the control signal extraction circuit 18 of the display device 1b extracts the superimposed control signal from the video signal or the synchronization signal output from the control signal superimposing circuit 16, and outputs it to the display control circuit 19 as well as the video. The signal is output to the video circuit 20 and the synchronization signal is output to the deflection circuit 21.

  The display control circuit 19 adjusts the video circuit 20 and the deflection circuit 21 by generating an adjustment signal for the video circuit 20 and the deflection circuit 21 based on the input control signal.

  In this way, the display screen is adjusted, and the image displayed on the cathode ray tube 22 is desired by the computer user.

  FIG. 2 is a block diagram showing a specific example of the control signal superimposing circuit 16 in FIG. 1, and FIG. 3 is a waveform diagram showing waveforms of main signals in FIG.

  In FIG. 2, 161 is an address decoder, 162 is a data latch circuit, 163 is a pulse edge detection circuit, 164 is a shift register circuit, 165 and 170 are AND circuits, 166 is a level conversion circuit that converts the signal level, and 167 is analog. A switch 168 is a counter circuit that counts 17 clock pulses, and 169 is a set-reset type flip-flop circuit (hereinafter referred to as an RSFF circuit).

  The operation of the figure is as follows.

  As described above, when a computer user inputs a control command for adjusting the display screen of the display device 1b from a keyboard connected to the computer main body 1a, the keyboard controller 12 digitally encodes the control command, Thereafter, the CPU 11 recognizes the control command and sends control data to the control signal superimposing circuit 16 via the computer bus.

  When the transmitted control data is control data for adjusting the display screen of the display device 1b, the address decoder 161 causes the data latch circuit 162 to take in the control data. Next, the edge detection circuit 163 detects the leading portion of the vertical synchronization signal Vs using the horizontal synchronization signal Hs, and outputs this edge detection pulse to the shift register circuit 164, the counter circuit 168, and the RSFF circuit 169.

  In the counter circuit 168, the edge detection pulse is used as a reset signal, the horizontal synchronization signal Hs is used as a clock signal, the counting operation is performed at the rising edge, and when 17 clocks are counted after the reset signal is input, the carry output is input to the reset input terminal of the RSFF circuit 169. send. Therefore, the V gate pulse shown in FIG. 3 is output from the RSFF circuit 169. A control signal for the display device 1b is superimposed during the high level period of the V gate pulse.

  On the other hand, the shift register circuit 164 reads the control data held in the data latch circuit 162 by the edge detection pulse from the edge detection circuit 163. Next, the shift register circuit 164 performs a shift operation using the horizontal synchronizing signal Hs output by the AND circuit 170 only during the high level period of the V gate pulse as a clock signal, and outputs the control data shown in FIG.

  Further, this control data is multiplied by the AND circuit 165 with the horizontal synchronizing signal Hs, and then converted into a video signal level by the level conversion circuit 166 and input to the switch circuit 167. Among the video signals, the B (blue) video signal is input to the other input of the switch circuit 167, and the V gate pulse is used as a switch switching control signal. In other periods of low level, the B video signal is selected, and the B video signal on which the control signal is superimposed as shown in FIG. 3 can be obtained. Here, the control signal is superimposed on the B video signal with low color visual sensitivity, but it may be superimposed on other R (red) and G (green) video signals and synchronization signals.

  Next, FIG. 4 is a block diagram showing a specific example of the control signal extraction circuit 18 and the display control circuit 19 in FIG. 1, and FIG. 5 is a waveform diagram showing the waveforms of the main signals in FIG.

  4, 401 is a distributor, 402 is a low pass filter (hereinafter referred to as LPF), 403 is a level conversion circuit, 404 and 405 are buffers, 406 is a 17 count circuit, 407 is an RSFF circuit, 408 and 409 are AND circuits, Reference numeral 410 denotes an inverter, 411 denotes a 16-stage shift register circuit, 412 denotes a decoder circuit, 413 denotes a D / A conversion circuit (hereinafter referred to as DAC), and 414 denotes an edge detection circuit.

  The operation of FIG. 4 will be described below with reference to FIG.

  The B video signal from the control signal superimposing circuit 16 is input to the distributor 401 and divided into two. One is output to the video circuit 20 shown in FIG. 1 together with the other video signal, and the other is output to the LPF 402. Is done. An unnecessary frequency component such as noise in the B video signal is removed from the B video signal input to the LPF 402 by the LPF 402, and then converted to a digital signal level by the level conversion circuit 403 in the next stage.

  The vertical synchronization signal Vs is input to the edge detection circuit 414 through the buffer 404, where the leading edge is detected, and the 17 count circuit 406, the RSFF circuit 407, 16 stages are detected as the edge detection pulse 418 shown in FIG. Each is output to the shift register circuit 411.

  First, in the 17 count circuit 406, when reset by the edge detection pulse 418, the horizontal synchronization signal Hs input through the buffer 405 is used as a counting clock, and the count operation is performed. Output a pulse. Next, the RSFF circuit 407 receives the edge detection pulse 418 as a set signal and the 17 detection pulse as a reset signal, and creates a V gate pulse 419 shown in FIG.

  The AND circuit 408 takes the product of the output of the level conversion circuit 403 and the V gate pulse from the RSFF circuit 407, and extracts and outputs the control signal 420 superimposed on the B video signal. The other AND circuit 409 takes the product of the V gate pulse and the horizontal synchronizing signal Hs from the buffer 405 logically inverted by the inverter 410 to generate a clock signal for the 16-stage shift register circuit 411 and the DAC 413.

  The 16-stage shift register circuit 411 resets the held contents by the edge detection pulse 418 and sequentially holds the control signal 420 by the clock signal from the AND circuit 409. When the decoder circuit 412 decodes the hold values of the first stage, the second stage, the 15th stage, and the 16th stage of the 16-stage shift register circuit 411 and detects the start bit and the stop bit in the control signal 420, the decoder circuit 412 uses the DAC 413 shown in FIG. The load pulse 422 is output. The output of the second stage of the 16-stage shift register circuit 411 is used as the serial data 421 of the DAC 413 shown in FIG.

  The DAC 413 is a multi-channel built-in type D / A converter with serial data input, and selects one of a plurality of built-in D / A converters according to the DAC control address in the serial data 421 shown in FIG. Then, the D / A conversion output value is updated with the value of the control data portion. At this time, serial data 421 is sequentially fetched in synchronization with the clock signal from the AND circuit 409, and the fetched data is determined at the rising edge of the load pulse 422 from the decoder circuit 412.

  Thus, the video circuit 20 and the deflection circuit 21 shown in FIG. 1 can be adjusted by the adjustment voltage or the adjustment current output as the adjustment signal from the DAC 413.

  FIG. 6 is a block diagram showing another specific example of the control signal extraction circuit 18 and the display control circuit 19 shown in FIG. In the figure, 601 is a selector, 602 is a one-chip microcomputer (hereinafter referred to as a microcomputer), 603 is a writable read-only memory (hereinafter referred to as an EEPROM), and the same reference numerals as those in FIG. 4 have the same functions. .

  The operation of the figure is as follows.

  The control circuit superimposed on the B video signal is extracted by the AND circuit 408 and the writing clock signal for the 16-stage shift register circuit 411 is generated by the AND circuit 409. Is the action. In this specific example, a control signal for the display device 1b sent from the computer main body 1a shown in FIG.

  First, the microcomputer 602 normally controls the selector 601 to select the clock signal for writing from the AND circuit 409 and write the control signal to the 16-stage shift register circuit 411. At this time, the edge detection pulse from the edge detection circuit 414 is input to the microcomputer 602 as an interrupt signal, and after a predetermined time has elapsed, the selector 601 is controlled to select a clock signal for reading from the microcomputer 602. To do.

  The control signals held in the 16-stage shift register circuit 411 are sequentially read by the read clock signal from the microcomputer 602 and input to the microcomputer 602. When the captured signal is a correct control signal, the microcomputer 602 outputs control data to the DAC 413 and adjusts a predetermined circuit in the display device 1b. The control data is also written in the EEPROM 603, and the control data is read out from the EEPROM 603 at the next power-on of the display device 1b and a predetermined adjustment is performed.

  In this specific example, by storing control data in the EEPROM 603 in advance, necessary control data can be read in accordance with a control signal from the computer main body 1a. Therefore, in addition to the control command from the keyboard, the control information for the display device 1b is programmed in advance on the software for operating the computer main body, so that it is possible to cope with each software.

  As described above, in the present embodiment, the case where the method of superimposing the control signal on the vertical blanking period of the video signal or the synchronization signal is used, but the DC level itself of the video signal is used as the control signal. It can also be used. In this case, the control signal extraction circuit 18 may reproduce the DC level of the video signal and adjust a predetermined circuit of the display device 1b according to the voltage value. In the present embodiment, an example in which the video circuit 20 and the deflection circuit 21 of the display device 1b are adjusted is described. However, it is of course possible to adjust the focus and the like by controlling the high-voltage circuit portion. .

  FIG. 7 is a block diagram showing a second embodiment of the present invention. In the same figure, 1c shows a computer main body different from the computer main body shown in FIG. 1, in which 70 is a control signal generating circuit. Reference numeral 1d denotes a display device different from the display device shown in FIG. 1, and reference numeral 71 denotes a display control circuit different from the display control circuit 19 shown in FIG. In addition, the same number as FIG. 1 shows the same function.

  The operation of FIG. 7 will be briefly described below.

  In the figure, the video signal and the synchronization signal are output from a display control circuit 15 similar to a general personal computer or workstation.

  Here, when a computer user inputs a control command for adjusting the display screen of the display device 1d from a keyboard (not shown) connected to the computer main body 1c, the control command is transmitted to the keyboard controller 12, The data is sent to the control signal generation circuit 70 via the CPU 11 via the computer bus.

  The control signal creation circuit 70 holds the control command, creates a control signal corresponding to the control command, and outputs it to the display device 1d at an appropriate timing. As an output method at this time, for example, an existing interface such as RS-232C, GP-IB, Centronics, or SCSI can be used. Therefore, the control signal generation circuit 70 includes a corresponding interface circuit.

  Next, the display control circuit 71 of the display device 1b inputs the control signal output from the control signal generating circuit 70 via the interface circuit included in the display control circuit 71 and similar to the interface circuit, and controls the control signal. Based on the signal, an adjustment voltage or an adjustment current as an adjustment signal for the video circuit 20 and the deflection circuit 21 is generated to adjust the video circuit 20 and the deflection circuit 21.

  In this embodiment, since the control signal is exchanged by the general-purpose interface, bidirectional communication is possible between the display device 1d side and the computer main body 1c side. For this reason, it is also possible to monitor whether the display device 1d has correctly received the control signal, the current control state of the display device 1d, or whether the display device 1d side is operating normally. .

  FIG. 8 is a block diagram showing a third embodiment of the present invention. In the figure, 1e shows a computer main body different from the computer main body shown in FIGS. 1 and 7, in which 81 is a display processing circuit for creating image data of a display display image, and 82 is an interface circuit. is there. 1f shows a display device different from the display device shown in FIGS. 1 and 7, 83 is an interface circuit, and 84 is a display controller for creating various signals for driving the display device 1b. The interface circuits (hereinafter referred to as I / F circuits) 82 and 83 are used to exchange signals between the display processing circuit 81 in the computer main body 1e and the display controller 84 in the display device 1f. In addition, the same numbers as those in FIGS. 1 and 7 indicate the same functions.

  The operation of FIG. 8 will be briefly described below.

  An image processing command issued from the CPU 11 is sent to the display processing circuit 81 via the computer bus. The display processing circuit 81 receives the image processing command and creates image data of a display display image.

  At this time, when a computer user inputs a control command for adjusting the display screen of the display device 1f from a keyboard (not shown) connected to the computer main body 1e, the control command is transmitted to the keyboard controller 12, The data is sent to the display processing circuit 81 via the computer bus via the CPU 11. When the control command is sent, the display processing circuit 81 creates a control signal at a predetermined location outside the image data area.

  The image data and the control signal created in this way are output to the display device 1f as image information corresponding to a predetermined interface specification, for example, a SCSI standard having a high transfer rate, by the I / F circuit 82. The

  In the display device 1 f, the I / F circuit 83 receives the image information from the I / F circuit 82 and sequentially sends it to the display controller 84. The display controller 84 sequentially writes the transmitted image information into the internal memory, and creates R, G, B video signals and synchronization signals from the image data portion of the written image information. If the control signal is present in the image information, an adjustment voltage or an adjustment current as an adjustment signal for the video circuit 20 and the deflection circuit 21 is generated to adjust the video circuit 20 and the deflection circuit 21.

  Further, the display controller 84 controls the video circuit 20 to reduce the amplitude of the video signal to the minimum level when the image information written in the internal memory is not updated within a predetermined time, so that the cathode ray tube 22 is controlled. Prevents seizure of.

  Also in this embodiment, since the interface between the computer main body 1e and the display device 1f is bidirectional, not only image data and control signals are sent from the computer main body 1e side, but also a reception confirmation signal from the display device 1f side. And reports on the operating status can be sent. Further, since the connection between the computer main body 1e and the display device 1f is a single interface cable, the troublesome connection can be eliminated.

  FIG. 9 is a block diagram showing a fourth embodiment of the present invention. In the figure, 1g shows a computer main body different from the computer main body shown in FIGS. 1, 7, and 8, and 91 is a modulation circuit. 1h shows a display device different from the display devices shown in FIGS. 1, 7, and 8, in which 92 is a display control circuit, 93 is a demodulation circuit, and 94 and 95 are power plugs. In addition, the same numbers as those in FIG. 1 have the same functions. The operation of FIG. 9 is as follows.

  When a computer user inputs a control command for adjusting the display screen of the display device 1h from a keyboard (not shown) connected to the computer main body 1g, the control command is sent to the CPU 11 via the keyboard controller 12. Sent to. The CPU 11 processes the control command and sends a control signal corresponding to the control command to the modulation circuit 91 via the computer bus. The modulation circuit 91 modulates the received control signal, superimposes it on the AC power supply, and then transmits it from the power plug 94 to the display device 1h side through the power supply line.

  In the display device 1h, when AC power is supplied from the power plug 95 through the power line, the demodulation circuit 93 demodulates the modulated control signal superimposed on the AC power and reproduces the original control signal. The reproduced control signal is input to the display control circuit 92. The display control circuit 92 generates an adjustment voltage or an adjustment current as an adjustment signal for the video circuit 20 and the deflection circuit 21 in accordance with the instruction content of the control signal. The video circuit 20 and the deflection circuit 21 are adjusted.

  In this way, in this embodiment, since the control signal for the display device 1h is transmitted through the power line, the display device 1h can be controlled without increasing the number of signal lines for the control signal.

  FIG. 10 is a block diagram showing a fifth embodiment of the present invention. In the figure, reference numeral 1i denotes a computer main body showing a general personal computer or workstation, and 1i denotes a display device different from the display devices shown in FIGS. 1, 7, 8, and 9. Among them, 101 is a command identification circuit, and 102 is a display control device. Reference numeral 1k denotes a keyboard connected to the computer main body 1i and the display device 1j. In addition, the same number as FIG. 1 shows the same function.

  The operation of FIG. 10 is as follows.

  In FIG. 10, when a computer user operates the keyboard 1k, a key input signal is input to the computer main body 1i and further to the display device 1j. Among these, in the display device 1j, the key input signal is processed by the command identification circuit 101, and when the key input signal is a control command for adjusting the display screen of the display device 1j, it is extracted as a control signal. The display control circuit 102 adjusts the video circuit 20 and the deflection circuit 21 by generating an adjustment voltage or an adjustment current as an adjustment signal for the video circuit 20 and the deflection circuit 21 in accordance with the instruction content of the control signal.

  In the present embodiment, the computer main body 1i does not create a control signal for the display device 1j, so there is no burden on the CPU on the computer main body 1i side. In this way, the computer user can control from the keyboard 1k without directly touching the display device 1j.

  Here, as a signal line connected from the keyboard 1k to the display device 1j, one connected to the computer main body 1i may be distributed as it is, or as a dedicated signal line for handling only a control command for the display device 1j. It doesn't matter. In the former case, a general keyboard 1k can be used as it is. In the latter case, a dedicated key for display control is added to the keyboard 1k.

  Furthermore, in order to reduce the connection line between the keyboard 1k and the display apparatus 1j, the troublesomeness by wiring can be suppressed by using a remote control circuit using infrared rays or the like. In this embodiment, the keyboard 1k is used as the control command input means, but it is of course possible to use an input device such as a mouse, a touch panel, or a light pen.

It is a block diagram which shows the 1st Example of this invention. FIG. 2 is a block diagram illustrating a specific example of a control signal superimposing circuit 16 in FIG. 1. FIG. 3 is a waveform diagram showing a waveform of a main part signal of FIG. 2. FIG. 2 is a block diagram illustrating a specific example of a control signal extraction circuit 18 and a display control circuit 19 in FIG. 1. It is a wave form diagram which shows the waveform of the principal part signal of FIG. It is a block diagram which shows the other specific example of the control signal extraction circuit 18 of FIG. 1, and the display control circuit 19. FIG. It is a block diagram which shows the 2nd Example of this invention. It is a block diagram which shows the 3rd Example of this invention. It is a block diagram which shows the 4th Example of this invention. It is a block diagram which shows the 5th Example of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a, 1c, 1e, 1g, 1i ... Computer main body, 1b, 1d, 1f, 1h, 1j ... Display apparatus, 16 ... Control signal superimposition circuit, 18 ... Control signal extraction circuit, 19, 71, 92, 102 ... Display control Reference numeral 70 is a control signal generation circuit, 81 is a display processing circuit, 84 is a display controller, 91 is a modulation circuit, 92 is a demodulation circuit, 1k is a keyboard, and 101 is a command identification circuit.

Claims (3)

In a display device connectable with a computer and capable of displaying video based on image information from the computer,
An interface circuit connected via an interface cable capable of two-way communication with the computer, and a memory circuit storing information related to display on the display device, the interface circuit from the computer as the image information Digital image data and a control signal for accessing the memory circuit are received via the interface cable, and a reception confirmation signal indicating that the control signal has been received is transmitted.
A display device characterized in that communication with the computer and reception of image information from the computer can be executed with a single interface cable. The display device according to claim 1, wherein the memory circuit is an EEPROM. The display device according to claim 1, wherein the interface circuit can also receive a second control signal for controlling a display screen of the display device from the computer.

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