JP3695405B2 - Sound generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sound source device that allows control means to access a waveform memory.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a waveform memory sound source is known in which a musical tone is generated based on waveform data read from a waveform memory in accordance with a pitch to be generated. FIG. 9 shows an example of the configuration of a sound source unit in a conventional musical tone generating apparatus incorporating such a waveform memory sound source.
In FIG. 9, the waveform memory 121 is constituted by a readable / writable SDRAM (Synchronous DRAM), and stores a plurality of short-term sampling waveforms. The tone generator 120 generates musical sounds based on the waveform data read from the waveform memory 121. When generating a musical sound, a CPU (Central Processing Unit) (not shown) in the musical sound generating apparatus supplies various sound source parameter information to the sound source control register 130 and issues a sound generation start instruction. The sound source parameter information is supplied from the CPU to the sound source control register 130 via the data bus (DATA102), and is stored in the register indicated by the address given from the CPU via the address bus (AD102) in the sound source control register 130.
[0003]
The sound source parameter information includes an assigned channel, a waveform memory read pitch (frequency number), a waveform memory read section, an envelope parameter, setting information for the mixer 133, and an effect coefficient. Of these, the waveform memory read section parameter is the start address AS of the waveform data to be read and its data length LPA. The tone generator control register 130 and the read / write circuit 131 generate musical tones for each channel by performing five processes of process A, process B, capture process, interpolation process, and X access process. The outline of each process is as follows. The process A reads out the waveform data of each channel according to the time division channel timing for generating a musical tone based on the waveform data start address AS supplied from the sound source control register 130 and information such as the data length LPA and pitch PITCH. This is a process for creating an address. The waveform data read address of each channel is a relative address and is held in a register (not shown) in the read / write circuit 131. The process B is a process executed in the read / write circuit 131, and is converted into a waveform data read address of an absolute address corresponding to the waveform memory 121 at a channel timing different from the time division channel timing. This is a process of supplying the read address to the waveform memory 121 via the address bus (AD101).
[0004]
The capturing process is a process executed by the read / write circuit 131. The waveform data read in accordance with the waveform data read address supplied to the waveform memory 121 by the process B is sent via the data bus (DATA101). This is the process of capturing and writing to the built-in waveform buffer for each channel. The interpolation process is a process executed by an interpolation circuit (not shown) in the read / write circuit 131. According to the time division channel timing, the waveform sample of each channel is read from the waveform buffer, and the waveform data of each channel is obtained by interpolation. This is a process of generating and outputting in time division. The interpolated waveform data is supplied from the read / write circuit 131 to the EG applying circuit 132.
[0005]
The X access process is a process executed under the control of the X access circuit 140 built in the sound source control register 130, and when the time slot for performing the process in the process B or the capture process described above becomes available, In the time slot, the CPU reads / writes waveform data from the waveform memory 121 and writes the mixed waveform data output from the mixer 133 to the waveform memory 121. In the X access processing in which the CPU reads waveform data from the waveform memory 121, the CPU outputs an address designating the XA register 142 built in the X access circuit 140 to the address bus (AD 102) and sends it to the XA register 142. Write the output waveform data read address to the data bus (DATA102). The read / write circuit 131 supplies the waveform data read address written in the XA register 142 to the waveform memory 121 via the address bus (AD101) using the time slot which is free in the process B or the capture process. At this time, the read / write circuit 131 also supplies a read enable signal to the waveform memory 121.
[0006]
As a result, the waveform data is read onto the data bus (DATA 101) according to the address supplied from the waveform memory 121. This waveform data is written to a FIFO (First In First Out) 141 built in the X access circuit 140 via the read / write circuit 131. The FIFO 141 is a first-in first-out buffer memory. When a predetermined amount of the read waveform data is written in the FIFO 141, the CPU outputs an address designating the FIFO 141 to the address bus (AD102) at the operation timing of the CPU, and the waveform data is output from the FIFO 141 to the data bus (DATA102). ) To read through.
[0007]
Further, the CPU supplies the start address and data length information of the waveform data to be read to the X access circuit 140, and the X access circuit 140 sequentially assigns addresses from the start address to the data length every time data is read from the waveform memory 121. Incremental waveform data read addresses are generated. This waveform data read address is written in the built-in XA register 142 and finally supplied to the waveform memory 121. As a result, waveform data of a predetermined number of samples written at consecutive address positions can be sequentially read out and stored in the FIFO 141 sequentially. The waveform data stored in the FIFO 141 is sequentially read out from the FIFO 141 by the CPU at a different operation timing of the CPU from the timing of writing.
[0008]
In the X access process for writing the waveform data output from the mixer 133 to the waveform memory 121, the waveform data output from the mixer 133 is written into the FIFO 141. The CPU writes the waveform data write address (first address) in the XA register 142 built in the X access circuit 140. The read / write circuit 131 supplies the waveform data write address written in the XA register 142 to the waveform memory 121 via the address bus (AD101) using the time slot which is vacant in the process B and the capture process. At the same time, the waveform data read from the FIFO 141 is output to the data bus (DATA 101) via the read / write circuit 131 and supplied to the waveform memory 121. Further, a write enable signal is supplied from the read / write circuit 131 to the waveform memory 121. As a result, the waveform data is written to the waveform memory 121.
[0009]
The CPU supplies the X access circuit 140 with information on the start address of the write address and the data length of the waveform data. The X access circuit 140 sequentially assigns addresses from the start address to the data length each time waveform data is written. Incrementing generates successive waveform data write addresses. This waveform data write address is written in the built-in XA register 142 and finally supplied to the waveform memory 121. As a result, the waveform data of a predetermined number of samples written from the mixer 133 to the FIFO 141 can be written to consecutive address positions in the waveform memory 121. In this case, waveform data is sequentially written into the FIFO 141 by one sample from the mixer 133 for each sampling period regardless of the empty state. Since the write speed from the FIFO 141 to the waveform memory 121 is at least one sample per sampling period, the FIFO does not become full. On the other hand, during the X access process of writing waveform data from the CPU to the waveform memory 121, the CPU checks the empty state of the FIFO 141, and writes the waveform data to the FIFO 141 only when there is an empty space.
[0010]
The waveform data of each channel output in a time-sharing manner from the read / write circuit 131 is provided with an envelope by the EG applying circuit 132. The given envelope is determined based on the envelope parameter of each channel given from the CPU and stored in the sound source control register 130.
For example, the waveform data for 32 channels to which the envelope has been added is supplied to the mixer 133. Further, the mixer 133 is subjected to effect processing output from the signal processing circuit (DSP) 134, for example, waveform data for 8 channels, and the external circuit 122 is subjected to filter processing, effect processing, etc., for example, 8 channels. Minute waveform data is supplied. The mixer 133 multiplies the supplied waveform data of each channel by a coefficient value for mixing.
[0011]
The coefficient value is given as a sound source parameter from the CPU to the sound source control register 130 and stored in a built-in register. As for the waveform data mixed in the mixer 133, the final output of the tone generator 120 is output to the DSP 134 for eight channels, to the external circuit 122 for eight channels, and to the X access circuit 140 in the tone generator control register 130 for one channel. The two channels (L and R outputs) are output to the DAC 123. As described above, the mixer 133 multiplies the waveform data of the channel designated by the CPU by the designated coefficient value and mixes the result, and sends the mixing result to the output unit based on the designation of the CPU through the designated channel. ing.
[0012]
[Problems to be solved by the invention]
By the way, in order to handle waveform data from the CPU side in the sound source unit 120, it is conceivable that the sound source unit 120 has a codec function. In this case, the sound source unit operates on the basis of the DAC cycle in the DAC, but the CPU operates at an operation timing not directly related to the DAC cycle, so an additional buffer is added to provide a codec function. There was a problem of having to.
[0013]
Accordingly, an object of the present invention is to provide a sound source device that can provide a codec function by adding a small number of circuits by utilizing a circuit originally prepared for accessing a waveform memory by a CPU.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a first sound generator according to the present invention includes a waveform memory in which waveform data can be read and written, waveform data read from the waveform memory, and based on the read waveform data. Cycle is Sampling period It is said Musical tone generating means for generating musical tone waveform data, and waveform data including the musical tone waveform data generated by the musical tone generating means are input, and mixing processing is performed. Cycle is Sampling period It is said Mixing means for outputting mixed waveform data, control means for controlling the operation of the musical tone generation means and the mixing means, and control of the control means during a time when the musical tone generation means is not accessing the waveform memory Based on the above, access to continuously read or write the waveform data in the waveform memory, and to access the waveform data input from the mixing means for each sampling period to the control means, and to the access means Built-in storage means, and the access means performs the first area of the storage means under the control of the control means. Said When reading waveform memory A buffer for temporarily storing the waveform data read to the control means, and Waveform data at the time of writing To pass to the waveform memory In addition to being used as a buffer for temporarily storing, the second area of the storage means can be used as a buffer for temporarily storing the waveform data input from the mixing means for delivery to the control means. .
[0015]
Next, a second sound source device according to the present invention capable of achieving the above object includes a waveform memory capable of reading and writing waveform data,
Read waveform data from the waveform memory, based on the read waveform data Cycle is Sampling period It is said Musical tone generating means for generating musical tone waveform data, and waveform data including the musical tone waveform data generated by the musical tone generating means are input, and mixing processing is performed. Cycle is Sampling period It is said Mixing means for outputting mixed waveform data, control means for controlling the operation of the musical tone generation means and the mixing means, and control of the control means during a time when the musical tone generation means is not accessing the waveform memory The access means for continuously reading or writing the waveform data in the waveform memory, and outputting the waveform data sequentially input from the control means to the mixing means at every sampling period, and the access Storage means incorporated in the means, and the access means is configured to perform the first area of the storage means under the control of the control means. Said When reading waveform memory A buffer for temporarily storing the waveform data read to the control means, and Waveform data at the time of writing To pass to the waveform memory While being used as a buffer for temporarily storing, the second area of the storage means can be used as a buffer for temporarily storing waveform data input from the control means to the mixing means.
[0016]
Further, in the first and second sound source devices of the present invention, the size of the first area and the size of the second area in the storage means can be changed according to a user instruction or an operating situation, respectively. It may be.
Further, in the first and second sound source devices of the present invention, the state of waveform data in the buffer which is the first area and the second area is further detected, and data reception or data supply to the control means. Detecting means for generating a request for the data, and a condition changing means for changing the detection condition in the detecting means, wherein the control means is configured to respond to the request for data reception or data supply in an area corresponding to the request. Data reception from a certain buffer or data supply to the buffer may be executed.
[0021]
According to the present invention, the storage means built in the access means for accessing the waveform memory under the control of the control means allows the waveform data to be written to the waveform memory or the waveform data from the waveform memory. Are read out, and a buffer for temporarily storing waveform data when the data is read out and a buffer for codec that is temporarily stored by the control means for handling the waveform data. As a result, the sound source device can be provided with the codec function without adding a buffer. In this case, in each buffer constituted by being divided, the interrupt condition to the control means and the data request generation condition can be changed. Therefore, even if the storage means is divided to constitute the buffer, Each buffer can be used efficiently.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a configuration example of a musical sound generating apparatus having a sound source device including a waveform memory according to an embodiment of the present invention.
In the musical sound generating device 1 shown in FIG. 1, the CPU 10 is a central processing unit (Central Processing Unit) that controls the operation of musical sound generation in the musical sound generating device 1 by executing various programs. It is a timer that indicates time or generates a timer interrupt at specific intervals, and is used for time management of automatic performance. The ROM 12 is a ROM (Read Only Memory) in which a program for musical tone generation processing executed by the CPU 10 and various data are stored. A RAM 13 is a main memory in the musical sound generating apparatus 1 and is a RAM (Random Access Memory) in which a work area of the CPU 10 is set.
[0023]
The disk 14 is a recording medium such as a hard disk, floppy disk, or removable disk, and stores waveform data to be loaded into the waveform memory 21. The drive 15 is a disk drive for reading / writing the set disk 14. The MIDI interface 16 is a MIDI interface that sends out a MIDI message created in the musical sound generating device 1 to the outside and receives a MIDI message from the outside. The network interface 17 is a network interface for connecting to a server computer via a communication network such as a LAN (Local Area Network), the Internet, or a telephone line. The panel switch (panel SW) 18 is a variety of switches provided on the panel of the musical tone generation device 1, and various instructions can be given to the musical tone generation device 1 by operating this switch. The panel display 19 is a display on which various information is displayed when a musical sound is generated.
[0024]
The sound source unit 20 reads waveform data (waveform sample) from the waveform memory 21 based on a sound generation start instruction from the CPU 10, and performs processing such as interpolation, envelope application, channel accumulation (mixing), and effect (effect) application. And output as musical sound waveform data. The musical sound waveform data output from the sound source unit 20 is converted into an analog signal by the DAC 23 and emitted by the sound system 24. The waveform memory 21 is constituted by a high-speed memory such as SDRAM, and stores a large number of waveform sample data sampled at a predetermined rate. One word waveform sample is represented by 16 bits or 32 bits, for example, and an address is assigned to each waveform sample unit. That is, one waveform sample is read out by one access. The waveform memory 21 stores waveform data read from the disk 14 or the like prior to the generation of musical sounds.
[0025]
The external circuit 22 includes an analog / digital converter (ADC) for taking in audio data such as voice and musical sound from the outside, an external DSP for performing an effect applying process, or a digital filter. The waveform data supplied from the sound source unit 20 to the external circuit 22 is subjected to effect applying processing and digital filter processing in the external circuit 22 and returned to the sound source unit 20. In the sound source unit 20, the returned waveform data is mixed with the waveform data of other channels and output. Note that the external circuit 22 may be built in the musical sound generating device 1 or provided outside the musical sound generating device 1. The digital / analog converter (DAC) 23 converts the stereo musical sound data finally output from the sound source unit 20 into a digital musical sound signal and emits it from the sound system. The bus 25 is a CPU bus that interconnects the above-described units including an address bus, a control bus, and a data bus.
[0026]
Next, FIG. 2 shows a detailed configuration of the sound source unit 20 that is a sound source device including the waveform memory according to the embodiment of the present invention, and FIG. When the number of sound generation channels is 128 in the sound source unit 20, the sound source unit 20 operates in a time-division 128 channel. For this reason, control signals such as a control clock signal and a channel count value, which are reference signals for time division, are supplied to each unit in the sound source unit 20.
In FIG. 2, the waveform memory 21 is constituted by a readable / writable SDRAM (Synchronous DRAM), for example, and a plurality of relatively short-term samplings read from the disk 14 or the like in advance when the tone generator 20 generates musical sounds. The waveform is stored. The tone generator 20 generates musical sounds for each channel based on the waveform data read from the waveform memory 21 by time division for each channel.
[0027]
When generating a musical sound in response to a note-on, the CPU 10 in the musical sound generating device 1 selects a channel (allocated channel) to be used for generating a musical sound in accordance with the note-on from the 128 channels, and assigns the sound source control register 30 to it. Various sound source parameters are set in the storage area corresponding to the channel, and a sound generation start instruction for the selected channel is issued. The sound source control register 30 is supplied with an address from the CPU 10 via the address bus (AD4) and exchanges various data via the data bus (DATA4). In FIG. 2, a plurality of data buses (DATA4) are shown, but are shown as a plurality of data buses for convenience of explanation, and are actually a single bus. The tone generator parameter information is supplied from the CPU 10 to the tone generator control register 30 via the data bus (DATA4), and is stored in the register indicated by the register address given from the CPU 10 via the address bus (AD4) in the tone generator control register 30. The
[0028]
The sound source parameter information supplied to the sound source control register 30 together with the sound generation start instruction is a waveform memory reading speed (corresponding to a musical tone pitch), a waveform memory reading section, an envelope parameter, setting information for the mixer 33, an effect coefficient, and the like. . Of these, the waveform memory read section parameter is the start address AS of the waveform data to be read and its data length LPA. In this case, the sound source parameter supplied via the data bus (DATA4) is stored in a specific register in the sound source control register 30 indicated by the register address on the address bus (AD4). As a result, the sound source parameters corresponding to the plurality of registers are respectively stored.
[0029]
The tone generator control register 30 and the read / write circuit 31 perform six processes: process A, process B, capture process, interpolation process, X access process, and codec input / output process. The outline and timing of each process are as follows. The process A is based on the waveform data start address AS supplied from the sound source control register 30 and the information such as the data length LPA and pitch PITCH, and the waveform data of each tone generation channel according to the time-division channel timing for generating a musical tone. This is a process for creating a read address. The address of each channel is held in a register (not shown) in the read / write circuit 31. If the number of sound generation channels is 128, the process A creates waveform data read addresses for 128 channels within one DAC period in the DAC 23. As will be described later, in the musical sound generating apparatus 1 according to the present invention, the last 16 channels out of the 128 channels are diverted as write channels for writing the waveform data output from the mixer 33 to the waveform memory 21. Is possible.
[0030]
In this case, as shown in FIG. 3, the 1DAC cycle is divided into the first half and the second half, and waveform data read addresses of 1ch to 64ch are created in the first half period (Processing A first half ch), and 65ch ~ in the second half period. A 128ch waveform data read address is created (second half of process A). In process A, read addresses are generated for all channels, and the channel from which waveform data is to be read is determined in accordance with the progress of the integer part of the read address of each channel. The channel number of the determined channel and its channel are determined. The number of samples to be read out in (corresponding to the progress amount) is stored in the control RAM. It should be noted that four-point interpolation in the interpolation process requires four consecutive sample waveform data, of which waveform data read from the waveform memory 21 in the past is already stored in the waveform buffer. A time slot for processing each channel of 1ch to 128ch is given by equally dividing one DAC cycle. That is, the time slot assigned to each channel in process A is T / 128, where 1 DAC period is T, and the time slots are processed in the order of channels as shown in the figure.
[0031]
Process B is executed in the read / write circuit 31 with a delay of approximately ½ DAC period from process A, and is performed on a channel for which process A has been completed at a later-described timing. Process B accesses the waveform memory as many times as the number of accesses stored in the control RAM based on the read address of the channel stored as a channel to be read out in the control RAM, and reads out waveform samples for that number of times. ing. In this case, as shown in FIG. 3, reading from the waveform memory 21 for 1ch to 64ch is executed in the first half period of the 1DAC cycle (processing B first half ch), and from the waveform memory 21 for 65ch to 128ch in the second half period. Is read (Process B second half ch). In this case, in the process A, the process B is not performed for a channel whose channel number is not stored in the control RAM as a channel from which waveform data is to be read. The time slot in which the process B is performed is ¼ of one time slot of the process A, and if the period of one DAC is T, the time slot is T / 512. The 512 times per 1 DAC period means that 4 samples of waveform data can be read out per channel of the sound source.
[0032]
For a channel in which the number of accesses stored in the process A is plural (that is, a channel in which a plurality of integer parts of the read address have progressed), the process B for each waveform data read address corresponds to the time corresponding to the number of accesses. Each slot is sequentially executed. For example, as shown in process B of FIG. 3, process B is performed in 1 time slot for 1ch, process B is not performed for 2ch, process B is performed in 3 time slots for 3ch, and process is performed for 4ch. B is not performed, processing B is performed in 1 time slot for 5ch, processing B is not performed for 6ch, processing B is performed in 2 time slots for 7ch, and processing is performed for 8ch to 64ch that are not sounded B will not be performed. For the channel set as the write channel, a waveform data write address is generated in process B. The number of accesses to the write channel is always once.
[0033]
As described above, since there is a channel where the process B is not performed, in the first half period of the process B, a time slot from the end of the 7ch process to the start of the second half period becomes vacant and also in the latter half period. Will be vacant in the time slot before the next first period begins. Therefore, the X access processing by the X access circuit 40 is performed using this vacant time slot. In the process B, until the time slot becomes empty, the read / write circuit 31 gives the selector control signal (CONT1) to the selector 35 and switches the selector 35 to the read / write circuit 31 side. As a result, the waveform data read address can be supplied from the read / write circuit 31 to the waveform memory 21 via the address bus (AD2). When the time slot becomes empty in the process B, the read / write circuit 31 switches the selector 35 to the X access circuit 40 side by the selector control signal (CONT1). Further, the read / write circuit 31 gives a selector control signal (CONT2) to the X access circuit 40 so that an X access process described later can be executed.
[0034]
The capturing process is a process executed by the read / write circuit 31. The waveform data read in accordance with the waveform data read address supplied to the waveform memory 21 by the process B is sent via the data bus (DATA1). This is the process of capturing and writing to the built-in waveform buffer for each channel. This waveform buffer is a buffer for storing waveform data for inter-sample interpolation, and stores the latest waveform data read from the waveform memory 21 for each sample for four channels. When the waveform data read address is supplied to the waveform memory 21 in the process B, the waveform data is immediately read out from the waveform memory 21, so that the capturing process is started with a slight delay from the process B as shown in FIG. become. In this case, since one waveform sample is read at one waveform data read address, one sample of waveform data is acquired for one channel as shown in the acquisition process of FIG. 3, and no waveform data is acquired for two channels. For 3ch, waveform data is captured for 3 samples, for 4ch, waveform data is not captured, for 5ch, waveform data is captured for 1 sample, for 6ch, waveform data is not captured, and for 7ch, waveform data is 2 samples. Waveform data is not captured for channels 8 to 64. For the channel set as the write channel, instead of this capture process, a write process for writing waveform data supplied by the mixer 33 for each DAC period to the waveform memory write address is performed. Done.
[0035]
As described above, since there is a channel from which waveform data is not captured, a time slot from the end of the 7ch process to the start of the second half period becomes vacant in the first half period of the capture process, and later in the second half period. Becomes empty in the time slot until the next first half period begins. Therefore, the vacant time slot is assigned as a time slot when the X access circuit 40 that performs the X access process described later accesses the waveform memory 21. Note that one time slot in the capturing process is the same as one time slot of process B, and T / 512 is T / 512. Note that the read / write circuit 31 supplies a selector control signal (CONT1) to the selector 35 and switches the selector 35 to the read / write circuit 31 side until the time slot becomes empty in the capture process. As a result, the waveform data read from the waveform memory 21 can be taken into the waveform buffer of the read / write circuit 31 via the data bus (DATA1), the selector 35 and the data bus (DATA2). When the time slot becomes empty in the capture process, the read / write circuit 31 switches the selector 35 to the X access circuit 40 side by the selector control signal (CONT1). Further, the read / write circuit 31 gives a selector control signal (CONT2) to the X access circuit 40 so that an X access process described later can be executed.
[0036]
The interpolation process is a process executed by an interpolation circuit (not shown) in the read / write circuit 31. The waveform sample required for each channel is read from the waveform buffer according to the time division channel timing, and 2-point interpolation or 4-point interpolation is performed. This is a process of outputting the waveform data subjected to the above. In this case, since the waveform data stored by the capturing process is stored in the waveform buffer, the interpolation process starts slightly later than the capturing process. The interpolated waveform data is supplied from the read / write circuit 31 to the EG applying circuit 32. In this case, as shown in FIG. 3, 1ch to 64ch interpolation processing is performed in the first half period of the 1DAC cycle (first interpolation channel), and 65ch to 128ch interpolation processing is performed in the second half period (interpolation second half channel). The interpolation processing time for each channel of 1ch to 128ch is given by equally dividing one DAC cycle. That is, the time slot assigned to each channel in the interpolation processing is T / 128, where 1 DAC period is T, and the time slots are processed in the order of channels as shown in the figure.
[0037]
The X access process is a process executed under the control of the X access circuit 40 provided in the sound source control register 30. This X access process is a process in which the CPU 10 reads / writes the waveform data from the waveform memory 21 in the time slot when the time slot for performing the process B or the capture process is vacant. At this time, the control signal (CONT2) is supplied from the read / write circuit 31 to the X access circuit 40, so that it can be executed in the time slot described above. Further, the selector 35 is switched to the X access circuit 40 side by the control signal (CONT1), and the address bus (AD3) and the data bus (DATA3) are connected to the waveform memory 21.
[0038]
When the CPU 10 executes an X access process for reading waveform data from the waveform memory 21, the CPU 10 outputs an address for designating the XA register 42 built in the X access circuit 40 to the address bus (AD4), and the XA register The head address of the waveform data read address output to the data bus (DATA4) is written to 42, and the data length is written to a data length register (not shown). The read / write circuit 31 supplies and switches the control signal (CONT1) to the selector 35 when the time slot becomes empty in the process B or the capture process, and addresses the waveform data read address written in the XA register 42 in the waveform memory 21. It is supplied via the bus (AD3), the selector 35 and the address bus (AD1). At this time, the read / write circuit 31 also supplies a read enable signal to the waveform memory 21.
[0039]
As a result, the waveform data is read from the waveform memory 21 onto the data bus (DATA1) according to the supplied address. This waveform data is written into the CPU access area 41a of the FIFO 41 built in the X access circuit 40 via the selector 35 and the data bus (DATA3). As will be described later, three areas are set in the FIFO 41, each of which is used as a first-in first-out buffer memory, and the total storage capacity of the three areas is 512 words. After the waveform data read from the waveform memory 21 is written to the CPU access area 41a of the FIFO 41, the CPU 10 outputs an address for designating the FIFO 41 to the address bus (AD4) at a unique timing independent of the DAC cycle. Thus, the waveform data is read from the CPU access area 41a of the FIFO 41 via the data bus (DATA4).
[0040]
In addition, the CPU 10 supplies the head address and data length information of the waveform data to be read to the X access circuit 40, and the X access circuit 40 sequentially assigns addresses from the head address to the data length every time data is read from the waveform memory 21. Incremental waveform data read addresses are generated. This waveform data read address is written in the built-in XA register 42 and finally supplied to the waveform memory 21. As a result, waveform data of a predetermined number of samples written at successive address positions can be sequentially read out and stored in the FIFO 41 sequentially. The waveform data stored in the FIFO 41 is read out and taken into the CPU 10 at an operation timing of the CPU 10 different from the writing timing.
[0041]
In the X access process for writing the waveform data to the waveform memory 21, the CPU 10 outputs an address designating the XA register 42 built in the X access circuit 40 to the address bus (AD 4), and sends it to the XA register 42. Write the start address of the waveform data write address output to the data bus (DATA4). Further, the CPU 10 outputs an address designating the CPU access area 41a of the FIFO 41 built in the X access circuit 40 to the address bus (AD4), and the waveform data written to the waveform memory 21 is stored in the CPU access area 41a of the FIFO 41. In addition to writing only a fixed amount, the data length is written in a data length register (not shown). The read / write circuit 31 supplies and switches the control signal (CONT1) to the selector 35 when the time slot becomes empty in the process B or the capture process, and the waveform data write address written in the XA register 42 is stored in the waveform memory 21. It is supplied via the address bus (AD3), the selector 35 and the address bus (AD1). At the same time, the waveform data is read from the FIFO 41 and supplied to the waveform memory 21 via the data bus (DATA3), the selector 35 and the data bus (DATA1). At this time, the read / write circuit 31 also supplies a write enable signal to the waveform memory 21. As a result, the waveform data supplied to the waveform memory 21 is written according to the supplied write address.
[0042]
The CPU 10 supplies the X access circuit 40 with information on the start address of the write address and the data length of the waveform data. The X access circuit 40 sequentially assigns addresses from the start address to the data length each time waveform data is written. Incrementing generates successive waveform data write addresses. This waveform data write address is written in the built-in XA register 42 and finally supplied to the waveform memory 21. As a result, waveform data of a predetermined number of samples written by a predetermined amount in the CPU access area 41a of the FIFO 41 can be written to successive address positions of the waveform memory 21. In this case, an interrupt request is generated in the CPU 10 according to the empty state in the CPU access area 41a of the FIFO 41, and waveform data is sequentially written from the CPU 10 into the CPU access area 41a of the FIFO 41.
[0043]
In the X access processing, the XA register 42 includes two registers, and two systems of addresses can be stored in each register. These two addresses are for stereo L channel and R channel, and the head address is supplied from the CPU 10. For example, when the CPU 10 captures stereo waveform data from the waveform memory 21 by the X access processing, the L channel address and the R channel address stored in the XA register 42 are time-divisionally divided alternately. To be supplied. As a result, stereo L data and R data are alternately read from the waveform memory 21. The L data and R data are interleaved in the FIFO 41 and written alternately. The CPU 10 only has to read out and capture the L data and R data stored in the FIFO 41 and interleaved. When the CPU 10 reads stereo waveform data from the waveform memory 21 by the X access processing, the L channel waveform data and the R channel waveform data recorded in the individual areas of the waveform memory 21 from the waveform memory 21 by the X access circuit 40 are stored. Automatically interleaved. Similarly, when the CPU 10 writes stereo waveform data to the waveform memory 21 by the X access processing, the L channel address and the R channel address stored in the XA register 42 are alternately supplied to the waveform memory 21. The interleaved waveform data from the CPU 10 is separated into L-channel waveform data and R-channel waveform data and written into different areas of the waveform memory 21. In this way, the CPU 10 does not have to perform interleaving and cancellation of stereo waveform data, and the load on the CPU 10 is reduced.
[0044]
Here, a process of writing the waveform data output from the mixer 31 to the waveform memory 21 by the read / write circuit 31 will be described. The CPU 10 selects a channel to be used for writing from the last 16 channels of the read / write circuit 31 and sets the sound source control register 30 to set the channel as a write channel, and the waveform data mixed by the mixer 31. One waveform data is selected from the above and settings are made to supply it to the write channel. Further, the CPU 10 sets the waveform data write address (start address) and the data length to be written to the data length LPA as the start address AS of the channel of the sound source control register 30, and instructs the start of the writing process.
[0045]
The read / write circuit 31 stores in the address counter of the write channel in the waveform memory 21 via the address bus (AD2), the selector 35 and the address bus (AD1) in the time slot corresponding to the write channel of the process B. Provided waveform data write address. At the same time, the waveform data supplied from the mixer 33 to the write channel is supplied to the waveform memory 21 via the data bus (DATA2), the selector 35 and the data bus (DATA1). Further, a write enable signal is supplied from the read / write circuit 31 to the waveform memory 21. As a result, the waveform data is written to the waveform memory 21.
By the way, the address counter of the write channel is loaded with the start address set as the start address AS at the start of writing. The count value of the address counter is sequentially incremented until it corresponds to the data length set in the data length LPA every time the write channel is written, and becomes a continuous waveform data write address. This waveform data write address is supplied to the waveform memory 21, and the waveform data supplied from the mixer 33 is written at the storage position indicated by the address in the waveform memory 21.
[0046]
Next, the interpolated waveform data of each channel output in a time division manner from the read / write circuit 31 is given an envelope in the EG giving circuit 32. The given envelope is determined based on the envelope parameter of each channel given from the CPU 10 and stored in the register of the sound source control register 30. Waveform data for 128 channels, for example, with an envelope is supplied to the mixer 33. Further, the mixer 33 is subjected to effect processing and the like output from the signal processing circuit (DSP) 34, for example, waveform data for 8 channels, and the external circuit 22 is subjected to filter processing and effect processing, for example, 8 channels. Minute waveform data is supplied. The mixer 33 multiplies the supplied waveform data of each channel by a coefficient value for mixing. The coefficient value is given from the CPU 10 to the sound source control register 30 and stored in a built-in register. Waveform data mixed in the mixer 33 includes 8 channels for the DSP 34, 8 channels for the external circuit 22, and 2 channels (L and R outputs) for the final output of the sound source unit 20 for the DAC 23. It is made to output. The musical tone signal converted into an analog signal by the DAC 23 is emitted from the sound system 24. As described above, the mixer 33 multiplies the waveform data of the channel designated by the CPU 10 by the designated coefficient value, mixes the result, and sends the mixing result to the output unit based on the designation of the CPU 10 through the designated channel. ing.
[0047]
Next, the codec input / output process will be described. The codec here refers to the CPU 10 supplying waveform data to the sound source unit 20 in the DAC cycle, or waveform data output from the sound source unit 20 in the DAC cycle. It means the codec input / output function for receiving. With this codec input / output function, waveform data can be directly input / output from the CPU 10. In the codec input / output processing, waveform data is exchanged between the sound source unit 20 that operates on the basis of the DAC cycle and the CPU 10 that operates at a different operation timing, and thus a waveform buffer is required. . Since the FIFO 41 is used as the waveform buffer, the FIFO 41 is divided into three as shown in FIG. For example, about 1/2 of the FIFO 41 is allocated as a waveform buffer when performing the above-described X access processing, and this area is referred to as a CPU access area 41a. Then, about 1/2 of the remaining area (about 1/4 of the entire area) is allocated as the output codec area 41c and the input codec area 41b.
[0048]
In the codec input / output processing, for example, when an AD converter is connected as the external circuit 22 and the input waveform is converted into digital waveform data by the AD converter and input to the mixer 33, the waveform is input by the input codec function. Data (stream data) can be captured and recorded by the CPU 10. In this case, the waveform data input from the AD converter is written to the input codec area 41 b of the FIFO 41 built in the sound source control register 30 via the mixer 33 for each DAC period. When a predetermined amount of waveform data is written in the input codec area 41 b of the FIFO 41, the CPU 10 is notified of a data read request, and the CPU 10 reads out the waveform data from the input codec area 41 b of the FIFO 41 and writes it in the RAM 13. As a result, the CPU 10 can capture and record the audio signal input from the external circuit 22. Instead of the CPU 10, a DMA (Direct Memory Access) controller may read the waveform data from the input codec area 41 b of the FIFO 41 and write it directly to the RAM 13. In this case, waveform data can be transferred without imposing a heavy burden on the CPU 10.
[0049]
In the codec input / output processing, the waveform data (stream data) stored in the RAM 13 can be retrieved and reproduced by the CPU 10 (output codec). In this process, the waveform data read from the RAM 13 is written into the output codec area 41c of the FIFO 41 built in the sound source control register 30 at the timing of the CPU 10 so that the data does not overflow from the area 41c. The waveform data written in the output codec area 41c of the FIFO 41 is sequentially input to the mixer 33 as a mixer input, one sample at each DAC period. For example, when the mixer 33 is set to supply the waveform data to the DSP 34, the DSP 34 can perform effect processing on the waveform data.
[0050]
This waveform data is mixed with the musical tone data generated in the mixer 33, supplied to the DAC 23, and emitted together with the musical tone signal. In this case, when the waveform data written in the output codec area 41c of the FIFO 41 becomes less than a predetermined amount, a data write request is notified to the CPU 10, and the CPU 10 responds to the free capacity of the output codec area 41c from the RAM 13. Is read out and written to the output codec area 41 c of the FIFO 41. As a result, the waveform data stored in the RAM 13 can be retrieved and reproduced by the CPU 10. Instead of the CPU 10, a DMA (Direct Memory Access) controller may read the stream data from the RAM 13 and directly write it in the output codec area 41c of the FIFO 41. In this case, waveform data can be transferred without imposing a heavy burden on the CPU 10.
[0051]
By the way, the FIFO 41 in the sound source unit 20 shown in FIG. 2 does not have to be divided and used as shown in FIG. That is, the entire FIFO 41 may be allocated as the CPU access area 41a as shown in FIG. 6A, or 3/4 of the FIFO 41 as the CPU access area 41a as shown in FIG. 6B. Allocation and the remaining 1/4 may be allocated as the output codec area 41c. As will be described later, the position and size of each area are controlled by the divided data in the FIFO control register 44. This setting may be changed at any time according to an instruction from the user or the operation status of the musical sound generating device 1. For example, when the input / output codec function is not used at all, the setting is made as shown in FIG. Further, when the X access function and the output codec function are used, the setting may be made as shown in FIG. 6B. If the output codec area is further increased to increase the stability of the output codec, FIG. In b), the capacity of the CPU access area 41a can be reduced to increase the output codec area 41c.
[0052]
In each area of the FIFO 41 that can be divided and used as described above, as shown in FIGS. 6A, 6B, and 6C, the address position to write data is indicated by the write pointer WP, and the address position to read is shown. It is indicated by a read pointer RP. Each time writing / reading is performed, the write pointer WP and the read pointer RP shift to an upper address in the upward direction indicated by an arrow by one address. Then, the highest address returns to the lowest address. For example, the CPU access area 41a is indicated by the write pointers WP1 and RP1, and data is written between the write pointer WP1 and the read pointer RP1 in this area 41a. When writing waveform data in the CPU access area 41a of the FIFO 41, the write pointer WP1 is advanced by one and the waveform data is written at the storage position indicated by the write pointer WP1. When reading the waveform data from the CPU access area 41a, the read pointer RP1 is advanced by one and the waveform data is read from the storage position indicated by the read pointer RP1. Further, the output codec area 41c is indicated by the write pointer WP2 and the read pointer RP2, and data is written between the write pointer WP2 and the read pointer RP2 in this area 41c. Further, the input codec area 41b is indicated by a write pointer WP3 and a read pointer RP3, and data is written between the write pointer WP3 and the read pointer RP3 in this area 41b. The progress of the write pointer WP and the read pointer RP is managed by the X access circuit 40, and the CPU 10 does not need to control them.
[0053]
These six pointers are stored in the pointer register 43 built in the X access circuit 40 shown in FIG. Each pointer in the pointer register 43 stores a count value counted by an address counter. In this case, each pointer value is obtained by using one address counter in a time-sharing manner. That is, the address counter stores the count value incremented according to the writing / reading of the data in each area. Note that writing / reading of each area in the FIFO 41 is controlled so that the read pointer RP does not overtake the write pointer WP. When the CPU 10 intends to set these pieces of information in the FIFO control register 44, the CPU 10 supplies the information to the data bus (DATA4) and sets an address indicating the FIFO control register 44 of the sound source control register 30 to the address bus. (AD4) to perform normal write operation.
[0054]
The FIFO 41 that can be divided and used in this way is controlled by the FIFO control register 44. The FIFO control register 44 stores divided data indicating where the FIFO 41 is divided and assigned to which area from the CPU 10 via the data bus (DATA4), and write data and read data in each area of the FIFO 41. Notification control information indicating a CPU interrupt or data request generation condition when the remaining data amount is equal to or less than a predetermined amount, and stereo instruction information indicating whether or not the data stored in each area in the FIFO 41 is stereo. Clear information for clearing each area in the FIFO 41 and bit number information indicating whether the data stored in each area in the FIFO 41 is 16 bits or 32 bits are supplied. When these pieces of information are supplied from the CPU 10 to the data bus (DATA4), the register address indicating the FIFO control register 44 is supplied from the CPU 10 to the sound source control register 30 via the address bus (AD4). 44.
[0055]
When the divided data for dividing the FIFO 41 is supplied to the FIFO control register 44, the FIFO control register 44 divides the FIFO 41 according to the divided data and sets a pointer corresponding to the number of divisions in the pointer register 43. As a result, the FIFO 41 can be divided and used. When the notification control information is supplied to the FIFO control register 44, the FIFO control register 44 determines the threshold of the remaining data amount in each area set in the FIFO 41 according to the notification control information. When the remaining data amount is less than or equal to this threshold, a CPU interrupt is issued to the CPU 10 or a data request is issued to the DMA controller, and data write / read is notified. In this notification control, up to three systems of notification control information are used so that the FIFO 41 can be divided into three.
[0056]
An example when the CPU 10 writes the threshold set by the notification control information in the CPU access area shown in FIG. 7 will be described. As shown in FIG. 7B, when a threshold value a for notifying a CPU interrupt requesting writing or a data request when a small amount of data is read is suitable, the notification is suitable when the size of the area is small. The number of times will increase. As shown in FIG. 7C, when almost half of the data in the area is read, if the CPU interrupt requesting writing or the threshold value b notifying the data request is used, the size of the area is medium. As a result, the number of notifications can be suppressed to some extent. As shown in FIG. 7D, when the data is read out until it becomes a fraction of the area, the CPU interrupt that requests writing and the threshold c that notifies the data request are used. This is suitable for a large size, and the number of notifications can be suppressed. As shown in FIG. 7 (e), when all the data in the area is read out, the CPU interrupt that requests writing or the threshold d that notifies the data request is used for data that does not require real-time performance. This is suitable, and the number of notifications can be set to a small number.
[0057]
Next, an example in which the CPU 10 reads from the CPU access area shown in FIG. 8 will be described. As shown in FIG. 8B, when a threshold value e for notifying a CPU interrupt requesting reading or a data request when a small amount of data is written is suitable, the number of notifications is suitable. It will increase. As shown in FIG. 8 (c), when the CPU interrupt that requests reading when almost half of the data in the area is written and the threshold f that notifies the data request are suitable, the area is suitable for a medium size. The number of notifications can be suppressed to some extent. As shown in FIG. 8 (d), when the size of the area is large when the CPU interrupt requesting reading when the data is written with a fraction of the area and the threshold value g notifying the data request are written. And the number of notifications can be suppressed. As shown in FIG. 8E, if the CPU interrupt that requests reading when data is written in most of the area and the threshold value h that notifies a data request are suitable for data that does not require real-time characteristics. The number of notifications can be set to a small number.
[0058]
Further, when the stereo instruction information is supplied to the FIFO control register 44, the FIFO control register 44 performs an interleaving process in which L data and R data are alternately written in the FIFO 41 to control to write waveform data. This stereo instruction information is stereo instruction information of a maximum of three systems so that when the FIFO 41 is divided into three, stereo instructions can be given in each area.
Further, when clear information is supplied to the FIFO control register 44, the FIFO control register 44 clears the FIFO 41. This clear information is made into three systems of clear information so that when the FIFO 41 is divided into three, it can be cleared in each area.
Furthermore, when the bit number information is supplied to the FIFO control register 44, the FIFO control register 44 handles the waveform data as 16 bits or 32 bits. Since the FIFO 41 is 512 words × 16 bits, the FIFO 41 is controlled in accordance with the designated number of bits. That is, when 32 bits are instructed by the bit number information, the FIFO control register 44 controls to read / write two words from the FIFO 41 when reading / writing one waveform data. The number-of-bits information is the number-of-three-system number-of-bits information so that when the FIFO 41 is divided into three, the number of bits can be indicated in each area.
[0059]
Next, FIG. 4 shows a data flow diagram in the sound source unit 20 having the configuration shown in FIG. 2, FIG. 5 shows its operation timing, and FIG. 6 shows a division form of the FIFO 41. With reference to these figures, the X access processing and A data flow in codec input / output processing will be described.
In FIG. 4, the control means 5 comprises a CPU 10, a system RAM (RAM 13 shown in FIG. 1), and a DMA controller, and controls the writing / reading of waveform data in the waveform memory 21 and the transfer control of waveform data. The FIFO 41 is divided into three parts: a CPU access FIFO 41a, an input codec FIFO 41b, and an output codec FIFO 41c.
[0060]
The writing means 52 is a function of the reading / writing circuit 31 and is means for writing waveform data into the waveform memory 21 using a specific channel among the channels for generating musical sounds. The tone generator 51 is a tone generator that generates musical tone data based on the waveform data read by the read / write circuit 31. This musical tone data consists of a maximum of 128 channels. The mixer means 53 has the functions of the mixer 33 and the DSP 34 and mixes the tone data of each channel generated by time division to create final tone data and supply it to the DAC 23, or the waveform data to the external circuit 22. Receives and effects-processed waveform data is received and mixed. The external circuit 22, the DAC 23, the sound source means 51, the writing means 52, and the mixer means 53 operate in synchronization with the sampling frequency Fs with 1 DAC period as a reference. On the other hand, data is written from the mixer unit 53 to the input codec FIFO 41b in synchronization with the sampling frequency Fs, but is read at a unique operation timing in the control unit 5. Similarly, data is written to the output codec FIFO 41 c from the control means 5 at a unique operation timing, but the data is read out in synchronization with the sampling frequency Fs and supplied to the mixer means 53.
[0061]
Here, the writing process executed by the writing means 52 is executed in the period c shown in FIG. FIG. 5A shows the processing periods a, b, and d of the process B described above, and the period c is immediately after the period b in which the process B is executed in the second half DAC cycle. This is based on the fact that the writing means 52 can write waveform data into the waveform memory 21 using the last 16 channels when the tone data generation channel is 128 channels. The operation timing shown in FIG. 5A is the operation timing when the X access process is not executed and the CPU 10 does not access.
[0062]
When X access processing is executed, the control means 5 (CPU 10 or DMA controller) uses the CPU access FIFO 41a as a buffer memory to write waveform data to the waveform memory 21 or from the waveform memory 21 to the waveform data. Read out. FIG. 5B shows an example of operation timing when data is written to the waveform memory 21 in the X access process. The timing at which the CPU 10 or DMA controller writes to the CPU access FIFO 41a is a period h indicated as CPU writing, and the timing at which the X access circuit 40 writes the waveform data written to the CPU access FIFO 41a to the waveform memory 21 is the period e, f and g. Thus, when the amount of data to be written is larger than the amount of data that can be transferred in one DAC period, the X access circuit 40 writes to the waveform memory 21 over a plurality of periods such as periods e, f, and g. If the amount of data to be written is larger than the capacity of the CPU access FIFO 41a, writing from the CPU 10 or DMA controller to the CPU access FIFO 41a is performed in a plurality of periods instead of one continuous period. In this case, the second and subsequent periods are started in response to the aforementioned CPU interrupt and data request notification. The same applies to the case where data is read from the waveform memory 21 in the X access processing. If the amount of data read from the waveform memory 21 to the CPU access FIFO 41a in the X access processing is larger than the data amount that can be transferred in one DAC period, transfer over a plurality of periods is possible. If the amount of data is larger than the capacity of the FIFO 41a, the CPU 10 or the DMA controller executes data reading from the CPU access FIFO 41a in a plurality of periods. The waveform data read from the waveform memory 21 is stored in the CPU access FIFO 41a, and an address offset from the address from which the waveform data is read is generated as a write address, and the waveform read from the CPU access FIFO 41a is generated. By writing the data to the waveform memory 21, the waveform data can be copied.
[0063]
Furthermore, when codec input / output processing is executed, waveform data input from the mixer means 53 for each DAC cycle, for example, an audio signal converted into a digital signal in the external circuit 22, is input to the input codec FIFO 41b. The data is stored, read from the input codec FIFO 41 b by the control means 5, and taken into the control means 5. The waveform data transferred from the control means 5 is stored in the output codec FIFO 41c, read out from the output codec FIFO 41c at every DAC period, supplied to the mixer means 53, mixed with the musical sound data, and sent to the DAC 23. Will be output. The input codec FIFO 41b and the output codec FIFO 41c can input and output 1/2 downsampled waveform data, and downsampling in this way reduces the number of accesses to the respective codec FIFOs 41b and 41c. be able to. When the waveform data is down-sampled, it is preferable to prevent the occurrence of aliasing noise by performing LPF processing by the DSP 34. Further, in the input codec FIFO 41b and the output codec FIFO 41c, the big endian in which the most significant bit of the bit string is located on the left side and the little endian in which the least significant bit of the bit string is located on the left side can be set.
[0064]
In the above description, the processing in the sound source unit 20 is executed in a section obtained by dividing the 1DAC cycle into the first half and the second half as shown in FIG. 3, but the present invention is not limited to this, and the 1DAC cycle is not limited to this. It may be divided into 1/3, 1/4,... And each process may be performed in units of those sections. In addition, each process may be performed without dividing one DAC period, and when dividing one DAC period, the period length of the section may not be divided into equal parts. Furthermore, it does not matter how the 1DAC cycle is divided. Anyway, it is sufficient that the waveform memory access by the read / write circuit 31 and the waveform memory access by the X access circuit can be divided in time.
[0065]
【The invention's effect】
As described above, in the present invention, the storage means built in the access means for accessing the waveform memory under the control of the control means allows the waveform data to be written to the waveform memory or the waveform data from the waveform memory. Are read out, and a buffer for temporarily storing waveform data when the data is read out and a buffer for codec that is temporarily stored by the control means for handling the waveform data. As a result, the sound source device can be provided with the codec function without adding a buffer. In this case, in each buffer constituted by being divided, the interrupt condition to the control means and the data request generation condition can be changed. Therefore, even if the storage means is divided to constitute the buffer, Each buffer can be used efficiently.
In addition, the codec function allows waveform data to be exchanged between the mixer unit of the sound source device that operates in synchronization with a predetermined sampling period and the control unit (CPU) that operates at a timing independent of the sampling period. it can. In particular, since the output destination / input source of the codec function is the mixer means, the following operation is possible by setting the mixer.
(1) It is possible to apply an effect to the waveform data generated by the musical sound generating means by the effect applying means and pass it to the control means (recording).
(2) The effect can be applied to the waveform data (software sound source or the like) supplied by the control unit.
(3) The waveform data generated by the musical tone generation means can be transferred to the control means, and an effect can be given by the control means (soft effect) and returned to the mixer means.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a musical sound generating apparatus having a sound source device including a waveform memory according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a detailed configuration of a sound source unit that is a sound source device including the waveform memory according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating an operation timing of the sound source device including the waveform memory according to the embodiment of the present invention.
FIG. 4 is a functional block diagram for explaining a data flow of the sound source device according to the embodiment of the present invention.
FIG. 5 is a diagram showing CPU access timing in the sound generator device according to the embodiment of the present invention;
FIG. 6 is a diagram showing a FIFO division form in the sound source device according to the embodiment of the present invention;
FIG. 7 is a diagram showing an aspect of an interrupt and a data request threshold when reading from the FIFO in the sound source device according to the embodiment of the present invention;
FIG. 8 is a diagram showing an aspect of an interrupt and a data request threshold at the time of writing from the FIFO in the tone generator according to the embodiment of the present invention;
FIG. 9 is a block diagram showing a configuration of a conventional waveform memory sound source.
[Explanation of symbols]
1 musical tone generator, 5 control means, 10 CPU, 11 timer, 12 ROM, 13 RAM, 14 disk, 15 drive, 16 MIDI interface, 17 network interface, 18 panel SW, 19 panel display, 20 tone generator, 21 waveform Memory, 22 External circuit, 23 DAC, 24 sound system, 25 bus, 30 Sound source control register, 31 Read / write circuit, 32 EG assigning circuit, 33 Mixer, 35 Selector, 40 X access circuit, 41a CPU access area, 41b Input codec area, 41c Output codec area, 42 XA register, 43 pointer register, 44 FIFO control register, 51 sound source means, 52 writing means, 52 writing means, 53 mixer means, 120 sound source section, 121 waveform memory, 122 External circuit 130 tone generator control register, 131 read-write circuit, 132 EG applying circuit, 133 a mixer, 134 DSP, 140 X access circuit, 141 FIFO, 142 XA register

Claims (4)

Waveform memory that can read and write waveform data,
It reads waveform data from the waveform memory, a tone generation means for periodically based on the read waveform data to generate tone waveform data which is the sampling period,
The waveform data including the generated tone waveform data of the tone generating means is input, and mixing means for performing mixing processing, period and outputs the waveform data mixed there is a sampling period,
Control means for controlling the operation of the tone generation means and the mixing means;
During the time when the musical sound generating means is not accessing the waveform memory, the waveform data in the waveform memory is accessed for continuous reading or writing under the control of the control means, and the sampling period from the mixing means Access means for transferring waveform data to be input every time to the control means;
Storage means built in the access means,
Said access means, wherein a first region of the storage means, the control means temporarily stored in order to pass to the control means the waveform data read out during the reading the waveform memory is carried out by the control of the And a buffer for temporarily storing waveform data at the time of writing to the waveform memory, and the second area of the storage means is used to control the waveform data input from the mixing means. A sound source device characterized in that it can be used as a buffer for temporary storage for delivery to a means. Waveform memory that can read and write waveform data,
It reads waveform data from the waveform memory, a tone generation means for periodically based on the read waveform data to generate tone waveform data which is the sampling period,
The waveform data including the generated tone waveform data of the tone generating means is input, and mixing means for performing mixing processing, period and outputs the waveform data mixed there is a sampling period,
Control means for controlling the operation of the tone generation means and the mixing means;
During the time when the tone generation means is not accessing the waveform memory, the waveform data in the waveform memory is accessed for continuous reading or writing under the control of the control means, and sequentially input from the control means. Access means for outputting the waveform data to be mixed to the mixing means for each sampling period;
Storage means built in the access means,
Said access means, wherein a first region of the storage means, the control means temporarily stored in order to pass to the control means the waveform data read out during the reading the waveform memory is carried out by the control of the And a buffer for temporarily storing waveform data at the time of writing to the waveform memory , and a second area of the storage means is input from the control means to the mixing means A sound source device that can be used as a buffer for temporarily storing waveform data.   3. The sound source device according to claim 1, wherein the size of the first area and the size of the second area in the storage unit can be changed according to a user instruction or an operation state, respectively. . Furthermore, detecting means for detecting a state of waveform data in the buffer which is the first area and the second area, and generating a request for data reception or data supply to the control means,
Condition changing means for changing detection conditions in the detecting means;
The control means executes data reception from a buffer which is an area corresponding to the request or data supply to the buffer in response to the data reception or data supply request. The sound source device according to 1 or 2.

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