JP3695358B2 - Disk drive - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk drive device that drives a loaded disk.
[0002]
[Prior art]
In the current portable MD (mini disk) device, the MD is driven by a brushless three-phase motor (hereinafter, also simply referred to as “motor”) that does not have a Hall element for detecting the rotational position. The rotational speed of the motor is calculated from the phase difference between a plurality of counter electromotive edge signals obtained by the rotation of the motor, and the phase switching timing is determined.
[0003]
Here, the counter electromotive edge signal means an output signal of a comparator that compares the reference intermediate potential with the counter electromotive voltage induced in each phase coil. In the following, the motor control by such a method is referred to as “control by the first delay mode”.
[0004]
However, if there is an offset variation between phases in a comparator that generates a detection signal corresponding to the rotational position of the motor, it is likely to be adversely affected when the rotational speed is low. That is, when compared with an ideal state where the comparator has no offset, an error occurs in the detection signal corresponding to the rotational position of the motor, and in some cases, this is masked by a mask signal that prevents erroneous detection of the edge. Therefore, there is a problem that the motor cannot be controlled normally.
[0005]
On the other hand, conventionally, there is a method for controlling a motor by calculating a rotational speed from a time interval between counter-electromotive edges corresponding to one cycle, that is, 1/4 rotation of the motor, in a single counter-electromotive edge signal. is there. In the following, the motor control by this method is referred to as “control in the second delay mode”.
[0006]
However, in the control in the second delay mode, since the rotation speed is calculated from the time interval between the counter-electromotive edges corresponding to 1/4 rotation of the motor, when the rotation of the motor is suddenly accelerated or decelerated, Since the generated back electromotive edge signal is deformed, there is a problem that phase switching of the motor is not performed at a normal timing.
[0007]
[Problems to be solved by the invention]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a disk drive device that can realize optimal control of a motor.
[0008]
[Means for Solving the Problems]
An object of the present invention is to provide a first timing signal generating means for generating a first timing signal for determining a phase switching timing of a motor according to a phase difference between a plurality of drive signals for driving the motor, Including period measuring means for selectively measuring the N period or M period (N and M are different natural numbers) of any one drive signal in accordance with the supplied selection signal, Every M cycles A second timing signal generating means for generating a second timing signal for determining the phase switching timing of the motor, and a motor for selectively supplying the first timing signal or the second timing signal to the driving means in accordance with the rotational speed of the motor This is achieved by providing a disk drive characterized by comprising control means. According to such means, the motor can be driven by the first timing signal or the second timing signal according to the rotational speed.
[0009]
Here, the second timing signal generating means is With the above configuration, The phase switching timing can be easily controlled, and the rotational speed of the motor can be easily changed by driving the motor with the second timing signal.
[0010]
Further, the motor control means further includes speed calculation means for calculating the rotation speed of the motor according to the drive signal and generating a selection signal according to the calculated rotation speed, and the motor control means adds the selection signal generated by the speed calculation means to the selection signal generated by the speed calculation means. Accordingly, if the first timing signal or the second timing signal is selectively supplied to the driving means, the rotation speed of the motor is calculated at a high speed by the speed calculation means, so that it corresponds to the rotation speed by the motor control means. Control can be speeded up.
Further, if the motor control means selectively supplies the first timing signal or the second timing signal to the drive means according to the control signal supplied from the outside, the motor control means from the outside to the motor control means at an arbitrary timing. By supplying the control signal, the degree of freedom in controlling the motor can be increased.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0012]
FIG. 1 is a block diagram showing the overall configuration of a disk drive device according to an embodiment of the present invention. As shown in FIG. 1, a disk drive device according to an embodiment of the present invention includes a spindle motor 3 that rotates a disk 1, a reading unit 5 that reads a signal recorded on the disk 1, a motor driver 10, An RF amplifier 11, a system LSI 20, and a headphone amplifier 21 are provided. The reading unit 5 includes a pickup 7 and an element unit 9 including a laser diode (LD) and a photodetect IC (PD). The system LSI 20 includes a CLV servo circuit 13, a motor controller 15, and an MCU 17. The spindle motor 3 is composed of the three-phase motor, which will be described in detail later.
[0013]
Here, the spindle motor 3 and the reading unit 5 are connected to the motor driver 10, and the RF amplifier 11 is connected to the element unit 9. The system LSI 20 is connected to the motor driver 10 and the RF amplifier 11, and the headphone amplifier 21 is connected to the system LSI 20.
The motor controller 15 is connected to the motor driver 10, and the CLV servo circuit 13 is connected to the motor controller 15 and the MCU 17. The MCU 17 is connected to the motor controller 15.
[0014]
In the disk drive device according to the present embodiment having the above-described configuration, the signal detected by the photodetector IC included in the element unit 9 is amplified by the RF amplifier 11 and subjected to predetermined processing by the system LSI 20. The The signal is amplified by the headphone amplifier 21 and output as an audio signal.
[0015]
On the other hand, the CLV servo circuit 13 generates a signal SPF and supplies it to the motor controller 15 by performing pulse width modulation in accordance with the signals SWDT, SCLK, and XLAT supplied from the MCU 17. The CLV servo circuit 13 generates a signal XWL and supplies it to the motor controller 15.
[0016]
The motor controller 15 is controlled by signals SWDT, SCLK, and XLAT supplied from the MCU 17, and generates a drive voltage VS for driving the spindle motor 3 based on the signal SPF supplied from the CLV servo circuit 13. To the motor driver 10. Further, the motor controller 15 generates logical drive signals DU, DV, DW for controlling the spindle motor 3 and supplies them to the motor driver 10.
The motor driver 10 generates signals CU, CV, and CW indicating the rotational position of the motor according to the supplied logical drive signals DU, DV, DW and the drive voltage VS, and supplies the signals to the motor controller 15.
[0017]
FIG. 2 is a diagram showing a configuration of a drive unit 10a included in the motor driver 10 shown in FIG. As shown in FIG. 2, drive unit 10a includes a three-phase control unit 23, a pre-driver 25, a comparator 27, N-channel MOS transistors NT1 to NT6, and intermediate nodes N1 to N3. Here, the three-phase control unit 23 is connected to the motor controller 15, and the pre-driver 25 is connected to the three-phase control unit 23.
[0018]
On the other hand, N channel MOS transistors NT1 and NT2, N channel MOS transistors NT3 and NT4, and N channel MOS transistors NT5 and NT6 are connected in series between a power supply voltage node Vcc and a ground node, respectively. The gates of NT1 to NT6 are connected to the pre-driver 25.
[0019]
Intermediate node N1 located between N channel MOS transistors NT1 and NT2, intermediate node N2 located between N channel MOS transistors NT3 and NT4, and intermediate node located between N channel MOS transistors NT5 and NT6 N3 is connected to the motor TPM and the comparator 27, and the midpoint CP of the motor TPM is connected to the comparator 27. The motor TPM is built in the spindle motor 3 shown in FIG.
[0020]
In the drive unit 10a having such a configuration, the three-phase control unit 23 determines the direction of the current that drives the motor TPM based on the logical drive signals DU, DV, DW and the drive voltage VS supplied from the motor controller 15. Then, a signal indicating the direction of the current is supplied to the pre-driver 25. At this time, the pre-driver 25 decodes the supplied signal and selectively supplies a voltage equal to or higher than the threshold voltage to the gates of the N-channel MOS transistors NT1 to NT6. As a result, the N channel MOS transistors NT1 to NT6 are selectively turned on, and the potentials of the intermediate nodes N1 to N3 are adjusted, whereby a current is supplied to the motor TPM in a predetermined direction.
[0021]
Further, the comparator 27 generates signals CU, CV, and CW indicating the rotational position of the motor by comparing the voltage of each phase (the potential of the intermediate nodes N1 to N3) with the potential of the midpoint CP, and the motor controller. 15 is supplied.
[0022]
FIG. 3 is a diagram showing a configuration of the motor controller 15 shown in FIG. As shown in FIG. 3, the motor controller 15 includes an edge detection unit 31 and a phase switching unit 33, a drive logic / brake logic circuit 35, an interpolation edge circuit 37, a delay unit 39, a command decode clock generation unit 40, a mask The circuit includes a limiter circuit 41, a window unit 43, a start-up circuit 45, a PWM circuit 47, a VS control unit 49, and a speed calculation circuit 91.
[0023]
Here, the edge detection unit 31 is connected to the motor driver 10, the phase switching unit 33 is connected to the edge detection unit 31, and the drive logic / brake logic circuit 35 is connected to the phase switching unit 33. The interpolation edge circuit 37 is connected to the edge detection unit 31, and the delay unit 39 is connected to the edge detection unit 31, the interpolation edge circuit 37, and the speed calculation circuit 91.
[0024]
The command decode clock generation unit 40 is connected to the CLV servo circuit 13, the delay unit 39, and the VS control unit 49. The mask limiter circuit 41 is connected to the phase switching unit 33 and the delay unit 39. Connected to the limiter circuit 41. The startup circuit 45 is supplied with startup parameters required for starting the spindle motor 3, and the PWM circuit 47 is connected to the startup circuit 45. The VS control unit 49 is connected to the edge detection unit 31 and the phase switching unit 33, the PWM circuit 47, the command decode clock generation unit 40, and the speed calculation circuit 91, and the speed calculation circuit 91 is connected to the delay unit 39.
[0025]
Hereinafter, the operation of the motor controller 15 having the above-described configuration will be described. The edge detection unit 31 will be described later. FIG. 6 (a) to 6 (c) and FIGS. 12 (a) to 12 (c), the transitions (edges) of the signals CU, CV, and CW were detected, and obtained by edge detection of each phase. An edge detection signal XEG is generated and output by performing NOR operation on the edge detection signal.
[0026]
The delay unit 39 calculates an amount of delay required when calculating the phase switching timing according to the edge detection signal XEG generated by the edge detection unit 31, and represents an edge representing the rotation speed of the spindle motor 3. The interval signal FEI is generated and will be described in detail later.
[0027]
In addition, when the edge is not accurately detected by the edge detection unit 31, the motor will step out. Therefore, even if the detected edge is missing, the interpolation edge circuit 37 does not rotate the spindle. In order to rotate the motor 3 normally, the phase switching unit 33 and the delay unit are configured to interpolate the edges in accordance with the edge detection signal XEG supplied from the edge detection unit 31 and the edge interval signal FEI supplied from the delay unit 39. An edge detection signal is supplied to 39.
[0028]
Further, the phase switching unit 33 is a mask set signal indicating the phase switching timing of the motor TPM according to the signal supplied from the edge detection unit 31 and the interpolating edge circuit 37 and the delay amount determined by the delay unit 39. XMS is generated and supplied to the mask limiter circuit 41 and the VS control unit 49, and a control signal for controlling the rotation of the spindle motor 3 is supplied to the drive logic / brake logic circuit 35.
[0029]
On the other hand, the startup circuit 45 generates the start signal ST and the phase switching signal according to the supplied startup parameter as described above, supplies the start signal ST to the phase switching unit 33, and switches the phase switching signal to the phase. To the unit 33 and the PWM circuit 47. At this time, the PWM circuit 47 performs pulse width modulation on the signal supplied from the activation circuit 45 to generate a pulse width modulation (PWM) signal. The drive logic / brake logic circuit 35 is a circuit for accelerating or decelerating the rotation of the spindle motor 3, and generates logical drive signals DU, DV, DW according to the control signal supplied from the phase switching unit 33. To do.
[0030]
Then, the mask limiter circuit 41 determines the mask time according to the edge interval signal FEI supplied from the delay unit 39 and the mask set signal XMS supplied from the phase switching unit 33, and changes the rotation speed of the spindle motor 3. Limit within a predetermined range. Note that the mask limiter circuit 41 generates a mask signal MSK and supplies it to the window unit 43.
[0031]
Here, the window unit 43 generates a window signal according to the supplied edge detection signal and mask signal MSK, and supplies the window signal to the edge detection unit 31. The window signal is a pulse signal indicating whether edge detection is permitted or not. For example, the edge detection signal is output from the edge detection unit 31 only during a high level.
[0032]
Further, the command decode clock generation unit 40 generates a serial signal SRDT according to the edge interval signal FEI supplied from the delay unit 39 and the signal BUSY supplied from the VS control unit 49 and supplies the serial signal SRDT to the MCU 17. At this time, the MCU 17 supplies the commands SWDT, SCLK, and XLAT to the command decode clock generator 40 while monitoring the serial signal SRDT by executing the software. Then, the command decode clock generation unit 40 decodes the commands SWDT, SCLK, and XLAT supplied from the MCU 17 and generates a maximum control signal SPLT, a selection signal SEL, a command signal SCD, and a control switching signal SSW.
[0033]
Further, the VS control unit 49 receives the pulse width modulation signal supplied from the PWM circuit 47, the edge interval signal FEI supplied from the delay unit 39, the signals SPF and XWL supplied from the CLV servo circuit 13, and the phase switching unit 33. In accordance with the supplied mask set signal XMS, the edge detection signal XEG supplied from the edge detection unit 31, the maximum control signal SPLT, the selection signal SEL and the command signal SCD supplied from the command decode clock generation unit 40, the drive voltage VS. Is generated and supplied to the motor driver 10.
[0034]
Further, the VS control unit 49 turns on / off so-called soft switching control for decreasing the maximum value of the drive voltage VS at the time of phase switching in accordance with the control switching signal SSW supplied from the command decode clock generating unit 40.
[0035]
The speed calculation circuit 91 calculates the rotation speed of the motor in accordance with the edge interval signal FEI supplied from the delay unit 39. If the calculated rotation speed is smaller than a preset threshold value, the speed calculation circuit 91 is high ( H) The level automatic switching signal ASS is output, and if it is large, the low (L) level automatic switching signal ASS is output.
[0036]
FIG. 4 is a diagram showing a configuration of the delay circuit 39a included in the delay unit 39 shown in FIG. As shown in FIG. 4, the delay circuit 39a includes a selector 93, a first delay circuit 95, a second delay circuit 97, and a switching circuit SW. Here, the selector 93 is connected to the edge detection unit 31 and the interpolation edge circuit 37, and the first delay circuit 95 is connected to the edge detection unit 31. The second delay circuit 97 is connected to the edge detection unit 31 and the selector 93, the command decode clock generation unit 40, and the phase switching unit 33. The switching circuit SW includes the first delay circuit 95, the second delay circuit 97, and the command decode clock. The generator 40 and the speed calculation circuit 91 are connected. The output terminal of the switching circuit SW is connected to the phase switching unit 33.
[0037]
In the delay circuit 39a having the above-described configuration, the first delay circuit 95 generates and outputs an edge interval signal FEI according to the edge detection signal XEG supplied from the edge detection unit 31, and outputs the phase switching signal SD1. Generated and supplied to the switching circuit SW. The phase switching signal SD1 is a signal for realizing control in the first delay mode.
[0038]
On the other hand, the selector 93 is supplied with signals RISEU, RISEV, RISEW from the edge detection unit 31, and is supplied with interpolation signals IRU, IRV, IRW from the interpolation edge circuit 37, and is supplied from the interpolation edge circuit 37. Depending on the selection signal IS, any one of the signals RISEU, RISEV, RISEW or the interpolation signals IRU, IRV, IRW is selectively output as signals RU, RV, RW. The second delay circuit 97 generates a phase switching signal SD2 from the signal supplied from the selector 93 in accordance with the command signal supplied from the command decode clock generation unit 40, supplies the phase switching signal SD2 to the switching circuit SW, and delays the delay. A signal DT indicating time is generated and supplied to the command decode clock generation unit 40.
[0039]
In the above, the phase switching signal SD2 is a signal for realizing the control in the second delay mode, and the signal DT is supplied to the MCU 17 for monitoring the motor rotation speed.
[0040]
The switching circuit SW also switches the phase switching generated by the first delay circuit 95 in response to the command selection signal CSEL1 supplied from the command decode clock generation unit 40 or the automatic switching signal ASS supplied from the speed calculation circuit 91. The phase switching signal SD2 generated by the signal SD1 or the second delay circuit 97 is selectively supplied to the phase switching unit 33. More specifically, when the switching circuit SW is supplied with the low-level automatic switching signal ASS, the switching circuit SW selectively outputs the phase switching signal SD1 to execute the control in the first delay mode, When the high-level automatic switching signal ASS is supplied, the phase switching signal SD2 is selectively output so as to execute the control in the second delay mode.
[0041]
FIG. 5 is a block diagram showing a configuration of first delay circuit 95 shown in FIG. As shown in FIG. 5, the first delay circuit 95 includes a delay edge measurement counter 99, a delay calculation circuit 101, a delay counter 103, and an FG edge register 105.
[0042]
Here, the delay edge measurement counter 99 is connected to the edge detector 31, and the delay calculation circuit 101 is connected to the delay edge measurement counter 99. The delay counter 103 is connected to the delay calculation circuit 101, and the FG edge register 105 is connected to the delay edge measurement counter 99. The output terminal of the delay counter 103 is connected to the switching circuit SW, and the FG edge register 105 outputs an edge interval signal FEI.
[0043]
Hereinafter, the operation of the first delay circuit 95 will be described with reference to FIG. The delay edge measurement counter 99 loads the supplied edge detection signal XEG and measures the time interval between the edges by the counter. Then, the delay edge measurement counter 99 supplies the count result to the delay calculation circuit 101 and the FG edge register 105 as data EI.
[0044]
The FG edge register 105 stores the supplied data EI and supplies an edge interval signal FEI corresponding to the data EI to the command decode clock generation unit 40. At this time, the command decode clock generation unit 40 supplies the MCU 17 with a signal indicating the time interval between the edges, so that the MCU 17 monitors the rotational speed of the motor in accordance with the signal.
[0045]
On the other hand, the delay calculation circuit 101 calculates the delay amount between the signals CU, CV, and CW of each phase, that is, the delay times Ta, Tb, and Tc shown in FIG. 6, according to the supplied data EI. Then, the delay calculation circuit 101 determines the timing for activating the phase switching signal SD1 indicating the phase switching timing to the low level according to the supplied command selection signal CSEL2.
[0046]
That is, as shown in FIG. 6, the delay calculation circuit 101 delays Ta / 2, Tb / 2, and Tc / from the transition timing of the signals CU, CV, and CW until the phase switching signal SD1 is activated to the low level. 2 is calculated. The coefficient ½ in the above example is selected according to the command selection signal CSEL2 supplied to the delay calculation circuit 101. The delay calculation circuit 101 will be described in detail later.
[0047]
The delay counter 103 counts the delay time calculated by the delay calculation circuit 101, that is, the delay times Ta / 2, Tb / 2, and Tc / 2 in the above example, and according to the count result, FIG. ) Is generated. In the first delay mode, the phase switching signal SD1 is supplied as the signal DO to the phase switching unit 33, and the phase switching unit 33 controls switching of the logical drive signals DU, DV, DW according to the signal DO.
[0048]
FIG. 7 is a block diagram showing a configuration of the delay calculation circuit 101 shown in FIG. As shown in FIG. 7, the delay calculation circuit 101 includes first to nth multiplication circuits 111a to 111c, first to nth multiplication circuits 111a to 111c, and commands connected in parallel to the delay edge measurement counter 99. And a selection circuit 113 connected to the decode clock generation unit 40. Here, the output terminal of the selection circuit 113 is connected to the delay counter 103.
[0049]
The first multiplication circuit 111a shown in FIG. 7 shifts the data EI indicating the supplied edge time interval by 1 bit (bit shift), thereby obtaining data having a value obtained by multiplying the time interval by 1/2. This is supplied to the selection circuit 113. Similarly, the second multiplying circuit 111b shown in FIG. 7 shifts the data EI indicating the supplied time interval by 2 bits to obtain data having a value obtained by multiplying the time interval by 1/4. This is supplied to the selection circuit 113. As described above, the n-th multiplication circuit 111c supplies the selection circuit 113 with data having a value obtained by multiplying the time interval by (n / m) (where n and m are arbitrary natural numbers).
[0050]
The selection circuit 113 selectively outputs the data supplied from the first to nth multiplication circuits 111a to 111c in accordance with the command selection signal CSEL2 supplied from the command decode clock generation unit 40.
[0051]
Hereinafter, the second delay circuit 97 shown in FIG. 4 will be described. FIG. 8 is a block diagram showing a configuration of the second delay circuit 97 shown in FIG. As shown in FIG. 8, the second delay circuit 97 includes a U delay unit 107a, a V delay unit 107b, a W delay unit 107c, and a delay count unit 109, which are arranged in parallel. Here, the signal RU is supplied from the selector 93 to the U delay unit 107a, the signal RV is supplied from the selector 93 to the V delay unit 107b, and the signal RW is supplied from the selector 93 to the W delay unit 107c.
[0052]
Further, the command selection signal CSEL3 supplied from the command decode clock generation unit 40 is supplied to the U delay unit 107a, the V delay unit 107b, and the W delay unit 107c. The delay count unit 109 is connected to the U delay unit 107a, the V delay unit 107b, and the W delay unit 107c, and is supplied with signals SU, SV, and SW from the phase switching unit 33, and receives an edge detection signal from the edge detection unit 31. XEG is supplied, and a command selection signal CSEL4 is supplied from the command decode clock generator 40.
[0053]
In the second delay circuit 97 having the above-described configuration, the U delay unit 107a, the V delay unit 107b, and the W delay unit 107c are respectively connected to the rising edges of the signals CU, CV, and CW (transition from low level to high level) or The time interval of falling (transition from high level to low level) is measured, which will be described in detail later.
The delay count unit 109 selects the time interval measured by the U delay unit 107a, the V delay unit 107b, and the W delay unit 107c according to the supplied signals SU, SV, SW and the edge detection signal XEG. And count. Accordingly, the delay count unit 109 generates a phase switching signal SD2 indicating the phase switching timing according to the count result, supplies the phase switching signal SD2 to the switching circuit SW, and outputs the signal DT indicating the time interval. The delay count unit 109 will be described later.
[0054]
FIG. 9 is a diagram illustrating a configuration of the U delay unit 107a illustrated in FIG. Note that the V delay unit 107b and the W delay unit 107c illustrated in FIG. 8 have the same configuration as the U delay unit 107a illustrated in FIG.
[0055]
As shown in FIG. 9, the U delay unit 107 a includes a counter 115, a selector 117, an edge measurement counter 119, and a register 121. Here, the counter 115 is connected to the selector 93, and the selector 117 is connected to the counter 115, the selector 93 and the command decode clock generator 40. The edge measurement counter 119 is connected to the selector 117, and the register 121 is connected to the edge measurement counter 119 and the selector 117.
[0056]
In the U delay unit 107a having the above-described configuration, the counter 115 supplies the activated signal ARU to the selector 117 every time two edges of the supplied signal RU are detected, for example. On the other hand, the selector 117 selectively outputs a signal RU or a signal ARU according to the supplied command selection signal CSEL3.
[0057]
The edge measurement counter 119 measures the edge time interval according to the supplied signal. When the signal RU is supplied, the one cycle Tun of the signal CU and the signal ARU shown in FIG. Is supplied, the time of two periods of the signal CU is measured.
[0058]
The register 121 stores a signal indicating the measurement result supplied from the edge measurement counter 119 and supplies a signal UET indicating the cycle of the signal CU to the delay count unit 109. Similarly, a signal VET indicating the cycle of the signal CV is supplied from the V delay unit 107b to the delay count unit 109, and a signal WET indicating the cycle of the signal CW is supplied from the W delay unit 107c.
[0059]
FIG. 10 is a block diagram showing a configuration of phase switching signal generation circuit 109a included in delay count unit 109 shown in FIG. As shown in FIG. 10, the phase switching signal generation circuit 109 a includes a decoder 123, selection circuits 125 and 129, first to nth multiplication circuits 127 a to 127 c, and a delay counter 131.
[0060]
Here, the decoder 123 is connected to the phase switching circuit 33 and the edge detection unit 31, and the selection circuit 125 is connected to the U delay unit 107 a, the V delay unit 107 b and the W delay unit 107 c, and the decoder 123. The first to nth multiplication circuits 127 a to 127 c are connected in parallel to the selection circuit 125, and the selection circuit 129 is connected to these first to nth multiplication circuits 127 a to 127 c and the command decode clock generation unit 40. . The delay counter 131 is connected to the selection circuit 129.
[0061]
In the above, the decoder 123 decodes the supplied signals SU, SV, SW and the edge detection signal XEG, and supplies the obtained decoded signal to the selection circuit 125. At this time, the selection circuit 125 selectively outputs one of the signal UET, the signal VET, and the signal WET according to the supplied decode signal.
[0062]
The first multiplication circuit 127a multiplies the data supplied from the selection circuit 125 by 1 bit to multiply the data by 1/2, and supplies the multiplication result to the selection circuit 129. The first multiplication circuit 127 b shifts the data supplied from the selection circuit 125 by 2 bits, multiplies the data by ¼, and supplies the multiplication result to the selection circuit 129. The n-th multiplier circuit 127c multiplies the data supplied from the selection circuit 125 by n bits or the like to multiply the data by (q / p) (where p and q are arbitrary natural numbers). The result is supplied to the selection circuit 129.
[0063]
The selection circuit 129 selectively supplies the multiplication results supplied from the first to n-th multiplication circuits 127 a to 127 c to the delay counter 131 in accordance with the command selection signal CSEL 4 supplied from the command decode clock generation unit 40. . At this time, the delay counter 131 counts the time indicated by the signal supplied from the selection circuit 129, thereby generating the phase switching signal SD2 that is activated to a low level at a predetermined timing.
[0064]
Here, as an example, by using the multiplication results of the first to n-th multiplier circuits 127a to 127c, the respective cycles Tun, Tvn, FIG. 11D shows the phase switching signal SD2 activated to the low level at a timing delayed by a time corresponding to 1/12 of Twn.
[0065]
As described above, the disk drive device according to the embodiment of the present invention includes the first delay circuit 95 that generates the phase switching signal SD1 necessary for controlling the motor in the first delay mode, and the motor in the second delay mode. A second delay circuit 97 that generates a phase switching signal SD2 necessary for control is provided, and an automatic switching signal ASS output from the speed calculation circuit 91 or a command selection signal CSEL1 corresponding to a command issued from the MCU 17 The phase switching signals SD1 and SD2 can be selectively supplied to the phase switching unit 33.
[0066]
That is, as shown in FIG. 12, the edge interval Tuv of the signals CU and CV shown in FIGS. 12 (a) and 12 (b) is set in advance by increasing the rotational speed of the motor. At time Tcr when the value is smaller than the value, the speed calculation circuit 91 changes the logic level of the automatic switching signal ASS to be output from the high level to the low level, as shown in FIG.
[0067]
Thus, as shown in FIG. 12E, a signal DO for phase switching is generated in the second delay mode until time Tcr, and a signal DO is generated in the first delay mode after time Tcr. .
[0068]
Therefore, when the spindle motor 3 is rotating at a speed slower than a preset rotation speed, the spindle motor 3 is controlled in the second delay mode in order to reduce the influence of the interphase offset variation. When rotating at a speed faster than the preset rotational speed, the spindle motor 3 is controlled in the first delay mode in order to detect the rotational position information of the motor at a high speed.
[0069]
On the other hand, the MCU 17 issues a command corresponding to the rotational speed of the spindle motor 3 to the motor controller 15 so that the spindle motor 3 can be optimally controlled according to the rotational speed.
[0070]
As described above, according to the disk drive device according to the embodiment of the present invention, it is possible to reduce defects in the rotation control of the motor due to process variations of the motor driver 10 that occur during mass production, and to increase the yield. .
[0071]
Further, when the motor rotation speed is high or when the motor rotation speed is suddenly accelerated or decelerated, the spindle motor 3 is controlled in the first delay mode as described above. By detecting, more accurate control can be realized.
[0072]
Moreover, since the motor control mode can be switched by the command issued from the MCU 17 as described above, the delay mode can be easily changed by using software.
[0073]
Furthermore, according to the disk drive device according to the embodiment of the present invention, the speed calculation circuit 91 can automatically switch the mode by generating the automatic switching signal ASS corresponding to the rotational speed of the motor. The execution load of software in the MPU 17 can be reduced, and the size of the ROM and RAM for storing the software after being encoded can be reduced, so that the cost can be reduced.
[0074]
Further, since the speed calculation circuit 91 for switching the delay mode is realized by a digital circuit provided in the system LSI 20, it is possible to easily achieve high integration, and also from this point, the cost can be suppressed. it can.
[0075]
【The invention's effect】
According to the disk drive device of the present invention, the motor can be driven by the first timing signal or the second timing signal according to the rotation speed, so that optimal control can be realized regardless of the rotation state of the motor. The reliability of the drive device can be increased.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a disk drive device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a circuit included in the motor driver shown in FIG. 1;
FIG. 3 is a block diagram showing a configuration of a motor controller shown in FIG. 1;
4 is a diagram illustrating a configuration of a delay circuit included in the delay unit illustrated in FIG. 3;
FIG. 5 is a block diagram showing a configuration of a first delay circuit shown in FIG. 4;
6 is a timing chart showing an operation of the first delay circuit shown in FIG. 5. FIG.
7 is a block diagram showing a configuration of a delay calculation circuit shown in FIG. 5. FIG.
8 is a block diagram showing a configuration of a second delay circuit shown in FIG. 4. FIG.
9 is a block diagram showing a configuration of a U delay unit shown in FIG.
10 is a block diagram showing a configuration of a phase switching signal generation circuit included in the delay count unit shown in FIG. 8. FIG.
11 is a timing chart showing an operation of the second delay circuit shown in FIG.
FIG. 12 is a timing chart showing the operation of the disk drive device shown in FIG. 1;
[Explanation of symbols]
1 disk, 3 spindle motor, 5 reading unit, 7 pickup, 9 element unit, 10 motor driver, 10a driver unit, 11 RF amplifier, 13 CLV servo circuit, 15 motor controller, 17 MCU (microcomputer unit), 20 system LSI , 21 Headphone amplifier, 23 Three-phase control unit, 25 Pre-driver, 27 Comparator, 31 Edge detection unit, 33-phase switching unit, 35 Drive logic / brake logic circuit, 37 Interpolation edge circuit, 39 Delay unit, 39a Delay circuit, 40 command decode clock generation unit, 41 mask limiter circuit, 43 window unit, 45 start circuit, 47 PWM circuit, 49 VS control unit, 91 speed calculation circuit, 93, 117 selector, 95 first delay circuit, 97 second delay Circuit, 99 de Delay measurement circuit, 101 delay calculation circuit, 103, 131 delay counter, 105 FG edge counter, 107a U delay unit, 107b V delay unit, 107c W delay unit, 109 delay count unit, 109a phase switching signal generation circuit, 111a , 127a First multiplication circuit, 111b, 127b Second multiplication circuit, 111c, 127c nth multiplication circuit, 113, 125, 129 selection circuit, 115 counter, 119 edge measurement counter, 121 register, 123 decoder, NT1 to NT6 N channel MOS transistor, TPM motor, SW switching circuit, N1-N3 intermediate node, Vcc power supply voltage node, CP midpoint.

Claims (3)

A disk drive device including drive means for driving a mounted disk by controlling a motor with a signal indicating phase switching timing,
First timing signal generating means for generating a first timing signal for determining a phase switching timing of the motor according to a phase difference of a plurality of drive signals for driving the motor;
Including period measuring means for selectively measuring an N period or an M period (N and M are different natural numbers) of any one of the drive signals in accordance with the supplied selection signal, and the period measured by the period measuring means Second timing signal generating means for generating a second timing signal for determining the phase switching timing of the motor every N cycles or M cycles ;
A disk drive device comprising: motor control means for selectively supplying the first timing signal or the second timing signal to the drive means in accordance with the rotational speed of the motor.   The apparatus further comprises speed calculating means for calculating a rotation speed of the motor according to the drive signal and generating a selection signal according to the calculated rotation speed, wherein the motor control means is generated by the speed calculation means. 2. The disk drive device according to claim 1, wherein the first timing signal or the second timing signal is selectively supplied to the driving unit in accordance with the selection signal.   2. The disk drive device according to claim 1, wherein the motor control means selectively supplies the first timing signal or the second timing signal to the drive means in accordance with a control signal supplied from outside.

Images