JP3694469B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3694469B2
JP3694469B2 JP2001158773A JP2001158773A JP3694469B2 JP 3694469 B2 JP3694469 B2 JP 3694469B2 JP 2001158773 A JP2001158773 A JP 2001158773A JP 2001158773 A JP2001158773 A JP 2001158773A JP 3694469 B2 JP3694469 B2 JP 3694469B2
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Prior art keywords
resin
semiconductor
thickness
semiconductor element
wafer
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JP2002016092A (en
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伸仁 大内
康雄 田中
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【０００１】
【産業上の利用分野】
本発明は、半導体装置の製造方法に関わるものである。
【０００２】
【従来の技術】
近年、半導体装置の高密度実装が進み、チップサイズパッケージ等の半導体装置が注目を集めている。このようなチップサイズパッケージ構造の半導体装置の一例として、特願平１１−１０２５９９号には、半導体素子と実装基板との熱膨張係数の差によって、半導体装置と実装基板との接合部にクラックが生じてしまうという問題を解決するために半導体素子の厚さを２００μｍ以下とし、半導体素子に対する樹脂の割合を大きくしている。また、特開平８―６４７２５号には、チップサイズパッケージに於て、半導体素子の回路形成面及び回路形成面と反対側の面に封止樹脂を形成し、ウエハの反りを防止することについて開示されている。
【０００３】
【発明が解決しようとする課題】
上記の通り最近のチップサイズパッケージ構造の半導体装置では、半導体素子と実装基板との接合部のクラックを防止するために、半導体素子の厚さを薄くして半導体素子に対する樹脂の割合を大きくする方向にある。
【０００４】
しかしながら半導体素子の厚さを２００μｍ以下に薄くして樹脂の厚さに対する半導体素子の厚さの割合を小さくしてしまうと、半導体素子の回路形成面側にしか樹脂が形成されていない場合、ウエハを分割することによって得られる個々の半導体素子に於ても反りが生じてしまう。
【０００５】
この様に半導体素子に反りがあると、実装基板に半導体装置の実装が良好に行えなくなってしまうという問題が生じる。
【０００６】
また特開平８―６４７２５号のように、半導体ウエハ裏面を研削した後、樹脂封止する場合、ウエハの厚さが２００μｍ以下の場合、ウエハの搬送時にウエハに破損が生じてしまうという問題がある。
【０００７】
本発明の目的は、厚さが２００μｍ以下の半導体素子を有するチップサイズパッケージ構造の半導体装置に於て、実装基板への実装を良好に行うことのできる半導体装置を提供することにある。
【０００８】
また本発明の別の目的は、半導体素子の両面に封止樹脂が形成されたチップサイズパッケージ構造の半導体装置の製造方法に関し、特に半導体素子の厚さが２００μｍ以下といった薄い半導体装置の製造方法を提供することにある。
【０００９】
【課題を解決するための手段】
上記課題を解決するために、本発明の半導体装置の製造方法は、以下のような工程を備えている。すなわち、表面及び裏面を有し、半導体集積回路が形成された複数の半導体素子を有する半導体ウエハを準備する工程と、半導体集積回路に接続される複数の電極を半導体ウエハの表面に形成する工程と、複数の電極の上面を露出するように半導体ウエハの表面上に第１の樹脂を形成する工程と、半導体ウエハの裏面を研磨することによって、半導体ウエハの厚さを２００μｍ以下の厚さにする工程と、半導体ウエハの裏面上に第２の樹脂を形成する工程であって、第１の樹脂の厚さをＡ、第２の樹脂の厚さをＢとした場合、０．２≦Ｂ／Ａ≦１を満たすように第２の樹脂を形成する工程と、第１及び第２の樹脂が形成された複数の半導体素子を取り出す工程とを備えている。
【００１０】
【発明の実施の形態】
図１は本発明の第１の実施の形態における半導体装置の構造を示す図である。以下図１を用いて本発明の第１の実施の形態について説明する。半導体素子１は２００μｍ以下、ここでは１５０μｍの厚さを有している。半導体素子１の主面（回路形成面）上には所定箇所にアルミ電極パッド２が形成されている。また半導体素子１の主面上には、導電性の突起電極、例えば銅のポスト３が形成されている。ポスト３の高さは１００μｍである。またポスト３はアルミ電極パッド２に銅の配線７を介して電気的に接続している。
【００１１】
半導体素子１の主面及びポスト３は、ポスト３の上面を露出させて樹脂４によって封止されている。樹脂４の厚さはポスト３と同様１００μｍである。ここで樹脂４の厚さを１００μｍと厚く形成するのは、実装基板に半導体装置を実装する際、樹脂によって半導体素子に加わるストレスを緩和するためや半導体素子に傷が生じるのを防ぐためである。樹脂４の表面に露出したポスト３の上に半田などによるバンプ電極５が形成されている。半導体素子１の主面の反対側の裏面は樹脂６によって封止されている。樹脂６の厚さは樹脂４と同様１００μｍである。
【００１２】
図７は本発明の第２の実施の形態の半導体装置の構造を示す図である。図１と同一構成要素には同一符号を付与し説明を省略する。図７では樹脂４の厚さは１００μｍであり、樹脂６の厚さは１００μｍである。この実施の形態ではバンプ電極を形成しないものである。
【００１３】
図２は、主面及び裏面の両面上に封止樹脂を形成した半導体素子の反り量を示した図である。図２の横軸は半導体素子主面上の樹脂と裏面上の樹脂との樹脂膜厚の比を示している。図２の縦軸は半導体素子の単位長さ当たりの反り量を示している。
【００１４】
図２のグラフに於て、半導体素子の厚さは１５０μｍであり、樹脂膜厚比が０のとき、半導体素子の主面側に形成される樹脂は１００μｍであり、半導体素子裏面側に形成される樹脂は０μｍである。そして、徐々に裏面樹脂厚を増していき、樹脂膜厚比が１．０のとき、半導体素子の主面側に形成される樹脂と半導体素子裏面側に形成される樹脂とは同一の厚さを有するものとなる。
【００１５】
図２を参照すると半導体素子主面上の樹脂と裏面上の樹脂との樹脂厚の差を大きくすると半導体素子の反りが大きくなってくるのが分かる。
【００１６】
ここで半導体素子の主面上に形成される樹脂厚をＡとし、裏面上に形成される樹脂厚をＢとすると、０．２≦Ｂ／Ａ ≦１．０のときは半導体素子の反り量が１．５μｍ／ｍｍより小さく、この程度の反り量では半導体装置を実装基板に実装するは比較的容易である。
【００１７】
図２を参照するとＢ／Ａが０．２より小さくなると急激に半導体素子の反り量が増大しているのが分かる。
【００１８】
ここで１．５μｍ／ｍｍを超えた半導体素子の反り量になると、半導体装置を実装基板に実装するに際し、半導体装置のバンプのいずれかが実装基板に接触しなくなり、半導体装置と実装基板との良好な接合ができなくなってしまう、または、実装基板からのバンプの高さが異なることにより、接合部の抵抗に違いが生じてしまう。
【００１９】
図３及び図４は本発明の第１又は第２の実施の形態の半導体装置の製造方法を示す図である。
【００２０】
図３及び図４を用いて第１の実施の形態の半導体装置の製造方法について説明する。
【００２１】
まず半導体ウエハ３０の主面（回路形成面）上に電気メッキ等により、高さ約１００μｍのＣｕのポスト３１を形成する（図３―Ａ）。このポスト３１はウエハ３０上に形成された電極パッド（図示していない）に電気的に接続されている。
【００２２】
その後、半導体ウエハ３０の主面及びポスト３１を封止するため樹脂３２を充填する（図３―Ｂ）。樹脂充填の方法はトランスファーモールド法、ポッテイング法、印刷法等で行う。
【００２３】
この段階の半導体ウエハ３０は、樹脂３２の応力などによって反りが生じないような十分な厚さを持っているものとする。
【００２４】
次に樹脂３２に埋もれてしまっているポスト３１の上面が露出し、樹脂３２及びポスト３１の高さが１００μｍとなるまで、研磨刃３３によって樹脂３２の表面を研磨する。（図３―Ｃ）その後、高速回転する外周刃３４によって、樹脂３２を充填した面から溝３５を形成する。この溝は後に個々の半導体装置に分割する部分に形成される。
【００２５】
この溝３５の深さは以下のように決定される。本実施の形態では半導体素子１の厚さを１５０μｍとするので、半導体ウエハ３０の部分には１５０μｍ以上の溝を形成する。この実施の形態では半導体ウエハ３０部分に２００μｍの溝を形成する。この工程で形成される溝３５の樹脂表面から底部までの深さは、樹脂厚＋ウエハの溝の深さで１００＋２００＝３００μｍとなる（図３―Ｄ）。
【００２６】
その後、基板の樹脂形成面に研削テープ３６を貼付する。この研削テープは紫外線を照射することによって、粘着力が落ち、簡単に剥がせるものである。
【００２７】
研削テープ３６を研削ステージ（図示していない）に固定する（図４―Ａ）。研削ステージに固定した状態でウエハ３０の裏面側の全面を研磨する。この研磨は前工程で形成した溝３５の底部を超えて、ウエハ３０の厚さが１５０μｍになるまで行う。
【００２８】
ウエハ３０の裏面の研磨を溝の底部を超えて行うことで、半導体ウエハは個々に分割される。つまり研削テープ３６の上に個々に分割された半導体素子３７が並ぶ状態となる（図４―Ｂ）。
【００２９】
さらに、半導体素子の裏面上に樹脂３８を形成する。樹脂の形成方法はトランスファーモールド法、ポッテイング法、印刷法の他、テープ状のポリイミド樹脂やエポキシ樹脂を貼付するという方法がある。（図４―Ｃ）
ここで研削テープ３６は封止後のキュア温度に絶えられるものを用いる。
【００３０】
また図５に示されるような回路形成面側の樹脂封止時における、半導体素子と主面面側の樹脂３２との総厚と、図６に示されるような半導体素子裏面側の樹脂封止時における、半導体素子と主面側の樹脂３２と裏面側の樹脂３８と研削テープ３６との総厚とを等しくすることで、トランスファーモールド法により、樹脂３２及び樹脂３８を形成する場合、同じ封止金型及び同一封止条件で封止を行うことができる。
【００３１】
その後、樹脂３８にマウントテープ３９が貼られ、研削テープが除去された後、高速回転する外周刃３４によって、先の溝３５に対応する樹脂３８部分をスクライブする。（図４−Ｄ）
その後、後工程へと供給される。
【００３２】
後工程では必要に応じて、ポスト３１上にバンプ電極などが形成される。
【００３３】
本実施の形態では、まず十分に厚いウエハを樹脂で封止する。この段階ではウエハに反りなどが生じる恐れはない。その後、樹脂側からウエハに溝を形成する。この溝の底部を超えてウエハの裏面を全面研磨して個々に分離する。よってウエハの固定時の反りの問題などが解消できる。
【００３４】
また半導体ウエハ上に樹脂を形成した後、ウエハを研削することによって個々の半導体素子に分割しているので、樹脂が形成されていない薄い半導体ウエハを搬送することによって半導体ウエハに破損が生じてしまうという問題を除去できる。これによって本発明の製造方法では、従来よりも半導体体素子の厚さを薄くした半導体装置の提供が可能となる。
【００３５】
また最終的に半導体素子が薄くなっても、半導体素子裏面にも樹脂が形成されるので、半導体装置を実装基板に実装する場合にも、半導体装置に反りがないので良好な実装を行うことができる。
【００３６】
【発明の効果】
本発明の半導体装置の製造方法によれば、実装基板への実装を良好に行うことのできる半導体装置を製造することができる。
【図面の簡単な説明】
【図１】本発明の第１実施の形態の半導体装置の構造を示す図
【図２】半導体素子の反り量を示す図
【図３】本発明の第１又は第２の実施の形態の半導体装置の製造方法を示す図
【図４】本発明の第１又は第２の実施の形態の半導体装置の製造方法を示す図
【図５】主面樹脂封止時の半導体装置の構造を示す図
【図６】裏面樹脂封止時の半導体装置の構造を示す図
【図７】本発明の第２の実施の形態の半導体装置の構造を示す図
【符号の説明】
１…半導体素子
２…電極パッド
３…ポスト
４、６…樹脂
７…配線[0001]
[Industrial application fields]
The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
In recent years, high-density mounting of semiconductor devices has progressed, and semiconductor devices such as chip size packages have attracted attention. As an example of a semiconductor device having such a chip size package structure, Japanese Patent Application No. 11-102599 discloses a crack in a joint portion between a semiconductor device and a mounting substrate due to a difference in thermal expansion coefficient between the semiconductor element and the mounting substrate. In order to solve this problem, the thickness of the semiconductor element is set to 200 μm or less, and the ratio of the resin to the semiconductor element is increased. Japanese Patent Application Laid-Open No. 8-64725 discloses that in a chip size package, a sealing resin is formed on a circuit forming surface of a semiconductor element and a surface opposite to the circuit forming surface to prevent warping of the wafer. Has been.
[0003]
[Problems to be solved by the invention]
As described above, in a recent semiconductor device having a chip size package structure, in order to prevent cracks at the junction between the semiconductor element and the mounting substrate, the thickness of the semiconductor element is reduced and the ratio of the resin to the semiconductor element is increased. It is in.
[0004]
However, if the thickness of the semiconductor element is reduced to 200 μm or less and the ratio of the thickness of the semiconductor element to the resin thickness is reduced, the resin is formed only on the circuit forming surface side of the semiconductor element. Warpage also occurs in individual semiconductor elements obtained by dividing.
[0005]
When the semiconductor element is warped in this manner, there arises a problem that the semiconductor device cannot be satisfactorily mounted on the mounting substrate.
[0006]
Also, as disclosed in JP-A-8-64725, there is a problem that when the semiconductor wafer is ground and then resin-sealed, if the wafer thickness is 200 μm or less, the wafer is damaged when the wafer is transferred. .
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a chip size package structure having a semiconductor element having a thickness of 200 μm or less, which can be satisfactorily mounted on a mounting substrate.
[0008]
Another object of the present invention relates to a method for manufacturing a semiconductor device having a chip size package structure in which a sealing resin is formed on both sides of the semiconductor element, and more particularly, to a method for manufacturing a thin semiconductor device having a thickness of 200 μm or less. It is to provide.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a method for manufacturing a semiconductor device of the present invention includes the following steps. A step of preparing a semiconductor wafer having a plurality of semiconductor elements each having a front surface and a back surface and having a semiconductor integrated circuit formed thereon; and a step of forming a plurality of electrodes connected to the semiconductor integrated circuit on the surface of the semiconductor wafer. The step of forming the first resin on the surface of the semiconductor wafer so as to expose the upper surfaces of the plurality of electrodes, and polishing the back surface of the semiconductor wafer, thereby reducing the thickness of the semiconductor wafer to 200 μm or less. And a step of forming a second resin on the back surface of the semiconductor wafer, where the thickness of the first resin is A and the thickness of the second resin is B, 0.2 ≦ B / A step of forming a second resin so as to satisfy A ≦ 1, and a step of taking out a plurality of semiconductor elements on which the first and second resins are formed .
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a structure of a semiconductor device according to the first embodiment of the present invention. Hereinafter, a first embodiment of the present invention will be described with reference to FIG. The semiconductor element 1 has a thickness of 200 μm or less, here 150 μm. On the main surface (circuit formation surface) of the semiconductor element 1, aluminum electrode pads 2 are formed at predetermined positions. On the main surface of the semiconductor element 1, a conductive protruding electrode, for example, a copper post 3 is formed. The height of the post 3 is 100 μm. The post 3 is electrically connected to the aluminum electrode pad 2 through a copper wiring 7.
[0011]
The main surface of the semiconductor element 1 and the post 3 are sealed with a resin 4 with the upper surface of the post 3 exposed. The thickness of the resin 4 is 100 μm like the post 3. The reason why the thickness of the resin 4 is formed as thick as 100 μm is to relieve stress applied to the semiconductor element by the resin and prevent the semiconductor element from being damaged when the semiconductor device is mounted on the mounting substrate. . A bump electrode 5 made of solder or the like is formed on the post 3 exposed on the surface of the resin 4. The back surface opposite to the main surface of the semiconductor element 1 is sealed with a resin 6. The thickness of the resin 6 is 100 μm like the resin 4.
[0012]
FIG. 7 is a diagram showing the structure of the semiconductor device according to the second embodiment of the present invention. The same components as those in FIG. In FIG. 7, the thickness of the resin 4 is 100 μm, and the thickness of the resin 6 is 100 μm. In this embodiment, bump electrodes are not formed.
[0013]
FIG. 2 is a diagram showing the amount of warpage of a semiconductor element in which a sealing resin is formed on both the main surface and the back surface. The horizontal axis in FIG. 2 indicates the ratio of the resin film thickness between the resin on the main surface of the semiconductor element and the resin on the back surface. The vertical axis in FIG. 2 indicates the amount of warpage per unit length of the semiconductor element.
[0014]
In the graph of FIG. 2, when the thickness of the semiconductor element is 150 μm and the resin film thickness ratio is 0, the resin formed on the main surface side of the semiconductor element is 100 μm and formed on the back surface side of the semiconductor element. The resin used is 0 μm. Then, the thickness of the back surface resin is gradually increased. When the resin film thickness ratio is 1.0, the resin formed on the main surface side of the semiconductor element and the resin formed on the back surface side of the semiconductor element have the same thickness. It will have.
[0015]
Referring to FIG. 2, it can be seen that the warpage of the semiconductor element increases as the difference in resin thickness between the resin on the main surface of the semiconductor element and the resin on the back surface increases.
[0016]
Here, when the resin thickness formed on the main surface of the semiconductor element is A and the resin thickness formed on the back surface is B, when 0.2 ≦ B / A ≦ 1.0, the warping amount of the semiconductor element Is less than 1.5 μm / mm, and it is relatively easy to mount the semiconductor device on the mounting substrate with this amount of warpage.
[0017]
Referring to FIG. 2, it can be seen that when B / A is smaller than 0.2, the amount of warpage of the semiconductor element increases rapidly.
[0018]
Here, when the warp amount of the semiconductor element exceeds 1.5 μm / mm, when the semiconductor device is mounted on the mounting substrate, any of the bumps of the semiconductor device does not contact the mounting substrate, and the semiconductor device and the mounting substrate A good bonding cannot be performed, or the bump heights from the mounting substrate are different, which causes a difference in the resistance of the bonding portion.
[0019]
3 and 4 are views showing a method of manufacturing the semiconductor device according to the first or second embodiment of the present invention.
[0020]
A method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.
[0021]
First, a Cu post 31 having a height of about 100 μm is formed on the main surface (circuit formation surface) of the semiconductor wafer 30 by electroplating or the like (FIG. 3A). The post 31 is electrically connected to an electrode pad (not shown) formed on the wafer 30.
[0022]
Thereafter, a resin 32 is filled to seal the main surface of the semiconductor wafer 30 and the post 31 (FIG. 3-B). The resin filling method is a transfer molding method, a potting method, a printing method, or the like.
[0023]
It is assumed that the semiconductor wafer 30 at this stage has a sufficient thickness so as not to be warped due to the stress of the resin 32 or the like.
[0024]
Next, the surface of the resin 32 is polished by the polishing blade 33 until the upper surface of the post 31 buried in the resin 32 is exposed and the height of the resin 32 and the post 31 becomes 100 μm. (FIG. 3C) Thereafter, the groove 35 is formed from the surface filled with the resin 32 by the outer peripheral blade 34 rotating at high speed. This groove is formed in a portion that is later divided into individual semiconductor devices.
[0025]
The depth of the groove 35 is determined as follows. In this embodiment, since the thickness of the semiconductor element 1 is 150 μm, a groove of 150 μm or more is formed in the semiconductor wafer 30. In this embodiment, a 200 μm groove is formed in the semiconductor wafer 30 portion. The depth from the resin surface to the bottom of the groove 35 formed in this step is 100 + 200 = 300 μm as the resin thickness + the groove depth of the wafer (FIG. 3-D).
[0026]
Thereafter, a grinding tape 36 is attached to the resin-formed surface of the substrate. This grinding tape can be easily peeled off by irradiating it with ultraviolet rays.
[0027]
The grinding tape 36 is fixed to a grinding stage (not shown) (FIG. 4-A). The entire back side of the wafer 30 is polished while being fixed to the grinding stage. This polishing is performed until the thickness of the wafer 30 reaches 150 μm beyond the bottom of the groove 35 formed in the previous step.
[0028]
By polishing the back surface of the wafer 30 beyond the bottom of the groove, the semiconductor wafer is divided into individual pieces. That is, the individual semiconductor elements 37 are arranged on the grinding tape 36 (FIG. 4-B).
[0029]
Further, a resin 38 is formed on the back surface of the semiconductor element. In addition to the transfer molding method, the potting method, and the printing method, the resin can be formed by attaching a tape-like polyimide resin or epoxy resin. (Fig. 4-C)
Here, as the grinding tape 36, one that can withstand the curing temperature after sealing is used.
[0030]
Also, the total thickness of the semiconductor element and the resin 32 on the main surface side during resin sealing on the circuit forming surface side as shown in FIG. 5, and the resin sealing on the back surface side of the semiconductor element as shown in FIG. When the resin 32 and the resin 38 are formed by the transfer molding method by equalizing the total thickness of the semiconductor element, the resin 32 on the main surface side, the resin 38 on the back surface side, and the grinding tape 36 at the same time, Sealing can be performed with a stationary die and the same sealing conditions.
[0031]
Thereafter, the mount tape 39 is affixed to the resin 38 and the grinding tape is removed, and then the portion of the resin 38 corresponding to the previous groove 35 is scribed by the outer peripheral blade 34 that rotates at high speed. (Fig. 4-D)
Then, it is supplied to a subsequent process.
[0032]
In the post process, a bump electrode or the like is formed on the post 31 as necessary.
[0033]
In the present embodiment, a sufficiently thick wafer is first sealed with resin. At this stage, there is no risk of warping of the wafer. Thereafter, grooves are formed in the wafer from the resin side. The entire back surface of the wafer is polished beyond the bottom of the groove and separated individually. Therefore, the problem of warping when the wafer is fixed can be solved.
[0034]
In addition, since the resin is formed on the semiconductor wafer and then divided into individual semiconductor elements by grinding the wafer, the semiconductor wafer is damaged by transporting the thin semiconductor wafer on which the resin is not formed. Can be eliminated. Thus, in the manufacturing method of the present invention, it is possible to provide a semiconductor device in which the thickness of the semiconductor body element is made thinner than before.
[0035]
In addition, even if the semiconductor element eventually becomes thin, resin is also formed on the back surface of the semiconductor element. Therefore, even when the semiconductor device is mounted on a mounting substrate, the semiconductor device does not warp, so that good mounting can be performed. it can.
[0036]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device that can be favorably mounted on a mounting substrate can be manufactured.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a warp amount of a semiconductor element. FIG. 3 is a semiconductor according to the first or second embodiment of the present invention. The figure which shows the manufacturing method of an apparatus. FIG. 4 is the figure which shows the manufacturing method of the semiconductor device of the 1st or 2nd embodiment of this invention. FIG. FIG. 6 is a diagram showing a structure of a semiconductor device when a back surface resin is sealed. FIG. 7 is a diagram showing a structure of a semiconductor device according to a second embodiment of the present invention.
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 2 ... Electrode pad 3 ... Post 4, 6 ... Resin 7 ... Wiring

Claims (1)

表面及び裏面を有し、半導体集積回路が形成された複数の半導体素子を有する半導体ウエハを準備する工程と、Preparing a semiconductor wafer having a plurality of semiconductor elements each having a front surface and a back surface and having a semiconductor integrated circuit formed thereon;
前記半導体集積回路に接続される複数の電極を前記半導体ウエハの表面に形成する工程と、Forming a plurality of electrodes connected to the semiconductor integrated circuit on the surface of the semiconductor wafer;
前記複数の電極の上面を露出するように前記半導体ウエハの表面上に第１の樹脂を形成する工程と、Forming a first resin on the surface of the semiconductor wafer so as to expose the upper surfaces of the plurality of electrodes;
前記半導体ウエハの裏面を研磨することによって、前記半導体ウエハの厚さを２００μｍ以下の厚さにする工程と、Polishing the back surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer to 200 μm or less;
前記半導体ウエハの裏面上に第２の樹脂を形成する工程であって、前記第１の樹脂の厚さをＡ、前記第２の樹脂の厚さをＢとした場合、０．２≦Ｂ／Ａ≦１を満たすように前記第２の樹脂を形成する工程と、A step of forming a second resin on the back surface of the semiconductor wafer, where the thickness of the first resin is A and the thickness of the second resin is B, 0.2 ≦ B / Forming the second resin so as to satisfy A ≦ 1,
前記第１及び第２の樹脂が形成された前記複数の半導体素子を取り出す工程とを備えたことを特徴とする半導体装置の製造方法。And a step of taking out the plurality of semiconductor elements on which the first and second resins are formed.
JP2001158773A 2001-05-28 2001-05-28 Manufacturing method of semiconductor device Expired - Fee Related JP3694469B2 (en)

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