JP3686480B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a TLB (Translation Lookaside Buffer) mounted on a microprocessor LSI or an associative memory device (hereinafter simply referred to as CAM) used for a cache memory, and a differential amplifier circuit suitable for the same.
[0002]
[Prior art]
Recent microprocessor LSIs are equipped with a TLB (Translation Lookaside Buffer) or a cache memory, which is composed of a CAM (Content Addressable Memory). For example, the TLB includes a CAM unit that stores a plurality of virtual addresses specified by a program and a RAM unit that stores an address conversion result (real address) for those virtual addresses, and requires address conversion for the virtual addresses. When the virtual address matching the virtual address is stored in the CAM unit with reference to the TLB, the converted real address for the virtual address is output from the RAM unit. This eliminates the need for repeated address translation.
[0003]
For TLB, the full associative method and the set associative method are mainly used. A typical TLB of the conventional full associative method checks a match between an input virtual address and each of a plurality of virtual addresses stored in the CAM section in the TLB, and among the stored virtual addresses. When there is a virtual address that matches the input virtual address, the real address stored in the RAM unit corresponding to the matched virtual address is output. In this way, a typical TLB of the conventional full associative method compares all virtual addresses stored in the CAM unit with the input virtual addresses.
[0004]
Therefore, such a TLB has a large number of coincidence detection circuits for performing the above comparison, and accordingly, the circuit area of the TLB increases, power consumption increases. In the above comparison, in the CAM unit The data (in this case, the virtual address) stored there is not read outside the CAM unit, so the reliability of the data stored in the CAM unit can be confirmed. The failure of failure diagnosis of the CAM device is a drawback. Further, in order to suppress an increase in circuit area, a simple coincidence detection circuit is used for the comparison, and the operation speed is often considered secondarily. For this reason, it takes a long time to compare data (in this case, a virtual address). However, since all stored data are compared, there is an advantage that the data matching probability is higher than the set associative TLB.
[0005]
As a conventional technique for speeding up the comparison of the full associative TLB, it has also been proposed to provide a coincidence detection circuit for comparing search data and stored data for each memory cell of the CAM unit ( JP-A-59-231789). However, this technique has a problem that the total number of coincidence detection circuits increases.
[0006]
A technique for speeding up the coincidence detection circuit is disclosed in IEEE Journal of Solid-State Circuits vol. 28, no. 11 pp. 1078-1083 (1993). In this prior art, for high-speed coincidence detection, in addition to the coincidence detection signal line, a reference signal line is provided in parallel with the coincidence detection signal line, and the voltage supply signal line is also in parallel with the coincidence detection signal line. A coincidence detection MOSFET constitutes a differential NOR circuit. Although this conventional TLB operates at high speed, the number of wires is three compared to the conventional TLB, which is one. Therefore, the circuit area is large.
[0007]
[Problems to be solved by the invention]
As described above, the conventional CAM has room for improvement in the operation speed of the coincidence detection circuit, the circuit area of the CAM unit, and the power consumption. As a technique for solving these problems, the present applicant has proposed an improved CAM suitable for TLB in Japanese Patent Application No. 7-58491 (filed on March 17, 1995). No. 7-231024 (filed on Sep. 8, 1995) proposed a CAM suitable for a cache memory.
[0008]
Further, in the conventional full associative TLB and virtual address cache memory, when a failure occurs in the data held therein, the input data that should not be hit may be hit.
[0009]
An object of the present invention is to provide a semiconductor integrated circuit having a higher speed CAM.
[0010]
Another object of the present invention is to provide a semiconductor integrated circuit having a CAM that does not hit accidentally when a failure occurs in retained data.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, an associative memory device provided in a semiconductor integrated circuit according to the present invention includes a potential difference between a potential of a coincidence detection signal line and a reference potential in a coincidence detection circuit for detecting the potential of the coincidence detection signal line. A differential amplifier and an acceleration circuit for detecting
The acceleration circuit rapidly raises the potential of the coincidence detection signal line to near the reference potential at the start of data coincidence detection, and since all of the plurality of memory cells output coincidence detection signals, the plurality of MOS transistors are all turned off. After that, the potential of the coincidence detection signal line is raised to a potential higher than the reference voltage, and at least one of the plurality of memory cells outputs a mismatch detection signal, so that at least one of the plurality of MOS transistors After being turned on, a current that makes the potential of the coincidence detection signal line smaller than the reference voltage is supplied to the coincidence detection signal line.
[0012]
In order to achieve the other object, the associative memory device provided in the semiconductor integrated circuit according to the present invention also stores parity bits of data stored in a plurality of memory cells in those memory cells.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the CAM according to the present invention will be described in more detail with reference to some embodiments shown in the drawings. In the following, the same reference numerals represent the same or similar items. In the second and subsequent embodiments, differences from the first embodiment will be mainly described.
[0014]
<Embodiment 1 of the Invention>
First, a microcomputer system having a TLB using a CAM according to the present invention will be described. In FIG. 14, the microprocessor unit (MPU) 100 accesses data in the memory unit 108 from the central processing unit (CPU) 101 via the memory control unit 106 and the real address cache 104, and passes through the input / output control unit 105. The external storage device 109 is accessed. The memory control unit 106 converts the virtual address given from the CPU into a real address, and accesses the data in the real address cache 104 and the memory unit 108 with the converted real address. The memory control unit 106 has a TLB 200 that holds this virtual address and the real address obtained by the above conversion, and uses the real address in the TLB 200 when the same virtual address is given from the CPU later. . At this time, the real address can be obtained without performing the address conversion in the memory control unit 106. This TLB is constituted by the CAM according to the present invention.
[0015]
FIG. 1 shows a schematic block of this TLB. In the figure, a CAM unit (1) 700 and a CAM unit (2) 710 are composed of a plurality of CAM cells arranged in a matrix for holding a plurality of address information, and each row holds one address information. . The CAM unit (1) 700 and the CAM unit (2) 710 divide and hold these address information. Hereinafter, when these CAM parts are collectively referred to, they may be simply referred to as CAM parts. The coincidence detection unit 730 includes a plurality of coincidence detection circuits provided corresponding to one row, and each coincidence detection circuit includes the address information supplied from the signal CPU via the line 92 and the CAM units 700 and 710. A match with the address information held in one row to which the match detection circuit is connected is detected. The address information sent from the CPU and the address information stored in the TLB include a virtual address (hereinafter referred to as VA) and other information.
[0016]
The data RAM unit 750 includes an SRAM memory having a plurality of memory cells for holding real addresses arranged in a matrix. Each row holds one real address and corresponds to one row of the CAM units 700 and 710. When the coincidence detection circuit corresponding to the row detects a coincidence, the real address held in the row in the data RAM unit 750 corresponding to the row is read, and the sense & output circuit 760 Output via the selector 770.
[0017]
The pre-CAM unit 780 holds address information less than the plurality of address information held in the CAM units 700 and 710, and operates before the coincidence detection in the CAM units 700 and 710. For this reason, the front CAM unit 780 is also composed of CAM cells arranged in a matrix for holding address information. However, the number of rows is much smaller than that of the CAM units 700 and 710. Further, these CAM cells are not divided into two parts like the CAM parts 700 and 710. The coincidence detection unit 830 includes coincidence detection circuits provided in correspondence with one row of the front CAM unit 780, and each has the same structure as the coincidence detection circuit in the coincidence detection unit 730.
[0018]
The data storage circuit 790 is made up of a plurality of registers for holding real addresses, each provided corresponding to one row of the front CAM unit 780, and any one of the match detection circuits in the match detection unit 830 is connected to a line. When a match with the address information supplied from 92 is detected, the real address in the register corresponding to the row to which the match detection circuit is connected is output. When the coincidence detection unit 830 detects a coincidence, the power supply control circuit 81 stops the power supply to the coincidence detection unit 730 and stops its operation, thereby reducing power.
[0019]
The write control unit 800 is a circuit that writes write data supplied from the CPU via the line 94 to the data storage circuit 790 or the data RAM unit 750. The decoder 69 selects one row specified by the row select signal supplied from the CPU via the line 90, and writes the address information supplied from the CPU via the line 92 to the line 94 from the CPU. The row in the data RAM unit 750 to which the data supplied via is to be written is selected. Similarly, the decoder 68 sets one row in the front CAM and one register in the data storage unit circuit 790 specified by the row select signal supplied from the CPU via the line 90 as address information. And select for writing write data.
[0020]
The block structure of the above circuit is basically the same as that described in Japanese Patent Application No. 7-58491 filed earlier, but this embodiment mainly includes coincidence detection units 730 and 830, a sense & output unit. 760 is different from that described in the prior application in that it is configured to operate at higher speed.
[0021]
FIG. 2 shows a circuit structure of the CAM unit (1) 700 and the CAM unit (2) 710. Reference numeral 70 denotes a main part of the CAM part (1) 700, and 23 denotes one of a plurality of, for example, approximately 30 CAM cells belonging to one row. Reference numeral 10 denotes an inverter provided in the column to which the memory cell belongs. 71 indicates a main part of the CAM unit (2) 710, and 93 indicates one of a plurality of CAM cells of the CAM unit (2) 710 belonging to the same row. Reference numeral 87 denotes a coincidence detection circuit for the CAM unit (2) 710 for this row in the coincidence detection unit 730. The CAM part (2) 710 is composed of a memory cell of several bits, here 3 bits, for each row. The coincidence detection circuit 87 is composed of a NAND circuit to which the outputs 84, 85, 86 of these memory cells are input. 73 is a coincidence detection circuit for the CAM unit (1) 700 and the CAM unit (2) 710 for this row in the coincidence detection unit 730. The differential detection circuit 32, the output circuit 43, the transistors 30, 31, 33, 35, and 36. The block 72 including the elements described above constitutes one row (one entry) of the CAM array constituting the TLB. In the present embodiment, 64 rows of circuit blocks 72 are provided to constitute a CAM array unit. The terminal 21 is one of the lines 92 (FIG. 1) connected to the CPU, and receives 1 bit of address information supplied from the CPU. The inverter 10 generates a complementary signal on the line 22 of the 1-bit signal 21.
[0022]
Of the structure of this CAM, in this embodiment, the circuit other than the acceleration circuit 356 in the coincidence detection circuit 73 is basically the same as the circuit described in Japanese Patent Application No. 7-58491. The operation and characteristics of the circuit are as described in the prior application. The acceleration circuit 356 includes transistors 35 and 36, and has a function of accelerating the detection operation in the differential amplifier circuit 32. Further, as will be described later, a circuit for generating a reference voltage to be supplied to the terminal 37 of the differential amplifier circuit 32 is devised to reduce the power consumption in the differential amplifier circuit 32.
[0023]
Hereinafter, the operation of the circuit of FIG. 2 will be described. One bit of the input address information is applied to the data line 21, and a complementary signal of the input signal is generated on the complementary data line 22 by the inverter 10 connected thereto. A pair of complementary signals on the data lines 21 and 22 are guided to the CAM cell 23. For example, when the input signal of the data line 21 is a high level signal and the storage data of the CAM cell 23 is at the high level of the node 18, the N-type MOS transistor (hereinafter referred to as NMOS) 19 becomes conductive, and the data line 22 Since a low level signal which is a complementary signal of the upper input signal is supplied to the gate of the NMOS 26, the NMOS 26 is turned off. Assume that the data matches this state. A case where the data do not match will be described. A case where the input data of the data line 21 is at a low level and the node 18 of the CAM cell 23 is at a high level will be described. Also at this time, the NMOS 19 is turned on to guide a high level signal to the gate of the NMOS 26, and the NMOS 26 is turned on. When the node 18 of the CAM cell 23 is at a low level, the relationship with the above-described input signal is merely switched, and the description thereof is omitted. In other words, in the CAM portion, the data match and mismatch are determined by the non-conduction and conduction of the NMOS 26.
[0024]
The CAM unit (1) 700 is provided with an element circuit indicated by reference numeral 70 in FIG. 2 by the number of bits of the CAM unit (2) 710 (3 in the present example) less than the number of bits of input address information. The drains of the NMOS corresponding to the NMOS 26 of all the element circuits are connected in parallel to the coincidence detection signal line 25. With this configuration, the coincidence detection signal line 25 is disconnected from the ground terminal only when all the bits minus 3 bits of the inputted address information coincide with the address information stored in the CAM cell. The word line 24 is for writing data into the CAM cell 23. By raising the word line 24 to a high level, the data on the data line pair 21 and 22 can be written into the CAM cell 23.
[0025]
As described above, when the address information bits input to the CAM unit (1) and the stored data of the same number of CAM cells in the CAM unit (1) all match, the match detection signal line 25 is disconnected from the ground terminal. Therefore, when a current is supplied by P-type MOS transistors (hereinafter referred to as PMOS) 30, 31, 35, and NMOS 36, the potential of the coincidence detection signal line 25 is raised. The final potential of the coincidence detection signal line 25 when a sufficient time has elapsed becomes a positive power supply voltage. Here, the NMOS 33 functions to adjust the detection condition by setting the coincidence detection signal line 25 to the ground potential at the start of the coincidence detection operation.
[0026]
A change of the coincidence detection signal line 25 when only one bit of the input address information and the data of the CAM cell does not coincide will be described. Assume that all 3 bits of the CAM part (2) match. As will be described later, in this case, a low level is supplied to the gate of the PMOS 30. When the input address information and the data of the CAM cell belonging to one row in the CAM part (1) do not match only one bit, the current supplied by the PMOS 30, 31, 35, and NMOS 36 is changed to the current flowing through one NMOS 26. If designed to be substantially equal, the potential of the coincidence detection signal line 25 reaches about ½ of the positive power supply voltage and does not increase any more. Since the supplied potential can be controlled by this supply current, this reached potential is set to a potential higher than the ground potential by Vt of NMOS by the control of the supplied current. In this way, almost no current flows through the differential amplifier circuit 32. That is, a current is supplied to the differential amplifier 32 only when a match occurs in all the CAM cells in one row, and a current hardly flows when a mismatch occurs in at least one CAM cell. Only one entry of CAM matches (one row in the CAM cell matrix is commonly referred to as an entry, so it will be referred to as an entry below), and the remaining entries are all inconsistent in data, so this setting greatly reduces power consumption. The
[0027]
The reference potential (potential supplied to the terminal 37) of the differential amplifier 32 will be described later, but is set to a potential slightly higher than the potential of the coincidence detection signal line 25 when only one piece of data does not coincide. A predetermined potential is applied to the gate of the NMOS 36 and functions to determine the upper limit of the potential at which the signal line 25 is pulled up by the current supplied from the PMOS 35. In this way, the signal line 25 can be pulled up to a predetermined potential in a short time by the current supplied from the PMOS 35, and the coincidence detection of the differential amplifier 32 can be speeded up. The signal lines 27, 28, and 29 are a PMOS control signal line that supplies current to the coincidence detection signal line, a signal line that supplies current to the NMOS 34 for current control of the differential amplifier, and a gate potential supply signal line for the NMOS 36.
[0028]
FIG. 3 is a circuit for generating a reference voltage applied to the terminal 37 of the differential amplifier circuit 32 of FIG. 2 and a voltage applied to the gate of the NMOS 36, and is configured to detect data coincidence in the differential amplifier circuit 32 at a higher speed. ing. The NMOS 102 has the same shape as the NMOS 26 in the CAM cell 23 of FIG. 2, and the voltage (Vcc-Vt) applied to the gate of the NMOS 102 is the high level of the coincidence detection voltage of the cell 23 (when the data does not coincide, the gate of the NMOS 26). Vcc is a positive power supply voltage and Vt is the threshold voltage of the NMOS 26). By this potential supply, a current equal to the current that flows when the CAM cells do not match is supplied to the PMOS 103. Supply. In a CAM cell using 11 MOSs, this potential is Vcc. The current flowing through the NMOS is supplied to the NMOSs 105 and 106 through the PMOS having the same shape as that of the PMOS 103 to generate a gate voltage VR1 on the line 29 to be applied to the NMOS 36 of FIG. With this circuit, the gate voltage VR1 is set to a potential approximately twice the NMOS threshold voltage Vt. The gate voltage VR1 does not have to be strictly this potential, and a separately generated voltage may be supplied. However, when the potential is set to twice the potential of Vt, the potential of the reference voltage VR described later is set to Vt, The power consumption of the differential amplifier 113 is small and the potential operates at high speed. The gate voltage VR1 is supplied to the gate 108. The NMOS 109 has the same shape as the NMOS 102, and the PMOS 110 has a supply current about 20% larger than the PMOS 35 (FIG. 2) that supplies current to the coincidence detection signal line. The PMOS 35 supplies a current to the coincidence detection signal line 25 at a predetermined time, and its gate is held at the ground level while the current is supplied.
[0029]
FIG. 4 shows the time change of the potential of the main node of the circuit of FIG. The signal Vacc is a signal applied to the PMOSs 31 and 35 via the line 27 that controls the supply current to the signal coincidence detection signal line 25, and is also called a detection acceleration pulse. When this signal changes from Vcc to the ground level, when all the CAM cells 23 connected to the coincidence signal line 25 coincide with each other, the coincidence detection signal line 25 as shown in the voltage waveform indicated as “coincidence” in FIG. The potential of increases with time. Here, the time change from the time Vacc is lowered to the ground level to the reference voltage VR is rapid because current is supplied from the PMOS 35 through the NMOS 36 to the reference voltage VR. When the potential of the coincidence detection signal line 25 reaches VR, the voltage between the gate and the source of the NMOS 36 becomes the threshold voltage Vt, so that the supply of current through the NMOS 36 is stopped, and thereby the rising speed of the potential of the coincidence detection signal line 25. Will decline. On the other hand, in FIG. 4, the time change of the signal line potential when only one of the CAM cells connected to the coincidence detection signal line 25 does not coincide is indicated by the symbol “mismatch”. At this time, the current continues to be supplied from the PMOS 35 via the NMOS 36. However, since the current of the PMOS 110 that supplies the current is larger than that of the PMOS 35, the potential rise stops without increasing to the reference voltage VR. It can be easily understood that the potential rise is further reduced when two or more CAM cells connected to the coincidence detection signal line 25 do not coincide.
[0030]
As described above, in the circuit of FIG. 2, coincidence detection can be detected by the difference between the potential of the coincidence detection signal line 25 and the reference voltage line VR, and the NMOS 31, immediately after the detection acceleration pulse Vacc is lowered to the ground level. Since the coincidence detection signal line is pulled up to the reference voltage VR at high speed by the current supplied by 36, the coincidence detection operation is speeded up. In addition, since the potential of the mismatch detection signal line does not exceed the reference voltage VR, it is not necessary to strictly limit the time for holding Vacc at the ground potential, and it is easy to control the circuit. It is a feature. However, since the current continues to be supplied to the mismatch detection signal line 25 by the MOSs 31 and 36 during the period when Vacc is at the ground level, Vacc is quickly raised to a high level if a match detection signal is output to reduce power consumption. It is desirable to stop the supply of the pull-up current. The reference voltage generation circuit 101 can also be applied to a differential amplifier other than the differential amplifier circuit 32 of FIG.
[0031]
Here, the operation of the CAM unit (2) 710 will be briefly described with reference to FIG. This circuit is substantially the same as that described in Japanese Patent Application No. 7-58491. In the CAM unit (2) 710, a signal of about 3 bits in the address input (input signal) is subjected to coincidence detection. The CAM cell 93 included therein has substantially the same structure as the memory cell 23 of the CAM unit (1), but the grounding of the circuits is different. 84, 85, and 86 become high levels, respectively. The coincidence detection circuit 87 for CAM (2) supplies the low level to the PMOS 30 in the corresponding coincidence signal generation circuit 73 and drives the circuit 73 only when these signal lines are all high. In this way, only a part of the all coincidence detection circuit 73 in the CAM unit (1) is driven.
[0032]
FIG. 5 shows a main part of the front CAM unit 780 and a main part of the coincidence detection circuit unit 830 therefor. In the figure, elements having the same structure as in FIG. 2 have the same reference numerals. As can be seen from FIGS. 5 and 2, the front CAM unit 780 has the same structure as the CAM unit (1) 700. The coincidence detection circuit 83 in the coincidence detection unit 830 for the front CAM unit does not have the coincidence detection circuit 87 for the CAM unit (2) 710 shown in FIG. 2, and accordingly, for the CAM unit. There is no NMOS 30 in the coincidence detection circuit 73. However, the coincidence detection circuit 83 in the coincidence detection unit 830 is provided with an acceleration circuit 356 including the PMOS 35 and the NMOS 36 in the coincidence detection circuit 73 for the CAM unit as in FIG. Accordingly, the circuit operation of the pre-CAM unit 780 and the coincidence detection circuit unit 830 for the same is the same as that of the CAM unit (1) 700 and the coincidence detection circuit unit 730, and thus description thereof is omitted.
[0033]
The RAM data portion 750 shown in FIG. 1 can generally be constituted by an SRAM memory. In SRAM, memory cells generally have a flip-flop structure and are connected to a pair of data lines. The sense & output circuit 760 has a sense amplifier corresponding to each data line pair for differentially detecting the voltage of the pair of data lines. FIG. 6 shows a sense amplifier suitable for such a sense amplifier. The feature of this circuit is that the offset voltage converted to the input of the differential amplifier is reduced and a minute voltage signal is detected by the differential amplifier at high speed.
[0034]
More specifically, there are provided NMOSs 201 and 202 having a gate connected to an input signal, a drain connected to a positive power supply Vcc, and a source connected to NMOSs 203 and 204 for supplying a predetermined current. The gates of NMOSs 205 and 206 constituting the dynamic amplifier are respectively connected. At this time, the gate-source voltage Vgs of the NMOSs 201 and 202 has a relationship of Ief = Io exp ((Vgs−Vt) / nkT) with the current Ief supplied from the NMOSs 203 and 204 when the current is small. That is, if Ief is controlled by the NMOSs 203 and 204, the voltage between the gate and source of the NMOSs 201 and 202 can be arbitrarily controlled.
[0035]
Here, if the current Ief is controlled so that the voltage difference between the output terminals 207 and 208 generated in the NMOSs 201, 202, 205, and 206 and the PMOSs 221 and 222 becomes zero, there is a mismatch in the characteristics of the NMOS that constitutes these circuits. However, these are corrected, and it is possible to realize the same performance as a circuit having completely the same characteristics. Further, even if the currents flowing through the NMOSs 201 and 202 slightly enter the region deviating from the above relationship, the relationship between them is uniquely determined, and it goes without saying that the same correction can be performed by adjusting the current. . Hereinafter, the operation of the circuit will be described in detail.
[0036]
A data line pair of the memory circuit is connected to the input terminals IN and INB, and a potential difference is generated between the two lines due to a current from the memory cell. This potential difference is 0 V at the start of data reading, and increases in proportion to time. The potential of the data line at the start of data reading is the positive power supply voltage Vcc. When Vcs and Vsw are raised to a high level before the start of data reading and current is supplied to the NMOSs 201 and 202, the potential of (Vcc-Vt) is applied to the gates of the NMOSs 205 and 206, and the potentials of the output terminals 207 and 208 Pull down. If the characteristics of the NMOSs 201 and 202, 205 and 206, and the PMOSs 221 and 222 are the same, the potentials of the output terminals 207 and 208 are equal, but if there is an imbalance, a potential difference occurs between the output terminals according to the imbalance.
[0037]
For example, when the potential of the terminal 208 becomes high, the potential is supplied to the gate of the NMOS 203 through the NMOS 209 and Ief increases. As a result, the gate potential of the NMOS 205 is lowered, the potential of the output terminal 207 is increased, and the potential difference between the output terminals 207 and 208 is reduced. The decreasing rate of the potential difference is the reciprocal of the voltage gain of the differential amplifier composed of the NMOSs 205, 206 and 203, 204. A voltage gain of 20 db was easily obtained with a two-stage differential amplifier, and the input unbalance was 5 mV or less. Thus, after correcting the imbalance, detection of the input signal is started. First, Vsw is lowered to disconnect the gate terminals of the NMOSs 203 and 204 from the output terminals 207 and 208. However, the gate potential is held by the capacitors 211 and 212. The change in the gate potential caused by the separation is reduced because the NMOSs 203 and 204 are differential circuits. When a detection signal is connected to the input terminals IN and INB in this state, the input signal can be detected in a state where the imbalance is corrected, and a circuit for detecting the signal at high speed is obtained.
[0038]
<Modification of Embodiment 1 of the Invention>
(1) Other sense amplifiers (1)
FIG. 7 shows another sense amplifier which is different from the sense amplifier shown in FIG. In this figure, in order to supply a predetermined current, the voltage difference between the output terminals 207 and 208 is examined, and the gates of the NMOSs 213 and 214 having a floating gate structure used in EPROM or the like so that the difference becomes zero. Is a circuit that adjusts the voltage of the floating gate to permanently set the potential difference between the output terminals to zero. According to this method, the mismatch of the device characteristics of the MOSFET can be corrected permanently only by setting the current Ief at the time of manufacturing the integrated circuit.
[0039]
(2) Other sense amplifiers (2)
FIG. 8 shows still another sense amplifier that is different from the sense amplifier shown in FIG. In this figure, three NMOSs are provided in advance as NMOS groups 215 and 216 for adjusting Ief, respectively, and the supplied Ief is controlled by controlling the conduction / non-conduction of these NMOSs. At this time, the control operation is simplified depending on whether the floating gate NMOS used in FIG. 7 is made conductive to the ground potential or to the positive power supply voltage Vcc. In addition, it is possible to perform conduction / non-conduction of the NMOS groups 215 and 216 for controlling Ief using a programmable ROM such as cutting a fuse.
[0040]
The circuit in FIG. 6 detects an input signal in a state where Ief is adjusted so that the potential difference between the output terminals becomes small immediately before the signal is detected. Therefore, even if the characteristics of the NMOS change with time, the characteristics are corrected, so that the characteristics can be corrected more accurately. On the other hand, once the correction is performed in the circuits of FIGS. 7 and 8, the subsequent correction is unnecessary, the usage is not limited, and the unbalance is corrected by a normal amplifier. However, it cannot be corrected for changes over time. Of course, the correction can be performed in the circuits of FIGS. 7 and 8 if correction is performed again at a desired time.
[0041]
(3) Other types of memory cells
In the first embodiment of the present invention, a memory cell having a comparison function known per se, for example, the one cited in Japanese Patent Application No. 7-58491 can be used instead of the memory cells 23 and 93. .
[0042]
(4) TLB corresponding to variable length data
It is also possible to modify the first embodiment of the invention so as to constitute a TLB corresponding to variable length data. At this time, as a memory cell used in the first embodiment of the present invention, for example, a memory cell for variable length data described in JP-A-1-220293 shown in FIG. 9 may be used. As a result of the examination of the TLB by the present inventor, new knowledge about the design and installation location of the NMOS 260 shown in FIG. 9 was obtained.
[0043]
The first is a decrease in coincidence detection current flowing in the CAM cell and an increase in coincidence detection time. In the TLB, the conduction / cutoff operation of the NMOS 260 is controlled by the variable length designation bit. However, when the current is conducted and current is passed, since the current is supplied in series with the NMOS 250, the current is larger than that of the conventional CAM cell. Decrease. For this reason, in order not to increase the delay time, it is required to improve the driving capability of the MOSFETs to be configured. For example, the gate widths of all MOSFETs may be increased by that amount. At this time, the load on the data line (for example, the data line to which the terminals 21 and 22 in FIG. Increases power consumption and power consumption. Therefore, it was examined to increase only the gate width of the NMOS 260. As a result, it has been found that if the gate width of the NMOS 260 is designed to be 1.5 times or more the gate width of the NMOS 250, the reduction in current can be greatly reduced. When the gate width of the NMOS 260 is increased, the area of the CAM cell is increased correspondingly, but the increase is slight, and the load on the VA input data line is hardly increased.
[0044]
The second is that, through this study, it is clear that it is advantageous to provide one NMOS 260 in a plurality of CAM cells from the viewpoint of area and electrical characteristics. That is, when the input VA data is compared with the data in the CAM cell, the minimum signal level of the signal indicating “mismatch” when there is a mismatch is determined by the NMOS in the CAM cell, for example, the NMOS 250 in FIG. One is in a conductive state. That is, it can be said that it is sufficient to install one MOS transistor (for example, NMOS 260) in common to a plurality of CAM cells.
[0045]
The third is a place where the NMOS 260 is installed. As a result of the examination, it was shown that the parasitic capacitance increase can be most suppressed by providing the drain of the NMOS 260 so as to be connected to the coincidence detection signal line. This variable length designation bit processing method is particularly used in the method of generating a coincidence signal by supplying a constant current (coincidence detection method by the coincidence detection circuit 73 in FIG. 2) described in the first embodiment of the invention. Since the supply current is limited, the effect was drawn out even better. Further, the area occupied by the circuit is reduced by sharing the NMOS 260.
[0046]
<Embodiment 2 of the Invention>
In this embodiment, a full associative TLB that operates normally even when an error occurs in stored data is provided. Specifically, the parity data of the data stored in the CAM unit is also stored in the CAM unit. The circuit of the memory (CAM) for collating the input data with the data stored in the memory to find matching data and outputting the storage information related to the data has been described in detail with reference to FIG. In addition, as a TLB circuit of an address translation device for a computer, the IEICE Transactions, Vol. 6, pp. 757-762. However, these circuits do not have parity bits for improving reliability. In order to add parity bits, the operation and configuration of the CAM are briefly summarized.
[0047]
As described in detail in the description of FIG. 2, the operation of the CAM is summarized as follows. First, data for comparison is input, and the input data is compared with data stored in a CAM arranged in a matrix. When the input data matches the stored data, in the CAM, the data (RAM data) related to the data to be compared with the data compared with the input data (CAM data) is compared with one line in the CAM. Since it is stored, the row is referred to as an entry), and the related data stored in it is read and output.
[0048]
FIG. 10 shows data for one entry stored in the CAM portion of FIG. VA10 to VA31 indicate data stored in a CAM unit (such as the CAM unit in FIG. 2). Consider a case where the data in FIG. 10 is inverted by 1 bit due to some trouble. If 1-bit data is inverted in the data from VA10 to VA31, even if the same data as the data before the failure is input to the CAM, the stored data is inverted by 1 bit due to the failure, resulting in a mismatch. . For this reason, processing is performed assuming that there is no data matching the CAM portion, and the operation of the CAM is normal. However, if the same data as the data inverted due to the failure is input, the two match, so the data in the RAM portion of the entry of the failed data is output, and the CAM outputs incorrect data. Thus, since the CAM operates differently from the operation of the conventional memory, the parity bit cannot be added according to the conventional concept.
[0049]
The present embodiment provides a configuration of a CAM that determines that data does not match even when data that matches the faulty data is input. This configuration is based on the finding of the following relationship by the inventors. This is because the parity bit value for the same input data as the stored data in which 1-bit data is inverted due to a failure is always different from the parity bit value of the data before the failure occurs. In other words, by comparing the parity bit of the failed data with the parity bit of the same input data as the failed data, it is determined whether the data is determined to be consistent or correctly matched because of the failure. To do. The function of such a parity bit is fundamentally different from the function used as a signal indicating that a failure has occurred with respect to data in which a conventional parity bit has failed. In other words, the configuration of the present embodiment is a method of using a parity bit to stop reading data when it is determined that the data in the wrong entry matches because of a failure. The function is completely different.
[0050]
Hereinafter, the configuration and operation of the CAM according to the present embodiment will be described in more detail with reference to the drawings.
[0051]
FIG. 17A shows the stored data for one entry according to the present embodiment. One parity bit Pc is provided at the right end of the CAM portion data. The configuration other than the parity bit is the same as that of FIG. The case where data to be compared with the data shown in FIG. 17 is input will be described. In FIG. 17 (a), if no failure occurs in the stored data, the same input data as the data in FIG. 17 (a) is matched in the CAM portion including the parity bit, and the other data is not matched. It is obvious that the CAM operates normally. An example of data when a 1-bit failure occurs is shown as data for one entry in FIG. Since this data causes a 1-bit failure, it does not match the input data that originally matches. This discrepancy determination is processed assuming that there is no data in the CAM, and the time required for the processing is disadvantageous, but erroneous data is not output, and the CAM operation is a normal operation. Next, consider the case where the same data as the data in which the failure occurred is input to the CAM. As described above, since the value of the parity bit is not correct for the failed data, it is different from the parity bit of the input data. Therefore, in the configuration of FIG. 17 in which data matching including parity bit Pc is checked, faulty data is not judged to be inconsistent and erroneous data is not output, and CAM operation is normal. From the above description, data reliability can be guaranteed by manufacturing a CAM having a data structure in which one parity bit is added to the CAM portion.
[0052]
<Modification 1 of Embodiment 2 of the Invention>
FIG. 18 shows storage data for one entry of the CAM as in FIG. A difference from FIG. 17 is that a parity bit Pr is added to the RAM unit. In this data structure, there is a possibility that two pieces of data match in the CAM as described in the above problem. In this embodiment, a circuit for detecting the coincidence of two pieces of data is provided, and when this circuit detects that the two pieces of data coincide with each other, the data is determined to be inconsistent. This solves the problem as described below. This will be described in detail below.
[0053]
When the stored data does not cause a failure, the data in the RAM portion of the entry corresponding to the stored data that matches the input data is read and the parity bit Pr entered in the RAM portion also matches, so the input data and the RAM portion The data stored in is checked for a match, and the reliability is guaranteed by the match. Further, when the same data as the data in which the failure has occurred is not stored in the CAM part, the circuit for detecting that the two data match does not operate, and the data in the RAM part is read out. However, the parity bit Pr of the read data is different in value from the parity bit of the data matched in the CAM part as described above. The two parity bits are compared and a mismatch is detected, and it is detected that the read data is incorrect data. From this detection result, a signal indicating that no matching data exists in the CAM is generated, so that erroneous data is not output, and the operation of the CAM is a normal operation. When the same data as the failed data is present in the CAM and the same data as that data is input, the data is erroneously detected by a circuit (circuit of FIG. 16) that detects that the two data match. If it is detected that there is no coincidence data, no erroneous data is output, and the CAM operation is normal.
[0054]
Hereinafter, the circuit of FIG. 16 will be described. Signal lines 500, 501, and 561 are signal lines indicating the entry that matches when the input address matches the data stored in the CAM portion, and are signals at the terminal 44 in FIG. That is, the signal line of the matched entry is designed to be high level, and the signal line of the mismatched entry is designed to be low level. This signal can also be used as the signal of the word line in the data RAM portion of FIG. The gates of the NMOSs 570 are connected to the signal lines 500, 501, and 561, respectively. The source of the NMOS is grounded, the drain is connected to the signal line 662 in parallel, and the signal line is connected to the drain of the PMOS 571. The source of the PMOS 572 having the same shape as the PMOS is connected to a positive power supply, and the gates of both PMOSs are connected to the drain of the NMOS 573. The drain of the PMOS 572 is connected to the drain of the NMOS 573 whose source is grounded, and the gate of the NMOS is connected to a positive power source. The shape of the NMOS 573 is set to 1.2 to 1.6 times the gate width of the NMOS 570 connected to the signal lines 500 to 561, and the current is designed to flow 1.2 to 1.6 times. The operation of this circuit will be described. In the circuit of FIG. 16, when there is no matching data, all the NMOSs 570 are OFF, so that the terminal 505 holds a high level. When one entry matches and the MOSFET is turned on, the current supplied from the PMOS 501 is larger than the current flowing through the matched NMOS 570, so that the potential at the terminal 575 is kept at a high level. When the two entries match, the current flowing through the two NMOSs 570 becomes larger than the current supplied from the PMOS 571, so that the terminal 575 is at a low level. By detecting the potential level of the terminal 575, it can be detected that the two entries match. Discarding the read data from the RAM unit with this signal or stopping the reading can be easily realized, so the presentation and description of the attached circuit are omitted.
[0055]
Based on the above description, the configuration of the CAM with parity according to the present embodiment is summarized in FIG. Since FIG. 19 has a configuration in which parity bits are added to FIG. 2, circuits having the same operations as those in FIG. The parity bit can be added to the CAM in two ways. The first is a configuration in which a CAM cell having a parity bit Pc 901 is added to the CAM portion of the conventional CAM. In this case, only one column of CAM cells 901 needs to be added. The second is that a circuit 900 (which is equivalent to the circuit of FIG. 16) for detecting that two or more data matches in the CAM is added, and this circuit confirms that two or more data matches. When detected, a signal indicating that there is no data matching the input data at that time is sent (not shown), and a function of stopping the output of the selector 770 by the signal 905 is added. Further, the parity bit read by adding one column of RAM cells Pr902 for the parity bit in the RAM portion is compared with the input parity bit signal 904 by the comparison circuit 903. Since the data is correct, data is output from the selector 770. If the data does not match, it is determined that the data is incorrect and the output from the selector is stopped.
[0056]
The reliability of the CAM data can be confirmed by the above two configurations. In addition, the parity bit put in the CAM part is controlled by using a mask bit described later so that two kinds of parity bits can be used in the same CAM configuration, so that the function of the parity bit of the CAM part is enabled or disabled. Needless to say, it can be controlled.
[0057]
<Modification 2 of Embodiment 2 of the Invention>
17 and 18 does not have a function that does not compare a part of input data (hereinafter, this function is referred to as a mask function). The configuration of the CAM with the mask function is Digest of Technical Papers of ISSCC 96 pp. 360-361 (1996) and JP-A-1-220293. From these circuits, it has been found that a mask function can be obtained simply by adding a memory cell for storing mask information to a conventional CAM and adding a function for controlling whether or not to compare in accordance with the stored mask information. To do. That is, the mask function is a function that can be easily designed by an engineer who can design a conventional CAM circuit by looking at the above-mentioned document. For this reason, only matters to be noted when adding a mask function are described below.
[0058]
A brief description of a CAM having a mask function will be added. In a CAM having a mask function, it is necessary to insert a parity bit as follows. One parity bit is put in each address area to be masked and one bit is put in the masked address area. In this way, when all the mask functions are functioning, it is shown that there is no error in the data by comparing only the parity bits in the unmasked address area. Since the parity bit is compared for each mask area when the masked address area is not masked, the parity bit only does not function when masked, and when it is not masked, the match is checked in the mask area. When considered as an area, it can be easily understood that the parity bit indicates the reliability of the data in the area, and if all the parity bits match, it is indicated that there is no error in the data.
[0059]
<Third Embodiment of the Invention>
In this embodiment, a CAM that can read CAM data is listed. If the data stored in the CAM can be read, the same failure analysis method as that of a normal RAM can be applied.
[0060]
In FIG. 11, in the coincidence comparison operation with the input signal, the control signals CAM and RE are set to the high level, and the CAMB and VWE are set to the low level. In this way, the input signal 21 is guided to the CAM data line and subjected to a coincidence comparison. In the CAM section data read operation, the control signals CAM and VWE are at a low level, CAMB is at a high level, the RE is set to a low level, the CAM data line is pulled up to a high level, and the RE is switched to a low level. Disconnect the data line from the positive power supply to high impedance. Thereafter, the data stored in the CAM cell 23 is read by raising the CAM word line 24 to a high level. In FIG. 9, the sense amplifier for the read signal of the data line is omitted. However, a conventionally widely used circuit may be used, and the use of the sense amplifier of FIGS. 6 to 8 already described speeds up the reading process. The
[0061]
A data comparison mask operation using the VWE signal will be described. In this mask operation, the signal CAM is at a low level, CAMB and RE are at a high level, VWE is set to a high level, and the CAM data line is pulled down to a low level. Since both of the CAM data line pairs are at a low level, it is understood that the NMOS 26 is turned off by this setting regardless of the input data, and comparison processing is not performed on this data.
[0062]
<Modification of Embodiment 3 of the Invention>
(1) Other failure detection methods (1)
In the circuit that reads the data stored in the CAM cell described above, in order to read the data stored in the CAM, as shown in the description of FIG. Both of them need to be brought into a high impedance state after being raised to a high level, and a circuit for this purpose is included in the flow of data input to the CAM. By adding this read circuit, the conversion time of the TLB using this CAM increases, or the access time of the cache memory increases. In order to prevent such conversion time from increasing, the following method is adopted.
[0063]
In this failure analysis, the VA stored in the CAM is stored in a separate storage circuit (not shown). In the failure analysis operation, this VA is input to the CAM, and the read data is a predetermined entry. Confirm. In this process, when the entry is not a predetermined one, or when it is determined that there is no matching data and there is a mistake, it can be detected that the entry has a failure. Here, the address of the CAM entry to be stored separately can be simply stored in the data RAM section of the TLB or cache memory. However, if VA is stored in the data RAM section, the number of columns (memory cell columns) in the data RAM section increases by the stored data, and the load on the word line increases and the data read time increases. In order to avoid this, another high-speed memory (that is, it is not common to the word line of the data RAM section, and it is an integrated memory such as providing this memory adjacently and sharing a decoder). (Preferably) and stored and read out during failure analysis.
[0064]
(2) Other failure detection methods (2)
The method of ensuring the reliability and adding the parity bits Pcm and Prm and the method of detecting the double match are described in the second embodiment. This is to ensure data reliability after an error has occurred. Other failure detection methods described above (Part 1 is applied to detect and eliminate data in error by comparing data stored in CAM with VA stored separately) Can reduce the occurrence of errors and reduce the processing associated with the occurrence of errors.
[0065]
<Embodiment 4 of the Invention>
FIG. 12 shows a configuration example of the novel TLB of the present invention. The conventional TLB has a function to convert the virtual address VA to the real address PA. However, in the multitask system, task IDs are added one after another, and all ID numbers are used and used once. It may be necessary to assign an ID number to a new task. In this way, when an ID number that has been used once is assigned to a new task, a mechanism that prevents the use of CAM cell data stored with the corresponding ID number is required. Conventionally, all TLB data has been disabled. However, if the scale of the TLB or cache memory increases, if all data cannot be used in this way, valid data cannot be used, so there is no matching data while new data is written, and the hit rate is high. In addition to the decrease, the data writing operation is also wasted. It goes without saying that it is desirable not to use data of only the newly assigned ID.
[0066]
In order to have this function, in this embodiment, the ID CAM is disconnected, and first, a method of checking the coincidence between the ID data and the VA data in parallel is adopted. In this way, the power consumption increases by that amount, but the decrease in the operation speed is small, and the ID CAM unit is provided with a function of prohibiting reading processing for a desired ID by providing an ID V bit (Valid bit). be able to. As a result, even if the ID increases and a new ID needs to be used, the processing can be continued without causing a decrease in the performance of the TLB or the cache memory. In addition, a symbol (encoding bit) is added so that the position (entry) where the ID selected by the input data exists can be identified, and the line number prohibited to be used by the ID V bit can be read. As a result, it has become possible to easily and efficiently select a row in which data is written.
[0067]
In this embodiment, an ID V bit is provided to prohibit read processing. If the V bit indicates a row in which read processing is prohibited, the TLB memory area can be efficiently used by preferentially rewriting the row when data is newly written. However, CAM prohibits a plurality of lines from matching input data. The feature of this embodiment is that this prohibition restriction is removed. For this purpose, the V bit of the entry selected by the CAM decoder can be read. As a result, the V bit is checked in advance, and the entry to be rewritten based on the V bit can be selected.
[0068]
The valid bit V indicating that the data is valid will be described. If the V bit can be changed for each process ID, the ID can be switched without being limited by the number of IDs. That is, when the ID is changed, if the V bit is invalidated all at once, the ID of that number can be used for a new process to start processing. For this purpose, it is only necessary to perform coincidence detection using only the ID and invalidate the coincident V bit. That is, input other than ID is not compared, and the potential of the word line of the data RAM may be held at a low level even if a match is detected when this comparison is performed. This makes it possible to invalidate the V bit for each ID within a short time.
[0069]
In the present embodiment, the V bit data of the desired entry can be read out by the decoder. As a result, the entry in which the V bit is invalid is checked in advance, and the data is updated in preference to the entry in which the V bit is invalid when the CAM data is updated. By this method, the time required for the V bit check at the time of data update can be saved, and an entry storing invalid data can be preferentially selected to update the data, thereby reducing the invalid area of the CAM data.
[0070]
Although a separate decoder may be provided for reading by the V-bit decoder, a NAND circuit 91 is provided as shown in FIG. 12 and only one V bit is read by setting the input 1 of the NAND circuit to the “low” level. In addition, data can be written to the CAM by setting the terminal to the “high” level. As a result, the decoder can be shared.
[0071]
<Modification of Embodiment 4 of the Invention>
The present embodiment provides a method for detecting at high speed that the V bit is invalid. The configuration shown in FIG. 13 is such that only one MOSFET is provided for each V-bit read word line, and only one MOSFET is connected to the data line. In FIG. 13, one MOSFET is indicated by a white circle. As a result, the encoder portion can perform a CAM operation with the V bit, and can detect in parallel a row in which the V bit is in a read-inhibited state (invalid state). However, the method of creating such an encoding bit is in a trade-off relationship that the area of the encoding section increases in proportion to the number of lines (the number of entries). In this embodiment, in order to suppress the area increase, the CAM used for the V-bit check is divided into a plurality of blocks. For example, in this embodiment, the number of rows included in the block is set to 8, and a circuit is configured that is high-speed and suppresses an increase in the area of the V-bit check circuit.
[0072]
<Application example>
Although various TLBs and technologies applied thereto have been described above, these technologies are widely applicable to general associative memories (CAM). For example, the present invention can be applied to a cache memory using CAM. FIG. 15 shows a computer system having such a cache memory. Access from the central control unit (CPU) 101 to the virtual address cache memory 102 is directly performed by a virtual address. The virtual address cache memory 102 uses the CAM of the present invention. In order to access the data in the memory unit 108 from the CPU, the memory control unit 106 converts the virtual address into a real address. The TLB already described is used for this conversion. The cache memory or memory unit data is accessed using the converted address.
[0073]
【The invention's effect】
According to the present invention, when the circuit for accelerating the potential of the coincidence detection signal line is provided in the associative memory device, the associative memory device can perform the coincidence detection operation at high speed.
[0074]
Furthermore, according to the present invention, when the associative memory device also stores the parity bit of the data stored therein, it is possible to prevent erroneous detection of coincidence even if a failure occurs in the stored data.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of a TLB according to the present invention.
FIG. 2 is a circuit diagram of a CAM section of the TLB of FIG.
3 is a circuit diagram of a reference voltage generation circuit used in the circuit of FIG.
4 is an operation waveform diagram of a coincidence detection circuit in the circuit of FIG. 2. FIG.
FIG. 5 is a circuit diagram of a front CAM unit of the TLB of FIG. 1;
6 is a circuit diagram of a sense amplifier suitable for a sense & output circuit in the TLB of FIG. 1;
7 is a circuit diagram of another sense amplifier suitable for the sense & output circuit in the TLB of FIG. 1. FIG.
FIG. 8 is a circuit diagram of still another sense amplifier suitable for the sense & output circuit in the TLB of FIG. 1;
FIG. 9 is a circuit diagram of another CAM cell that can be used in the TLB of FIG. 1;
FIG. 10 is a diagram showing the structure of data stored in another TLB according to the present invention.
FIG. 11 is a circuit diagram of the main part of still another TLB according to the present invention.
FIG. 12 is a schematic block diagram of still another TLB according to the present invention.
FIG. 13 is a schematic block diagram of still another TLB according to the present invention.
FIG. 14 is a schematic block diagram of a microprocessor to which the TLB of FIG. 1 is applied.
15 is a schematic block diagram of a microprocessor to which the CAM in the TLB of FIG. 1 can be applied.
FIG. 16 is a schematic diagram of a double coincidence detection circuit usable in a TLB according to the present invention.
FIG. 17 is a diagram showing the structure of another data stored in the TLB according to the present invention.
FIG. 18 is a diagram showing another structure of further data stored in the TLB according to the present invention.
FIG. 19 is a circuit diagram of the main part of still another TLB according to the present invention.
[Explanation of symbols]
356 ... Acceleration circuit

Claims (2)

A plurality of data lines for supplying a plurality of bit input signals in parallel;
A plurality of memory cells each connected to a corresponding one of the plurality of data lines;
A coincidence detection signal line provided corresponding to the plurality of memory cells;
A plurality of MOS transistors for connecting the corresponding one of the plurality of memory cells and the coincidence detection signal line in parallel;
An associative memory device connected to the coincidence detection signal line and having a coincidence detection circuit for detecting the potential thereof;
Each memory cell responds to one input bit supplied from the data line corresponding to the memory cell, and indicates whether or not the supplied input bit matches the information stored in the memory cell. Switch the detection signal or mismatch detection signal to a predetermined node in the memory cell and output it,
Each MOS transistor has a gate connected to the predetermined node of the corresponding memory cell, a drain connected to the coincidence detection signal line, and a source supplied with a predetermined potential.
The coincidence detection circuit
A differential amplifier circuit for detecting a difference between the potential of the coincidence detection signal line and a reference potential;
An acceleration circuit,
The acceleration circuit rapidly raises the potential of the coincidence detection signal line to near the reference potential at the start of data coincidence detection, and since all of the plurality of memory cells output coincidence detection signals, the plurality of MOS transistors are all turned off. After that, the potential of the coincidence detection signal line is raised to a potential larger than the reference potential , and at least one of the plurality of MOS transistors outputs a mismatch detection signal, so that at least one of the plurality of MOS transistors After being turned on, a semiconductor integrated circuit that supplies a current that makes the potential of the coincidence detection signal line smaller than the reference potential to the coincidence detection signal line. The acceleration circuit stops supplying the current after supplying the current to the coincidence detection signal line for a predetermined time,
The semiconductor integrated circuit according to claim 1, wherein the differential amplifier circuit starts a detection operation after the stop.

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