JP3683695B2 - Latch circuit and DFF circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a latch circuit and a DFF circuit configured by a CMOS circuit, and more particularly to a latch circuit and a DFF circuit that prevent a through current to reduce power consumption and achieve high-speed operation.
[0002]
[Prior art]
A conventional static CMOS latch circuit L3 is shown in FIG. The latch circuit L3 includes transfer gates 1 and 2, NAND gate 3, and inverters 4 and 5. 6 is an input terminal, 7 is an output terminal, 8 is an inverted output terminal, 9 is a clock terminal, and 10 is a reset terminal.
[0003]
Here, when the reset terminal 10 is set to “L”, the output signal of the NAND gate 3 is fixed to “H” regardless of the input signal, the output terminal 7 is set to “L”, and the inverted output terminal 8 is set to “H”. "Reset state".
[0004]
When the reset terminal 10 is set to “H”, the reset is released, and the data input to the input terminal 6 passes through the transfer gate 1 when the clock terminal 9 is “H”. It is inverted and appears at the output terminal 7. The output of the inverting output terminal 8 is obtained from the output side of the NAND gate 3. Next, when the clock terminal 9 becomes “L”, the transfer gate 1 is cut off, but when the transfer gate 2 becomes conductive, the data of the output terminal 7 is fed back to the NAND gate 3 and the data is held. As described above, data input to the input terminal 6 is captured when the clock terminal 9 is “H”, held during the “L” period, and output from the output terminals 7 and 8.
[0005]
FIG. 13 is a diagram showing a conventional dynamic CMOS latch circuit L4. The circuit L4 is basically a circuit obtained by removing the data holding transfer gate 2 from the static CMOS latch circuit L3 shown in FIG. 12, and the same components are denoted by the same reference numerals. .
[0006]
In the latch circuit L4, the data input to the input terminal 6 is fetched when the clock terminal 9 is “H”, and held at the load of the output terminals 7 and 8 and the parasitic capacitance of the wiring when the clock terminal 9 is “L”. Here, a feedback circuit for holding data is not used.
[0007]
FIG. 14A shows a master-slave type DFF circuit configured by using the static type latch circuit L3 shown in FIG. Here, the odd-numbered latch circuit L3 is on the master side, and the even-numbered latch circuit L3 is on the slave side. 11 is an input terminal, 12 and 13 are output terminals, 14M is a master clock terminal for supplying a clock to the latch circuit L3 on the master side, and 14S is a clock having a phase opposite to that of the clock to the master side to the latch circuit L3 on the slave side. This is the slave clock pin to be used. Reference numeral 15 denotes a reset terminal. FIG. 14B is an operation waveform diagram, where IN is input data, CKM and CKS are clock signals, R is a reset signal, and OUT1 and OUT2 are output data. As described above, here, clocks of opposite phases are used on the master side and the slave side so that data skipping does not occur. Note that the dynamic latch circuit L4 shown in FIG.
[0008]
FIG. 15A shows a register circuit configured using the static latch circuit L3 shown in FIG. This register circuit is configured by alternately connecting latch circuits L3 and delay circuits DLY. 21 is an input terminal, 22 to 25 are output terminals, 26 is a clock terminal, and 27 is a reset terminal. (B) of FIG. 15 is the operation | movement waveform diagram, CK is a clock signal, Q1, Q1 ', Q2, Q2' is output data. Here, since a common clock is used for the latch circuit L3, the delay circuit DLY is connected so that no data slips out. Note that the dynamic latch circuit L4 shown in FIG.
[0009]
FIG. 16A shows the configuration of the delay circuit DLY shown in FIG. 15A. This delay circuit DLY is configured by connecting an even number of inverters 28 in series. Further, when the delay time by such an even number of inverters 28 is insufficient, as shown in FIG. 16B, a transfer gate 29 which is always conducted between the inverters 28 is provided. Interpolation is performed, and a delay time is earned at the transfer gate 29.
[0010]
[Problems to be solved by the invention]
However, the latch circuits L3 and L4 shown in FIGS. 12 and 13 have a problem that a through current is generated when a signal is inverted in the NAND gate 3 and the inverters 4 and 5, thereby increasing current consumption. This problem also occurs in the inverter 28 of the delay circuit of FIG. 15 (FIG. 16) that constitutes a register.
[0011]
In the latch circuits L3 and L4 shown in FIG. 12 and FIG. 13, the clock signal for controlling the transfer gates 1 and 2 needs to fully swing from the power supply voltage to the ground voltage. A lot of power is consumed in the circuit. In particular, in the DFF circuit shown in FIG. 14A, two types of clocks that are 180 degrees out of phase are required, which raises the problem of power consumption.
[0012]
The present invention has been made in view of the above points, and an object of the present invention is to provide a latch circuit and a DFF circuit that solve the above-described problems.
[0013]
[Means for Solving the Problems]
A first invention for achieving the above object is to provide a CMOS inverter circuit, a through current prevention transistor connected in series to each transistor of the CMOS inverter circuit, and a series connection to one of the through current prevention transistors. A first type inverter composed of a clock transistor, a second type inverter composed of a CMOS inverter circuit, and a feedback transistor, wherein the first type inverter is connected to an input terminal in a multi-stage series, In the subsequent stage, the second type inverter is connected to a plurality of stages, the feedback transistor is connected across the even number stages of the second type inverter connected to the plurality of stages, and the clock of the first type inverter is connected. The gate of the transistor is connected to the first clock terminal and the feedback transistor. The gate of the transistor is connected to a second clock terminal to which a clock whose phase is inverted from that of the clock input to the first clock terminal is input, and the gate of the through current prevention transistor of the first type inverter is an even number from the inverter. It was configured by connecting to the output side of the inverter at the rear stage.
According to a second invention, in the first invention, a reset transistor is connected between a common connection point of the first type inverter and the second type inverter and a ground, or set between the common connection point and a power source. For this purpose, a transistor was connected.
According to a third invention, two latch circuits of the first invention are connected in series, and the first clock terminal of the preceding latch circuit and the second clock terminal of the succeeding latch circuit are the master clock terminal and the slave clock. The first clock terminal of the latch circuit in the previous stage and the first clock terminal of the latch circuit in the rear stage are connected in common to one of the terminals, and the other.
A fourth invention comprises a CMOS inverter circuit, a through current prevention transistor connected in series to each transistor of the CMOS inverter circuit, and a clock transistor connected in series to one of the through current prevention transistors. 3 types of inverters, a CMOS inverter circuit, and a fourth type inverter composed of a through-current preventing transistor connected in series to each transistor of the CMOS inverter circuit, and the third type inverter is connected to the input terminal. In addition to connecting to the multiple stage series, the fourth type inverter is connected to the multiple stage series in the subsequent stage, the gate of the clock transistor of each of the third type inverters is connected to a common clock terminal, and the third type For preventing through current of the inverter in the foremost stage The gate of the transistor is connected to the output side of the inverter of the even number stage subsequent to the inverter, and the gate of the through current prevention transistor of the last stage inverter of the fourth type inverter is connected to the inverter of the even number stage preceding the inverter. Connected to the input side, the gate of the through-current prevention transistor of the inverter at the other stage is connected to the input side of the inverter at the preceding stage of the even stage or the output side of the inverter at the subsequent stage of the even stage.
According to a fifth invention, in the fourth invention, a reset transistor is connected between a common connection point of the third type inverter and the fourth type inverter and a ground, or set between the common connection point and a power source. A transistor was connected.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
FIG. 1 is a diagram showing a static latch circuit L1 according to a first embodiment of the present invention. Reference numerals 31 and 32 denote the first type inverter having the configuration shown in FIG. 2, reference numerals 33 and 34 denote the second type inverter composed of only a pMOS transistor and an nMOS transistor, MN31 denotes a reset nMOS transistor, and MN32 denotes a feedback (holding) ) NMOS transistor. 35 is an input terminal, 36 is an output terminal, 37 is an inverted output terminal, 38A is a clock terminal, 38B is an inverted clock terminal, and 39 is a reset terminal.
[0015]
In FIG. 2 showing the first type inverters 31 and 32, MP1 and MN1 are pMOS and nMOS transistors constituting a CMOS inverter circuit, MP2 and MN2 are pMOS and nMOS transistors for preventing through current, and MN3 Is a clock nMOS transistor. Reference numeral 311 denotes an input terminal, 312 denotes an output terminal, 313 denotes a through current control terminal, and 314 denotes a clock terminal. As shown in the figure, the through current prevention transistors MP2 and MN2 are connected to the most power supply side and the ground side, and the drain of the clock transistor MN3 is connected to the output terminal 312. If the clock transistor MN3 is thus connected to the inside, the influence of leakage of the transistor MN1 constituting the CMOS inverter can be mitigated. That is, when the transistor MN1 is inverted from off to on, the influence of charge leakage on the diffusion capacitance located between the transistors MN1 and MN2 can be reduced.
[0016]
In the latch circuit L1 of FIG. 1, the inverter 31 inputs the output signal of the inverter 33 in the second stage after that to the through current control terminal 313, and the inverter 32 passes the output signal of the inverter 34 in the second stage after that. The current is input to the current control terminal 313.
[0017]
When the clock terminal 38A is "L", the clock terminal 38B is "H" (latched state), and the reset terminal 39 is "L" (non-reset state), the output terminal 36 is "H" and the inverted output terminal 37 Is assumed to be “L”.
[0018]
At this time, since the feedback transistor MN32 is on, the output “H” of the inverter 34 is fed back to the inverter 33, and the data “H” is held. In the first-stage inverter 31, the output “L” of the inverter 33 is input to the through current control terminal 313, so that the transistor MP2 is on and the MN2 is off. In the inverter 32 at the next stage, the output “H” of the inverter 34 is input to the through current control terminal 313. Conversely, the transistor MP2 is off and the MN2 is on.
[0019]
Next, when the clock terminal 38A is inverted to “H” and 38B is inverted to “L”, the feedback transistor MN32 is turned off, and the transistor MN3 of the inverters 31 and 32 is turned on. Therefore, if data “L” is input to the input terminal 35 at this time, the output of the inverter 31 becomes “H” in combination with the transistor MP1 being turned on and the transistor MP2 being turned on in advance. As a result, the output of the inverter 32 becomes “L” in combination with the transistor MN1 being turned on and the transistors MN2 and MN3 being turned on in advance.
[0020]
As described above, when the clock terminal 38A is “H” and 38B is “L”, if the input terminal 35 is “L”, the inverters 31 to 34 are inverted, and the output terminal 36 is “L”. The output terminal 37 becomes “H”. At this time, since the through current control terminal 313 of the inverter 31 changes to “H” and the through current control terminal 313 of the inverter 32 changes to “L” after a delay of two inverter stages, the transistor MP2 is turned off in the inverter 31. The transistor MN2 is turned on, and the inverter 32 is turned on and the transistor MN2 is turned off to cut off the power line and the ground line.
[0021]
Next, when the clock terminal 38A is inverted to “L” and 38B is inverted to “H”, the feedback transistor MN32 is turned on and the “L” state of the output terminal 36 and the “H” state of the inverted output terminal 37 are maintained.
[0022]
Further, when the clock terminal 38A is inverted to “H” and 38B is inverted to “L”, the feedback transistor MN32 is turned off and the transistor MN3 of the inverters 31 and 32 is turned on as described above. Therefore, when data “H” is input to the input terminal 35 at this time, the transistor 31 of the inverter 31 is turned on and its output becomes “L”, and thus the inverter 32 has its transistor MP1 turned on and its output is “H”. "become.
[0023]
At the time of this inversion, since the transistor MP1 of the inverter 31 is turned off in advance, the through current does not flow. Also, since the transistor MN1 of the inverter 32 is turned off in advance, no through current flows.
[0024]
That is, in the latch circuit L1 shown in FIG. 1, the through current control terminal 313 of the inverters 31 and 32 is controlled by the held data, and input data for creating a state different from the current state is input and inverted. When doing so, the line of the pMOS or nMOS transistor to be turned off based on the data is blocked in advance by the transistor for preventing through current, so that no through current flows in the inverters 31 and 32.
[0025]
3A is a diagram showing a master-slave type DFF circuit configured using the latch circuit L1 shown in FIG. 1, and FIG. 3B is a diagram showing its operation waveform. Reference numeral 41 is an input terminal, 42 and 43 are output terminals, 44M is a master clock terminal, 44S is a slave clock terminal, and 45 is a reset terminal.
[0026]
In the latch circuit L1 constituting this DFF circuit, it is only necessary to control the clock terminal 38A to “H” at the time of data writing and only to control the clock terminal 38B to “H” at the time of data holding. The clock signals CKM and CKS input to the clock terminal 44M and the slave clock terminal 44S do not need to fully swing from the ground potential VSS to the power supply potential VDD. Vtn is the threshold voltage of the nMOS transistor. As this Vtn, a fraction of a full swing is sufficient.
[0027]
Therefore, the power consumption of the clock driver circuit, which has been a factor of increasing the power consumption in the conventional MOS-LSI, can be greatly reduced, and the time required for inversion of the clock signal can be shortened. Contribute to.
[0028]
[Second Embodiment]
FIG. 4 is a diagram showing another latch circuit L1 ′ obtained by modifying the latch circuit L1 shown in FIG. Here, unlike the above-described latch circuit L1, modified first type inverters 46 and 47 are used, and a pMOS transistor is used for the clock. Further, a pMOS transistor MP31 is used for resetting, and a pMOS transistor MP32 is used for holding data. In this latch circuit L1 ', just like the latch circuit L1, data is held when the clock terminal 38A is "H" and 38B is "L", and when the clock terminal 38A is "L" and 38B is "H". Data capture is performed. Reference numeral 39 'denotes a set terminal. When this is set to "L", the output terminal 36 is set to "H" and the inverted output terminal 37 is set to "L".
[0029]
FIG. 5 is a specific circuit diagram of the modified first type inverters 46 and 47. In the figure, MP4 and MN4 are pMOS and nMOS transistors constituting the CMOS inverter circuit, MP5 and MN5 are pMOS and nMOS transistors for preventing through current, and MP6 is a clock pMOS transistor. Reference numeral 461 denotes an input terminal, 462 denotes an output terminal, 463 denotes a through current control terminal, and 464 denotes a clock terminal. As shown in the figure, the through current preventing transistors MP5 and MN5 are connected to the most power supply side and the ground side, and the drain of the clock transistor MP6 is connected to the output terminal 462.
[0030]
6A is a diagram illustrating a master-slave type DFF circuit configured using the latch circuit L1 ′ illustrated in FIG. 4, and FIG. 6B is a diagram illustrating operation waveforms thereof. The same reference numerals are given to the same components as those shown in FIG. Reference numeral 45 ′ denotes a set terminal for setting the interior by setting it to “L”.
[0031]
In the latch circuit L1 ′ constituting this DFF circuit, the clock terminal 38B only needs to be controlled to “L” when data is written, and the clock terminal 38A only needs to be controlled to “L” when data is held. The clock signals input to the master clock terminal 44M and the slave clock terminal 44S do not need to fully swing from the power supply potential VDD to the ground potential VSS, but may swing from the power supply potential VDD as much as less than VDD−Vtp. Vtp is a threshold voltage of the pMOS transistor. For this Vtp, an amplitude that is a fraction of the full swing is sufficient.
[0032]
Therefore, even when the latch circuit L1 ′ of the second embodiment is used for the master-slave type DFF circuit, the power consumption of the clock driver circuit can be greatly reduced and the time required for the inversion of the clock signal can be reduced. This contributes to a faster circuit operation.
[0033]
[Third Embodiment]
FIG. 7 is a diagram showing a configuration of a dynamic latch circuit L2 according to the third embodiment. Here, the third type inverters 51 and 52 and the fourth type inverters 53 to 56 shown in FIG. 8 are connected in series. Inverters 51 and 52 constitute a latch unit, and inverters 53 to 56 constitute a delay unit. Reference numeral 57 is an input terminal, 58 to 61 are output terminals, 62 is a clock terminal, and 63 is a reset terminal.
[0034]
As shown in FIG. 8A, the third type of inverters 51 and 52 include pMOS and nMOS transistors MP7 and MN7, a pMOS for preventing through current, and nMOS transistors MP8 and MN8, which constitute a CMOS inverter circuit. The clock nMOS transistor MN9 is used. Reference numeral 511 denotes an input terminal, 512 denotes an output terminal, 513 denotes a through current control terminal, and 514 denotes a clock terminal. FIG. 8B shows a symbol.
[0035]
As shown in FIG. 9A, the fourth type of inverters 53 to 56 are composed of pMOS and nMOS transistors MP10 and MN10, pMOS for preventing through current, and nMOS transistors MP11 and MN11 constituting the CMOS inverter circuit. It is configured. Reference numeral 531 denotes an input terminal, 532 denotes an output terminal, and 533 denotes a through current control terminal. FIG. 9B shows a symbol.
[0036]
In this latch circuit L 2, the through current control terminal 513 of the inverter 51 receives the output of the inverter 55 in the fourth stage and the through current control terminal 513 of the inverter 52 receives the output of the inverter 56 in the fourth stage. The current control terminal 533 receives the output of the inverter 55 in the second stage, the through current control terminal 533 of the inverter 54 receives the output of the inverter 56 in the second stage, and the through current control terminal 533 of the inverter 55 is the inverter in the second stage. 53, the through current control terminal 533 of the inverter 56 receives the input of the inverter 54 at the preceding stage. That is, the front-stage inverter 51 receives the output signal of the even-numbered-stage subsequent-stage inverter, the last-stage inverter 56 receives the input signal of the even-numbered-stage previous-stage inverter, and the other inverters 52 to 55 output the output of the even-numbered-stage subsequent-stage inverter. Receives the signal or the input signal of the inverter at the preceding stage of the even number stage.
[0037]
When the clock terminal 62 is “L” and the reset terminal 63 is “H”, the transistor MN51 is turned on, the output terminal 58 is “L”, the output of the inverter 53 is “H”, and the output terminal 59 is The output of the inverter 55 is “H”, the output terminal 61 is “H”, the output of the inverter 56 is “L”, and the output terminal 60 is “L”. This state is a reset state.
[0038]
At this time, since the through current control terminal 513 of the inverter 51 becomes “H”, the through current prevention transistor MP8 is turned off and the MN8 is turned on, and the inverter 52 has its through current control terminal 513 of “L”. The through current prevention transistor MP8 is turned on and MN8 is turned off, and the inverter 53 has the through current control terminal 533 at “H”, so that the through current prevention transistor MP11 is turned off and the MN11 is turned on, and the inverter 54 is turned on. Since 533 becomes “L”, the through current prevention transistor MP11 is turned on and MN11 is turned off, and since the through current control terminal 533 of the inverter 55 becomes “H”, the through current prevention transistor MP11 is turned off and MN11 is turned on. The inverter 56 is turned on and the through current control terminal 533 is set to “L”. Since the, the through current prevention transistor MP11 is turned on, MN11 is turned off.
[0039]
Next, when data of “H” is input to the input terminal 57, the transistor MN8 of the inverter 51 is turned on before this time, and the transistor MP8 of the inverter 52 is turned on, so that the clock terminal 62 is “H” and the reset terminal 63 is turned on. Becomes “L”, the output of the inverter 51 becomes “L” and the output of the inverter 52 becomes “H”. Further, the transistor MP11 of the inverters 53 and 55 is turned on in advance, the MN11 is turned off, and further, the transistor MP11 of the inverters 54 and 56 is turned off in advance and the MN11 is turned on. Are inverted to “L”, “H”, “L”, and “H”, respectively.
[0040]
As described above, since the through-current preventing transistor connected in series to the pMOS or nMOS that is turned off from the on-state by the inversion of the input signal is turned off in advance, the through-current flows in each inverter 51 to 56 at the time of the inversion. There is nothing. Also, the inverters 51 and 52 were delayed by four stages of inverters from the inversion, and the inverters 53 and 54 were turned off by turning off the through-current prevention transistors that were turned on after the delay of the two-stage inverters. The through current prevention transistor is turned on. The inverters 55 and 56 are turned off after the through-current preventing transistor is turned on and turned off, and then inverted after the delay of the two-stage inverter.
[0041]
As described above, the “H” data input to the input terminal 57 is taken in at the timing when the clock terminal 52 becomes “H”, and the “H” data is output from the output terminal 58 to the output terminal 59. "L" data is output by inverting. This is output to the output terminal 60 after being delayed by the inverters 53 to 56, and is output to the output terminal 61 after being delayed and inverted by the inverters 53 to 55.
[0042]
Next, after the data “H” is captured from the input terminal 57, the data is retained even if the clock terminal 62 is inverted to “L”. That is, when the clock terminal 62 becomes “L”, even if the data at the input terminal 57 is subsequently inverted to “L”, the inverter 51 is inverted and its output is set to “H”. Since MN9 is off, it cannot be inverted and the output data is held by the parasitic capacitance of the output terminal 58, so the data of the output terminals 58 to 61 does not change.
[0043]
Note that the above is the case where “H” data is input to the input terminal 57. Similarly, even when “L” data is input, when the clock terminal 62 becomes “H”, When data is taken in and the clock terminal 62 is set to “L”, the data is held.
[0044]
As described above, the latch circuit L2 according to the third embodiment is simply controlled by a single-phase clock. Therefore, when configuring a CMOS sequential circuit such as a register, the clock driver and clock wiring are only single-phase. As in the latch circuit L1 of the first embodiment, the amplitude from VSS to VSS + Vtn is sufficient. In addition, since it is composed of only a CMOS gate that can prevent a through current, power consumption can be greatly reduced.
[0045]
[Fourth Embodiment]
FIG. 10 is a diagram showing a configuration of a dynamic latch circuit L2 ′ according to the fourth embodiment. Here, the modified third type inverters 71 and 72 shown in FIG. 11 and the aforementioned fourth type inverters 53 to 56 are connected in series. MP51 is a set pMOS transistor, and 63 'is a set terminal. Others are the same as those shown in FIG.
[0046]
As shown in FIG. 11A, the modified third type inverters 71 and 72 include pMOS and nMOS transistors MP12 and MN12, pMOS for preventing through current, and nMOS transistors MP13 and MN13 that constitute a CMOS inverter circuit. , And a clock pMOS transistor MP14. Reference numeral 711 denotes an input terminal, 712 denotes an output terminal, 713 denotes a through current control terminal, and 714 denotes a clock terminal. FIG. 11B shows symbols of these inverters 71 and 72.
[0047]
In the latch circuit L2 ′, when the set terminal 73 ′ is “L”, the output terminals 58 and 60 are set to “H”, and the output terminals 59 and 61 are set to “L”. Further, when the clock terminal 62 is “L”, the data to be input to the input terminal 57 is fetched, and the data is held during the period when the clock terminal 62 is “H”. Other delay operations and through current prevention operations are the same as those of the latch circuit L2 of the third embodiment. Therefore, the latch circuit L2 ′ can be controlled only by a single-phase clock, and the through current is prevented, similarly to the latch circuit L2. As with the latch circuit L1 ′ of the second embodiment, the clock signal is sufficient if the amplitude is lower than VDD by VDD−Vtp.
[0048]
【The invention's effect】
As described above, according to the first to fifth aspects of the present invention, it is possible to prevent a through current when data is inverted, thereby reducing current consumption. In addition, since the clock to be used does not need to fully swing from VSS to VDD, the power consumption of the clock driver can be reduced and high speed operation is possible. Furthermore, according to the fourth and fifth inventions, the clock is only required for a single phase, so that the number of wirings is reduced and the area is reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a static latch circuit according to a first embodiment;
FIG. 2 is a circuit diagram of a first type inverter constituting the latch circuit of FIG. 1;
3A is a circuit diagram of a master-slave type DFF circuit constituted by the latch circuit of FIG. 1, and FIG. 3B is an operation waveform diagram thereof.
FIG. 4 is a circuit diagram showing a static latch circuit according to a second embodiment.
FIG. 5 is a circuit diagram of a modified first type inverter constituting the latch circuit of FIG. 4;
6A is a circuit diagram of a master-slave type DFF circuit constituted by the latch circuit of FIG. 4, and FIG. 6B is an operation waveform diagram thereof.
7 is a circuit diagram illustrating a dynamic latch circuit according to a third embodiment; FIG.
8A is a circuit diagram of a third type of inverter constituting the latch circuit of FIG. 7, and FIG. 8B is a diagram illustrating symbols thereof;
9A is a circuit diagram of a fourth type of inverter constituting the latch circuit of FIG. 7, and FIG. 9B is a diagram showing symbols thereof;
FIG. 10 is a circuit diagram illustrating a dynamic latch circuit according to a fourth embodiment.
11A is a circuit diagram of a modified third type inverter that constitutes the latch circuit of FIG. 10, and FIG. 11B is a diagram illustrating symbols thereof;
FIG. 12 is a circuit diagram of a conventional static latch circuit.
FIG. 13 is a circuit diagram of a conventional dynamic latch circuit.
14A is a circuit diagram of a master-slave type DFF circuit using the latch circuit of FIG. 12, and FIG. 14B is an operation waveform diagram thereof.
15A is a circuit diagram of a register using the latch circuit of FIG. 12, and FIG. 15B is an operation waveform diagram thereof.
16A and 16B are circuit diagrams of a delay circuit of the register of FIG.
[Explanation of symbols]
L3: Static latch circuit, L4: Dynamic latch circuit, 1, 2: Transfer gate, 3: NAND gate, 4, 5: Inverter, 6: Input terminal, 7, 8: Output terminal, 9: Clock terminal 10: Reset terminal, 11: Input terminal, 12, 13: Output terminal, 14M, 14S: Clock terminal, 15: Reset terminal, 21: Input terminal, 22-25: Output terminal, 26: Clock terminal, 27: Reset Terminal, 28: inverter, 29: transfer gate,
L1, L1 ′: static type latch circuit 31, 32: first type inverter, 311; input terminal, 312: output terminal, 313: through current control terminal, 314: clock terminal, 33, 34: second type 35: input terminal, 36, 37: output terminal, 38A, 38B: clock terminal, 39: reset terminal, 39 ′: set terminal, 41: input terminal, 42, 43: output terminal, 44M, 44S: clock Terminal, 45: reset terminal, 45 ′: set terminal, 46, 47: modified first type inverter, 461: input terminal, 462: output terminal, 463: through current control terminal, 464: clock terminal,
L2, L2 ': Dynamic latch circuit 51, 52: Third type inverter, 511: Input terminal, 512: Output terminal, 513: Through current control terminal, 514: Clock terminal, 53-56: Fourth type Inverter, 531: Input terminal, 532: Output terminal, 533: Through current control terminal, 57: Input terminal, 58 to 61: Output terminal, 62: Clock terminal, 63: Reset terminal, 63 ′: Set terminal, 71, 72: Modified third type inverter 711: Input terminal 712: Output terminal 713: Through current control terminal 714: Clock terminal

Claims (5)

A first inverter comprising a CMOS inverter circuit, a through current prevention transistor connected in series to each of the transistors of the CMOS inverter circuit, and a clock transistor connected in series to one of the through current prevention transistors; Including a second type inverter composed of a CMOS inverter circuit and a feedback transistor;
The first type inverter is connected to the input terminal in a multi-stage series, and the second type inverter is connected to the multi-stage series in the subsequent stage.
Connecting the feedback transistor so as to straddle an even number of stages of the second type inverter connected in multiple stages;
The gate of the clock transistor of the first type inverter is connected to a first clock terminal, and a clock whose phase is inverted with respect to the clock input to the gate of the feedback transistor is input to the first clock terminal. Connect to the clock terminal,
The gate of the through current prevention transistor of the first type inverter is connected to the output side of the inverter at the subsequent stage of the even number stage from the inverter.
A latch circuit characterized by the above. A reset transistor is connected between a common connection point of the first type inverter and the second type inverter and a ground, or a setting transistor is connected between the common connection point and a power source. The latch circuit according to Item 1. Two of the latch circuits of claim 1 are connected in series, and the first clock terminal of the preceding latch circuit and the second clock terminal of the succeeding latch circuit are commonly connected to one of the master clock terminal and the slave clock terminal. A master-slave type DFF circuit, wherein the second clock terminal of the latch circuit in the preceding stage and the first clock terminal of the latch circuit in the subsequent stage are connected in common to the other. A third inverter comprising a CMOS inverter circuit, a through-current preventing transistor connected in series to each of the transistors of the CMOS inverter circuit, and a clock transistor connected in series to one of the through-current preventing transistors; A CMOS inverter circuit, and a fourth type inverter composed of a through-current prevention transistor connected in series to each of the transistors of the CMOS inverter circuit,
The third type inverter is connected to the input terminal in a multiple stage series, and the fourth type inverter is connected to the subsequent stage in a multiple stage series.
A gate of a clock transistor of each of the third type inverters is connected to a common clock terminal;
The gate of the through current prevention transistor of the first-stage inverter of the third type inverter is connected to the output side of the even-numbered-stage subsequent-stage inverter from the inverter, and the rearmost-stage inverter of the fourth-type inverter The through-current prevention transistor gate of the inverter is connected to the input side of the inverter of the even-numbered stage before the inverter, and the through-current prevention transistor gate of the inverter of the other stage is connected to the input side of the inverter of the even-numbered stage before the inverter or Connected to the output side of the inverter of the even numbered stage,
A latch circuit characterized by the above. The reset transistor is connected between a common connection point of the third type inverter and the fourth type inverter and the ground, or a set transistor is connected between the common connection point and a power source. 4 latch circuit.

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