JP3680091B2 - Random number generator - Google Patents

Description

【００１４】
となる。実際ａが0.５近辺の値を取った場合、ｂはどうなるか計算して図７に示す。
【００１５】
ａ、ｂの0.５との差分と0.５との比率を以下では、乱数の偏差と表現することとする。図７を見ると分かるように、素乱数の偏差が１％の場合で、出力した乱数の偏差は１０^-6と非常に小さくできる。
【００１６】
本発明で採用している反転トリガ信号生成機構は、反転トリガ信号生成機構に入力する素乱数が１の時に同期して反転トリガ信号を０から１又は１から０へ切り替え、素乱数が０の時は反転トリガ信号を変化させない。素乱数の乱数列には規則性が無いため、生成した反転トリガ信号は０と１の出現比率は理論上均等になる。図６は、素乱数２１とこの素乱数２１を元に生成した反転トリガ信号２２の関係の一例を信号の波形で表している。信号の波形が上にある時の信号の値が１を表し、信号の波形が下にある時の信号の値が０を表す。素乱数２１は０の出現比率が高いが、反転トリガ信号２２は０と１の出現比率はほぼ等しくなっているのがわかる。
【００１７】
反転トリガ信号の規則性は、素乱数の偏差と同程度の影響がある。なぜなら、規則性の一つである０の後１になる確率、１の後０になる確率は、素乱数の１が出現する確率に等しいからである。しかし、後述する実施の形態で見てみた場合、うまく回路を構成することによって、アナログ・デジタル変換機構の出力のうち、偏差が１〜２％程度の素乱数を得ることが可能であり、前述したように、この程度の偏差が出力の偏差に与える影響は非常に小さくできる。また、規則性が存在するソフトウェア乱数と組み合わせて乱数を生成しても、乱数性の高い乱数が得られる。
【００１８】
【発明の実施の形態】
以下、本発明の実施の形態を図面を参照しながら詳細に説明する。
【００１９】
図１は、本発明の一実施の形態である乱数生成装置の構成の一例を示す概念図である。本実施の形態の乱数生成装置は、経時的に不規則なノイズ１８Ａを発生するダイオード１０Ａ、ノイズ１８Ａを素乱数１６Ａ〜１６Ｄのディジタルデータに変換するアナログ・デジタル変換機構１２Ａ、反転トリガ信号１７Ａ〜１７Ｄを生成する反転トリガ信号生成機構１４、アナログ・デジタル変換機構１２Ａおよび反転トリガ信号生成機構１４にクロック信号１９を供給するクロック発生機構１１、乱数を使用する外部の任意の情報処理装置等との間のインタフェースを提供する乱数データまとめ部１５、を含んでいる。
【００２０】
すなわち、ダイオード１０Ａが出力するノイズ１８Ａをアナログ・デジタル変換機構１２Ａに入力する。アナログ・デジタル変換機構１２Ａの出力する素乱数のうちの素乱数１６Ａ〜１６Ｄを反転機構１３Ａ〜１３Ｂのデータ入力に、反転トリガ信号生成機構１４の出力する反転トリガ信号１７Ａ〜１７Ｂは、反転機構１３Ａ〜１３Ｂの反転トリガ入力に接続する。反転機構の１３Ａの出力は、乱数データまとめ部１５に接続する。
【００２１】
このような構成の本実施の形態の乱数生成装置の動作としては、まず、アナログ・デジタル変換機構１２Ａは、クロック信号１９に同期して、ノイズ１８Ａの電圧をデジタル・データに変換する。このデジタル・データから素乱数１６Ａ〜１６Ｄを取り出す。反転機構１３Ａ〜１３Ｂは、素乱数１６Ａ〜１６Ｄと反転トリガ信号生成機構１４の出力する反転トリガ信号１７Ａ〜１７Ｂの排他的論理和を出力し、乱数データまとめ部１５に送る。乱数データまとめ部１５は、外部からの要求でデータを取り出しやすいように加工し、２進乱数データ１５ａとして出力する。素乱数のビット数と反転機構の数は同じだが、反転トリガ信号はそれと異なっても構わない。
【００２２】
図２は、前述の図１に例示された乱数生成装置のより具体的な変形例を示す概念図である。すなわち、この図２の構成例は、図１の反転トリガ信号生成機構１４の実現方法の一つを提示している。
【００２３】
この図２の構成では、反転トリガ信号生成機構１４は、複数の反転トリガ信号更新論理１４０Ａ〜１４０Ｂおよび反転トリガ信号レジスタ１４１Ａ〜１４１Ｂを含んでいる。そして、アナログ・デジタル変換機構１２Ａの出力する素乱数のうち反転機構１３Ａ〜１３Ｂに直接送られなかった素乱数１６Ｅ〜１６Ｆを、それぞれ反転トリガ信号生成機構１４内の反転トリガ信号更新論理１４０Ａ〜１４０Ｂに接続する。反転トリガ信号更新論理１４０Ａ〜１４０Ｂの出力はそれぞれ反転トリガ信号レジスタ１４１Ａ〜１４１Ｂに接続し、反転トリガ信号レジスタ１４１Ａ〜１４１Ｂの出力する反転トリガ信号１７Ａ〜１７Ｂは、反転機構１３Ａ〜１３Ｂのいずれかの反転トリガ入力と、それぞれ反転トリガ信号更新論理１４０Ａ〜１４０Ｂに接続する。
【００２４】
この図２の変形例の動作としては、反転トリガ信号更新論理１４０Ａは、反転トリガ信号１７Ａと素乱数１６Ｅの排他的論理和を出力する。反転トリガ信号レジスタ１４１Ａは、クロック信号１９に同期して、保持する値を反転トリガ信号更新論理１４０Ａの出力に置き換える。反転トリガ信号更新論理１４０Ｂと反転トリガ信号１７Ｂ、素乱数１６Ｆ、反転トリガ信号レジスタ１４１Ｂの動作も同様である。このようにして、反転トリガ信号１７Ａ、１７Ｂを生成する以外は図１の説明と同様である。
【００２５】
図３は、本発明の他の実施の形態である乱数生成装置の構成の一例を示す概念図である。この図３の構成の場合、アナログ・デジタル変換機構１２Ａは８ビット出力のものとし、アナログ・デジタル変換機構１２Ａの出力する８個の素乱数のうち１個の素乱数１６Ａを１個の反転機構１３Ａのデータ入力に、別の１個の素乱数１６Ｂを反転トリガ信号生成機構１４内の１個の反転トリガ信号更新論理１４０Ａに接続する。反転トリガ信号更新論理１４０Ａの出力は反転トリガ信号レジスタ１４１Ａに接続し、反転トリガ信号レジスタ１４１Ａの出力する反転トリガ信号１７Ａは、反転機構１３Ａの反転トリガ入力と、反転トリガ信号更新論理１４０Ａの入力側に接続する。
【００２６】
反転機構１３Ａの出力は、乱数データまとめ部１５内のシフト・レジスタ１５０に接続し、シフト・レジスタ１５０の出力は、乱数データまとめ部１５内の乱数データ・バッファ１５２に接続する。乱数データまとめ部１５内のデータまとめ部制御論理１５１の出力は、乱数データ・バッファ１５２に接続する。クロック発生機構１１が出力するクロック信号１９は、アナログ・デジタル変換機構１２Ａと、反転トリガ信号レジスタ１４１Ａと、シフト・レジスタ１５０と、データまとめ部制御論理１５１に接続する。
【００２７】
この図３の構成の乱数生成装置の動作としては、まず、アナログ・デジタル変換機構１２Ａは、クロック信号１９に同期して、ノイズ１８Ａの電圧を８ビットのデジタル・データに変換する。このデジタル・データから２個の素乱数１６Ａと１６Ｂを取り出す。反転トリガ信号更新論理１４０Ａは、反転トリガ信号１７Ａと素乱数１６Ｂの排他的論理和を出力する。反転トリガ信号レジスタ１４１Ａは、クロック信号１９に同期して、保持する値を反転トリガ信号更新論理１４０Ａの出力に置き換える。反転機構１３Ａは、素乱数１６Ａと反転トリガ信号１７Ａの排他的論理和を出力し、シフト・レジスタ１５０に入力する。シフト・レジスタ１５０は、８ビットのシフト・レジスタで、クロック信号１９に同期してシフト動作と、反転機構１３Ａの出力の取り込みを行う。シフト・レジスタ１５０は、８ビット幅の出力を乱数データ・バッファ１５２に送り、データまとめ部制御論理１５１は、クロック信号１９に同期して、８サイクルに１回、乱数データ・バッファ１５２に書き込み指示を行う。乱数データ・バッファ１５２は、書き込み指示を受けた時のシフト・レジスタ１５０からのデータ（２進乱数データ１５ａ）を記憶する。また乱数データ・バッファ１５２は、外部からの読み出し要求に対して、２進乱数データ１５ａの書き出しと、書き出した２進乱数データ１５ａの消去を行う機能と、たとえばＰＣＩ等の汎用バス等に対する接続インターフェースを有し、８ビットの乱数データ（２進乱数データ１５ａ）を外部の任意の装置等に供給することができる。
【００２８】
図４は本発明の他の実施の形態である乱数生成装置の構成の一例を示す概念図である。この図４の構成では、反転トリガ信号生成機構１４に対する素乱数の入力手段として専用のダイオード１０Ｂおよびアナログ・デジタル変換機構１２Ｂを設けた構成となっている。
【００２９】
すなわち、反転機構１３Ａ〜１３Ｂに接続する素乱数１６Ａ〜１６Ｂに、ダイオード１０Ａが出力するノイズ１８Ａをアナログ・デジタル変換機構１２Ａがアナログ・デジタル変換した出力を用い、反転トリガ信号生成機構１４内の反転トリガ信号更新論理１４０Ａ〜１４０Ｂに接続する素乱数１６Ｅ〜１６Ｆに、ダイオード１０Ｂが出力するノイズ１８Ｂをアナログ・デジタル変換機構１２Ｂがアナログ・デジタル変換した出力を用いている。
【００３０】
この図４の構成では、複数のダイオード１０Ａおよび１０Ｂと、アナログ・デジタル変換機構１２Ａおよび１２Ｂの組合せを２系統用意したことにより、複数の反転機構１３Ａおよび１３Ｂに入力される素乱数１６Ａおよび１６Ｂと、反転トリガ信号１７Ａおよび１７Ｂとの間の相関を無くすことが可能となり、最終的に乱数データまとめ部１５から出力される２進乱数データ１５ａにおいてより高い乱数性を実現することができる。
【００３１】
図５は、図４に例示した本発明の乱数生成装置の変形例を示す概念図である。この図５の構成では、ダイオード１０Ａおよびアナログ・デジタル変換機構１２Ａと、ダイオード１０Ｂおよびアナログ・デジタル変換機構１２Ｂ、の２系列の素乱数１６Ａ、素乱数１６Ｂ、および素乱数１６Ｇ、素乱数１６Ｈ、に対して、対応した反転機構１３Ａ、１３Ｂおよび反転機構１３Ｃ、１３Ｄを設けるとともに、反転機構１３Ａ、１３Ｂおよび反転機構１３Ｃ、１３Ｄの各々に対する反転トリガ信号１７Ａおよび反転トリガ信号１７Ｂが、互いに他方のアナログ・デジタル変換機構１２Ｂおよび１２Ａから発生された素乱数１６Ｅおよび素乱数１６Ｊにてクロスして生成される構成としたものである。
【００３２】
すなわち、ダイオード１０Ａが出力するノイズ１８Ａを８ビット出力のアナログ・デジタル変換機構１２Ａに入力する。ダイオード１０Ｂが出力するノイズ１８Ｂを８ビット出力のアナログ・デジタル変換機構１２Ｂに入力する。アナログ・デジタル変換機構１２Ａの出力する８個の素乱数のうち１個の素乱数１６Ａを反転機構１３Ａのデータ入力に、１個の素乱数１６Ｂを反転機構１３Ｂのデータ入力に、１個の素乱数１６Ｃを反転トリガ信号生成機構１４内の反転トリガ信号更新論理１４０Ｂに接続する。アナログ・デジタル変換機構１２Ｂの出力する８個の素乱数のうち１個の素乱数１６Ｇを反転機構１３Ｃのデータ入力に、１個の素乱数１６Ｈを反転機構１３Ｄのデータ入力に、１桁の素乱数１６Ｊを反転トリガ信号生成機構１４内の反転トリガ信号更新論理１４０Ａに接続する。反転トリガ信号更新論理１４０Ａの出力は反転トリガ信号レジスタ１４１Ａに接続し、反転トリガ信号レジスタ１４１Ａの出力する反転トリガ信号１７Ａは、反転機構１３Ａ、１３Ｂの反転トリガ入力と、反転トリガ信号更新論理１４０Ａの入力側に接続する。反転トリガ信号更新論理１４０Ｂの出力は反転トリガ信号レジスタ１４１Ｂに接続し、反転トリガ信号レジスタ１４１Ｂの出力する反転トリガ信号１７Ｂは、反転機構１３Ｃ、１３Ｄの反転トリガ入力と、反転トリガ信号更新論理１４０Ｂに接続する。反転機構の１３Ａ、１３Ｂ、１３Ｃ、１３Ｄの出力は、乱数データまとめ部１５に接続する。クロック発生機構１１が出力するクロック信号１９は、アナログ・デジタル変換機構１２Ａ、１２Ｂと、反転トリガ信号レジスタ１４１Ａ、１４１Ｂと、乱数データまとめ部１５に接続する。前述の図３の実施の形態と異なるのは、
（１）ダイオードとアナログ・デジタル変換機構が２個ずつあること、
（２）１個のアナログ・デジタル変換機構に対して、２個の反転機構を備え、２個の素乱数を１個ずつ、それぞれの反転機構に入力していること、
（３）アナログ・デジタル変換機構１２Ａの出力する素乱数１６Ａ、１６Ｂの接続する、反転機構１３Ａ、１３Ｂに入力する反転トリガ信号１７Ａは、もう一方のアナログ・デジタル変換機構１２Ｂの出力する素乱数１６Ｊを利用して更新し、アナログ・デジタル変換機構１２Ｂの出力する素乱数１６Ｇ、１６Ｈの接続する、反転機構１３Ｃ、１３Ｄに入力する反転トリガ信号１７Ｂは、もう一方のアナログ・デジタル変換機構１２Ａの出力する素乱数１６Ｅを利用して更新していること、
である。
【００３３】
乱数データまとめ部１５内では図３の実施の形態と同じように、外からの読み出し要求に応答できるようにデータの形を整え記憶する。本実施の形態では、ダイオードから乱数データまとめ部１５の前までの回路を倍にし、利用する素乱数も倍にして乱数生成速度の性能を向上し、しかも反転トリガ信号１７Ａ、反転トリガ信号１７Ｂを更新するための素乱数１６Ｊ、１６Ｅを交換しあうことで、素乱数１６Ａ、１６Ｂおよび素乱数１６Ｇ、１６Ｈと、反転トリガ信号１７Ａ、１７Ｂを別系統の乱数源から生成するため、反転機構１３Ａ、１３Ｂおよび反転機構１３Ｃ、１３Ｄのデータ入力（素乱数１６Ａ、１６Ｂおよび素乱数１６Ｇ、１６Ｈ）、反転トリガ信号１７Ａ、１７Ｂの間の予期せぬ相関から規則性が生じることを回避している。
【００３４】
なお、上述の図２〜図５における乱数生成装置の構成例では、反転トリガ信号生成機構１４において反転トリガ信号１７Ａ、１７Ｂ等を生成するための素乱数は、ダイオード１０Ａ、１０Ｂおよびアナログ・デジタル変換機構１２Ａ、１２Ｂ等を用いてハードウェア的に得られた素乱数を用いているが、これに限らず、図８に例示されるように、ソフトウェア乱数生成装置３０において、たとえばＭ系列法、合同式法等の所望のアルゴリズムを用いたソフトウェアにて生成されたソフトウェア素乱数３０ａを、素乱数１６Ｂ、１６Ｅ、１６Ｆ、１６Ｊ、等の代わりに用いても、同様に、得られる２進乱数データ１５ａの生成速度が高速で、乱数列に規則性が無く、均質な０と１の出現比率を同時に実現することが可能になる。この場合、ソフトウェア乱数生成装置３０は、たとえば図示しないマイクロプロセッサや、乱数を生成するためのソフトウェア等が格納されるＲＯＭ、ＲＡＭ等を備えた一般的に情報処理装置で構成することができる。
【００３５】
さらに、図９のフローチャートに例示されるように、反転トリガ信号生成機構１４および反転機構１３Ａ〜１３Ｄ等で行われる素乱数１６Ａ、１６Ｂ、１６Ｈ、１６Ｇ等の反転処理を、当該素乱数１６Ａ〜１６Ｇを利用する任意の情報処理装置の内部で、ソフトウェア的に行わせることもできる。この場合、物理現象を利用する乱数発生機構としては、本発明の上述の実施の形態で例示したダイオード１０Ａ、アナログ・デジタル変換機構１２Ａ、乱数データまとめ部１５等で構成された、素乱数１６Ａ等をそのまま外部に出力する構成の物理乱数生成装置を用いることができる。
【００３６】
すなわち、任意の情報処理装置において、物理乱数生成装置から得られる素乱数１６Ａを用いるプログラムでは、前処理として、図９のフローチャートに例示された以下のような処理を行うことで乱数性の向上を達成することができる。
【００３７】
すなわち、まず、物理乱数生成装置から得られた素乱数１６Ａ（２進ハードウェア乱数）を、整数変数ＨＲに格納する（ステップ２０１）。
【００３８】
次に、自前のソフトウェアによる乱数発生ルーチンから２進ソフトウェア乱数を生成して整数変数ＳＲに格納する（ステップ２０２）。
【００３９】
整数変数ＳＲの各ビットを指定するためのビット指標変数ｎを０に初期化する（ステップ２０３）。だだし、ＳＲ〔ｎ＝０〕はＬＳＢを示す。
【００４０】
次に、ＳＲのＬＳＢ（ＳＲ〔ｎ＝０〕）を“０”との排他的論理和をとって更新する（ステップ２０４）。
【００４１】
その後、ビット指標変数ｎをインクリメントして（ステップ２０５）、ビット位置がＳＲのＭＳＢを越えたか否かを判定（ステップ２０６）しながら、ＳＲのＭＳＢ方向に隣接する第ｎビットと第ｎ−１ビットとの排他的論理和をとって当該第ｎビット位置のビット値を更新する（ステップ２０７）操作を、ＭＳＢまで反復し、このステップ２０７の操作が終わったら、整数変数ＨＲに格納された２進ハードウェア乱数と、整数変数ＳＲに格納された反転操作後の２進ソフトウェア乱数との間で各ビット毎の排他的論理和をとり、結果を整数変数ＨＲに書き戻す処理（ステップ２０８）、を行う。
【００４２】
これにより、整数変数ＨＲ内には、結果として、図１の乱数データまとめ部１５から得られる２進乱数データ１５ａと同様に、乱数列に規則性が無く、均質な０と１の出現比率を持つ、２進ハードウェア乱数が得られる。
【００４３】
この場合には、ソフトウェア的にビット反転処理を行うため、多少、生成速度は犠牲になるが、素乱数１６Ａを供給する物理乱数生成装置は任意のものを用いることができ、物理乱数を利用する情報処理装置のソフトウェアの側のわずかな変更で、高い乱数性を持つ物理乱数を使用できるようになる、という利点がある。また、生成速度の点も、物理乱数を利用する情報処理装置の実行速度が改善されれば問題にならなくなり、乱数生成の高速性の要求も満たされる。
【００４４】
以上説明したように、本実施の形態の乱数生成装置では、ハードウェアによる高速な生成速度の乱数生成処理において、０と１の出現比率については均等にでき、素乱数の偏差が最終的に出力される乱数の規則性へ与える影響を少なくすることができる。図７で示したとおり、乱数列の規則性の偏りは、素乱数の０と１の出現比率の偏りが２％の場合で１０^-5以下、１％で１０^-6に改善することができる。
【００４５】
本発明の特許請求の範囲に記載された以外のの特徴を列挙すれば以下の通りである。
【００４６】
＜１＞ ノイズ源としてのダイオードと、アナログ・デジタル変換機構と、乱数データまとめ部と、クロック発生機構を有し、クロック発生機構が発生するクロック信号を、前記アナログ・デジタル変換機構に接続し、前記ダイオードに逆バイアスをかけた場合のツェナー降伏領域もしくはアバランシェ領域で発生するノイズの電圧を、前記アナログ・デジタル変換機構で前記クロックに同期してｎビット（ｎ＞１）のデジタル・データに変換し、該デジタル・データのうちｍビット（１≦ｍ≦ｎ）を乱数データまとめ部で乱数として利用できる形にまとめる乱数生成装置において、
データ入力と反転トリガ入力の２個の入力を持つｍ個の反転機構と、反転トリガ信号生成機構を備え、該反転トリガ信号生成機構は、０と１が変化しながらほぼ同じ比率で現れる反転トリガ信号をｓ個（１≦ｓ≦ｍ）生成し、該ｓ個の反転トリガ信号を、合計ｍ個全ての前記反転機構の反転トリガ入力に１対１もしくは１対多で接続し、前記乱数データまとめ部に送られる直前のｍビットのデジタル・データを該ｍ個の反転機構のデータ入力に１対１で接続し、該ｍ個の反転機構はデータ入力と反転トリガ入力の排他的論理和を出力し、該出力を、前記アナログ・デジタル変換機構が出力したｍ桁のデジタル・データの代わりに前記乱数データまとめ部に送ることを特徴とする乱数生成装置。
【００４７】
＜２＞ 反転トリガ信号を保持するｓ個の反転トリガ信号レジスタと、ｓ個の反転トリガ信号更新論理を有し、
前記アナログ・デジタル変換機構の出力するデジタル・データのうちｓビットをｓ個の該反転トリガ信号更新論理全てに１対１で接続し、該反転トリガ信号更新論理は対応する反転トリガ信号レジスタが保持する反転トリガ信号と前記入力されたデジタル・データとの排他的論理和を出力し、前記反転トリガ信号レジスタに前記クロックを接続し、該反転トリガ信号レジスタが保持している反転トリガ信号を、クロックに同期して前記反転トリガ信号更新論理の出力に置き換え、該反転トリガ信号レジスタの保持している反転トリガ信号を出力することを特徴とする反転トリガ信号生成機構を備える項目＜１＞記載の乱数生成装置。
【００４８】
＜３＞ プログラム生成乱数を前記反転トリガ信号として出力する反転トリガ信号生成機構を有する、項目＜１＞記載の乱数生成装置。
【００４９】
＜４＞ 前記ダイオードと前記アナログ・デジタル変換機構の組み合わせを、前記反転機構のデータ入力に接続するものと、前記反転トリガ信号更新論理に接続するものを独立して２系統用意することを特徴とする項目＜２＞記載の乱数生成装置。
【００５０】
＜５＞ 前記ダイオードと前記アナログ・デジタル変換機構と反転機構の組み合わせを２系統有し、該反転機構の出力を別の反転機構のデータ入力と反転トリガ入力に接続することを特徴とする項目＜１＞記載の乱数生成装置。
【００５１】
＜６＞ 時間軸方向に不規則な物理量から２値の素乱数を生成するステップと、
０と１が変化しながらほぼ同じ比率で現れる反転トリガ信号を生成するステップと、
前記素乱数と前記反転トリガ信号との排他的論理和をとって２進乱数として出力するステップと、
を含むことを特徴とする乱数生成方法。
【００５２】
以上本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
【００５３】
たとえば、物理量発生手段としては、上述の実施の形態に例示したダイオードに限らず、時間軸方向に不規則な物理量を出力する一般の機器を広く用いることができる。
【００５４】
【発明の効果】
本発明の乱数生成装置によれば、ハードウェアによって乱数列を生成する乱数生成技術において、高速な乱数生成速度と、乱数列に規則性が無く、均質な０と１の出現比率を同時に実現することができる、という効果が得られる。
【図面の簡単な説明】
【図１】本発明の一実施の形態である乱数生成装置の構成の一例を示す概念図である。
【図２】図１に例示された乱数生成装置のより具体的な変形例を示す概念図である。
【図３】本発明の他の実施の形態である乱数生成装置の構成の一例を示す概念図である。
【図４】本発明の他の実施の形態である乱数生成装置の構成の一例を示す概念図である。
【図５】図４に例示した本発明の乱数生成装置の変形例を示す概念図である。
【図６】素乱数と、この素乱数を元に生成した反転トリガ信号の関係の一例を信号の波形で表した線図である。
【図７】本発明の一実施の形態である乱数生成装置の作用の一例を表形式で例示した説明図である。
【図８】本発明の他の実施の形態である乱数生成装置の構成の一例を示す概念図である。
【図９】本発明の乱数生成技術をソフトウェアにて行わせる場合の一例を示すフローチャートである。
【符号の説明】
１０Ａ，１０Ｂ…ダイオード、１１…クロック発生機構、１２Ａ，１２Ｂ…アナログ・デジタル変換機構、１３Ａ〜１３Ｄ…反転機構、１４…反転トリガ信号生成機構、１５…乱数データまとめ部、１５ａ…２進乱数データ、１６Ａ〜１６Ｊ…素乱数、１７Ａ〜１７Ｄ…反転トリガ信号、１８Ａ，１８Ｂ…ノイズ、１９…クロック信号、２１…素乱数、２２…反転トリガ信号、３０…ソフトウェア乱数生成装置、３０ａ…ソフトウェア素乱数、１４０Ａ〜１４０Ｂ…反転トリガ信号更新論理、１４１Ａ〜１４１Ｂ…反転トリガ信号レジスタ、１５０…シフト・レジスタ、１５１…データまとめ部制御論理、１５２…乱数データ・バッファ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a random number generation technique, and more particularly, to a random number generation technique suitable for speeding up a generation process and realizing high randomness when generating random numbers by hardware.
[0002]
[Prior art]
Random numbers are used in fields such as uncertain elements in various simulations, selection means for random extraction, and key generation for encryption techniques. For example, the wind given by the simulation of a wind tunnel experiment is not homogeneous, and uncertainties are required for several parameters such as wind direction, wind speed, and pressure. In the mathematical world, random numbers such as the Monte Carlo method are used for calculation. Many of these random numbers are software-generated random numbers.
[0003]
However, as software random numbers are called pseudo-random numbers, the output random number sequence has a certain regularity, and the result may have an incorrect directivity or may affect the convergence of the results.
[0004]
Randomness generated by hardware can be removed from regularity such as software random numbers by selecting a physical phenomenon having randomness in the random number source and having no regularity in the time direction. For example, as described in the literature such as Naoto Niki “Engineering Random Number Generation”, Institute of Statistical Mathematics, Vol. 27, No. 1 1980 115-131, etc., it is selected as a random number source for past hardware random number generation. Examples of random physical phenomena include radiation dose of cobalt-60, gamma-ray radiation due to decay of cesium-137, thermal noise of transistors, thermal noise of diodes, and noise from neon discharge tubes.
[0005]
Two examples are shown as processing methods for random numbers. One is a method of generating a binary one-digit random number depending on whether the result of counting the radiation dose or noise pulsed for a predetermined time is an even number or an odd number. The other is a method of using a random physical phenomenon that can obtain noise, converting the obtained noise to analog to digital, and using several digits of the output as a random number. As an example of the latter, in the technique disclosed in Japanese Patent Laid-Open No. 6-314188, noise on a conducting wire is converted from analog to digital to generate a random number.
[0006]
[Problems to be solved by the invention]
Measures for evaluating the randomness of binary random numbers include:
(1) The ratio of occurrence of 0 and 1 is equal,
(2) The ratio of occurrence of 0 and 1 in a certain digit is not influenced by the pattern of another digit that appears before,
There is.
[0007]
In the present specification, (1) is expressed as “the appearance ratio of 0 and 1 is equal”, and (2) is expressed as “there is no regularity of the random number sequence”. Taking (2) as an example, if the ratio of 0 and 1 appearing after 00 is 1: 3, it is “regular”, and that is why “randomness is poor”. Since both (1) and (2) are statistical evaluations, the larger the evaluation target population, the more accurately it can be evaluated, and this is not always true when the population is small.
[0008]
The random number generation device that counts a certain physical phenomenon at a certain time described in the prior art requires time for the counted value to be sufficiently large. As an extreme example, assuming that the result of counting for a certain time is about 0 to 1, if it is almost 0, the appearance ratio of even and odd numbers is remarkably uneven, and the output random number has directivity. For example, if a sufficiently large and sufficiently variable value is counted so that a value from 50 to 150 can be counted centering on 100, an imbalance between the even and odd appearance ratios can be ignored. However, if the counting time is increased in order to reduce the difference in the appearance ratio, the random number generation speed becomes inversely proportional. Taking a time such that the value from 50 to 150 can be measured centering on the above-mentioned 100, theoretically, only a random number generation speed of 1/150 or less, perhaps 1/200 to 1/300, can be obtained. .
[0009]
In the other method described in the prior art, in which random noise is converted from analog to digital and several digits of the output are used as random numbers, 0 in each digit is generated due to a habit on the circuit of the analog / digital conversion mechanism. The appearance ratio of 1 and 1 may not be equal. Compared with the method of counting physical phenomena, the method of analog-to-digital conversion of noise can obtain a random number generation speed substantially equal to the operating frequency of the circuit. However, the power supply line derived from the diode of the noise source, including the difference in the speed at which the signal in the analog-to-digital conversion mechanism in the circuit changes from 0 to 1, 1 to 0, and the threshold voltage. An error occurs between the voltage value of actual noise and the value of digital data output from the analog-digital conversion mechanism due to a characteristic peculiar to the circuit such as noise on the ground line and signal line. For example, when the noise before conversion is an intermediate voltage between x and x + 1, if the output result of the analog-digital conversion mechanism has a higher probability of outputting x + 1 than x, 0 and 1 of each digit to be output If the appearance ratio is biased, and this is a random number, the appearance ratio of 0 and 1 has a bias. The habit of a circuit depends on various conditions such as the characteristics of elements constituting the circuit, temperature, supply voltage, and operating frequency, and it is difficult to eliminate the bias by improving the circuit.
[0010]
An object of the present invention is to simultaneously realize a high-speed random number generation speed and a uniform appearance ratio of 0 and 1 with no regularity in a random number sequence in a random number generation technique for generating a random number sequence by hardware.
[0011]
[Means for Solving the Problems]
In the present invention, a bit (hereinafter referred to as a prime random number) of digital data output from an analog-digital conversion mechanism that converts a physical quantity having no regularity in the time axis direction obtained from the physical quantity generating means into a digital quantity is inverted. The trigger signal and the exclusive OR are taken as random numbers. The inversion trigger signal has an appearance ratio of 0 and 1 of 1: 1, and generates a signal having as little regularity as possible. By this method, when 0 is output as a random number, there are cases where the analog / digital conversion mechanism outputs 0 or 1 and the same applies when 1 is output as a random number. Since the analog / digital conversion mechanism outputs 0 or 1 in both cases, the influence of the unique habit of the analog / digital conversion circuit on the output can be eliminated. .
[0012]
Even when the inverted trigger signal has regularity, the regularity of the output random number sequence is improved. Assuming that the regularity of the inversion trigger signal is a: 1-a (0 <a <1) when the probability of 0 and 1 appearing after 0 appears, the appearance ratio of 0 and 1 is 1: 1, so 1 The probability of 0 and 1 appearing after appearing is 1-a: a. Since the bias of the appearance ratio of prime random numbers 0 and 1 is also simple, if a: 1-a, and the value of a deviates from 0.5, how much will it affect the regularity of the random number sequence to be output? Try to calculate. The regularity of the output random number sequence is the probability that 0 and 1 appear after 0 appears in the same way as the above expression, the probability that 0 and 1 appear after b: 1-b and 1 appear. 1-b: Expressed as b. Then
[0013]
[Expression 1]

[0014]
It becomes. FIG. 7 shows the calculation of what happens to b when a actually takes a value around 0.5.
[0015]
In the following, the ratio of the difference between a and b from 0.5 to 0.5 will be expressed as the deviation of random numbers. As can be seen from FIG. 7, when the deviation of the prime random number is 1%, the deviation of the output random number is 10%. ^-6 And can be very small.
[0016]
The inversion trigger signal generation mechanism employed in the present invention switches the inversion trigger signal from 0 to 1 or 1 to 0 in synchronization with the prime random number input to the inversion trigger signal generation mechanism being 1, and the prime random number is 0. At times, the inversion trigger signal is not changed. Since the random number sequence of prime random numbers has no regularity, the generated inverted trigger signal has a theoretically uniform appearance ratio of 0 and 1. FIG. 6 shows an example of the relationship between the prime random number 21 and the inverted trigger signal 22 generated based on the prime random number 21 in the waveform of the signal. The value of the signal when the signal waveform is at the top represents 1 and the value of the signal when the signal waveform is at the bottom represents 0. It can be seen that the prime random number 21 has a high appearance ratio of 0, but the inverted trigger signal 22 has substantially the same appearance ratio of 0 and 1.
[0017]
The regularity of the inverted trigger signal has the same effect as the deviation of the prime random number. This is because the probability of becoming 1 after 0, which is one of the regularities, is equal to the probability of 1 appearing as a prime random number. However, when viewed in the embodiments described later, it is possible to obtain a prime random number with a deviation of about 1 to 2% from the output of the analog-digital conversion mechanism by configuring the circuit well. As described above, the influence of this degree of deviation on the output deviation can be very small. Moreover, even if random numbers are generated in combination with software random numbers having regularity, random numbers with high randomness can be obtained.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0019]
FIG. 1 is a conceptual diagram showing an example of the configuration of a random number generation device according to an embodiment of the present invention. The random number generator of this embodiment includes a diode 10A that generates irregular noise 18A over time, an analog / digital conversion mechanism 12A that converts the noise 18A into digital data of prime random numbers 16A to 16D, and inverted trigger signals 17A to 17A. An inversion trigger signal generation mechanism 14 that generates 17D, a clock generation mechanism 11 that supplies a clock signal 19 to the analog / digital conversion mechanism 12A and the inversion trigger signal generation mechanism 14, an arbitrary external information processing device that uses random numbers, and the like And a random number data summarizing unit 15 that provides an interface between them.
[0020]
That is, the noise 18A output from the diode 10A is input to the analog / digital conversion mechanism 12A. The prime random numbers 16A to 16D among the prime random numbers output from the analog / digital conversion mechanism 12A are used as data inputs to the inversion mechanisms 13A to 13B, and the inversion trigger signals 17A to 17B output from the inversion trigger signal generation mechanism 14 are the inversion mechanisms 13A. Connect to ~ 13B inversion trigger input. The output of 13A of the reversing mechanism is connected to the random number data summarizing unit 15.
[0021]
As an operation of the random number generation device of the present embodiment having such a configuration, first, the analog / digital conversion mechanism 12A converts the voltage of the noise 18A into digital data in synchronization with the clock signal 19. Prime random numbers 16A to 16D are extracted from the digital data. The inversion mechanisms 13 </ b> A to 13 </ b> B output the exclusive OR of the prime random numbers 16 </ b> A to 16 </ b> D and the inversion trigger signals 17 </ b> A to 17 </ b> B output from the inversion trigger signal generation mechanism 14 and send them to the random number data summarizing unit 15. The random number data summarizing unit 15 processes the data so that it can be easily taken out in response to an external request, and outputs the data as binary random number data 15a. The number of prime random numbers and the number of inversion mechanisms are the same, but the inversion trigger signal may be different.
[0022]
FIG. 2 is a conceptual diagram illustrating a more specific modification of the random number generation device illustrated in FIG. 1 described above. That is, the configuration example of FIG. 2 presents one method for realizing the inversion trigger signal generation mechanism 14 of FIG.
[0023]
In the configuration of FIG. 2, the inversion trigger signal generation mechanism 14 includes a plurality of inversion trigger signal update logics 140A to 140B and inversion trigger signal registers 141A to 141B. Of the prime random numbers output from the analog / digital conversion mechanism 12A, the prime random numbers 16E to 16F that have not been directly sent to the inversion mechanisms 13A to 13B are used as the inversion trigger signal update logic 140A to 140B in the inversion trigger signal generation mechanism 14, respectively. Connect to. The outputs of the inversion trigger signal update logics 140A to 140B are connected to the inversion trigger signal registers 141A to 141B, respectively. The inversion trigger signals 17A to 17B output from the inversion trigger signal registers 141A to 141B are any of the inversion mechanisms 13A to 13B. Connected to the inverted trigger input and inverted trigger signal update logic 140A-140B, respectively.
[0024]
As an operation of the modified example of FIG. 2, the inverted trigger signal update logic 140A outputs an exclusive OR of the inverted trigger signal 17A and the prime random number 16E. The inverted trigger signal register 141A replaces the value to be held with the output of the inverted trigger signal update logic 140A in synchronization with the clock signal 19. The operations of the inverted trigger signal update logic 140B, the inverted trigger signal 17B, the prime random number 16F, and the inverted trigger signal register 141B are the same. Thus, it is the same as that of FIG. 1 except generating the inversion trigger signals 17A and 17B.
[0025]
FIG. 3 is a conceptual diagram showing an example of the configuration of a random number generation device according to another embodiment of the present invention. In the case of the configuration of FIG. 3, the analog / digital conversion mechanism 12A has an 8-bit output, and one prime random number 16A out of the eight prime random numbers output by the analog / digital conversion mechanism 12A is one inversion mechanism. Another prime random number 16B is connected to one inverted trigger signal update logic 140A in the inverted trigger signal generation mechanism 14 for the data input of 13A. The output of the inversion trigger signal update logic 140A is connected to the inversion trigger signal register 141A, and the inversion trigger signal 17A output from the inversion trigger signal register 141A is the inversion trigger input of the inversion mechanism 13A and the input side of the inversion trigger signal update logic 140A. Connect to.
[0026]
The output of the inversion mechanism 13A is connected to the shift register 150 in the random number data summarizing unit 15, and the output of the shift register 150 is connected to the random number data buffer 152 in the random number data summarizing unit 15. The output of the data summarizing unit control logic 151 in the random number data summarizing unit 15 is connected to the random number data buffer 152. The clock signal 19 output from the clock generation mechanism 11 is connected to the analog / digital conversion mechanism 12A, the inversion trigger signal register 141A, the shift register 150, and the data summarizing unit control logic 151.
[0027]
In the operation of the random number generation apparatus having the configuration shown in FIG. 3, first, the analog / digital conversion mechanism 12A converts the voltage of the noise 18A into 8-bit digital data in synchronization with the clock signal 19. Two prime random numbers 16A and 16B are extracted from this digital data. The inverted trigger signal update logic 140A outputs an exclusive OR of the inverted trigger signal 17A and the prime random number 16B. The inverted trigger signal register 141A replaces the value to be held with the output of the inverted trigger signal update logic 140A in synchronization with the clock signal 19. The inversion mechanism 13A outputs an exclusive OR of the prime random number 16A and the inversion trigger signal 17A and inputs it to the shift register 150. The shift register 150 is an 8-bit shift register that performs a shift operation in synchronization with the clock signal 19 and captures the output of the inversion mechanism 13A. The shift register 150 sends an 8-bit width output to the random number data buffer 152, and the data summarizing unit control logic 151 instructs writing to the random number data buffer 152 once every eight cycles in synchronization with the clock signal 19. I do. The random number data buffer 152 stores data (binary random number data 15a) from the shift register 150 when a write instruction is received. The random number data buffer 152 also has a function of writing the binary random number data 15a and erasing the written binary random number data 15a in response to an external read request, and a connection interface to a general-purpose bus such as a PCI. 8 bits of random number data (binary random number data 15a) can be supplied to any external device.
[0028]
FIG. 4 is a conceptual diagram showing an example of the configuration of a random number generation device according to another embodiment of the present invention. In the configuration of FIG. 4, a dedicated diode 10 </ b> B and an analog / digital conversion mechanism 12 </ b> B are provided as means for inputting prime random numbers to the inversion trigger signal generation mechanism 14.
[0029]
That is, the inversion in the inversion trigger signal generation mechanism 14 is performed by using the output of the analog / digital conversion mechanism 12A that has converted the noise 18A output from the diode 10A into the prime random numbers 16A to 16B connected to the inversion mechanisms 13A to 13B. For the prime random numbers 16E to 16F connected to the trigger signal update logics 140A to 140B, an output obtained by analog / digital conversion of the noise 18B output from the diode 10B by the analog / digital conversion mechanism 12B is used.
[0030]
In the configuration of FIG. 4, by preparing two combinations of a plurality of diodes 10A and 10B and analog / digital conversion mechanisms 12A and 12B, prime random numbers 16A and 16B inputted to the plurality of inversion mechanisms 13A and 13B The correlation between the inverted trigger signals 17A and 17B can be eliminated, and higher randomness can be realized in the binary random number data 15a finally output from the random number data summarizing unit 15.
[0031]
FIG. 5 is a conceptual diagram showing a modification of the random number generation device of the present invention illustrated in FIG. In the configuration of FIG. 5, two series of random numbers 16A, prime random numbers 16B, prime random numbers 16G, prime random numbers 16H, a diode 10A and an analog / digital conversion mechanism 12A, and a diode 10B and an analog / digital conversion mechanism 12B. On the other hand, corresponding reversing mechanisms 13A and 13B and reversing mechanisms 13C and 13D are provided, and the reversing trigger signal 17A and the reversing trigger signal 17B for each of the reversing mechanisms 13A and 13B and the reversing mechanisms 13C and 13D are connected to each other. This configuration is such that the prime random number 16E and the prime random number 16J generated from the digital conversion mechanisms 12B and 12A are crossed and generated.
[0032]
That is, the noise 18A output from the diode 10A is input to the analog / digital conversion mechanism 12A having an 8-bit output. The noise 18B output from the diode 10B is input to the analog / digital conversion mechanism 12B having an 8-bit output. One prime random number 16A among the eight prime random numbers output from the analog / digital conversion mechanism 12A is used as a data input to the inverting mechanism 13A, and one prime random number 16B is used as a data input to the inverting mechanism 13B. The random number 16C is connected to the inverted trigger signal update logic 140B in the inverted trigger signal generation mechanism 14. Of the eight prime random numbers output from the analog / digital conversion mechanism 12B, one prime random number 16G is input to the data input of the inverting mechanism 13C, and one prime random number 16H is input to the data input of the inverting mechanism 13D. The random number 16J is connected to the inverted trigger signal update logic 140A in the inverted trigger signal generation mechanism 14. The output of the inversion trigger signal update logic 140A is connected to the inversion trigger signal register 141A, and the inversion trigger signal 17A output from the inversion trigger signal register 141A is the inversion trigger input of the inversion mechanisms 13A and 13B and the inversion trigger signal update logic 140A. Connect to the input side. The output of the inversion trigger signal update logic 140B is connected to the inversion trigger signal register 141B, and the inversion trigger signal 17B output from the inversion trigger signal register 141B is supplied to the inversion trigger input of the inversion mechanisms 13C and 13D and the inversion trigger signal update logic 140B. Connecting. The outputs of the reversing mechanisms 13A, 13B, 13C, and 13D are connected to the random number data summarizing unit 15. The clock signal 19 output from the clock generation mechanism 11 is connected to the analog / digital conversion mechanisms 12A and 12B, the inversion trigger signal registers 141A and 141B, and the random number data summarizing unit 15. The difference from the embodiment shown in FIG.
(1) There are two diodes and two analog / digital conversion mechanisms.
(2) Two inversion mechanisms are provided for one analog-digital conversion mechanism, and two prime random numbers are input to each inversion mechanism one by one.
(3) The inversion trigger signal 17A input to the inversion mechanisms 13A and 13B connected to the prime random numbers 16A and 16B output from the analog / digital conversion mechanism 12A is the prime random number 16J output from the other analog / digital conversion mechanism 12B. The inversion trigger signal 17B input to the inversion mechanisms 13C and 13D to which the prime random numbers 16G and 16H output from the analog / digital conversion mechanism 12B are connected is the output of the other analog / digital conversion mechanism 12A. Updating using the prime random number 16E
It is.
[0033]
In the random number data summarizing unit 15, as in the embodiment of FIG. 3, the data shape is adjusted and stored so that it can respond to a read request from the outside. In this embodiment, the circuit from the diode to the front of the random number data summarizing unit 15 is doubled, the prime random number to be used is doubled to improve the performance of the random number generation speed, and the inverted trigger signal 17A and the inverted trigger signal 17B are In order to generate prime random numbers 16A, 16B and prime random numbers 16G, 16H and inverted trigger signals 17A, 17B from random sources of different systems by exchanging prime random numbers 16J, 16E for updating, the inversion mechanism 13A, The occurrence of regularity is prevented from an unexpected correlation between the data input (primary random numbers 16A, 16B and prime random numbers 16G, 16H) of 13B and the inversion mechanisms 13C, 13D and the inversion trigger signals 17A, 17B.
[0034]
In the configuration example of the random number generation device in FIGS. 2 to 5 described above, the prime random numbers for generating the inverted trigger signals 17A, 17B and the like in the inverted trigger signal generating mechanism 14 are diodes 10A, 10B and analog / digital conversion. Although prime random numbers obtained in hardware using the mechanisms 12A, 12B and the like are used, the present invention is not limited to this, and as illustrated in FIG. Even if the software prime random number 30a generated by software using a desired algorithm such as an equation method is used instead of the prime random numbers 16B, 16E, 16F, 16J, etc., the binary random number data 15a obtained is similarly obtained. Can be generated simultaneously, and the random number sequence has no regularity, and a uniform appearance ratio of 0 and 1 can be realized simultaneously. In this case, the software random number generation device 30 can be generally configured by an information processing device including a microprocessor (not shown), ROM, RAM, and the like in which software for generating random numbers is stored.
[0035]
Further, as illustrated in the flowchart of FIG. 9, the reversal processing of the prime random numbers 16A, 16B, 16H, 16G and the like performed by the inversion trigger signal generation mechanism 14 and the reversal mechanisms 13A to 13D is performed. It is also possible to perform the processing in software inside an arbitrary information processing apparatus that uses. In this case, as a random number generation mechanism using a physical phenomenon, a prime random number 16A configured by the diode 10A, the analog / digital conversion mechanism 12A, the random number data summarizing unit 15, and the like exemplified in the above-described embodiment of the present invention. Can be used as it is.
[0036]
That is, in an arbitrary information processing device, a program using the prime random number 16A obtained from the physical random number generation device can improve randomness by performing the following processing illustrated in the flowchart of FIG. 9 as preprocessing. Can be achieved.
[0037]
That is, first, the prime random number 16A (binary hardware random number) obtained from the physical random number generator is stored in the integer variable HR (step 201).
[0038]
Next, a binary software random number is generated from a random number generation routine by its own software and stored in the integer variable SR (step 202).
[0039]
A bit index variable n for designating each bit of the integer variable SR is initialized to 0 (step 203). However, SR [n = 0] indicates LSB.
[0040]
Next, the LSB of SR (SR [n = 0]) is updated by taking an exclusive OR with “0” (step 204).
[0041]
Thereafter, the bit index variable n is incremented (step 205), and it is determined whether the bit position has exceeded the MSB of the SR (step 206). The operation of taking the exclusive OR with the bit and updating the bit value at the n-th bit position (step 207) is repeated up to the MSB, and when the operation of this step 207 is completed, 2 stored in the integer variable HR A process of taking an exclusive OR for each bit between the binary hardware random number and the binary software random number after the reversal operation stored in the integer variable SR, and writing the result back to the integer variable HR (step 208); I do.
[0042]
As a result, in the integer variable HR, as a result, the random number sequence has no regularity and has a uniform appearance ratio of 0 and 1 as in the binary random number data 15a obtained from the random number data summarizing unit 15 in FIG. A binary hardware random number is obtained.
[0043]
In this case, since bit inversion processing is performed in software, the generation speed is somewhat sacrificed, but any physical random number generation device that supplies the prime random numbers 16A can be used, and physical random numbers are used. There is an advantage that physical random numbers having high randomness can be used with slight changes on the software side of the information processing apparatus. Also, the generation speed will not be a problem if the execution speed of the information processing apparatus using physical random numbers is improved, and the requirement for high speed generation of random numbers is also satisfied.
[0044]
As described above, in the random number generation device of this embodiment, in the random number generation processing at a high generation speed by hardware, the appearance ratio of 0 and 1 can be made equal, and the deviation of the prime random number is finally output. The influence on the regularity of the random number to be generated can be reduced. As shown in FIG. 7, the regularity bias of the random number sequence is 10 when the bias of the appearance ratio of the prime random numbers 0 and 1 is 2%. ^-Five Below, 10% at 1% ^-6 Can be improved.
[0045]
Features other than those described in the claims of the present invention are listed as follows.
[0046]
<1> A diode as a noise source, an analog / digital conversion mechanism, a random number data summarizing unit, and a clock generation mechanism, and a clock signal generated by the clock generation mechanism is connected to the analog / digital conversion mechanism, The voltage of noise generated in the Zener breakdown region or avalanche region when the diode is reverse-biased is converted into n-bit (n> 1) digital data in synchronization with the clock by the analog-digital conversion mechanism. In the random number generator that collects m bits (1 ≦ m ≦ n) of the digital data into a form that can be used as a random number in the random number data summarizing unit,
Inverted trigger that has two inputs, data input and inverted trigger input, and an inverted trigger signal generation mechanism, and the inverted trigger signal generation mechanism appears at approximately the same ratio while 0 and 1 change. S signals (1 ≦ s ≦ m) are generated, and the s inverted trigger signals are connected to the inverted trigger inputs of all the m inversion mechanisms in a one-to-one or one-to-many manner, and the random number data The m-bit digital data immediately before being sent to the summary unit is connected to the data inputs of the m inversion mechanisms on a one-to-one basis, and the m inversion mechanisms perform exclusive OR of the data input and the inversion trigger input. And outputting the output to the random number data summarizing unit instead of the m-digit digital data output by the analog-digital conversion mechanism.
[0047]
<2> It has s inverted trigger signal registers for holding inverted trigger signals and s inverted trigger signal update logics,
Of the digital data output by the analog-digital conversion mechanism, s bits are connected to all the s inverted trigger signal update logics in a one-to-one relationship, and the inverted trigger signal update logic is held in the corresponding inverted trigger signal register. Outputs an exclusive OR of the inverted trigger signal and the input digital data, connects the clock to the inverted trigger signal register, and converts the inverted trigger signal held by the inverted trigger signal register to the clock Random number according to item <1>, comprising an inversion trigger signal generation mechanism, wherein the inversion trigger signal update logic is replaced with the output of the inversion trigger signal update logic and the inversion trigger signal held in the inversion trigger signal register is output. Generator.
[0048]
<3> The random number generation device according to item <1>, further including an inverted trigger signal generation mechanism that outputs a program generated random number as the inverted trigger signal.
[0049]
<4> A combination of the diode and the analog-to-digital conversion mechanism is prepared in two systems independently, one connected to the data input of the inverting mechanism and one connected to the inverted trigger signal update logic. The random number generation device according to item <2>.
[0050]
<5> Item having two combinations of the diode, the analog / digital conversion mechanism, and the inverting mechanism, and connecting the output of the inverting mechanism to the data input and the inverting trigger input of another inverting mechanism <1> Random number generation device.
[0051]
<6> generating a binary prime random number from an irregular physical quantity in the time axis direction;
Generating an inverted trigger signal that appears at approximately the same ratio as 0 and 1 vary;
Taking an exclusive OR of the prime random number and the inverted trigger signal and outputting as a binary random number;
A random number generation method comprising:
[0052]
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0053]
For example, the physical quantity generating means is not limited to the diodes exemplified in the above-described embodiments, and general equipment that outputs irregular physical quantities in the time axis direction can be widely used.
[0054]
【The invention's effect】
According to the random number generation device of the present invention, in a random number generation technique for generating a random number sequence by hardware, a high-speed random number generation rate and a uniform appearance ratio of 0 and 1 are realized at the same time without randomness in the random number sequence. The effect that it can be obtained.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram illustrating an example of a configuration of a random number generation device according to an embodiment of the present invention.
FIG. 2 is a conceptual diagram illustrating a more specific modification of the random number generation device illustrated in FIG. 1;
FIG. 3 is a conceptual diagram showing an example of a configuration of a random number generation device according to another embodiment of the present invention.
FIG. 4 is a conceptual diagram showing an example of the configuration of a random number generation device according to another embodiment of the present invention.
FIG. 5 is a conceptual diagram showing a modification of the random number generation device of the present invention illustrated in FIG. 4;
FIG. 6 is a diagram showing an example of a relationship between a prime random number and an inverted trigger signal generated based on the prime random number in a signal waveform.
FIG. 7 is an explanatory diagram illustrating an example of the operation of the random number generation device according to the embodiment of the present invention in a tabular format.
FIG. 8 is a conceptual diagram showing an example of a configuration of a random number generation device according to another embodiment of the present invention.
FIG. 9 is a flowchart showing an example in which the random number generation technique of the present invention is performed by software.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10A, 10B ... Diode, 11 ... Clock generation mechanism, 12A, 12B ... Analog-digital conversion mechanism, 13A-13D ... Inversion mechanism, 14 ... Inversion trigger signal generation mechanism, 15 ... Random number data summarizing part, 15a ... Binary random number data 16A to 16J ... prime random numbers, 17A to 17D ... inverted trigger signal, 18A, 18B ... noise, 19 ... clock signal, 21 ... prime random number, 22 ... inverted trigger signal, 30 ... software random number generator, 30a ... software prime random number , 140A to 140B ... inverted trigger signal update logic, 141A to 141B ... inverted trigger signal register, 150 ... shift register, 151 ... data summary control logic, 152 ... random number data buffer.

Claims (5)

Physical quantity generating means for generating a physical quantity having no regularity in the time axis direction; data converting means for converting the physical quantity into first digital data of 2 bits or more; and at least part of the first digital data is random number data. An external output interface that outputs to the outside as a random number generator,
An inverted trigger signal generating means for generating an inverted trigger signal that appears at an equal ratio while 0 and 1 vary irregularly;
Provided between the data conversion means and the external output interface, and obtains an exclusive OR of at least a part of the bits of the first digital data and the inverted trigger signal, and a data inversion means for outputting to the external output interface as the second digital data instead, only including,
The inverted trigger signal generating means takes an exclusive OR of digital random number data input in time series from an arbitrary random number generating means and its own output, and outputs the inverted trigger update logic as the inverted trigger signal. And an inversion trigger signal latch means for latching the inversion trigger signal output from the inversion trigger update logic in synchronization with a clock signal and outputting the latched data to the inversion trigger update logic. Random number generator. The random number generation device according to claim 1 ,
A random number generating apparatus using a part of the first digital data as the random number data input to the inverted trigger update logic of the inverted trigger signal generating means. The random number generation device according to claim 1 ,
The combination of the physical quantity generation means and the data conversion means is a set for inputting digital data to the data inversion means, and a set for inputting the digital data as the random number data to the inversion trigger update logic of the inversion trigger signal generation means. A random number generator characterized by providing two systems. The random number generation device according to claim 1 ,
The combination of the physical quantity generation means and the data conversion means is a set for inputting digital data to the data inversion means, and a set for inputting the digital data as the random number data to the inversion trigger update logic of the inversion trigger signal generation means. A random number generating apparatus using the other digital data as the digital data input as the random number data to the inversion trigger update logic. The random number generation device according to claim 1 ,
A random number generation device using software generated random numbers as the random number data input to the reverse trigger update logic.

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