JP3678923B2 - Magnetic disk unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic disk device capable of reading and writing information using a magnetic disk as a recording medium.
[0002]
[Prior art]
In a magnetic disk device, a plurality of disk-shaped recording media (magnetic disks) are provided, and information is written to and read from the recording medium through a plurality of heads.
[0003]
The head output signal is amplified by a differential amplifier. As described in `` ISSCC94 / SESSION17 / DISK-DRIVE ELECTRONICS / PAPER FA 17.6 A Low-Power 3V-5.5V Read / Write Preamplifier for Rigid-Drives '' as a technology to reduce the input capacity of the differential amplifier, In order to reduce the mirror capacitance between the base and the collector of the input transistor, a method of applying positive feedback to the base electrode of the grounded base transistor connected to the collector electrode of the input transistor is known. In this method, the level for applying positive feedback is created by the load resistance of the differential amplifier.
[0004]
[Problems to be solved by the invention]
The input capacity of the differential amplifier is the sum of the base-emitter capacity and the base-collector capacity of the input transistor, but because of the Miller capacity (CM), as shown in the following equation, the base-collector capacity of the element It becomes larger than the capacity (CJC).
[0005]
CM = (1 + Av) CJC
Here, Av is the gain of the collector output voltage with respect to the base input voltage of the input transistor. Usually, in order to reduce the mirror capacitance, a base ground circuit is connected to the collector electrode so that the collector level of the input transistor does not fluctuate. However, the mirror resistance due to the emitter operating resistance re and the emitter parasitic resistance RE of the common base transistor remains. Further, the mirror effect is also caused by the wiring resistance of the collector electrode, and the mirror effect cannot be sufficiently reduced. When the mirror capacitance is large and the input capacitance is large, the bandwidth of the differential amplifier is deteriorated. The circuit shown in the above-mentioned document applies positive feedback to the base electrode of the grounded base circuit, eliminates the mirror effect, and makes the mirror capacitance CM equal to or lower than the base-collector capacitance CJC of the element. Since the bandwidth is determined by the CR time constant of the load resistance and the surrounding parasitic capacitance, the bandwidth of the differential amplifier can be increased by reducing the parasitic capacitance. In the circuit described in the above document, a transistor for creating a positive feedback level is connected to the load resistance, which may increase the parasitic capacitance and hinder the widening of the amplifier.
[0006]
When the input capacity of the differential amplifier is large, the bandwidth of the differential amplifier is narrowed, and high-speed reading becomes difficult in a magnetic disk device equipped with such a differential amplifier.
[0007]
An object of the present invention is to provide a technique for enabling high-speed reading by reducing an input capacitance without hindering a wide band of a differential amplifier in a magnetic disk device.
[0008]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0009]
  That is, it includes a head (103a) for writing information to the magnetic disk and reading information from the magnetic disk, a first transistor (Q1), and a second transistor (Q2) differentially coupled thereto. A magnetic disk device including a differential stage (Q1, Q2) capable of amplifying a signal detected by the head and an output amplifier (23) for transmitting the signal amplified by the differential stage to a subsequent circuit , A first grounded transistor circuit (Q5, Q6) including a third transistor (Q5) grounded at the base and a fourth transistor (Q6) grounded at the base, and disposed at the preceding stage of the output amplifier; A fifth transistor (Q3) interposed between the third transistor and the first transistor and connected in series to the third transistor; A second base grounded transistor circuit (12a) including a sixth transistor (Q4) interposed between the fourth transistor and the second transistor and connected in series thereto, and a collector potential of the fifth transistor Is provided with a first emitter follower (Q9) for positive feedback to the sixth transistor and a second emitter follower (Q10) for positive feedback of the collector potential of the sixth transistor to the fifth transistor.
[0010]
  the aboveofAccording to the means, the second grounded-base transistor circuit acts to cancel the mirror effect of the differential stage by positive feedback, which reduces the mirror capacitance of the differential stage, and further the amplifier. By increasing the bandwidth, the read operation in the magnetic disk device can be speeded up.At this time, the first emitter follower and the second emitter follower operate to supply a sufficient base current to the second base grounded transistor circuit.
[0011]
At this time, the wiring resistance between the first base grounded transistor circuit and the second base grounded transistor circuit and the wiring resistance ratio between the second base grounded transistor circuit and the differential stage are utilized. The amount of positive feedback can be adjusted.
[0012]
  Also,A head (103a) for writing information to and reading information from the magnetic disk; a first transistor (Q1); and a second transistor (Q2) differentially coupled to the head (103a), In a magnetic disk device including a differential stage (Q1, Q2) capable of amplifying a signal detected by a head and an output amplifier (23) for transmitting a signal amplified by the differential stage to a subsequent circuit, A first grounded transistor circuit (Q3, Q4) disposed in front of the output amplifier, including a third grounded transistor (Q5) and a fourth grounded transistor (Q6); A fifth transistor (Q3) interposed between one transistor and the third transistor and connected in series to the first transistor; A second grounded transistor circuit (12a) including a sixth transistor (Q4) interposed between the second transistor and the fourth transistor and connected in series to the second transistor; A seventh transistor (Q11) is interposed between the transistor and the fifth transistor, and is connected in series to the seventh transistor (Q11), and is interposed between the fourth transistor and the sixth transistor. A third base grounded transistor circuit (Q11, Q12) including an eighth transistor (Q12) connected to the first transistor for positive feedback of the collector potential of the seventh transistor to the sixth transistor and the eighth transistor. The collector potential of the emitter follower (Q9) and the eighth transistor is set to the fifth transistor. It can be provided and a second emitter follower (Q10) for causing positive feedback to static and the seventh transistor.
[0013]
  At this time, the third base grounded transistor circuit acts to prevent an increase in amplifier noise at a high frequency by reducing the charge and discharge currents to the parasitic capacitance.
[0014]
A first chip formed on one semiconductor substrate including the differential pair and the second grounded base transistor circuit, and a first chip formed on one semiconductor substrate including the first grounded base transistor and the output stage. When two chips are included, the first chip is placed closer to the head than the second chip in order to shorten the distance between the first chip and the head as much as possible to reduce parasitic inductance there. Can be arranged.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 7 shows a configuration example of a magnetic disk device according to the present invention.
[0016]
In the magnetic disk device, a combination of a magnetic disk portion which is a storage medium and an MR head assembly is fixed.
[0017]
Although omitted in FIG. 7, in the magnetic disk device, a plurality of disk-shaped recording media (magnetic disks) are provided, and information is written to and read from the recording medium by a plurality of MR heads. 103a, 103b,... Although not particularly limited, each of the MR heads 103a, 103b,... Includes a read MR head and a write inductive head. The MR head is not particularly limited, but a permalloy one is applied. Start / stop is performed with the MR head in contact with the MR head disk surface. When the disk reaches constant speed rotation, the MR head is lifted from the 0.4 to 1.5 μm disk surface by the air flow, and a gap is formed between the disk surface. When fine dust enters such a gap, it causes an MR head crash, so the MR head assembly is tightly sealed. The MR heads 103a and 103b are coupled to the read / write circuit 50. The read / write circuit 50 includes a read amplifier group 105 and a write amplifier group 106 provided corresponding to the MR heads 103a and 103b, an MR head selection circuit 52 for switching MR heads, an amplification circuit 53, and a flip-flop 54, respectively. Although not particularly limited, it is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. Such a read / write circuit 50 is attached to an arm member or the like that supports the MR heads 103a and 103b and is coupled to the main board 60 by various signal lines in order to reduce the influence of noise.
[0018]
The main board 60 includes a controller 55 for controlling the entire apparatus of the present embodiment, a signal processing circuit 56 for processing a write signal and a read signal to the magnetic disk, and positioning of the MR heads 103a and 103b. A servo data processing circuit 111 for performing servo data processing, an MR head actuator control circuit 112 for controlling the operation of the MR head actuator 113 based on a processing output signal of the servo data processing circuit 111, and the like are mounted. The controller 55 is constituted by a microcomputer or the like. In the signal processing circuit 56, binary data for writing is modulated in accordance with a predetermined recording method. On the other hand, at the time of data reading, a peak detection process is performed on the output signal from the amplification circuit 53, and a timing pulse and data separation process is performed by demodulation.
[0019]
The read amplifier group 105 includes a plurality of read amplifiers 105a, 105b,... Arranged corresponding to the MR heads 103a, 103b,..., And the write amplifier group 106 includes the MR heads 103a, 103b,. Are arranged corresponding to the plurality of write amplifiers 106a, 106b,.
[0020]
Information read from the MR heads 103a and 103b is amplified by the corresponding read amplifiers 105a and 105b. The MR heads 103a and 103b are supplied with a write current via the corresponding write amplifiers 106a and 106b. The output signals of the read amplifiers 105a and 105b are amplified by the amplifier circuit 53 disposed in the subsequent stage and then transmitted to the signal processing circuit 56 of the main board 60. The write data from the signal processing circuit 56 is transmitted to the write amplifiers 106a and 106b via the flip-flop 54 and the MR head selection circuit 52.
[0021]
The MR heads 103a and 103b are positioned on the target track by an MR head positioning system formed by the MR head actuator 113, the servo data processing circuit 111, the MR head actuator control circuit 112, and the like. Although not particularly limited, the MR head positioning system is a track following type that uses servo data on the recording medium surface for track position detection.
[0022]
FIG. 2 shows a configuration example of the read amplifier group 105.
[0023]
The read amplifier group 105 includes a plurality of read amplifiers 105a, 105b,... Arranged corresponding to the MR heads 103a, 103b,..., But is common among the plurality of read amplifiers in order to reduce the number of components. There is a part that has become. The read amplifier group 105 basically includes a load and amplifier unit 11, base grounding units 12a to 12d, input first stage units 13a to 13h, and a current source unit 14, and the input first stage units 13a to 13h are MR heads. The base grounding portions 12a to 12d are arranged at a ratio of two to the input first stage portions 12a to 12d. Further, the load and amplifier unit 11 and the current source unit 14 are each one.
[0024]
The input first stage sections 13a to 13h are amplification circuits for differentially amplifying weak signals from the corresponding MR heads, and the current used for the amplification operation and the bias current of the MR head are a current source. Supplied from the unit 14. The load and amplifier unit 11 is a common load of the input first stage units 13a to 13h, and the base ground units 12a to 12d are provided to minimize the parasitic capacitance in the load and the amplifier unit 11, Is one of the characteristic points of the read amplifier group 105.
[0025]
The detailed configuration of each part will be described.
[0026]
FIG. 1 shows a configuration example of a load and amplifier unit 11, a base grounding unit 12a, an input first stage unit 13a, and a current source unit 14.
[0027]
Input first stage portion 13a includes pnp bipolar transistor Q7 and npn bipolar transistor Q8 for switching a bias current flowing through MR head 103a, and npn bipolar transistors Q1 and Q2 forming a differential pair. The pnp bipolar transistor Q7 is coupled to one terminal of the MR head 103a and is controlled in operation by a control signal VSW * (* indicates low active or signal inversion), and the npn bipolar transistor Q8 is operated by a control signal VSW. Be controlled. One terminal of MR head 103a is coupled to the base electrode of npn type bipolar transistor Q1, and the other terminal of MR head 103a is coupled to the base electrode of npn type bipolar transistor Q2.
[0028]
The current source section 14 includes a constant current source 16 for flowing a constant current I1 through the npn bipolar transistor Q1, a constant current source Q2 for flowing a constant current I1 through the npn bipolar transistor Q2, and the MR head 103a. Constant current sources 18 and 19 for supplying a predetermined bias current Imr. The pnp bipolar transistor Q7 is coupled to the high potential power source Vcc via the constant current source 18, and the npn bipolar transistor Q8 is coupled to the low potential power source Vee via the constant current source 19. The npn-type bipolar transistors Q1 and Q2 are coupled to a low potential side power source Vee through constant current sources 16 and 17, respectively. A capacitor C1 is provided to capacitively couple the emitter electrodes of the npn-type bipolar transistors Q1 and Q2.
[0029]
The load and amplifier unit 11 is connected to the collector electrode of the npn bipolar transistor Q1 through the grounded base portion 12a and to the collector electrode of the npn bipolar transistor Q2 through the grounded base portion 12a. It has an npn bipolar transistor Q6 to be coupled, a bias power supply 20 for supplying a predetermined bias voltage V1 to the base electrodes of the transistors Q5 and Q6, and resistors R1 and R2. The collector electrodes of npn bipolar transistors Q5 and Q6 are coupled to high potential side power supply Vcc through resistors R1 and R2, respectively. An output amplifier 23 is provided for amplifying the potential difference between the collector electrodes of bipolar transistors Q5 and Q6. The output of the output amplifier 23 is OUTX and OUTY.
[0030]
Base ground portion 12a includes npn bipolar transistors Q3 and Q4. The collector electrodes of npn type bipolar transistors Q3 and Q4 are coupled to the emitter and emitter electrodes of npn type bipolar transistors Q5 and Q6 in amplifier 11. The emitter electrodes of npn bipolar transistors Q3 and Q4 are coupled to the collector electrodes of npn bipolar transistors Q1 and Q2 in input first stage portion 13a. The base electrode of npn bipolar transistor Q3 is coupled to the collector electrode of npn bipolar transistor Q4, and the base electrode of npn bipolar transistor Q4 is coupled to the collector electrode of npn bipolar transistor Q3.
[0031]
The operation of the above configuration will be described.
[0032]
Any one of the input first stage portions 13a to 13h is selected, and the pnp bipolar transistor Q7 and the NPN bipolar transistor Q8 are turned on. Thereby, the MR head 103a is current-biased by supplying a predetermined bias current Imr from the current source unit 14 to the MR head 103a. For signal readout, a magnetoresistive effect is used in which the resistance value changes with a magnetic field. The resistance value of the MR head 103a is changed according to the data written on the disk. When the resistance value changes by ΔRMR, ΔV represented by the following equation is generated between the terminals of the MR head 103a.
[0033]
ΔV = Imr × ΔRMR
This voltage ΔV is transmitted to the base electrodes of npn-type bipolar transistors Q1, Q2. The emitter electrodes of the npn-type bipolar transistors Q1 and Q2 are capacitively coupled by the capacitor C1 and are open in terms of DC, but are short-circuited in the signal band.
[0034]
The npn-type bipolar transistors Q1 and Q2 are biased by the same current I1, and the low-side levels of the resistors R1 and R2 are equal in direct current. It operates as a general differential amplifier in the signal band, and its gain G is
G = R1 / re
It becomes. Here, re is the emitter operating resistance of the npn-type bipolar transistors Q1 and Q2.
[0035]
The signal amplified by the input first stage unit 13a is further amplified by the amplifier 23 disposed in the subsequent stage, and then output through the output terminals OUTX and OUTY.
[0036]
The input capacitance of the input first stage portion 13a includes the base-emitter capacitance (CJE) of the npn bipolar transistors Q1, Q2, the mirror capacitance (CM = CJC (1 + Av)) generated between the base and the collector, and the capacitance of the peripheral circuit ( Q7, Q8). Here, Av is a gain when a signal is input from the base electrodes of the npn-type bipolar transistors Q1 and Q2 and an output is obtained from the collector electrode. If the input capacitance is large, the signal input to the amplifier is attenuated from a low frequency, so that the amplifier band is degraded. In order to widen the amplifier bandwidth, it is necessary to reduce the input capacitance.
[0037]
The base-emitter capacitances (CJE) of the npn bipolar transistors Q1 and Q2 and the peripheral circuit capacitances (Q7 and Q8) are determined by the size of the transistor cell. The npn bipolar transistors Q1 and Q2 need to have a small base resistance in order to reduce amplifier noise, resulting in a relatively large cell. The npn bipolar transistors Q1 and Q2 are determined by the optimum design of amplifier noise and input capacitance. The sizes of the pnp bipolar transistor Q7 and the npn bipolar transistor Q8 are determined by the current capacity.
[0038]
Next, the operation of the base grounding portion 12a will be described.
[0039]
Here, in the circuit configuration of FIG. 1, a case where the base grounding portion 12a is omitted and the collector electrodes of the npn bipolar transistors Q1 and Q2 are directly connected to the resistors R1 and R2 is considered.
[0040]
If npn-type bipolar transistors Q3, Q4, Q5, and Q6 do not exist, gain Av when a signal is input from the base electrode of npn-type bipolar transistors Q1 and Q2 and an output is obtained from the collector electrode is
Av = R1 / re
Therefore, the mirror capacity becomes very large. On the other hand, by providing npn type bipolar transistors Q5 and Q6 (without Q3 and Q4), fluctuations in the collector level of npn type bipolar transistors Q1 and Q2 are suppressed, and an increase in mirror capacitance is suppressed. The npn-type bipolar transistors Q5 and Q6 have an emitter operating resistance re1 and an emitter parasitic resistance RE1,
Av = (re1 + RE1) / re
The mirror capacity corresponding to Further, when the wiring resistance (RAL) between the npn bipolar transistors Q1 and Q2 and the npn bipolar transistors Q5 and Q6 cannot be ignored,
Av = (re + RE1 + RAL) / re
Thus, the mirror capacity is further increased.
[0041]
On the other hand, when the base grounding portion 12a is provided, the input capacitance can be reduced as follows.
[0042]
Here, for convenience of explanation, it is assumed that the emitter operating resistance re1 and the emitter parasitic resistance RE of the npn bipolar transistors Q3 to Q6 are equal to each other.
[0043]
The resistance of the MR head 103a is changed, ΔV is input between the bases of the npn bipolar transistors Q1 and Q2, the collector current of the npn bipolar transistor Q1 changes by + Δi, and the collector current of the npn bipolar transistor Q2 is −Δi. Only change. In this case, the emitter level of the npn-type bipolar transistor Q5, that is, the base level of the npn-type bipolar transistor Q4 changes by −Δi × (re + RE1), and the emitter level of the npn-type bipolar transistor Q6, that is, the npn-type bipolar transistor Q3. The base level changes by + Δi × (re1 + RE1).
[0044]
Therefore, the emitter level of the npn-type bipolar transistor Q3 is canceled and does not change between the amount that the transistor Q3 tries to decrease at re1 and RE1 and the amount that the base potential of the npn-type bipolar transistor Q3 increases. Similarly, the emitter level of the npn-type bipolar transistor Q4 does not change.
[0045]
In the above case, Av = 0 and CM = CJC, and the mirror effect is eliminated, so that the input capacitance can be reduced accordingly.
[0046]
Next, the wiring resistance (RAL1) between the npn bipolar transistors Q5 and Q6 and the npn bipolar transistors Q3 and Q4, and the wiring resistance between the npn bipolar transistors Q3 and Q4 and the npn bipolar transistors Q1 and Q2 When (RAL2) cannot be ignored, it will be explained that the wiring resistance can be used to reduce the mirror capacitance.
[0047]
When the ΔV is input, the base level of the npn bipolar transistor Q4 changes by −Δi × (re1 + RE1 + RAL1), and the base level of the npn bipolar transistor Q3 changes by + Δi × (re1 + RE1 + RAL1).
[0048]
The emitter level of the npn-type bipolar transistor Q3 changes by −Δi × (re1 + RE1 + RAL2) + Δi × (re1 + RE1 + RAL1). When RAL1 = RAL2, the variation of the emitter level becomes zero.
[0049]
If the arrangement is made so that RAL1> RAL2 and the positive feedback amount is increased, the mirror capacitance CM can be further reduced.
[0050]
As shown in FIG. 2, when there are a plurality of base grounding parts 12a to 12d, the load and the amplifier part 11 and the wiring length to the input first stage parts 13a to 13h are different, and even when the values of RAL1 + RAL2 are different, In this wiring, if the ratio of RAL1: RAL2 is made constant, the amount of positive feedback becomes equal to each other. By making the ratios equal in this way, the mirror capacitance becomes equal, so that there is no variation in input capacitance between MR heads.
[0051]
The internal configurations of the base grounding unit 12a and the input first stage unit 13a have been described representatively. However, the other base grounding units 12b to 12d and the input first stage units 13b to 13g also have the base grounding unit 12a and the input first stage unit 13a, respectively. It is configured in the same way.
[0052]
Next, the arrangement of the read amplifier unit 105 will be described.
[0053]
FIG. 3 shows an arm 40 for supporting the MR head 103a.
[0054]
The tip of the arm 40 is provided with a flat head support called ICS, and the MR head 103a is attached to the ICS. An FPC (flexible printed circuit) is provided at the center of the arm 40, and a first chip mounting area 34 is formed there. The end 32 of the arm 40 to which the MR head 103a is not attached is called a carriage, and a second chip mounting area 35 is formed there. The read amplifier group 105 is not particularly limited, but is divided into a first chip mounting area 34 and a second chip mounting area 35.
[0055]
In the first chip mounting area 34, the base grounding portions 12a to 12d and the input first stage portions 13a to 13h are mounted. The circuit mounted in the first chip mounting area 34 is divided into a plurality of chips by dividing each circuit or a plurality of circuits. In the second chip mounting area 35, the load and amplifier unit 11 and the current source unit 14 are mounted. A circuit mounted in the second chip mounting area 35 is also divided into one chip or a plurality of circuits to form a plurality of chips. The chip mounted on the second chip mounting area 35 is coupled to the substrate 60 mounted with the signal processing LSI via the FPC 33.
[0056]
In this case, the load and amplifier unit 11, the base grounding units 12a to 12d, the input first stage units 13a to 13h, and the current source unit 14 are formed on one semiconductor substrate, and are provided in the second chip formation region 35. This is effective in reducing the influence of parasitic inductance. That is, the base grounding parts 12a to 12d and the input first stage parts 13a to 13h are close to the mounting position of the MR head, and the distance between the base grounding parts 12a to 12d and the input first stage parts 13a to 13h and the MR head is as follows. As a result, the amount of inductance parasitic on signal transmission can be reduced, and the influence thereof can be reduced.
[0057]
According to the above example, the following effects can be obtained.
[0058]
(1) The npn-type bipolar transistors Q3 and Q4 as the second base-grounded transistor circuit act so as to cancel the mirror effect of the differential stage by positive feedback, which reduces the mirror capacitance of the differential stage. Furthermore, the read operation in the magnetic disk device can be speeded up by widening the amplifier.
[0059]
(2) Wiring resistance between npn-type bipolar transistors Q5 and Q6 which are first base-grounded transistor circuits and npn-type bipolar transistors Q3 and Q4 which are second-base-grounded transistor circuits, and the second base-grounded transistor circuit The amount of positive feedback can be adjusted using the ratio of the wiring resistance to the differential stage.
[0060]
(3) The first chip includes base grounding units 12a to 12d and input first stage units 13a to 13h, and the second chip includes a load and amplifier unit 11 and a current source unit 14. The first chip is provided in the first chip mounting area 31 and the second chip is provided in the second chip mounting area 32. In this case, the load and amplifier unit 11, the base grounding units 12a to 12d, the input first stage units 13a to 13h, and the current source unit 14 are formed on one semiconductor substrate, and are provided in the second chip formation region 35. This is effective in reducing the influence of parasitic inductance.
[0061]
FIG. 4 shows another configuration example of the main part of the magnetic disk device.
[0062]
In the configuration shown in FIG. 4, positive feedback is performed to the grounded base portion 12a via the emitter followers of the npn-type bipolar transistors Q9 and Q10.
[0063]
The load and amplifier unit 11 is provided with npn-type bipolar transistors Q9 and Q10. The collector electrodes of npn bipolar transistors Q9 and Q10 are coupled to high potential side power supply Vcc, and the emitter electrodes are coupled to low potential side power supply Vee through constant current sources 21 and 22 for flowing constant current I2, respectively. . The base electrode of npn bipolar transistor Q4 is coupled to the emitter electrode of npn bipolar transistor Q9, and the base electrode of npn bipolar transistor Q3 is coupled to the emitter electrode of npn bipolar transistor Q10, whereby npn bipolar transistor Q3. , Q4 is positively fed back. Thus, even when positive feedback to the grounded base portion 12a is performed via the emitter followers of the npn-type bipolar transistors Q9 and Q10, the same effect as that shown in FIG. 1 can be obtained. Further, since the emitter followers of npn bipolar transistors Q9 and Q10 are interposed, a sufficient base current can be supplied to npn bipolar transistors Q4 and Q3.
[0064]
FIG. 5 shows still another configuration example of the main part of the magnetic disk device.
[0065]
The configuration shown in FIG. 5 is obtained by adding a grounded base circuit using npn-type bipolar transistors Q11 and Q12 to the configuration shown in FIG.
[0066]
In the circuit shown in FIG. 4, the wiring between the npn-type bipolar transistors Q5 and Q6 and Q3 and Q4 becomes relatively long and the wiring capacitance increases. If there is a relative error between the wiring capacitance on the emitter electrode of npn bipolar transistor Q5 and the wiring capacitance on the emitter electrode of npn bipolar transistor Q6, the wiring capacitance is charged and discharged from npn bipolar transistors Q5 and Q6 at high frequency. The amount of current is different, which causes amplifier noise. In addition, PSRR (power supply voltage fluctuation ratio) also deteriorates. In order to reduce the charge and discharge currents, the wiring potential may be kept constant. Therefore, the npn-type bipolar transistors Q11 and Q12 keep the wiring potential between the blocks constant so as to reduce the charging and discharging currents.
[0067]
The base electrodes of npn-type bipolar transistors Q3 and Q4 are input to the emitter electrodes of npn-type bipolar transistors Q9 and Q10 via diodes D1 and D2 in terms of DC potential distribution. The circuit operation is shown in FIG. The circuit is the same as that described. When voltage ΔV is input to input first stage portion 13a, the emitter level of npn bipolar transistor Q5 changes by −Δi × (re + RE1). In the circuit configuration shown in FIG. 5, the emitter wiring of the npn bipolar transistor Q11 is long, but a level depending on the level of the emitter electrode of the npn bipolar transistor Q6 is input to the base electrode of the npn bipolar transistor Q11. When the voltage ΔV is input to the input first stage portion 13a, the emitter level of the npn-type bipolar transistor Q6 changes by + Δi × (re1 + RE1). Therefore, the two cancel each other and the emitter level of the npn bipolar transistor Q11 does not change. Since the emitter level does not change in this way, there is no charge or discharge current from the wiring capacitance, and neither the amplifier noise nor PSRR deteriorates.
[0068]
FIG. 6 shows still another configuration example of the main part of the magnetic disk device.
[0069]
The configuration shown in FIG. 6 is significantly different from the configuration shown in FIG. 5 in that the base electrodes of npn-type bipolar transistors Q3 and Q4 constituting the grounded base circuit are coupled to the emitter electrodes of npn-type bipolar transistors Q12 and Q11. It is a point that has been. In this case, the diodes D1 and D2 shown in FIG. 5 are unnecessary. The amount of positive feedback for canceling the mirror capacitance is set by the wiring resistance between the npn-type bipolar transistors Q11, Q12 and Q3, Q4 and between the npn-type bipolar transistors Q3, Q4 and Q1, Q2.
[0070]
Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.
[0071]
For example, npn bipolar transistors Q3 and Q4 as the second base grounded transistor can be shared by all MR heads in order to reduce the number of elements. Although the bipolar transistor has been described, it may be replaced with a MOS transistor.
[0072]
In the above description, the case where the invention made by the present inventor is applied to a magnetic disk device using an MR head, which is the field of use behind the invention, has been described. However, the present invention is not limited thereto. The present invention can be widely applied to various magnetic disk devices.
[0073]
The present invention can be applied on condition that at least a head for writing information to and reading information from a magnetic disk is provided.
[0074]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0075]
In other words, the second base grounded transistor circuit acts to cancel the mirror effect of the differential stage by positive feedback, thereby reducing the mirror capacitance of the differential stage and further increasing the bandwidth of the amplifier, thereby reducing the magnetic field. The reading operation in the disk device can be speeded up.
[0076]
At this time, the wiring resistance between the first base grounded transistor circuit and the second base grounded transistor circuit and the wiring resistance ratio between the second base grounded transistor circuit and the differential stage are utilized. By increasing the amount of positive feedback, the input capacity of the differential stage can be further reduced. Further, the emitter follower is interposed in the path for positively feeding back the signal formed based on the combined resistance including the emitter operating resistance and the emitter parasitic resistance of the first base grounded transistor circuit to the second base grounded transistor circuit. A sufficient base current can be supplied to the 2-base grounded transistor circuit.
[0077]
Further, by providing the third base ground transistor circuit between the first base ground transistor circuit and the second base ground transistor circuit, it is possible to suppress the potential fluctuation of the wiring having a large parasitic capacitance, The increase in amplifier noise at high frequencies can be prevented by reducing the charge and discharge current to the capacitor.
[0078]
A first chip formed on a semiconductor substrate including the differential pair and the second grounded base transistor circuit and formed on a semiconductor substrate, and formed on a single semiconductor substrate including the first grounded transistor and the output stage. The first chip is arranged closer to the head than the second chip, thereby reducing the distance between the first chip and the head as much as possible. The parasitic inductance can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a configuration example of a main part in a magnetic disk device according to the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a read amplifier group in the magnetic disk device.
FIG. 3 is an explanatory diagram of an arrangement position of an arm and the read amplifier group included in the magnetic disk device.
FIG. 4 is a circuit diagram showing another configuration example of the main part of the magnetic disk device.
FIG. 5 is a circuit diagram of still another configuration example of the main part of the magnetic disk device.
FIG. 6 is a circuit diagram of still another configuration example of the main part of the magnetic disk device.
FIG. 7 is a block diagram showing an example of the overall configuration of the magnetic disk device.
[Explanation of symbols]
11 Load and amplifier
12a-12d Base grounding part
13a-13h Input first stage
14 Current source
23 Output amplifier
34 First chip mounting area
35 Second chip mounting area
40 arms
Q1, Q2, Q3, Q4, Q5, Q6, Q9, Q10 npn type bipolar transistor

Claims (4)

A head for writing information to the magnetic disk and reading information from the magnetic disk;
A differential stage including a first transistor and a second transistor differentially coupled thereto, and capable of amplifying a signal detected by the head;
An output amplifier for transmitting a signal amplified by the differential stage to a subsequent circuit;
A first base-grounded transistor circuit including a third transistor grounded at the base and a fourth transistor grounded at the base, and disposed in a stage preceding the output amplifier;
A fifth transistor connected in series with the third transistor and the first transistor, a fifth transistor connected in series to the third transistor, and a fourth transistor and the second transistor. A second base grounded transistor circuit including a sixth transistor connected;
A first emitter follower for positive feedback of the collector potential of the fifth transistor to the sixth transistor;
And a second emitter follower for positively feeding back the collector potential of the sixth transistor to the fifth transistor.   The positive feedback using the ratio of the wiring resistance between the first base grounded transistor circuit and the second base grounded transistor circuit and the wiring resistance between the second base grounded transistor circuit and the differential stage. 2. The magnetic disk device according to claim 1, wherein the amount of the magnetic disk device is adjusted. A head for writing information to the magnetic disk and reading information from the magnetic disk;
A differential stage including a first transistor and a second transistor differentially coupled thereto, and capable of amplifying a signal detected by the head;
An output amplifier for transmitting a signal amplified by the differential stage to a subsequent circuit;
A first base-grounded transistor circuit including a third transistor grounded at the base and a fourth transistor grounded at the base, and disposed in a stage preceding the output amplifier;
While being interposed between the first transistor and the third transistor, being interposed between the fifth transistor connected in series to the first transistor, the second transistor and the fourth transistor, A second base-grounded transistor circuit including a sixth transistor connected in series to the second transistor;
The seventh transistor is interposed between the third transistor and the fifth transistor, and is connected in series to the seventh transistor. The fourth transistor is interposed between the fourth transistor and the sixth transistor. A third base grounded transistor circuit including an eighth transistor connected;
A first emitter follower for positively feeding back the collector potential of the seventh transistor to the sixth transistor and the eighth transistor;
And a second emitter follower for positively feeding back the collector potential of the eighth transistor to the fifth transistor and the seventh transistor. A first chip formed on one semiconductor substrate including the differential pair and the second grounded base transistor circuit, and a first chip formed on one semiconductor substrate including the first grounded base transistor and the output amplifier. when including a two-chip, the first chip, the magnetic disk device according to any one of claims 1 to 3 than the second chip are arranged in a vicinity of the head.

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