JP3678715B2 - Distributed shared memory multiprocessor system and tag control method used therefor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a distributed shared memory multiprocessor system and a tag control method used therefor, and more particularly, to a tag (hereinafter referred to as TAG) control method used in a shared memory multiprocessor system.
[0002]
[Prior art]
Conventionally, in a shared memory multiprocessor system, multiple processors store a copy of the system memory in a cache. In this case, the shared memory multiprocessor system requires a cache coherent mechanism in order to maintain the consistency between the data stored in the plurality of caches of the same memory line and the memory.
[0003]
A TAG (or directory) is provided to realize this cache coherent mechanism. The TAG stores the address of each memory line and the state of the system memory and the cache.
[0004]
In recent years, the capacity of caches installed in computer systems for accelerating access to system memory has been greatly increased. In addition, the system memory has been greatly increased in capacity. The TAG stores a large amount of information as the system memory and the cache increase in capacity, thereby improving the throughput of the entire system.
[0005]
[Problems to be solved by the invention]
However, in the conventional shared memory multiprocessor system described above, if a TAG having the same capacity as the system memory or the cache is installed, the amount of hardware increases, the cost burden increases, and the control complexity increases. However, the access speed is slow and the control becomes complicated.
[0006]
Therefore, an object of the present invention is to solve the above-mentioned problems, reduce the load on the bus, increase the cache hit rate, and improve the performance of the entire system, and a distributed shared memory multiprocessor system and It is to provide a tag control method used therefor.
[0007]
[Means for Solving the Problems]
  A distributed shared memory multiprocessor system according to the present invention holds a plurality of central processing units having a cache, a memory controller for processing a request from one of the central processing unit and the input / output device, and information on the cache A distributed shared memory type multiprocessor system including a plurality of nodes configured by a bus connection between the central processing unit and the memory controller,
  An inter-node address bus that connects each of the plurality of nodes; and a crossbar that connects each of the plurality of nodes and performs processing of data between the plurality of nodes and processing of a request from the input / output device.,
  The memory controller includes a tag memory that holds information on the cache, a tag swap buffer that holds tag flush information in the tag memory, a tag control circuit that controls a request issued from the node, and each of the nodes A request control unit that controls a request to access, and a reply control circuit that controls reply data in the node;
  The tag control circuit includes a mechanism for indexing, registering, invalidating, and issuing a coherent request for the tag memory and the tag swap buffer.
  A determination circuit for determining an index result of the tag memory and the tag swap buffer;
  The determination circuit invalidates information in the tag swap buffer and re-registers in the tag memory when detecting that the area of the tag memory is an invalidation target and the same set address exists in the tag swap buffer. Doneing.
[0008]
  A tag control method according to the present invention includes a plurality of central processing units having a cache, a memory controller that processes a request from one of the central processing unit and the input / output device, and a distributed shared memory that holds information of the cache A distributed shared memory multiprocessor system tag control method including a plurality of nodes formed by bus connection between the central processing unit and the memory controller,
  Each of the plurality of nodes is connected by an inter-node address bus and a crossbar that performs processing of data between the plurality of nodes and processing of a request from the input / output device,
  In the tag memory holding the cache information and the tag swap buffer holding the tag sweep information in the tag memory, the address and status information registered in the cache in the node are held,
  When newly registering the tag memory area in the tag swap buffer, the address and status information obtained by swapping any one of the areas are stored.,
  When determining the index result of the tag memory and the tag swap buffer, when it is detected that the area of the tag memory is an invalidation target and the same set address exists in the tag swap buffer, the tag swap buffer Invalidate information and re-register in the tag memorying.
[0009]
That is, the distributed shared memory type multiprocessor system of the present invention has a bus connection between a plurality of CPUs (central processing units) having a cache and each CPU and a memory controller, and the CPU or I / O (input / output). Each node is composed of a memory controller that processes requests from a device and a distributed shared memory, and each of the above nodes is connected via an inter-node address bus and a crossbar. At the same time as processing data, requests from I / O devices are processed.
[0010]
The memory controller of each node includes a tag memory (hereinafter referred to as “TAG”) that holds information on a cache mounted on each CPU in the node, a TAG swap buffer that holds TAG flush information, and a node or other node. TAG control circuit comprising a mechanism for controlling issued requests and issuing index, registration, invalidation and coherent requests for TAG memory and TAG swap buffer, request control unit for controlling requests to access each node, and each And a reply control circuit for controlling reply data in the node.
[0011]
The TAG memory and the TAG swap buffer hold the address and status information registered in the CPU cache in each node. The TAG swap buffer holds the address and status information obtained by swapping any one area when a new registration is performed in a state where the area of the TAG memory is fully registered.
[0012]
When the TAG control circuit receives the TAG index request, the TAG memory and the TAG swap buffer are simultaneously indexed, the addresses held in the TAG memory or the TAG swap buffer match, and the status information is valid (P or S). The TAG control circuit issues a request to the bus by performing registration, update, and invalidation according to each index result.
[0013]
In the circuit for determining the index result of the TAG memory and the TAG swap buffer, if it is determined that the area of the TAG memory is the object to be invalidated and the same set address exists in the TAG swap buffer, the information of the TAG swap buffer is invalidated. And re-register in the TAG memory.
[0014]
In the above processing, when a plurality of identical set addresses exist in the TAG swap buffer, re-registration is performed with priority given to the status information “P” indicating any one of the states of the cache. The TAG swap buffer determines whether there is valid information based on the status information held in each entry, reads out from the TAG swap buffer when the buffer is full, and a swap from the TAG memory occurs, and a TAG control circuit Issue an invalidate request to the bus.
[0015]
In each determination circuit that determines the index results of the TAG memory and the TAG swap buffer, the status information is determined, and a plurality of evictions (swaps) from the TAG memory are cached in the system from the status information “P”. Priority is given to “S” indicating a possible state or a state where caching is not performed.
[0016]
Similarly to the above, in each determination circuit that determines the index result of the TAG memory and the TAG swap buffer, the status information is written back from the cache by giving priority to “S” over “P” as the status information. Reduce processing.
[0017]
Similarly to the above, if it is determined that all the statuses of the TAG swap buffer are “P” and the status information to be swapped from the TAG memory is “S”, the status is not stored in the TAG swap buffer but is stored in the bus. Issue an invalidate request.
[0018]
Therefore, as described above, by controlling the TAG memory and the TAG swap buffer, coherent control between a plurality of nodes can be performed, and at the same time, the entry of the TAG memory can be effectively used, and the CPU cache can be used. Since the data sweeping operation registered with the status information “M” is reduced, the cache hit rate is increased, and the load on the bus is suppressed, so that the performance of the entire system is improved.
[0019]
Therefore, in the distributed shared memory multiprocessor system of the present invention, the TAG memory and the TAG swap buffer that can be mounted on the LSI (Large Scale Integrated circuit) are fully utilized, the load on the bus is reduced, and the cache hit rate is increased. As a result, the performance of the entire system is improved.
[0020]
In recent years, the capacity of the main memory and the capacity of the cache mounted on the memory CPU have increased. Holding information in the entire memory space with the TAG memory requires a huge amount of hardware investment. Further, an increase in the capacity of the TAG memory complicates the control, and at the same time, does not always ensure the performance commensurate with the hardware investment.
[0021]
In the distributed shared memory type multiprocessor system of the present invention, the TAG swap buffer that holds the swept information from the TAG memory and the TAG memory has effective information in the TAG swap buffer. When the TAG memory area is free, the TAG Re-register from the swap buffer.
[0022]
The TAG swap buffer does not issue a coherent request to the bus until it is full. Further, when there are a plurality of re-registration targets in the TAG swap buffer, the one with the TAG status “P” is prioritized over “S”. Even when a coherent request is issued from the TAG swap buffer to the bus, the load on the bus in each node is reduced and the TAG memory is enabled by providing a mechanism that prioritizes the status “P” over “S”. By utilizing, the flushing from the cache mounted on the CPU is reduced. Therefore, the performance of the entire system is improved.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a distributed shared memory multiprocessor system according to an embodiment of the present invention. In FIG. 1, a distributed shared memory multiprocessor system according to an embodiment of the present invention includes nodes (# 0 to # 3) 1 to 4, a crossbar 5, and I / O (input / output) devices 6-1 to 6-6. -4.
[0024]
Each of the nodes (# 0 to # 3) 1 to 4 includes a plurality of CPUs (central processing units) 11 to 14,..., 41 to 44, a memory controller 15,. , 46. In FIG. 1, only the configurations of the nodes (# 0, # 3) 1 and 4 are illustrated, and the configurations of the other nodes (# 1, # 2) 2 and 3 are omitted. The configuration of the nodes (# 1, # 2) 2, 3 is the same as the configuration of the nodes (# 0, # 3) 1, 4.
[0025]
The CPUs 11-14,..., 41-44 have caches 11a, 12a, 13a, 14a,..., 41a, 42a, 43a, 44a, respectively, and the memory controller 15 via the buses 110,. ,..., 45 are connected. The memory controllers 15, ..., 45 process requests from the CPUs 11-14, ..., 41-44 or the I / O devices 6-1 to 6-4.
[0026]
The crossbar 5 processes data between the plurality of nodes 1 to 4 via the data lines 301,..., 304, and simultaneously processes requests from the plurality of I / O devices 6-1 to 6-4.
[0027]
FIG. 2 is a block diagram showing the configuration of the memory controller 15 of FIG. In FIG. 2, only the configuration of the memory controller 15 is illustrated, but the memory controllers of the nodes (# 1, # 2) 2 and 3 and the memory controller 45 of the node (# 3) 4 are the same as the memory controller 15. It has a configuration.
[0028]
The memory controller 15 includes a tag (hereinafter referred to as TAG) memory 151, a TAG swap buffer 152, a TAG control circuit 153, a request control unit 154, a determination circuit 155, and a reply control circuit unit 156. .
[0029]
FIG. 3 is a diagram showing the contents held in the TAG memory 151 of FIG. In FIG. 3, the TAG memory 151 holds a CPU cache status, a code, and an outline.
[0030]
The CPU cache status “M (Modified)” has a code “11” and its outline is “only caching in the system. It is not a copy of the shared memory”. The CPU cache status “E (Exclusive)” has a code of “10”, and its outline is “the only caching in the system and has a copy of the shared memory”.
[0031]
The CPU cache status “S (Shared)” has a code “01” and its outline is “There may be multiple caches in the system, and there is a copy of the shared memory”. . The CPU cache status “I (Invalid)” has a code “00” and its outline is “no caching”.
[0032]
FIG. 4 is a diagram showing the contents held in the TAG swap buffer 152 of FIG. In FIG. 4, the TAG swap buffer 152 holds a TAG status, a code, and a CPU cache status.
[0033]
The TAG status “P (Private)” has a code “11” and a CPU cache status “M / E / S / I status”. The TAG status “S (Share)” has a code “10” and a CPU cache status “S / I status”. The TAG status “U (Uncached)” has a code “00” and a CPU cache status “I (not cached)”. In other words, the TAG status “P” indicates any one of the CPU cache statuses, and the TAG status “S” indicates that “there is a possibility that a plurality of caches are in the system, and there is a copy of the shared memory”. Indicates a status or “not caching” status.
[0034]
The memory controller 15 will be described in detail with reference to FIGS.
[0035]
The TAG memory 151 holds information on the caches 11a, 12a, 13a, and 14a mounted on the CPUs 11 to 14 in the node 1. The TAG swap buffer 152 holds TAG flush information. The determination circuit 155 determines requests / replies issued from the other nodes 2 to 4 or the I / O devices 6-1 to 6-4.
[0036]
The transfer control of the TAG control circuit 153 is performed by the determination circuit 155, and the TAG control circuit 153 has a mechanism for issuing an index, registration, invalidation, and coherent request for the TAG memory 151 and the TAG swap buffer 152. The request control unit 154 controls a request for accessing each of the nodes (# 0 to 3) 1 to 4. The reply control circuit unit 156 controls reply data in each of the nodes 1 to 4.
[0037]
The TAG memory 151 and the TAG swap buffer 152 of each of the nodes 1 to 4 are connected to the caches 11a, 12a, 13a of the CPUs 11 to 14,. 14a,..., 41a, 42a, 43a, 44a, and the registered address and status information are held.
[0038]
The TAG swap buffer 152 holds the address and status information obtained by swapping any one area when a new registration is performed in a state where the area of the TAG memory 151 is fully registered.
[0039]
When the TAG control circuit 153 receives the TAG index request, the TAG control circuit 153 simultaneously indexes the TAG memory 151 and the TAG swap buffer 152, the addresses held in the TAG memory 151 or the TAG swap buffer 152 match, and status information (hereinafter referred to as TAG). If the status information of the swap buffer 152 (see FIG. 4) is valid (“P” or “S”), registration, update, and invalidation are performed according to the index results, and requests are issued to the bus 110 as necessary. I do.
[0040]
FIG. 5 is a block diagram showing a control mechanism of the TAG memory 151 and the TAG swap buffer 152 of FIG. In FIG. 5, the control mechanism of the TAG memory 151 and the TAG swap buffer 152 is targeted from the register 161, the determination circuits 162, 164, and 166 that determine the index results of the TAG memory 151 and the TAG swap buffer 152, and the determination results. It is composed of selection circuits 163 and 165 for selecting data, and is controlled as follows. Here, the TAG memory 151 is a generally designed nWAY • set associative memory.
[0041]
The determination circuit 162 determines whether the valid entry (“P” or “S”) of the TAG swap buffer 152 is full, “1” when it is full, and “0” when it is not full. To 153.
[0042]
The determination circuit 164 determines whether the valid entry (status is “P” or “S”) in the TAG swap buffer 152, the set address match, and the key address match when receiving the TAG index request. If they do not match, “0” is transmitted.
[0043]
The determination circuit 166 outputs a matching condition with the key address and status information registered in the TAG memory 151. The determination circuit 166 also determines whether the area for the set address of the index request is fully used.
[0044]
The selection circuit 163 selects the update / invalidation processing target based on the index request from the result of the determination circuit 164 described above. The selection circuit 163 selects one of the “address + status” to be re-registered from the TAG swap buffer 152 into the TAG memory 151 or to be evicted from the TAG swap buffer 152.
[0045]
The selection circuit 165 selects a target for update, registration, and invalidation processing by an index request from the result of the determination circuit 166 described above. Further, the selection circuit 165 selects the target to be evicted from the TAG memory 151 when evicting processing is required from the TAG memory 151 (when the effective area “P” or “S” is stored in the full area for the set address). select.
[0046]
Further, the selection circuit 165 selects one of the “address + status” to be re-registered from the TAG swap buffer 152 to the TAG memory 151 or to be evicted from the TAG swap buffer 152.
[0047]
FIG. 6 is a flowchart showing eviction control from the TAG memory 151 of FIG. The eviction control from the TAG memory 151 will be described with reference to FIG. 2, FIG. 5, and FIG. Hereinafter, although the node (# 0) 1 will be described, the eviction control from the TAG memory in the other nodes (# 1 to # 3) 2 to 4 is the same as this.
[0048]
When the memory controller 15 does not match the address from the result of the determination circuit 166 with respect to the TAG index request and the valid information is fully stored in the area corresponding to the set address, new registration is required (step S1 in FIG. 6). To S4), when only "S" is present (step S5 in FIG. 6), any one is selected at random, and it is expelled (step S6 in FIG. 6).
[0049]
When “S” and “P” coexist (step S7 in FIG. 6), the memory controller 15 preferentially selects one of “S” and drives it out (step S8 in FIG. 6). In addition, when only “P” is present (step S9 in FIG. 6), the memory controller 15 selects one at random and drives it out (step S10 in FIG. 6).
[0050]
FIG. 7 is a flowchart showing the eviction control from the TAG swap buffer 152 of FIG. The eviction control from the TAG swap buffer 152 will be described with reference to FIG. 2, FIG. 5, and FIG. Hereinafter, although the node (# 0) 1 will be described, the eviction control from the TAG swap buffer in the other nodes (# 1 to # 3) 2 to 4 is the same as this.
[0051]
When the TAG swap buffer 152 is full and there is an eviction from the TAG memory 151 (steps S11 and S12 in FIG. 7), the memory controller 15 determines that the TAG swap buffer 152 is only “S” and the TAG memory When the target to be evicted from 151 is “S” or “P” (step S13 in FIG. 7), any “S” in the TAG swap buffer 152 is preferentially evicted (step S14 in FIG. 7).
[0052]
In the memory controller 15, when “S” and “P” are mixed in the TAG swap buffer 152 and the eviction target from the TAG memory 151 is “S” or “P” (step S 15 in FIG. 7), the TAG swap buffer Either “S” of 152 is preferentially driven out (step S16 in FIG. 7).
[0053]
When the TAG swap buffer 152 is only “P” and the eviction target from the TAG memory 151 is “P” (step S17 in FIG. 7), the memory controller 15 evoke any “P” in the TAG swap buffer 152 ( FIG. 7 step S18). Note that if the target to be evicted from the TAG memory 151 is “S” (step S19 in FIG. 7), the memory controller 15 issues it directly to the bus 110 (step S20 in FIG. 7).
[0054]
FIG. 8 is a flowchart showing re-registration control from the TAG swap buffer 152 of FIG. 2 to the TAG memory 151. The re-registration control from the TAG swap buffer 152 to the TAG memory 151 will be described with reference to FIG. 2, FIG. 5, and FIG. Hereinafter, although the node (# 0) 1 will be described, the re-registration control from the TAG swap buffer to the TAG memory in the other nodes (# 1 to # 3) 2 to 4 is the same as this.
[0055]
When the TAG memory 151 is invalidated “I” by the determination circuit 166 and the result of the determination circuit 164 is “S” or “P”, the memory controller 15 has an address match of “S” or “P” (step in FIG. 8). S21, S22), when only “S” exists in the TAG swap buffer 152 (step S23 in FIG. 8), one of “S” is selected by the selection circuit 163 and re-registered in the TAG memory 151. (FIG. 8, step S24).
[0056]
When the target existing in the TAG swap buffer 152 is “S” or “P” (step S25 in FIG. 8), the memory controller 15 selects one of “P” with priority by the selection circuit 163 and selects the TAG memory. 151 is registered again (step S26 in FIG. 8).
[0057]
Therefore, as described above, by controlling the TAG memory 151 and the TAG swap buffer 152, coherent control between a plurality of nodes can be performed, and at the same time, the entry of the TAG memory 151 can be effectively used. The cache 11a to 14a of the CPUs 11 to 14 reduce the data sweeping operation registered with the status information “M” (refer to FIG. 4 for cache status information below), so the hit rate of the caches 11a to 14a is increased. In addition, since the load on the bus 110 can be suppressed, the performance of the entire system is improved.
[0058]
9 to 19 are flowcharts showing the read processing for the distributed shared memories 16 and 46 shown in FIG. 1, and FIGS. 20 to 33 are flowcharts showing the write processing for the distributed shared memories 16 and 46 shown in FIG. The read processing and write processing for the distributed shared memories 16 and 46 will be described with reference to FIGS.
[0059]
In this embodiment, when viewed from the node (# 0) 1, the read to the distributed shared memory 16 of the own node, the read to the distributed shared memory 46 of the other node (# 3) 4, There is a write to the distributed shared memory 46 of the other node (# 3) 4.
[0060]
Note that reading and writing to the distributed shared memory of other nodes (# 1, # 2) 2 and 3 are the same as reading and writing to the distributed shared memory 46 of other nodes (# 3) 4. Regarding the operation description, the status of data to be registered, updated, or invalidated in the caches (in this embodiment, the cache is a store-in cache) 11a to 14a, the TAG memory 151, and the TAG swap buffer 152 is shown in FIG. 3 and FIG. 4 shall be referred to.
[0061]
First, reading from the distributed shared memory 16 of the own node (# 0) 1 will be described. In this case, the request issuer is the CPU 11. Even when issued from the CPUs 12 to 14 in the own node (# 0) 1, the cache control in each of the CPUs 12 to 14 and the operation of requests related thereto are assumed to be the same as the processing of the CPU 11.
[0062]
In the CPU 11, when the data to be accessed is registered as “M” in the cache 11a (step S31 in FIG. 9), the cache 11a is hit and the data in the cache 11a is returned to the CPU 11 (step S32 in FIG. 9). ), The read request is completed.
[0063]
In the CPU 11, when the data to be accessed is registered with “E” in the cache 11 a (step S 33 in FIG. 9), the cache 11 a is hit and the data in the cache 11 a is returned to the CPU 11 (step S 32 in FIG. 9). ), The read request is completed.
[0064]
In the CPU 11, when the access target data is registered with “S” in the cache 11 a (step S 34 in FIG. 9), the cache 11 a is hit and the data in the cache 11 a is returned to the CPU 11 (step S 32 in FIG. 9). ), The read request is completed.
[0065]
In the CPU 11, when the access target data is not registered in the cache 11a (step S35 in FIG. 9), the cache 11a issues a bus acquisition request to the bus 110 (step S36 in FIG. 9). (Step S37 in FIG. 9), a line read request is issued (Step S38 in FIG. 9).
[0066]
In the above line read request, when the access target data is registered as “M” in any of the caches 12a, 13a, and 14a of the CPUs 12 to 14 connected to the bus 110 (step S39 in FIG. 10). The caches 12a, 13a, and 14a write back (data reply) the data registered with “M” in the bus 110 (step S40 in FIG. 10).
[0067]
The caches 12a, 13a, and 14a that have issued the write-back are invalidated and set to “I” (step S41 in FIG. 10). The above write back is transmitted to the distributed shared memory 16 via the request control unit 154 (step S42 in FIG. 10). Since the cache in the same node (# 0) 1 is already in the “M” state, the TAG status registered in the TAG memory 151 or the TAG swap buffer 152 remains “P” (step S43 in FIG. 10). .
[0068]
The cache 11a receives the write-back data as reply data via the bus 110, registers it as “E”, and returns the data to the CPU 11 (step S44 in FIG. 10). Further, the above write-back data is also transmitted to the distributed shared memory 16 of the own node (# 0) 1 and the contents thereof are updated. This completes the read process.
[0069]
In the above line read request, when the access target data is registered as “E” in any of the caches 12a, 13a, and 14a of the CPUs 12 to 14 connected to the bus 110 (step S45 in FIG. 11). The caches 12a, 13a, and 14a are updated to “S” (step S46 in FIG. 11).
[0070]
The line read request is transferred to the TAG control circuit 153 and the distributed shared memory 16 via the request control unit 154 (step S47 in FIG. 11). The TAG control circuit 153 indexes the TAG memory 151 and the TAG swap buffer 152 (step S48 in FIG. 11), and updates the access target status to “S” from the output of the determination circuit 164 or the determination circuit 166 (step S49 in FIG. 11). .
[0071]
The data reply read from the distributed shared memory 16 by the line read request is transmitted to the request issuing cache 11a via the reply control circuit 156 and the bus 110, registered as “S”, and returns the data to the CPU 11. (FIG. 11, step S50), the read process is completed.
[0072]
In the above line read request, when the access target data is registered as “S” in any of the caches 12a, 13a, and 14a of the CPUs 12 to 14 connected to the bus 110 (step S51 in FIG. 12). The cache is updated to “S” (step S52 in FIG. 12).
[0073]
The line read request is transferred to the TAG control circuit 153 and the distributed shared memory 16 via the request control unit 154 (step S53 in FIG. 12). The TAG control circuit 153 does not update the TAG memory 151 and the TAG swap buffer 152 (step S54 in FIG. 12).
[0074]
Further, the data reply read from the distributed shared memory 16 by the line read request is transmitted to the cache 11a of the request issuer via the reply control circuit 156 and the bus 110, registered with “S”, and returns the data to the CPU 11. (Step S55 in FIG. 12), the read process is completed.
[0075]
In the above line read request, when all of the caches 12a, 13a and 14a of the CPUs 12 to 14 connected to the bus 110 have not registered access target data (step S56 in FIG. 13), the line read request is The data is transferred to the TAG control circuit 153 and the distributed shared memory 16 via the request control unit 154 (step S57 in FIG. 13).
[0076]
The TAG control circuit 153 issues a line request to the inter-node address bus 200, and transfers the line request to the memory controllers of the other nodes (# 1 to # 3) 2 to 4 (step S58 in FIG. 13).
[0077]
When the TAG control circuit of each memory controller of each of the other nodes (# 1 to # 3) 2 to 4 receives a line request from another node (step S71 in FIG. 14), the TAG memory and the TAG swap buffer are indexed (FIG. 14). Step S72). Hereinafter, the processing for each index result will be described, but the processing will be described with respect to the node (# 3) 4. However, the nodes (# 1, 2) 2 and 3 perform the same operation as the node (# 3) 4.
[0078]
When the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 matches the address and is “P” (step S73 in FIG. 14), the TAG control control circuit sends a line read & invalidate to the bus 140. A request is issued (step S74 in FIG. 14), and the access target of the TAG memory or the TAG swap buffer of the node (# 3) 4 is invalidated (step S75 in FIG. 14).
[0079]
In the node (# 3) 4, the caches 41a, 42a, 43a, 44a of the CPUs 41 to 44 are indexed (step S76 in FIG. 14). If the index result is “M” (step S77 in FIG. 14), “M” is registered. The cache that is writing writes the data back to the bus 140 and transfers it to the request control unit (step S78 in FIG. 14). The cache in which “M” is registered is invalidated (step S79 in FIG. 14).
[0080]
The write back is transferred as a data reply to the crossbar 5 via the data line 304 (step S80 in FIG. 14), and is transferred to the memory controller 15 of the node (# 0) 1 via the data line 301.
[0081]
The determination circuit 155 of the memory controller 15 transfers the data reply transferred via the data line 301 to the reply control circuit 156 and the request control unit 154 (steps S59 and S60 in FIG. 13). The reply control circuit 156 transmits a data reply to the CPU 11 on the bus 110, and the cache 11a registers “E” (step S61 in FIG. 13). The data reply is returned to the CPU 11 and the read process is completed.
[0082]
On the other hand, the request controller 154 of the memory controller 15 transfers the data reply to the TAG control circuit 153 and indexes the TAG memory 151 and the TAG swap buffer 152 (step S101 in FIG. 17). Here, the index result of the TAG memory 151 is as follows depending on the result of the determination circuit 166 or the output of the determination circuit 164 that determines the index result of the TAG swap buffer 152.
[0083]
If there is an empty area in the access target area of the TAG memory 151 (step S102 in FIG. 17), the key address and status “P” are registered in the empty area (step S103 in FIG. 17).
[0084]
If all the access target areas of the TAG memory 151 are registered with “P” (step S104 in FIG. 17), one of the areas is expelled to the TAG swap buffer 152, and instead the data reply key address and status “P” "Is registered (step S105 in FIG. 17).
[0085]
When the access target area of the TAG memory 151 is filled with “P” or “S” (step S106 in FIG. 17), either “S” is pushed out to the TAG swap buffer 152, and instead a data reply key. The address and status “P” are registered (step S107 in FIG. 17).
[0086]
If all the access target areas of the TAG memory 151 are registered as “S” (step S108 in FIG. 17), any area is expelled to the TAG swap buffer 152, and instead the key address and status “P” of the data reply "Is registered (step S109 in FIG. 17).
[0087]
In the above processing, when the TAG swap buffer 152 is full from the result of the determination circuit 164 (step S110 in FIG. 18), if all stored in the TAG swap buffer 152 are “P” (step S111 in FIG. 18). Then, any “P” is driven out (step S112 in FIG. 18). The TGA control circuit 153 issues an invalid request to the bus 110 with the address to be evicted (step S113 in FIG. 18). The operation of the invalidate request will be described below.
[0088]
If “M” is registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 for the address of the invalidate request (step S121 in FIG. 19), write back to the bus 110, Invalidation “I” is performed (step S122 in FIG. 19). The write back is routed to the distributed shared memory 16 to be accessed via the request control unit 154, and the contents of the memory are updated (step S123 in FIG. 19).
[0089]
If “E” is registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 for the address of the invalidate request (step S124 in FIG. 19), the cache is invalidated “I”. "(Step S125 in FIG. 19).
[0090]
If “S” is registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 for the address of the invalidate request (step S126 in FIG. 19), the cache is invalidated “I”. "(Step S125 in FIG. 19).
[0091]
If the address of the invalidate request is not registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 (step S127 in FIG. 19), nothing is done.
[0092]
The node (# 3) 4 indexes the caches 41a, 42a, 43a, 44a of the CPUs 41 to 44 (step S76 in FIG. 14). If the index result is “E” (step S87 in FIG. 16), “E” is registered. The cache that is being used is invalidated (step S88 in FIG. 16).
[0093]
In this case, in the memory controller 15, the data reply is read from the distributed shared memory 16 and sent to the bus 110 via the reply control circuit 156 (steps S59 and S62 in FIG. 13). The cache 11a registers the data reply with “E”, returns the data to the CPU 11 (step S63 in FIG. 13), and the read processing is completed. Note that the control and eviction control for the TAG memory 151 and the TAG swap buffer 152 are the same as the processing shown in FIGS. 17 and 18 described above.
[0094]
In the node (# 3) 4, the caches 41a, 42a, 43a, 44a of the CPUs 41 to 44 are indexed (step S76 in FIG. 14). If the index result is “S” (step S89 in FIG. 16), “S” is registered. The cache that is being used is invalidated (step S90 in FIG. 16).
[0095]
In this case, in the memory controller 15, the data reply is read from the distributed shared memory 16 and sent to the bus 110 via the reply control circuit 156 (steps S59 and S62 in FIG. 13). The cache 11a registers the data reply with “E”, returns the data to the CPU 11 (step S63 in FIG. 13), and the read processing is completed. Note that the control and eviction control for the TAG memory 151 and the TAG swap buffer 152 are the same as the processing shown in FIGS. 17 and 18 described above.
[0096]
In the node (# 3) 4, the caches 41a, 42a, 43a, 44a of the CPUs 41 to 44 are indexed (step S76 in FIG. 14), and if no cache is hit (step S91 in FIG. 16), nothing is done.
[0097]
In this case, in the memory controller 15, the data reply is read from the distributed shared memory 16 and sent to the bus 110 via the reply control circuit 156 (step S62 in FIG. 13). The cache 11a registers the data reply with “E”, returns the data to the CPU 11 (step S63 in FIG. 13), and the read processing is completed. Note that the control and eviction control for the TAG memory 151 and the TAG swap buffer 152 are the same as the processing shown in FIGS. 17 and 18 described above.
[0098]
When the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 is an address match and “S” (step S81 in FIG. 15), the TAG control control circuit sends a line read & invalidate request to the bus 140. Issue (step S82 in FIG. 15). The access target of the TAG memory or the TAG swap buffer of the node (# 3) 4 is invalidated “I” (step S83 in FIG. 15).
[0099]
Since the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 is “S”, the caches 41a, 42a, 43a, 44a on the bus 140 are “S” or “I”. If the index result is “S” (step S84 in FIG. 15), the cache in which “S” is registered is invalidated (step S90 in FIG. 16). If the index result is “I” (step S85 in FIG. 15), nothing is done. The registration, update, and eviction control of the TAG memory 151 and the TAG swap buffer 152 of the node (# 0) 1 are the same as the processes shown in FIGS. 17 and 18 described above.
[0100]
When the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 does not match the address or matches the address but is “I” (the matching condition is not satisfied with the valid data) (step in FIG. 15) S86), do nothing. The registration, update, and eviction control of the TAG memory 151 and the TAG swap buffer 152 of the node (# 0) 1 are the same as the processes shown in FIGS. 17 and 18 described above.
[0101]
Regarding the read to the distributed shared memory 46 of the other node (# 3) 4, the control of the cache 41a, 42a, 43a, 44a of each of the TAG memory, the TAG memory swap buffer, and the CPUs 41 to 44 is performed by the node (# 0) 1 described above. It is the same as the processing. The distributed shared memory 46 to be accessed is a node other than the request issuing node, and only the data transfer path between the nodes is different.
[0102]
Data read from the distributed shared memory 46 is transferred from the memory controller 45 to the memory controller 15 via the data line 304, the crossbar 5, and the data line 301. This data is transmitted from the determination circuit 155 to the bus 110 via the reply control circuit 156, and is registered in the cache 11a that issued the request.
[0103]
Further, in the other node (# 3) 4, only the data reply path changes depending on whether the invalidation of the cache from “M” to “I” occurs in the node (# 0) 1 or the other node.
[0104]
Next, writing to the distributed shared memory 16 of the own node (# 0) 1 will be described. In this case, the request issuer is the CPU 11. Even when issued from the CPUs 12 to 14 in the own node (# 0) 1, the cache control in each of the CPUs 12 to 14 and the operation of requests related thereto are assumed to be the same as the processing of the CPU 11.
[0105]
In the CPU 11, when the access target data is registered as “M” in the cache 11 a (step S 131 in FIG. 20), the cache 11 a is hit, the data in the cache 11 a is updated, and the status of the cache 11 a is “ M ”remains (step S132 in FIG. 20), and the write process is completed.
[0106]
In the CPU 11, when the data to be accessed is registered as “E” in the cache 11a (step S133 in FIG. 20), the cache 11a is hit, the data in the cache 11a is updated, and the status of the cache 11a is also “ M ″ is updated (step S134 in FIG. 20), and the write process is completed.
[0107]
In the CPU 11, when the access target data is registered with “S” in the cache 11 a (step S 135 in FIG. 20), the cache 11 a issues a bus acquisition request to the bus 110 (step S 137 in FIG. 20). Is acquired (step S138 in FIG. 20), a line read & invalidate request is issued (step S139 in FIG. 20).
[0108]
In the above line read & invalidate request, if the cache 11a is caching the write target with “S” (step S140 in FIG. 21), a memory line read & invalidate request is issued to the bus 110 (FIG. 21). Step S141).
[0109]
If any one of the store-in caches on the bus 110 is cached with “S” (step S142 in FIG. 21), it is invalidated and the registration of the cache 11a is invalidated “I” (step 21 in FIG. 21). S143).
[0110]
In parallel, the line read & invalidate request issued from the cache 11a is transferred to the TAG control circuit 153 via the request control unit 154 and issued to the inter-node address sharing bus 200 (step S144 in FIG. 21).
[0111]
In response to the transferred memory read & invalidate request, the TAG memory and the TAG swap buffer are indexed in the other nodes, and when the address coincides and “P” or “S” is detected (step S151 in FIG. 22), the invalidation “ I "(step S152 in FIG. 22), and an invalidate request is issued to the bus in the same node (step S153 in FIG. 22).
[0112]
Subsequently, in the other node, the cache registration cached in “S” is invalidated “I” (step S154 in FIG. 22), and the completion notification of the memory read & invalidate request is transmitted (step S155 in FIG. 22). Complete the index.
[0113]
In other nodes, when the index result of the TAG memory and the TAG swap buffer is “I” (step S156 in FIG. 22), nothing is done and a memory read & invalidate request completion notification is transmitted (step S155 in FIG. 22). To complete.
[0114]
When the TAG control circuit 153 receives the completion notification (snoop result) of the memory read & invalidate request issued to another node (step S145 in FIG. 21), the target area in either the TAG memory 151 or the TAG swap buffer 152 Is registered with “P” (step S146 in FIG. 21).
[0115]
Read reply data is read from the distributed shared memory 16 to which the address of the memory line read & invalidate request is mapped (step S147 in FIG. 21), and is returned to the cache 41a via the reply control circuit 156 (step S148 in FIG. 21). ).
[0116]
When the cache 11a receives the read reply data, it merges the read reply data with the write data and registers it as “M” (step S149 in FIG. 21), thereby completing the write process.
[0117]
In the CPU 11, when the data to be accessed does not match the address in the cache 11 a or the address matches but is invalidated “I” (step S 136 in FIG. 20), the cache 11 a issues a bus acquisition request to the bus 110. (Step S137 in FIG. 20) When the bus 110 has been acquired (Step S138 in FIG. 20), a line read & invalidate request is issued (Step S139 in FIG. 20).
[0118]
In the above line read & invalidate request, when the data to be accessed is registered as “M” in any of the caches 12a, 13a, and 14a of the CPUs 12 to 14 connected to the bus 110 (FIG. 23). In step S161), the caches 12a, 13a, and 14a write back (data reply) “M” data to the bus 110 (step S162 in FIG. 23).
[0119]
The caches 12a, 13a, and 14a that issued the write-back are invalidated and set to “I” (step S163 in FIG. 23). The above write back is transmitted to the distributed shared memory 16 via the request control unit 154 (step S164 in FIG. 23). Since the cache in the same node (# 0) 1 is already in the “M” state, the TAG status registered in the TAG memory 151 or the TAG swap buffer 152 remains “P” (step S165 in FIG. 23). .
[0120]
When the cache 11a receives the write-back data as reply data via the bus 110, the cache 11a registers with “M” to update the data (step S166 in FIG. 23) and completes the write process.
[0121]
In the above line read & invalidate request, when the access target data is registered as “E” in any of the caches 12a, 13a, and 14a of the CPUs 12 to 14 connected to the bus 110 (FIG. 24). In step S167), the caches 12a, 13a, and 14a are invalidated “I” (step S168 in FIG. 24), and the line read & invalidate request is transferred to the TAG control circuit 153 and the distributed shared memory 16 via the request control unit 154. (Step S169 in FIG. 24).
[0122]
The TAG control circuit 153 indexes the TAG memory 151 and the TAG swap buffer 152 (step S170 in FIG. 24), and updates the access target status to “P” from the output of the determination circuit 164 or the determination circuit 166 (step S171 in FIG. 24). .
[0123]
The data reply read from the distributed shared memory 16 by the line read request is transmitted to the cache 11a that issued the request via the reply control circuit 156 and the bus 110, and the cache 11a merges with the write data and becomes “M”. Registration (step S172 in FIG. 24) completes the write process.
[0124]
In the above line read & invalidate request, when the access target data is registered as “S” in any of the caches 12a, 13a, and 14a of the CPUs 12 to 14 connected to the bus 110 (FIG. 25). In step S173), the cache is invalidated “I” (step S174 in FIG. 25).
[0125]
The line read & invalidate request is transferred to the TAG control circuit 153 and the distributed shared memory 16 via the request control unit 154 (step S175 in FIG. 25). Further, since there is a possibility that the cache of another node is “S”, the TAG control circuit 153 issues an invalidate request to the inter-node address bus 200 (step S176 in FIG. 25).
[0126]
The memory controller of each node that has received the invalidate request (step S191 in FIG. 27) issues an invalidate request to the bus in the node (step S192 in FIG. 27). All the caches registered in “S” are invalidated “I” (step S193 in FIG. 27). If it is not cached (step S194 in FIG. 27), nothing is done. The area to be accessed in the TAG memory and the TAG swap buffer of the other node is invalidated “I” (step S195 in FIG. 27).
[0127]
The TAG control circuit 153 of the memory controller 15 in the own node (# 0) 1 updates the TAG memory 151 and the TAG swap buffer 152 to “P” (step S177 in FIG. 25).
[0128]
Further, the data reply read from the distributed shared memory 16 by the line read & invalidate request is transmitted to the request issuing source cache 11a via the reply control circuit 156 and the bus 110 (step S178 in FIG. 25). The cache 11a merges the data reply with the write data and registers it with “M” (step S179 in FIG. 25), and the write process is completed.
[0129]
In the above line read & invalidate request, when all of the caches 12a, 13a, 14a of the CPUs 12 to 14 connected to the bus 110 have not registered access target data (step S180 in FIG. 26), the line The read & invalidate request is transferred to the TAG control circuit 153 and the distributed shared memory 16 via the request control unit 154 (step S181 in FIG. 26).
[0130]
The TAG control circuit 153 issues a line read & invalidate request to the inter-node address bus 200 (step S182 in FIG. 26), and transfers the line request to the memory controllers of the other nodes (# 1 to # 3) 2 to 4.
[0131]
When the TAG control circuit of each of the memory controllers of the other nodes (# 1 to # 3) 2 to 4 receives a line request from the other node (step S201 in FIG. 28), the TAG memory and the TAG swap buffer are indexed (FIG. 28). Step S202). Hereinafter, the processing for each index result will be described, but the processing will be described with respect to the node (# 3) 4. However, the nodes (# 1, 2) 2 and 3 perform the same operation as the node (# 3) 4.
[0132]
When the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 matches the address and is “P” (step S203 in FIG. 28), the TAG control circuit issues an invalid request to the bus 140. (Step S204 in FIG. 28), the access target of the TAG memory or the TAG swap buffer of the node (# 3) 4 is invalidated “I” (Step S205 in FIG. 28).
[0133]
In the node (# 3) 4, the caches 41a, 42a, 43a, 44a of the CPUs 41 to 44 are indexed (step S206 in FIG. 28), and when the index result is “M” (step S207 in FIG. 28), “M” is registered. The cache that is writing writes the data back to the bus 140 and transfers it to the request controller (step S208 in FIG. 28). The cache registering “M” is invalidated “I” (step S209 in FIG. 28).
[0134]
The write-back is transferred as a data reply to the crossbar 5 via the data line 304 (step S210 in FIG. 28) and transferred to the memory controller 15 of the node (# 0) 1 via the data line 301.
[0135]
The determination circuit 155 of the memory controller 15 transfers the data reply to the reply control circuit 156 and the request control unit 154. The reply control circuit 156 transmits a data reply to the CPU 11 on the bus 110. The cache 11a merges the data reply and the write data and registers them with “M” (steps S183 and S184 in FIG. 26), and the write processing is completed.
[0136]
In the above process, the TAG control circuit 153 that issued the request receives the data reply and indexes the TAG memory 151 and the TAG swap buffer 152 in the same manner as the control of the TAG memory 151 and the TAG swap buffer 152 during the read operation. (FIG. 31, step S231). Here, the index result of the TAG memory 151 is as follows depending on the result of the determination circuit 166 or the output of the determination circuit 164 that determines the index result of the TAG swap buffer 152.
[0137]
If there is an empty area in the access target area of the TAG memory 151 (step S232 in FIG. 31), the key address and status “P” are registered in the empty area (step S233 in FIG. 31).
[0138]
If all the access target areas of the TAG memory 151 are registered as “P” (step S234 in FIG. 31), one of the areas is evicted to the TAG swap buffer 152, and the data reply key address and status “P” are used instead. "Is registered (step S235 in FIG. 31).
[0139]
When the access target area of the TAG memory 151 is filled with “P” or “S” (step S236 in FIG. 31), either “S” is pushed out to the TAG swap buffer 152, and instead a data reply key. The address and status “P” are registered (step S237 in FIG. 31).
[0140]
If all the access target areas of the TAG memory 151 are registered with “S” (step S238 in FIG. 31), one of the areas is expelled to the TAG swap buffer 152, and instead the key address and status “P” of the data reply "Is registered (step S239 in FIG. 31).
[0141]
In the above processing, when the TAG swap buffer 152 is full based on the result of the determination circuit 162 (step S240 in FIG. 32), if all stored in the TAG swap buffer 152 are “P” (step S241 in FIG. 32). , One of “P” is driven out (step S242 in FIG. 32). The TGA control circuit 153 issues an invalid request to the bus 110 with the address to be evicted (step S243 in FIG. 32). The operation for the invalid request will be described below.
[0142]
If “M” is registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 for the address of the invalidate request (step S251 in FIG. 33), write back to the bus 110, Invalidation “I” is performed (step S252 in FIG. 33). The write back is routed to the distributed shared memory 16 to be accessed via the request control unit 154, and the contents of the memory are updated (step S253 in FIG. 33).
[0143]
If “E” is registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 for the address of the invalid request (step S254 in FIG. 33), the cache is invalidated “I”. "(Step S255 in FIG. 33).
[0144]
If “S” is registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 for the address of the invalidate request (step S256 in FIG. 33), the cache is invalidated “I”. "(Step S255 in FIG. 33).
[0145]
If the address of the invalidate request is not registered in any of the caches 11a, 12a, 13a, and 14a on the bus 110 (step S257 in FIG. 33), nothing is done.
[0146]
In the node (# 3) 4, the caches 41a, 42a, 43a, 44a of the CPUs 41 to 44 are indexed (step S206 in FIG. 28), and when the index result is “E” (step S217 in FIG. 30), “E” is registered. The cache that has been invalidated is “I” (step S218 in FIG. 30).
[0147]
In this case, in the memory controller 15, the data reply is read from the distributed shared memory 16, and sent to the bus 110 via the reply control circuit 156 (steps S183 and S185 in FIG. 26). The cache 11a merges the data reply and the write data and registers them as “M” (step S186 in FIG. 26), and the write process is completed. Note that the control and eviction control for the TAG memory 151 and the TAG swap buffer 152 are the same as the processing shown in FIGS. 31 and 32 described above.
[0148]
In the node (# 3) 4, the caches 41a, 42a, 43a and 44a of the CPUs 41 to 44 are indexed (step S206 in FIG. 28). If the index result is “S” (step S219 in FIG. 30), “S” is registered. The invalidated cache is “I” (step S220 in FIG. 30).
[0149]
In this case, in the memory controller 15, the data reply is read from the distributed shared memory 16, and sent to the bus 110 via the reply control circuit 156 (steps S183 and S185 in FIG. 26). The cache 11a merges the data reply and the write data and registers them as “M” (step S186 in FIG. 26), and the write process is completed. Note that the control and eviction control for the TAG memory 151 and the TAG swap buffer 152 are the same as the processing shown in FIGS. 31 and 32 described above.
[0150]
In the node (# 3) 4, the caches 41a, 42a, 43a and 44a of the CPUs 41 to 44 are indexed (step S206 in FIG. 28), and if no cache is hit (step S221 in FIG. 30), nothing is done.
[0151]
In this case, in the memory controller 15, the data reply is read from the distributed shared memory 16, and sent to the bus 110 via the reply control circuit 156 (steps S183 and S185 in FIG. 26). The cache 11a merges the data reply and the write data and registers them as “M” (step S186 in FIG. 26), and the write process is completed. Note that the control and eviction control for the TAG memory 151 and the TAG swap buffer 152 are the same as the processing shown in FIGS. 31 and 32 described above.
[0152]
When the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 is an address match and “S” (step S211 in FIG. 29), the TAG control control circuit issues an invalid request to the bus 140 ( FIG. 29 step S212). The access target of the TAG memory or the TAG swap buffer of the node (# 3) 4 is invalidated “I” (step S213 in FIG. 29).
[0153]
Since the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 is “S”, the caches 41a, 42a, 43a, 44a on the bus 140 are “S” or “I”. When the index result is “S” (step S214 in FIG. 29), the cache in which “S” is registered is invalidated “I” (step S220 in FIG. 30). If the index result is “I” (step S215 in FIG. 29), nothing is done. The registration, update, and eviction control of the TAG memory 151 and the TAG swap buffer 152 of the node (# 0) 1 are the same as the processes shown in FIGS. 31 and 32 described above.
[0154]
If the index result of the TAG memory and the TAG swap buffer of the node (# 3) 4 does not match the address or matches the address but is “I” (the matching condition is not satisfied with the valid data) (step in FIG. 29) S216), do nothing. The registration, update, and eviction control of the TAG memory 151 and the TAG swap buffer 152 of the node (# 0) 1 are the same as the processes shown in FIGS. 31 and 32 described above.
[0155]
For writing to the distributed shared memory 46 of the other node (# 3) 4, the control of the TAG memory, the TAG memory swap buffer, and the caches 41a, 42a, 43a, 44a of each of the CPUs 41 to 44 of the node (# 0) 1 described above. It is the same as the processing. The distributed shared memory 46 to be accessed is a node other than the request issuing node, and only the data transfer path between the nodes is different.
[0156]
Data read from the distributed shared memory 46 is transferred from the memory controller 44 to the memory controller 15 via the data line 304, the crossbar 5, and the data line 301. This data is transmitted from the determination circuit 155 to the bus 110 via the reply control circuit 156, and is registered in the cache 11a that issued the request.
[0157]
Further, in the other node (# 3) 4, only the data reply path changes depending on whether the invalidation of the cache from “M” to “I” occurs in the node (# 0) 1 or the other node.
[0158]
In recent years, the capacity of the main memory and the capacity of the cache mounted on the CPU have been increased. Holding information in the entire memory space with the TAG memory requires a huge amount of hardware investment. In addition, increasing the capacity of the TAG memory complicates the control, and at the same time, does not necessarily ensure the performance commensurate with the hardware investment.
[0159]
In this embodiment, the TAG swap buffer 152 has effective information by the TAG memory 151 and the TAG swap buffer 152 that holds the swept information from the TAG memory 151. When the area of the TAG memory 151 becomes empty, the TAG swap buffer Re-registration from 152 is performed.
[0160]
The TAG swap buffer 152 does not issue a coherent request to the bus 110 until it is full. In addition, when there are a plurality of re-registration targets in the TAG memory 151 in the TAG swap buffer 152, priority is given to the one whose TAG status is “P” rather than “S”.
[0161]
Even when a coherent request from the TAG swap buffer 152 to the bus 110 is issued, the load on the bus in each node is reduced by providing a mechanism in which “P” is given priority over “S”. Since the memory 151 is effectively used, sweeping out from the caches 11a, 12a, 13a, 14a,..., 41a, 42a, 43a, 44a mounted on the CPUs 11 to 14,. . Therefore, the performance of the entire system is improved.
[0162]
【The invention's effect】
As described above, according to the present invention, the tag swap and the tag swap buffer that holds the swept information from the tag memory 151 have effective information in the tag swap buffer. By performing re-registration from the buffer, it is possible to reduce the load on the bus and to increase the cache hit rate and improve the performance of the entire system.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a distributed shared memory multiprocessor system according to an embodiment of the present invention.
2 is a block diagram showing a configuration of a memory controller in FIG. 1. FIG.
FIG. 3 is a diagram showing the contents held in the TAG memory of FIG. 2;
4 is a diagram showing the contents held in the TAG swap buffer of FIG. 2; FIG.
5 is a block diagram showing a control mechanism of the TAG memory and the TAG swap buffer in FIG. 2;
6 is a flowchart showing eviction control from the TAG memory of FIG. 2. FIG.
7 is a flowchart showing eviction control from the TAG swap buffer of FIG. 2; FIG.
FIG. 8 is a flowchart showing re-registration control from the TAG swap buffer of FIG. 2 to the TAG memory.
FIG. 9 is a flowchart showing a read process for the distributed shared memory in FIG. 1;
10 is a flowchart showing a read process for the distributed shared memory of FIG. 1. FIG.
FIG. 11 is a flowchart showing a read process for the distributed shared memory in FIG. 1;
12 is a flowchart showing a read process for the distributed shared memory in FIG. 1; FIG.
FIG. 13 is a flowchart showing a read process for the distributed shared memory of FIG. 1;
14 is a flowchart showing a read process for the distributed shared memory in FIG. 1. FIG.
15 is a flowchart showing a read process for the distributed shared memory of FIG. 1. FIG.
16 is a flowchart showing a read process for the distributed shared memory of FIG. 1. FIG.
FIG. 17 is a flowchart showing a read process for the distributed shared memory in FIG. 1;
FIG. 18 is a flowchart showing a read process for the distributed shared memory of FIG. 1;
FIG. 19 is a flowchart showing a read process for the distributed shared memory in FIG. 1;
20 is a flowchart showing a write process for the distributed shared memory in FIG. 1; FIG.
FIG. 21 is a flowchart showing a write process for the distributed shared memory in FIG. 1;
FIG. 22 is a flowchart showing a write process for the distributed shared memory in FIG. 1;
FIG. 23 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
24 is a flowchart showing a write process for the distributed shared memory in FIG. 1; FIG.
FIG. 25 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
FIG. 26 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
FIG. 27 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
FIG. 28 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
FIG. 29 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
30 is a flowchart showing a write process for the distributed shared memory in FIG. 1; FIG.
FIG. 31 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
32 is a flowchart showing a write process for the distributed shared memory in FIG. 1. FIG.
FIG. 33 is a flowchart showing a write process for the distributed shared memory of FIG. 1;
[Explanation of symbols]
1 to 4 nodes (# 0 to # 3)
5 Crossbar
6-1 to 6-4 I / O device
11-14, 41-44 CPU
11a, 12a, 13a,
14a, 41a, 42a,
43a, 44a cash
15, 45 Memory controller
16, 46 Distributed shared memory
151 TAG memory
152 TAG swap buffer
153 TAG control circuit
154 Request control unit
155, 162, 164
166 judgment circuit
156 reply control circuit section
161 registers
163,165 selection circuit

Claims (15)

A plurality of central processing units having a cache; a memory controller that processes a request from either the central processing unit or the input / output device; and a distributed shared memory that holds information of the cache. A distributed shared memory multiprocessor system including a plurality of nodes formed by bus connection between a device and the memory controller,
An inter-node address bus that connects each of the plurality of nodes, and a crossbar that connects each of the plurality of nodes and performs data processing between the plurality of nodes and processing of requests from the input / output devices. And
The memory controller includes a tag memory that holds information on the cache, a tag swap buffer that holds tag flush information in the tag memory, a tag control circuit that controls a request issued from the node, and each of the nodes A request control unit that controls a request to be accessed, and a reply control circuit that controls reply data in the node;
The tag control circuit includes a mechanism for indexing, registering, invalidating, and issuing a coherent request for the tag memory and the tag swap buffer,
A determination circuit for determining an index result of the tag memory and the tag swap buffer;
The determination circuit invalidates information in the tag swap buffer and re-registers in the tag memory when detecting that the area of the tag memory is an invalidation target and the same set address exists in the tag swap buffer. distributed shared memory multi-processor system and performs. The tag memory and the tag swap buffer hold address and status information registered in the cache in the node,
2. The tag swap buffer, when newly registering in a state where the area of the tag memory is fully registered, holds the address and status information obtained by swapping any one area. Distributed shared memory multiprocessor system. The tag control circuit simultaneously indexes the tag memory and the tag swap buffer when a tag index request is received, and the addresses held in the tag memory and the tag swap buffer match and status information is valid. 3. The distributed shared memory multiprocessor system according to claim 1 , wherein registration, update, invalidation, and request issuance to the bus are performed according to each index result. The decision circuit, wherein the claim 1, characterized in that to re-registration in the tag memory from the tag swap buffer when valid information to the tag swap buffer is empty present and the tag memory area Item 4. The distributed shared memory multiprocessor system according to any one of Items 3 to 4 . The determination circuit invalidates information of the tag swap buffer and re-registers it in the tag memory when it is determined that the area of the tag memory is to be invalidated and the same set address exists in the tag swap buffer. 5. The distributed shared memory type multiprocessor system according to claim 1 , wherein the distributed shared memory type multiprocessor system is used. The determination circuit preferentially re-registers the status information having a first value indicating one of all the states of the cache when a plurality of identical set addresses exist in the tag swap buffer. 6. The distributed shared memory multiprocessor system according to claim 1 , wherein the distributed shared memory type multiprocessor system is used. The determination circuit is in a state where there is a possibility that a plurality of status information is cached in the system from the tag memory and the tag swap buffer, and a state where the status information is not cached. 7. The distributed shared memory multiprocessor system according to claim 6, wherein the second value indicating the priority is given priority. The determination circuit does not hold in the tag swap buffer when all the statuses of the tag swap buffer are determined to be the first value and the status information to be swapped from the tag memory is determined to be the second value. 8. The distributed shared memory multiprocessor system according to claim 7, wherein A plurality of central processing units having a cache; a memory controller that processes a request from either the central processing unit or the input / output device; and a distributed shared memory that holds information of the cache. A tag control method for a distributed shared memory multiprocessor system including a plurality of nodes formed by bus connection between a device and the memory controller,
Each of the plurality of nodes is connected by an inter-node address bus and a crossbar that performs processing of data between the plurality of nodes and processing of a request from the input / output device,
The tag memory that holds the cache information and the tag swap buffer that holds the tag sweep information in the tag memory hold the address and status information registered in the cache in the node,
When newly registering the tag memory area with the tag memory area being fully registered in the tag swap buffer, the address and status information obtained by swapping any one of the areas are retained .
When determining the index result of the tag memory and the tag swap buffer, when it is detected that the area of the tag memory is an invalidation target and the same set address exists in the tag swap buffer, the tag swap buffer A tag control method characterized by invalidating information and performing re-registration in the tag memory . When the tag index request is received, the tag memory and the tag swap buffer are simultaneously indexed, and the addresses held in the tag memory and the tag swap buffer coincide with each other and the status information is valid according to the index result. The tag control method according to claim 9 , further comprising a step of performing registration, update, invalidation, and request issuance to the bus. Claims in determining the index results, and performs re-registration from the tag swap buffer when valid information to the tag swap buffer is empty present and the tag memory area to the tag memory Item 13. A tag control method according to Item 10 . When determining the index result, when it is determined that the area of the tag memory is to be invalidated and the same set address exists in the tag swap buffer, the information of the tag swap buffer is invalidated and the tag memory The tag control method according to claim 10 or 11 , wherein the tag control method is re-registered with the tag. When determining the index result, when there are a plurality of identical set addresses in the tag swap buffer, the status information is re-prioritized with the first value indicating one of all the states of the cache. The tag control method according to claim 11, wherein the tag control method is registered. When determining the index result, we have state and caching the valid clusters the status information is likely to have multiple caching in the system than the first value from the tag memory and the tag swap buffer 14. The tag control method according to claim 13 , wherein priority is given to the second value indicating any of the non-existing states. When determining the index result, the tag swap buffer when the status information of the swap target of all status from said first value a and the tag memory of the tag swap buffer determines that the second value 15. The tag control method according to claim 14 , wherein the tag is not held.

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