JP3678541B2 - Phase correction circuit, phase correction DLL circuit, multi-phase clock generation DLL circuit, and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a phase correction circuit, a phase correction DLL circuit, a multi-phase clock generation DLL circuit and a communication circuit, and a semiconductor device such as an MPU, a memory, or a logic LSI.BikoThe present invention relates to a semiconductor device including any of these circuits.
[0002]
[Prior art]
In the multi-phase clock generation DLL circuit using the VCO, the phase synchronization accuracy is high. However, when noise is applied to the input of the VCO, the synchronization is lost, and the lock time, which is the time until the synchronization is relatively long, is further increased during standby. There is much current consumption. In addition, since this DLL circuit processes an analog signal with high accuracy, circuit characteristics are likely to change due to variations in the manufacturing process.
[0003]
On the other hand, the multi-phase clock generation DLL circuit that controls the number of delay stages of the logic gate is digital signal processing, so the lock time is relatively short, the current consumption during standby is small, and noise and fluctuations in the manufacturing process And is easier to design than an analog DLL circuit.
FIG. 15 shows a schematic configuration of a conventional digital multi-phase clock generation DLL circuit.
[0004]
The multi-phase clock generation circuit 10 generates and outputs generated clocks φ1 to φn obtained by shifting the phase of the supplied reference clock CLK by θ, 2θ, 3θ,. FIG. 16 shows the generated clocks φ1 to φ6 when n = 6 together with the reference clock CLK.
The phase comparison circuit 12 supplies a shift pulse to the bidirectional shift register 11 so that the phase of the generated clock φn matches the reference clock CLK, and controls the number of delay stages in the multi-phase clock generation circuit 10. Thereby, the generated clock φn is synchronized with the reference clock CLK, and the phase difference θ is determined.
[0005]
[Problems to be solved by the invention]
However, since the number of delay stages of the logic gate is an integer, in FIG. 16, the phase synchronization error time ΔT of the generated clock φ6 with respect to the reference clock CLK is six times the phase error time τ of the generated clock φ1. For example, when the delay time of one delay stage is 100 psec, | τ | is 50 psec on average and | ΔT | = 300 psec. The ratio | ΔT | / T increases as the clock cycle T decreases as the operation speed increases.
[0006]
In order to make the ratio | ΔT | / T smaller, the phase matching determination range of the phase comparison circuit 12 is narrowed, that is, the phase synchronization determination accuracy is increased, and the number of phase stages is controlled more accurately. There is a need.
In view of the above problems, an object of the present invention is to provide a phase correction circuit, a phase correction DLL circuit, a multi-phase clock generation DLL circuit, and any one of these that can correct a phase error of the generated multi-phase clock. Another object is to provide a semiconductor device including such a circuit.
[0008]
[Means for solving the problems and their effects]
  In the phase correction circuit of claim 1Slow[Im / n] extension elements cascaded(However, when [im / n] = 1, “one connection”)The generated clock φi having a phase iθ with respect to the reference clock is [j (i / n)] of the [im / n] delays in response to the first control signal CCj (1 ≦ j ≦ m). An i-th delay circuit to which a bypass switch element is connected so as to be taken out through the element, for each i of 1 ≦ i ≦ n,
  Where [] is a rounding integer symbol, n ≧ 2,m ≧ 2,m ≧ [n / 2], and i, j, m, and n are all natural numbers.
[0009]
  The phase synchronization error time of the generated clock φi with respect to the reference clock is that of the generated clock φ1.iHowever, according to this phase correction circuit, the phase synchronization error of the generated clock φi is corrected by a value substantially proportional to i, so that all of the corrected phase synchronization errors of the generated clocks φ1d to φnd are average. In addition, there is an effect that the delay time is about half of the delay time of one delay element.
[0010]
According to a second aspect of the present invention, in the first aspect, the i-th delay circuit includes an i-th input wiring to which the generated clock φi is supplied, and for each j of 1 ≦ j ≦ m, the i-th input wiring and the i-th input wiring The bypass switch element is connected to the input terminal of the [j (i / n)]-th delay element from the output side of the i-th delay circuit, and the i-th input line and the output of the i-th delay circuit A through switch element is connected to the wiring.
[0011]
According to a third aspect of the present invention, in the phase correction circuit of the second aspect, the delay element includes an even number of inverters connected in cascade, and the bypass switch element includes an nMOS transistor and a pMOS transistor connected in parallel.
In the phase correction circuit of claim 4, in claim 2,
The delay element includes a first logic gate that is a NOR gate or a NAND gate, and an inverter connected to one input terminal of the first logic gate.
The bypass switch element of the i-th delay circuit has the first control signal supplied to one input terminal, the other input terminal connected to the i-th input wiring, and an output terminal connected to the i-th delay circuit. A second logic gate which is a NOR gate or a NAND gate connected to the other input terminal of the one logic gate.
[0012]
According to this phase correction circuit, the second logic gate through which the generated clock φi passes functions as a part of the delay element, and the delay time in each delay unit composed of one delay element and one bypass switch element is mutually As a result, the correction accuracy is improved.
In claim 5, in claim 1, the generated clock φi is supplied to an input terminal of the delay element at the first stage of the i-th delay circuit,
The i-th delay circuit has an i-th output line from which a clock obtained by delaying the generated clock φi is taken out. For each j of 1 ≦ j ≦ m, the i-th output line and the input of the i-th delay circuit The bypass switch element is connected to the output terminal of the [j (i / n)]-th delay element from the side, and the through switch is connected between the i-th output line and the input line of the i-th delay circuit. Switch element is connected.
[0013]
In the phase correction DLL circuit according to claim 6, the phase correction circuit according to any one of claims 1 to 5,
A first bidirectional shift register to which the first control signal CCj is output in parallel;
A phase comparison circuit that shifts the bidirectional shift register in one direction or in the other direction in accordance with the advance / delay of the phase so that the phase of the generated clock φn substantially matches the phase of the reference clock.
[0014]
According to this phase correction DLL circuit, even if the phase synchronization error changes due to a change in temperature or the like, the phase synchronization error including the phase correction circuit, the phase comparison circuit, and the bidirectional shift register can minimize the phase synchronization error. There is an effect of being automatically controlled.
In the multi-phase clock generation DLL circuit according to claim 7, the phase correction DLL circuit according to claim 6,
A multi-phase clock generation circuit for generating the generated clocks φ1 to φn having a phase corresponding to the second control signal PCk with respect to the reference clock;
And a second bidirectional shift register that is shift-controlled by the phase comparison circuit and that outputs the second control signal PCj in parallel.
[0015]
According to the multi-phase clock generation DLL circuit, the phase-locking error of the multi-phase clock generation DLL circuit is automatically controlled by both phase-locked loops of the phase correction DLL circuit and the multi-phase clock generation DLL circuit so as to be as small as possible. There is an effect.
In the multi-phase clock generation DLL circuit according to claim 8, the multi-phase clock generation circuit according to claim 7,
N delay elements are cascaded, and in response to the second control signal PCk, a first delay line in which a signal supplied to one end passes through the k consecutive delay elements in the N,
N delay elements are cascaded, one end is connected to the other end of the first delay line, and in response to the second control signal PCk, a signal supplied to the one end is a continuous k of the N. A second delay line through the delay elements;
A selection circuit that selects one of the output of the other end of the second delay line and the reference clock and supplies the selected one to the one end of the first delay line;
A first ring counter that is shifted by the output of the other end of the first delay line and outputs in parallel the odd numbered ones of the generated clocks φ1 to φn;
A second ring counter that is shifted by the output of the other end of the second delay line and outputs in parallel the even-numbered ones of the generated clocks φ1 to φn;
A selection control circuit that causes the selection circuit to select a leading edge or a trailing edge of the reference clock and to select an output of the other end of the first delay line in the remaining time.
[0016]
  According to this multi-phase clock generation DLL circuit, since the same clock circulates the first delay line and the second delay line a plurality of times, the number of delay line elements is reduced as compared with the configuration in which the first clock does not circulate, and the generated clocks φ1 to There is an effect that the phase difference between φn becomes more accurate..
[0017]
According to this phase comparison circuit, since the operations of the first nMOS transistor and the second nMOS transistor are faster than those of the pMOS transistor, even if the width of the positive pulse supplied to the gate of the first nMOS transistor is narrow, the second nMOS transistor The positive charge on the output wiring can be extracted at high speed through the first nMOS transistor and the second nMOS transistor when is turned on, and thereby the range in which it is determined that the phase of the generated clock matches the reference clock Can be made narrower than the conventional configuration using MOS transistors, and therefore the phase synchronization determination accuracy is improved.
[0023]
  Claim9In the semiconductor device according to any one of claims 1 to 5, the phase correction circuit according to any one of claims 1 to 5, and the phase correction DLL circuit according to claim 6.Or, Claim 7Or claim 8Described multi-phase clock generation DLL timesThe roadI have.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 shows a schematic configuration of a multi-phase clock generation DLL circuit according to the first embodiment of the present invention.
[0025]
This circuit is provided in a semiconductor device 1 such as an MPU, a memory, a communication LSI, or a logic LSI. The multi-phase clock generation circuit 10A outputs generated clocks φ1 to φn obtained by shifting the phase of the supplied reference clock CLK by θ, 2θ, 3θ,. The generated clocks φ1 to φn are supplied to the phase correction circuit 13 and delayed, respectively, and are extracted as generated clocks φ1d to φnd. Both the multi-phase clock generation circuit 10A and the phase correction circuit 13 can control the number of delay stages therein, and the number of these stages is determined by the outputs of the bidirectional shift registers 11 and 14, respectively. The phase comparison circuit 12A supplies a shift signal to the bidirectional shift registers 11 and 14 so that the phase of the generated clock φnd matches the reference clock CLK. The control circuit 15 supplies enable signals EN1 and EN2 to the bidirectional shift registers 11 and 14, respectively. The enable signals EN1 and EN2 are generated as described later based on the reset signal RST.
[0026]
FIG. 2 shows a configuration example of the phase correction circuit 13 together with the bidirectional shift register 14 when n = 6. In the figure, the block in which S is entered is a switch element, and the block in which TD is entered is a delay element. These switch elements are ON / OFF controlled by outputs B0 to B6 (first control signal CCj) of bits 140 to 146 of the bidirectional shift register 14.
[0027]
  For example, the delay element D61 and the switch element S61 constitute one delay unit, and a configuration example thereof is shown in FIG.
  The delay element D61 is formed by cascading an inverter D611 and an inverter D612 in order to delay the binary input without inverting it. The switch element S61 includes a transfer gate S611 in which an nMOS transistor and a pMOS transistor are connected in parallel, and an inverter S612 that inverts the binary value of B1 and supplies it to the gate of the pMOS transistor of the transfer gate S611. B1 is supplied to the gate of the nMOS transistor of the transfer gate S611. When B1 is ‘H’, the transfer gate S611 is turned on, and the generated clock φ6 passes through the transfer gate S611, the inverter D612, and the inverter D611. When B1 is 'L', the switch element S61 is turned off. FIG.InThe other delay units have the same configuration as this delay unit.
[0028]
FIG. 3B shows a configuration example of a selection circuit including the switch element S60 and the switch element S6 on the output side of the phase correction circuit 13.
The switch element S60 has the same configuration as the switch element S61 in FIG. The switch element S6 has the same configuration as the transfer gate of the switch element S60, and its control input terminal is wired so that the switch element S6 is turned on / off with respect to the on / off of the switch element S60.
[0029]
In FIG. 2, the phase correction circuit 13 includes delay circuits C1 to C6 that delay the generated clocks φ1 to φ6 and output the generated clocks φ1d to φ6d, respectively. The delay circuit C1 has one delay element, and each of the delay circuits C2 to C6 has 2 to 6 delay elements connected in cascade.
The switch element Sij (1 ≦ i ≦ 6, 1 ≦ j ≦ 6) of the phase correction circuit 13 has an input line Li to which the generated clock φi is supplied and k = [j (i / n) from the output side of the delay circuit Ci. )] Is connected to the input terminal of the delay element Dik. Here, [] is a rounded integer symbol, and this rounding is rounded off, for example. For example, the switch element S34 is connected between the input line L3 and the input terminal of [4 (3/6)] = 2nd delay element D32 from the output side of the delay circuit C3. The switch element S35 is connected between the input line L3 and the input terminal of the third delay element D33 [5 (3/6)] = third from the output side of the delay circuit C3. The switch element S13 is connected between the input line L1 and the input terminal of [3 (1/6)] = 1st delay element D11 from the output side of the delay circuit C1.
[0030]
When the number of delay element stages through which the generated clock φ6 passes is m, the number of delay element stages through which the generated clock φi (i = 1 to 5) passes is [m (i / n)].
For example, when B0 to B7 are '0000001', the switch elements S16, S26, S36, S46, S56 and S66 in the first column are turned on from the input side of the phase correction circuit 13, and the switch on the output side of the phase correction circuit 13 is turned on. The elements S1 to S6 are turned on, and all other switch elements are turned off. In this state, the generated clock φ6 is extracted from the input line L6 as the generated clock φ6d through the switch element S66, the delay elements D66 to D61, and the switch element S6, and m = 6. Therefore, the number of stages of delay elements through which the generated clock φi passes is [6 (i / 6)] = i.
[0031]
More specifically, the generated clock φ1 is extracted from the input line L1 as the generated clock φ1d through the switch element S16, the delay element D11, and the switch element S1. The generated clock φ2 passes through the switch element S26, the delay elements D22 and D21, and the switch element S2 from the input line L2, and is extracted as the generated clock φ2d. The generated clock φ3 passes through the switch element S36, the delay elements D33 to D31, and the switch element S3 from the input line L3 and is extracted as the generated clock φ3d. The generated clock φ4 is extracted as φ4d from the input line L4 through the delay elements D44 to D41 and the switch element S4. The generated clock φ5 is extracted as φ5d from the input line L5 through the switch element S56, the delay elements D55 to D51, and the switch element S5.
[0032]
For example, when B0 to B6 are “0001000”, the switch elements S13, S23, S33, S43, S53, and S63 in the fourth column are turned on from the input side of the phase correction circuit 13, and the switch on the output side of the phase correction circuit 13 is turned on. The elements S1 to S6 are turned on, and all other switch elements are turned off. In this state, the generated clock φ6 is extracted from the input line L6 through the switch element S63, the delay elements D63 to D61 and the switch element S6 as φ6d, and m = 3. Therefore, the number of stages of delay elements through which the generated clock φi passes is [3 (i / 6)] = [i / 2], and becomes 1, 1, 2, 2, and 3 when i = 1 to 5, respectively.
[0033]
More specifically, the generated clock φ1 is extracted from the input line L1 as the generated clock φ1d through the switch element S13, the delay element D11, and the switch element S1. The generated clock φ2 is taken out from the input line L2 as the generated clock φ2d through the switch element S23, the delay element D21, and the switch element S2. The generated clock φ3 is extracted from the input line L3 as the generated clock φ3d through the switch element S33, the delay elements D32 and D31, and the switch element S3. The generated clock φ4 is taken out from the input line L3 as the generated clock φ4d through the switch element S42, the delay elements D42 and D41, and the switch element S4. The generated clock φ5 passes through the switch element S53, the delay elements D53 to D51, and the switch element S5 from the input line L5 and is extracted as the generated clock φ5d.
[0034]
For each of i = 1 to 6, a through switch element Si0 is connected between the input wiring Li and the output wiring of the delay circuit Ci.
Next, the operation of the circuit of FIG. 1 configured as described above will be described.
Due to the pulse of the reset signal RST to the semiconductor device 1, the contents of the bidirectional shift register 14 are initialized to, for example, “1000000”, the phase correction circuit 13 enters the through state, and the enable signal EN2 is deactivated to both The operation of the direction shift register 14 is stopped, the enable signal EN1 is activated, and the same operation as in FIG. 15 is performed. That is, the multi-phase clock generation DLL circuit including the multi-phase clock generation circuit 10A, the phase comparison circuit 12A, and the bidirectional shift register 11 controls the phase of the generated clock φnd to match the phase of the reference clock CLK.
[0035]
As a result, the generated clocks φ1 to φ6 become as shown in FIG. 4, for example, with respect to the reference clock CLK. The phase differences between the rising edges of the generated clocks φ1 to φn and the rising edge of the reference clock CLK are θ to 6θ, respectively. Since the number of delay stages is an integer, the phase synchronization error time ΔT of the generated clock φ6 with respect to the reference clock CLK is six times the phase synchronization error time τ of the generated clock φ1, for example, one delay in the multiphase clock generation circuit 10A. When the delay time ta of the element is 100 psec, on average, | τ | = 50 psec and | ΔT | = 300 psec.
[0036]
Next, the enable signal EN1 is deactivated to stop the operation of the bidirectional shift register 11, the enable signal EN2 is activated, and the phase comprising the phase correction circuit 13, the phase comparison circuit 12A, and the bidirectional shift register 14 is reached. The bidirectional shift register 14 is shift-controlled by the correction DLL circuit so that the phase of the generated clock φnd matches that of the reference clock CLK, and the number of delay stages of the phase correction circuit 13 is controlled.
[0037]
As a result, the generated clocks φ1d to φ6d become as shown in FIG. 4, for example, with respect to the reference clock CLK. FIG. 4 shows a case where the outputs B0 to B6 of the bidirectional shift register 14 are adjusted to '0001000'. The delay time td of one delay element in the phase correction circuit 13 is substantially equal to that ta in the multiphase clock generation circuit 10A. The phase correction error time of the generated clocks φ1 to φ6 is corrected by td, td, 2td, 2td, 3td, and 3td, respectively, by the phase correction circuit 13, and the phase synchronization error time of the generated clock φ6d is the phase synchronization error time in FIG. ΔTd. In this case, the absolute values of the phase synchronization error times of the generated clocks φ1d to φ6d are about d / 2, 0, d / 2, 0, d / 2, and 0, respectively. In general, the average absolute value of the phase synchronization error times of the generated clocks φ1d to φ6d is about half of the delay time of one delay element.
[0038]
When the multiphase clock generation circuit 10A further delays the generated clock φ1 by the delay time ta corresponding to one stage of the delay element, the generated clocks φ2 to φ6 in FIG. 4 are 2ta, 3ta, 4ta, 5ta and 6ta, respectively. Just delay further. Since ta is substantially equal to td, the absolute values of the phase synchronization error times of the generated clocks φ1 to φ6 in this case are about td, 2td, 3td, 4td, and 5td, respectively. If this error is corrected by the phase correction circuit 13, the absolute values of the phase synchronization error times of the generated clocks φ1d to φ6d are about d / 2, 0, d / 2, 0, d / 2, and 0, respectively.
[0039]
According to the first embodiment, even if the phase synchronization error time ΔT changes due to a temperature change or the like, the phase synchronization error including the phase correction circuit 13, the phase comparison circuit 12A, and the bidirectional shift register 14 causes the phase synchronization error. The time ΔTd is automatically controlled so as to be as small as possible.
In the case of ΔT = 6ta, the multiphase clock generation circuit 10A can set ΔT = 0, so that the phase correction circuit 13 in FIG. 2 is controlled by the outputs B0 to B5 of the bidirectional shift register 14. Is sufficient. If the circuit element can be reduced to shorten the delay time ta, or depending on the allowable error, the number of delay stages that can be corrected is 5 or less, for example 3, generally [n / 2] may be considered. Here, [] is a rounded integer symbol.
[0040]
Next, the multi-phase clock generation circuit 10A in FIG. 1 will be described.
Although this circuit can have the same configuration as the conventional one, in this embodiment, the configuration shown in FIG. 5 is used.
In the reciprocating delay line 20, the output end of the delay line 21 is connected to the input end of the delay line 22, and the output end of the delay line 22 passes from one input end to the other end of the selection circuit 23 through the output end. Connected to the end, a loop is formed. The reference clock CLK is supplied to the other input terminal of the selection circuit 23, and the reference clock CLK is selected near the rising time of the reference clock CLK and supplied to the input terminal of the delay line 21. This clock passes through the delay line 21 and is supplied to the clock input terminal of the ring counter 24 as the clock FCK, and the ring counter 24 is shifted by 1 bit. The clock FCK further passes through the delay line 22 and is supplied to the clock input terminal of the ring counter 25 as the clock BCK, and the ring counter 25 is shifted by 1 bit. The clock BCK is selected by the selection circuit 23 and supplied to the input end of the delay line 21. When the same clock goes around the round-trip delay line 20 three times, the selection circuit 23 selects the vicinity of the rising edge of the reference clock CLK, and the above operation is repeated.
[0041]
Based on the reference clock CLK, the control circuit 26 generates a selection control signal CSEL that becomes a positive pulse near the rising point of the reference clock CLK, as shown in FIG. 7, and supplies it to the selection control input terminal of the selection circuit 23. The selection circuit 23 selects and outputs the reference clock CLK only during this pulse period. The control circuit 26 also detects the falling edge of the selection control signal CSEL, outputs a positive pulse, and supplies this to the gate of the nMOS transistor 27 as a clock pulse reset signal CRST. By this pulse, the nMOS transistor 27 is turned on, the input terminal of the delay line 21 is set to ‘L’, and the pulse width of the clock FCK is made shorter than that of the reference clock CLK.
[0042]
Both the ring counters 24 and 25 are initialized to “001” by the reset signal RST as shown in FIG. The contents of the ring counters 24 and 25 change as shown in FIG. 7 according to the pulses of the clocks FCK and BCK. The 3-bit parallel output of the ring counter 24 is taken out as generated clocks φ1, φ3 and φ5, and the 3-bit parallel output of the ring counter 25 is taken out as generated clocks φ2, φ4 and φ6.
[0043]
By such an operation, the time from the rise of the generated clock φ1 to the rise of the generated clock φ2, the time from the rise of the generated clock φ3 to the rise of the generated clock φ4, and the rise of the generated clock φ5 to the rise of the generated clock φ6 Are equal to the delay time ta of the delay line 22. The time from the rising edge of the generated clock φ2 to the rising edge of the generated clock φ3 and the time from the rising edge of the generated clock φ4 to the rising edge of the generated clock φ5 are all equal to the delay time ta of the delay line 21.
[0044]
The delay lines 21 and 22 are both cascaded with delay elements, and the number of delay stages can be controlled by the output of the bidirectional shift register 11.
FIG. 6 shows a configuration example of the round-trip delay line 20 together with the bidirectional shift register 11.
The delay line 21 includes cascade-connected delay elements D211 to D216, and switch elements S211 to S216 connected between the input line L7 and the input ends of the delay elements D211 to D216, respectively. The outputs (second control signal PCk) of the bits 111 to 116 of the bidirectional shift register 11 are supplied to the control input terminals of the switch elements S211 to S216, respectively. The delay line 22 includes cascaded delay elements D221 to D226, and switch elements S221 to S226 connected between the output wiring L8 and the input terminals of the delay elements D221 to D226, respectively. Output signals of bits 111 to 116 of the bidirectional shift register 11 are supplied to control input terminals of the switch elements S221 to S226, respectively. The switch element and the delay element have the same configuration as those of the phase correction circuit 13 described above.
[0045]
For example, when the output of the bits 111 to 116 is “000100”, the clock supplied to the input wiring L7 passes through the switch element S214, the delay elements D214, D215, and D216 to become the clock FCK, and further the delay elements D226, D225, D224, and The clock BCK passes through the switch element S224.
Next, the phase comparison circuit 12A in FIG. 1 will be described.
[0046]
FIG. 8 shows a configuration example of this circuit.
The reference clocks CLK and φn pass through the 1/2 frequency dividers 121 and 122, respectively, and become the reference clocks HCLK and Hφn whose frequency is the original half. The 1/2 frequency dividers 121 and 122 are for detecting the phase advance / delay accurately even if the phase difference between the reference clock CLK and the generated clock φn is π or more.
[0047]
In the phase advance detection circuit 123, the source of the pMOS transistor 31 is connected to the power supply line VDD, and the nMOS transistor 32 and the nMOS transistor 33 are connected in series between the ground line and the drain of the pMOS transistor 31 from which the down signal * DWN is extracted. It is connected. The edge detection circuit 34 detects the rising edge of the reference clock HCLK, generates a negative pulse, supplies this to the gate of the pMOS transistor 31 as the rising edge detection signal * RD1, and detects the falling edge of the reference clock HCLK to detect a positive pulse. Is supplied to the gate of the nMOS transistor 32 as the fall detection signal FD1. The inverting circuit 35 inverts the binary value of the generated clock Hφn and supplies it to the gate of the nMOS transistor 33 as the clock * Hφnd. The signal propagation delay time of the inverting circuit 35 is made substantially equal to the time required from the falling edge of the reference clock HCLK to its detection by the edge detection circuit 34.
[0048]
In the phase lag detection circuit 124, the source of the pMOS transistor 41 is connected to the power supply line VDD, and the nMOS transistor 42 and the nMOS transistor 43 are connected in series between the ground line and the drain of the pMOS transistor 41 from which the up signal * UP is extracted. It is connected. The edge detection circuit 44 detects the falling edge of the generated clock Hφn, generates a negative pulse, supplies this to the gate of the pMOS transistor 41 as the falling detection signal * FD2, and detects the positive edge of the generated clock Hφn. A pulse is generated and supplied to the gate of the nMOS transistor 42 as the rising detection signal RD2. The non-inverting circuit 45 delays the reference clock HCLK by a time substantially equal to the time required from the rising edge of Hφn to its detection by the edge detection circuit 44, and supplies it to the gate of the nMOS transistor 43 as the reference clock HCLKd.
[0049]
A more detailed configuration example of the phase comparison circuit 12A is shown in FIG.
In the edge detection circuit 34, the reference clock HCLK is delayed by an odd number of cascaded inverters 341 to 343 and supplied to one input terminal of the NAND gate 344 and the NOR gate 345, and the reference clock is supplied to the other input terminal of the NAND gate 344 and the NOR gate 345. A clock HCLK is supplied. Thus, the rising detection signal * RD1 and the falling detection signal FD1 are output from the NAND gate 344 and the NOR gate 345, respectively.
[0050]
In the edge detection circuit 44, the logic value of the generated clock Hφn is inverted through the inverter 440 and further delayed by an odd number of cascaded inverters 441 to 443 and supplied to one input terminal of the NAND gate 444 and the NOR gate 445. Then, the output of the inverter 440 is supplied to the other input terminals of the NAND gate 444 and the NOR gate 445. As a result, the falling detection signal * FD2 and the rising detection signal RD2 are output from the NAND gate 444 and the NOR gate 445, respectively.
[0051]
10 and 11 are time charts showing the operation of the circuit of FIG. 8 or FIG.
The pMOS transistor 31 is turned on by the negative pulse of the reference clock HCLK rising detection signal * RD1, and at this time, the nMOS transistor 32 is turned off, and the output wiring of the phase advance detection circuit 123 is charged to the power supply potential VDD. The nMOS transistor 32 is turned on by the positive pulse of the reference clock HCLK falling detection signal FD1, and at this time, as shown in FIG. 10, if the phase of Hφn is delayed from the reference clock HCLK, the clock * Hφnd is set to “L”. Thus, the nMOS transistor 33 is off, and the down signal * DWN remains “H”. On the contrary, as shown in FIG. 11, if the phase of the generated clock Hφn is ahead of the reference clock HCLK, the clock * Hφnd is' H ', the nMOS transistor 33 is on, and the down signal * DWN is' L Transition to '.
[0052]
Since the nMOS transistors 32 and 33 operate faster than the pMOS transistor 31, even if the pulse width of the falling detection signal FD1 is narrow, the nMOS transistors 32 and 33 are on the output wiring of the phase advance detection circuit 123 when the nMOS transistor 33 is on. Positive charges can be extracted to the ground side at high speed. This makes it possible for the phase advance detection circuit 123 to narrow the range in which it is determined that the phase of the generated clock φn matches the reference clock CLK compared to the conventional case.
[0053]
Further, the pMOS transistor 41 is turned on by the negative pulse of the generated clock Hφn falling detection signal * FD2, and at this time, the nMOS transistor 42 is turned off, and the output wiring of the phase lag detection circuit 124 is charged to the power supply potential VDD. The The nMOS transistor 42 is turned on by a positive pulse of the generated clock Hφn rising detection signal RD2, and if the phase of the generated clock Hφn is delayed from the reference clock HCLK as shown in FIG. The nMOS transistor 43 is on and the up signal * UP changes to 'L'. On the contrary, as shown in FIG. 11, if the phase of the generated clock Hφn is ahead of the reference clock HCLK, the reference clock HCLK is “L”, the nMOS transistor 43 is off, and the up signal * UP is “H”. 'Still.
[0054]
Since the nMOS transistors 42 and 43 operate faster than the pMOS transistor 41, even if the pulse width of the rising detection signal RD2 is narrow, the nMOS transistors 42 and 43 are positive on the output wiring of the phase lag detection circuit 124 when the nMOS transistor 43 is on. Charges can be extracted to the ground side at high speed. Thereby, also in the phase lag detection circuit 124, the range in which it is determined that the phase of the generated clock φn matches the reference clock CLK can be made narrower than before.
[0055]
Therefore, the phase synchronization determination accuracy of the phase comparison circuit 12A using the MOS transistor is improved as compared with the conventional configuration using the MOS transistor.
[Second Embodiment]
FIG. 12 shows a part of the phase correction circuit according to the second embodiment of the present invention. This circuit is a configuration example of a part of the delay circuit C5 in FIG. 2, and portions corresponding to those in FIG.
[0056]
The switch elements S53 to S56 are configured by NOR gates. One input terminal of each of the switch elements S53 to S56 is connected to the input line L5 as a data input terminal, and the other input terminal serves as a control input terminal. Supplied.
In the delay element D55, the output terminal of the switch element S56 is connected to one input terminal of the NOR gate D551, and the output terminal of the inverter D552 is connected to the other input terminal. The input terminal of the inverter D552 is connected to the power supply line VDD, whereby the NOR gate D551 functions as an inverter. Delay element D54 has the same configuration as delay element D55, and NOR gate D541 and inverter D542 thereof correspond to NOR gate D551 and inverter D552 of delay element D55, respectively. The input terminal of the inverter D542 is connected to the output terminal of the NOR gate D551. The delay element D53 has the same configuration as the delay element D54 except that the NOR gate D531 has three inputs. The NOR gate D531 and the inverter D532 correspond to the NOR gate D541 and the inverter D542 of the delay element D54, respectively. The input terminal of the inverter D532 is connected to the output terminal of the NOR gate D541. The output ends of the switch elements S53 and S54 which are NOR gates are connected to the input end of the NOR gate D531.
[0057]
The logical values of the shift register outputs B3 to B6 are inverted from the case of the first embodiment. For example, when B3 to B6 are “1110”, the outputs of the switch elements S53 to S55 are fixed to “L”, the NOR gates D531 and D541 function as an inverter, and the switch element S56 functions as an inverter. Therefore, the generated clock φ5 passes through the switch element S56, the NOR gate D551, the inverter D542, the NOR gate D541, the inverter D532, and the NOR gate D531.
[0058]
In this case, in the delay unit composed of the switch element S56 and the delay element D55, the signal is delayed by the switch element S56 and the NOR gate D551, and in the delay unit composed of the switch element S55 and the delay element D54, the signal is transmitted by the inverter D542 and the NOR gate D541. In the delay unit including the switch element S53 and the delay element D53, the signal is delayed by the inverter D532 and the NOR gate D531.
[0059]
Therefore, the number of delay logic gate stages in each delay unit is two.
[Third Embodiment]
FIG. 13 shows a configuration example of the phase correction circuit 13A according to the third embodiment of the present invention, together with the bidirectional shift register 14.
The phase correction circuit 13A has a configuration in which the input and output of the phase correction circuit 13 in FIG. 2 are reversed and the switch elements S1 to S6 of the phase correction circuit 13 are omitted. The shift direction of the phase comparison circuit 12A with respect to the bidirectional shift register 14 is opposite to that in the first embodiment.
[0060]
The switch elements Sij (1 ≦ i ≦ 6, 1 ≦ j ≦ 6) of the phase correction circuit 13A are connected to the output wiring Fi from which the generated clock φid is output and k = [j (i / n) from the input side of the delay circuit CiA. )] Is connected between the output terminal of the delay element Dik. For example, the switch element S34 is connected between the output wiring F3 and the output terminal of the second delay element D32 [4 (3/6)] = 2 from the input side of the delay circuit C3A. The switch element S35 is connected between the output wiring F3 and the output terminal of the third delay element D33 [5 (3/6)] = third from the input side of the delay circuit C3A. The switch element S13 is connected between the output wiring F1 and the output terminal of the delay element D11 of [3 (1/6)] = 1st from the input side of the delay circuit C1A.
[0061]
When the number of delay element stages through which the generated clock φ6 passes is m, the number of delay element stages through which the generated clock φi (i = 1 to 5) passes is [m (i / n)].
For example, when the outputs B6 to B0 of the bits 146 to 140 of the bidirectional shift register 14 are “0010000”, the generated clocks φ1 to φ6 first pass through the delay path, and then the fifth column from the input side of the phase correction circuit 13A. Pass through the eye switch element to the output wiring.
[0062]
[Fourth Embodiment]
FIG. 14 shows a phase comparison circuit 12B according to the fourth embodiment of the present invention.
The phase advance detection circuit 123A and the phase delay detection circuit 124A of this circuit have the same configuration as the phase delay detection circuit 124 and the phase advance detection circuit 123 of FIG. Even in such a configuration, signals supplied to the edge detection circuit 44 and the non-inverting circuit 45 of the phase advance detection circuit 123A are supplied to the edge detection circuit 44 and the non-inverting circuit 45 of the phase advance detection circuit 123 of FIG. Therefore, the down signal * DWN can be generated by the phase advance detection circuit 123A. The same applies to the phase lag detection circuit 124A.
[0063]
Note that the present invention includes various other modifications.
For example, the bidirectional shift register 11 and the bidirectional shift register 14 may be activated at the same time to control two synchronous loops simultaneously. Further, the phase comparison circuit is a combination of the phase advance detection circuit 123 of FIG. 8 and the phase delay detection circuit 124A of FIG. 14, or a combination of the phase delay detection circuit 124 of FIG. 8 and the phase advance detection circuit 123A of FIG. May be. The multi-phase clock generation circuit of FIG. 5 may be configured to return the clock FCK to the selection circuit 23 without using the delay line 22 and shift the ring counter 25 at the falling edge of the clock FCK.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a multi-phase clock generation DLL circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of a phase correction circuit in FIG. 1 together with a shift register.
3A is a circuit diagram showing a configuration example of a delay unit in FIG. 2, and FIG. 3B is a circuit diagram showing a configuration example of a selection circuit in FIG. 2;
4 is a timing chart showing the operation of the circuit of FIG.
FIG. 5 is a block diagram showing a configuration example of the multi-phase clock generation circuit in FIG. 1 together with a shift register.
6 is a block diagram showing a configuration example of a reciprocating delay line in FIG. 5 together with a shift register. FIG.
7 is a time chart showing the operation of the circuit of FIG.
8 is a diagram illustrating a configuration example of a phase comparison circuit in FIG. 1. FIG.
FIG. 9 is a diagram illustrating a configuration example of the circuit of FIG. 8;
10 is a time chart showing the operation of the circuit of FIG. 8 or FIG. 9;
11 is a time chart showing the operation of the circuit of FIG. 8 or FIG. 9;
FIG. 12 is a diagram showing a part of a phase correction circuit according to a second embodiment of the present invention.
FIG. 13 is a block diagram showing a configuration example of a phase correction circuit according to a third embodiment of the present invention, together with a shift register.
FIG. 14 is a diagram illustrating a configuration example of a phase comparison circuit according to a fourth embodiment of the present invention.
FIG. 15 is a block diagram showing a schematic configuration of a conventional multi-phase clock generation DLL circuit.
16 is a time chart showing the operation of the circuit of FIG.
[Explanation of symbols]
10, 10A multi-phase clock generation circuit
11, 14 Bidirectional shift register
12, 12A, 12B Phase comparison circuit
123, 123A phase advance detection circuit
124, 124A phase delay detection circuit
13, 13A Phase correction circuit
31, 41 pMOS transistor
32, 33, 42, 43 nMOS transistors
34, 44 Edge detection circuit
35 Inversion circuit
45 Non-inverting circuit
C1 to C6, C1A to C6A delay circuit
L1-L7 input wiring
L8, F1-F6 output wiring
S1 to S6, S10 to S66 switch elements
D11, D21, D22, D31 to D33, D41 to D44, D51 to D55, D61 to D66 Delay element

Claims (9)

[Im / n] delay elements are connected in cascade (however, when [im / n] = 1, “1 connection”) , and the generated clock φi whose phase is iθ with respect to the reference clock is the first control signal CCj (1 .Ltoreq.j.ltoreq.m) The i-th delay circuit to which the bypass switch element is connected so as to be taken out through the [j (i / n)] delay elements out of the [im / n]. For each i of 1 ≦ i ≦ n,
Here, [] is a rounded integer symbol, n ≧ 2, m ≧ 2, m ≧ [n / 2], and i, j, m, and n are all natural numbers. A phase correction circuit.   The i-th delay circuit has an i-th input wiring to which the generated clock φi is supplied. For each j of 1 ≦ j ≦ m, the i-th input circuit and the output side of the i-th delay circuit [j (I / n)] the bypass switch element is connected to the input terminal of the i th delay element, and the through switch element is connected between the i th input line and the output line of the i th delay circuit. The phase correction circuit according to claim 1, wherein the phase correction circuit is connected.   3. The phase correction circuit according to claim 2, wherein the delay element is formed by connecting an even number of inverters in cascade, and the bypass switch element is formed by connecting an nMOS transistor and a pMOS transistor in parallel. The delay element includes a first logic gate that is a NOR gate or a NAND gate, and an inverter connected to one input terminal of the first logic gate.
The bypass switch element of the i-th delay circuit has the first control signal supplied to one input terminal, the other input terminal connected to the i-th input wiring, and an output terminal connected to the i-th delay circuit. A second logic gate that is a NOR gate or a NAND gate connected to the other input terminal of the one logic gate;
The phase correction circuit according to claim 2, further comprising: The generated clock φi is supplied to the input terminal of the delay element at the first stage of the i-th delay circuit,
The i-th delay circuit has an i-th output line from which a clock obtained by delaying the generated clock φi is taken out. For each j of 1 ≦ j ≦ m, the i-th output line and the input of the i-th delay circuit The bypass switch element is connected to the output terminal of the [j (i / n)]-th delay element from the side, and the through switch is connected between the i-th output line and the input line of the i-th delay circuit. The phase correction circuit according to claim 1, wherein a switching element is connected. A phase correction circuit according to any one of claims 1 to 5;
A first bidirectional shift register to which the first control signal CCj is output in parallel;
A phase comparison circuit that shifts the bidirectional shift register in one direction or the other in accordance with the advance / delay of the phase so that the phase of the generated clock φn with respect to the reference clock is substantially matched;
A phase correction DLL circuit comprising: A phase correction DLL circuit according to claim 6;
A multi-phase clock generation circuit for generating the generated clocks φ1 to φn having a phase corresponding to the second control signal PCk with respect to the reference clock;
A second bidirectional shift register that is shift-controlled by the phase comparison circuit and outputs the second control signal PCj in parallel;
A multi-phase clock generation DLL circuit comprising: The multi-phase clock generation circuit is
N delay elements are cascaded, and in response to the second control signal PCk, a first delay line in which a signal supplied to one end passes through the k consecutive delay elements in the N,
N delay elements are cascaded, one end is connected to the other end of the first delay line, and in response to the second control signal PCk, a signal supplied to the one end is a continuous k of the N. A second delay line through the delay elements;
A selection circuit that selects one of the output of the other end of the second delay line and the reference clock and supplies the selected one to the one end of the first delay line;
A first ring counter that is shifted by the output of the other end of the first delay line and outputs in parallel the odd numbered ones of the generated clocks φ1 to φn;
A second ring counter that is shifted by the output of the other end of the second delay line and outputs in parallel the even-numbered ones of the generated clocks φ1 to φn;
A selection control circuit that causes the selection circuit to select a leading edge or a trailing edge of the reference clock and to select an output of the other end of the first delay line in the remaining time;
The multi-phase clock generation DLL circuit according to claim 7, comprising:   A phase correction circuit according to any one of claims 1 to 5, a phase correction DLL circuit according to claim 6, or a multi-phase clock generation DLL circuit according to claim 7 or 8. A semiconductor device characterized by the above.

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