JP3666580B2 - DMA transfer control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a direct memory access (Direct Memory Access, hereinafter simply referred to as “DMA”) transfer control device, and more particularly to a DMA transfer control device using a data transfer request signal and a Write / Read clock signal.
[0002]
[Prior art]
DMA is a method for directly exchanging data between an input / output device and a memory or between memories without using a CPU. According to this method, when a large amount of data is transferred, processing can be performed in a lump, so that the data transfer speed can be improved as compared with that via the CPU. In the meantime, by causing the CPU to perform other work, the work can be efficiently performed as a whole.
[0003]
FIG. 5 is a diagram showing a configuration example of an interface using a conventional DMA transfer control device.
In FIG. 5, the first device 1 and the second device 2 are connected by an external bus 3 standardized by IEEE 1394 or the like. The first device 1 includes a first integrated circuit 4 and a second integrated circuit 5, and the first integrated circuit 4 and the second integrated circuit 5 transmit a transfer request signal (DMARQ) that requests data transfer. ) 6, a transfer clock signal (NIORD) 7 for reading data, a transfer clock signal (NIOWR) 8 for writing data, and a data line (Data) 9 for transmitting / receiving n-bit data. Connected by a DMA interface.
[0004]
Here, data transfer from the first integrated circuit 4 to the second integrated circuit 5 is referred to as a Read operation in the DMA interface, and data transfer from the second integrated circuit 5 to the first integrated circuit 4 is a Write operation in the DMA interface. That's it.
[0005]
Next, the Read operation and the Write operation will be described.
FIG. 6 is a diagram for explaining the timing of a Read operation taking 3Word data transfer as an example, and FIG. 7 is a diagram for explaining the timing of a Write operation taking 3Word data transfer as an example.
[0006]
First, the timing of the Read operation will be described with reference to FIG.
At time t0, the first integrated circuit 4 asserts DMARQ6 (signal rise) to notify the start of data transfer. At time t1, the second integrated circuit 5 recognizes the start of data transfer and changes NIORD 7 to “L”. At this time, the first integrated circuit 4 outputs data “W00” in synchronization with the change of NIORD 7 to “L”. At time t2, the second integrated circuit 5 changes NIORD7 to “H” and captures data “W00”. Therefore, 1 Word of data is transferred from the first integrated circuit 4 to the second integrated circuit 5 by the above-described operation.
[0007]
At time t3, after the first integrated circuit 4 outputs the last data “W02”, at time t4, the first integrated circuit 4 negates DMARQ 6 (signal falls) to notify the completion of data transfer. At time t5, the second integrated circuit 5 recognizes the completion of the data transfer, and when the NIORD 7 is changed to “H”, the data transfer is completed.
[0008]
Here, the first integrated circuit 4 outputs the data “W” in synchronization with the change of NIORD 7 to “L” in the second integrated circuit 5. Therefore, in order to notify the completion of data transfer, the first integrated circuit 4 must negate the DMARQ 6 during a period from time t3 to time t5, that is, during a period when NIORD7 is changed to “L”.
[0009]
Next, the timing of the write operation will be described with reference to FIG.
At time t6, the first integrated circuit 4 notifies the start of data transfer by asserting DMARQ6. At time t7, the second integrated circuit 5 recognizes the start of data transfer, changes NIOWR8 to “L”, and outputs data “W10”. At time t8, the second integrated circuit 5 changes NIOWR8 to “H”. At this time, the first integrated circuit 4 captures the data “W10” in synchronization with the change of NIOWR8 to “H”. Therefore, 1 Word of data is transferred from the second integrated circuit 5 to the first integrated circuit 4 by the above-described operation.
[0010]
At time t9, the second integrated circuit 5 changes NIOWR8 to “L” and outputs the last data “W12”. Then, the first integrated circuit 4 recognizes that the NIOWR 8 has changed to “L”, negates the DMARQ 6 at time t 10, and notifies the completion of the data transfer. At time t11, the second integrated circuit 5 recognizes the completion of data transfer, and when the NIOWR 8 is changed to “H”, the data transfer is completed.
[0011]
Here, the first integrated circuit 4 captures the data “W” in synchronization with the NIOWR 8 being changed to “H” in the second integrated circuit 5. Therefore, in order to notify the completion of data transfer, the first integrated circuit 4 must negate the DMARQ 6 during the period from the time t9 to the time t11, that is, during the period when the NIOWR8 is changed to “L”.
[0012]
However, generally, the first integrated circuit 4 and the second integrated circuit 5 often have different system clock frequencies. Therefore, when the conventional DMA transfer control device in FIG. 5 is configured, a circuit that operates by NIORD 7 and NIOWR 8 that is not synchronized with the system clock frequency is required. Therefore, a control circuit for controlling the DMA is required in the first integrated circuit 4 as shown in FIGS.
[0013]
FIG. 8 is a circuit configuration diagram of a DMA interface employing the burst transfer method.
In FIG. 8, the first integrated circuit 10 includes a logic circuit 20 and a DMA counter 22. The logic circuit 20 manages n-bit data, and outputs a transfer HOLD signal 29 for stopping the data transfer and a transfer start signal 28 for starting the data transfer. The DMA counter 22 has a counter for setting a data transfer amount, receives a transfer HOLD signal 29 and a transfer start signal 28, transmits a transfer request signal (DMARQ) 27 to the second integrated circuit 11, and outputs a second signal. Transfer clock signals (NIORD24, NIOWR25) are received from the integrated circuit 11. Further, the logic circuit 20 and the DMA counter 22 are operated by the clock 23.
[0014]
Next, the operation of the burst transfer DMA interface described above will be described with reference to FIG.
FIG. 9 is a diagram for explaining the timing of the Read operation and the Write operation of the burst transfer system DMA interface.
[0015]
At time t20, the logic circuit 20 changes the transfer start signal 28 to “H”. At time t21, the DMA counter 22 receives the transfer start signal 28 from the logic circuit 20, initializes the counter value, and asserts the DMARQ 27 to notify the start of data transfer. At time t22, the second integrated circuit 11 recognizes the start of data transfer and changes NIORD 24 or NIOWR 25 to “L”. At this time, if NIORD 24 is changed to “L”, the first integrated circuit 10 outputs Data 26 in synchronization with the change of NIORD 24 to “L”, and the second integrated circuit 11 outputs n-bit data. take in. On the other hand, if the NIOWR 25 is changed to “L”, the second integrated circuit 11 outputs Data 26 and the first integrated circuit 10 captures n-bit data. Therefore, data is transferred by the above-described operation. The DMA counter 22 detects that the NIORD 24 or NIOWR 25 has been changed to “L” and updates the counter value. This operation is performed in synchronization with the clock 23.
[0016]
On the other hand, when the logic circuit 20 cannot transfer data, the logic circuit 20 outputs a transfer HOLD signal 29. For example, when the logic circuit 20 changes the transfer HOLD signal 29 to “H” at time t23, the DMA counter 22 negates the DMARQ 27 at time t24. Therefore, data transfer is stopped at this point. At time t25, when the logic circuit 20 changes the transfer HOLD signal 29 to “L”, at the same time, the DMA counter 22 reasserts the DMARQ 27 and starts data transfer.
[0017]
When the counter value becomes “0” at time t26, the DMA counter 22 negates the DMARQ 27 at time t27 to notify the completion of data transfer. At time t28, the second integrated circuit 5 recognizes the completion of data transfer and changes NIORD 24 or NIOWR 25 to “H”. The data transfer is completed by the above operation.
[0018]
FIG. 10 is a circuit configuration diagram of a DMA interface employing a handshake method.
In FIG. 10, the first integrated circuit 30 includes a logic circuit 40, a DMARQ generation circuit 41, and a DMA counter 42. The logic circuit 40 manages n-bit data, and outputs a transfer HOLD signal 50 for stopping the data transfer and a transfer start signal 46 for starting the data transfer. The DMARQ generation circuit 41 transmits a transfer request signal (DMARQ) 48 to the second integrated circuit 31 and receives transfer clock signals (NIORD44, NIOWR45) from the second integrated circuit 31, and updates the counter value of the DMA counter 42. The clock detection signal 49 is output. The DMA counter 42 has a counter for setting the data transfer amount, receives a transfer HOLD signal 50 and a transfer start signal 46 from the logic circuit 40, and receives a counter update signal 47 for notifying that the counter value has been updated. The data is output to the DMARQ generation circuit 41. The logic circuit 40, the DMARQ generation circuit 41, and the DMA counter 42 are operated by a clock 43.
[0019]
Next, the operation of the above-described handshake DMA interface will be described with reference to FIG.
FIG. 11 is a diagram for explaining the timing of the Read operation and the Write operation of the handshake DMA interface.
At time t40, the logic circuit 40 changes the transfer start signal 46 to “H”. At time t41, the DMA counter 22 receives the transfer start signal 46 from the logic circuit 40, initializes the counter value, changes the counter update signal 47 to “H”, and outputs it to the DMARQ generation circuit 41. At the same time, the DMARQ generation circuit 41 notifies the start of data transfer by asserting DMARQ. At time t42, the second integrated circuit 31 recognizes the start of data transfer and changes NIORD 44 or NIOWR 45 to “L”. At this time, if NIORD 44 is changed to “L”, the first integrated circuit 30 outputs Data 51 in synchronization with the change of NIORD 44 to “L”, and the second integrated circuit 31 outputs n-bit data. take in. On the other hand, if the NIOWR 45 is changed to “L”, the second integrated circuit 31 outputs Data 51 and the first integrated circuit 30 takes in n-bit data. Therefore, data is transferred by the above-described operation.
[0020]
Subsequently, in the logic circuit 40, when data transfer becomes impossible, the DMARQ generation circuit 41 detects that the NIORD 44 or NIOWR 45 has been changed to “L”, and negates the DMARQ 48 at time t43. Therefore, data transfer is stopped at this point. At time t44, the second integrated circuit 31 recognizes that the DMARQ 48 has been negated, and changes the NIORD 44 or NIOWR 45 to “H”.
[0021]
Further, the DMARQ generation circuit 41 detects that the NIORD 44 or NIOWR 45 has been changed to “L” at the time t42, and outputs the clock detection signal 49 at the time t45. As a result, the DMA counter 42 updates the counter value. If the transfer HOLD signal 50 is not output from the logic circuit 40 at this time, the DMARQ generation circuit 41 reasserts the DMARQ 48 at time t46 to resume data transfer.
[0022]
[Problems to be solved by the invention]
However, the DMA interface circuit based on the burst transfer system updates the counter value when NIORD 24 or NIOWR 25 changes to “L”, and negates DMARQ 27 when the counter value becomes “0”. Therefore, if the DMA counter 22 negates the DMARQ 27 while the NIORD 24 or NIOWR 25 is changed to “L”, the clock frequency must be at least twice that of the NIORD 24 or NIOWR 25. However, when the frequency of NIORD 24 or NIOWR 25 is increased in order to improve the data transfer performance of the first integrated circuit 10 and the second integrated circuit 11, the frequency of the clock 23 that controls the first integrated circuit 10 becomes NIORD 24 or Since the frequency increases at twice the speed of NIOWR25, it is necessary to design a circuit that operates with a very high-speed clock, which is a serious obstacle in semiconductor design.
[0023]
In addition, since DMARQ 48 is negated regardless of the clock 43 in the DMA interface circuit based on the handshake method, the operation of NIORD 44 or NIOWR 45 operates independently of the frequency of the clock 43, unlike the burst transfer method described above. This is advantageous in terms of semiconductor design. However, since the internal processing must be completed (operation from time t44 to time t46) before the DMARQ 48 is negated and asserted again, the transfer performance is caused by the processing time overhead of the first integrated circuit 30. There has been a problem that is greatly deteriorated.
[0024]
The present invention has been made to solve such a problem, and can transfer data at high speed and efficiently by the handshake method without reducing the cycle of the internal clock by the burst transfer method. An object is to provide a DMA transfer control device.
[0025]
[Means for Solving the Problems]
  A DMA transfer apparatus according to the present invention is a DMA transfer control apparatus that controls direct memory access (DMA) transfer between integrated circuits, and the integrated circuit that transmits data of the DMA transfer control apparatus is configured to transmit the DMA transfer data. With multiple buffer memory to store,UpIn parallel with each of the multiple buffer memoriesA plurality of handshake circuits for outputting a buffer memory data transfer request signal for requesting transfer of the data when a write request signal for requesting writing of data stored in each buffer memory is input; A DMA counter that counts based on a write clock signal for writing, and a write pointer that counts when the write clock signal is input, and the buffer memory according to the value of the write pointer, A write control circuit for outputting the write request signal to the handshake circuit;Requests reading of data from the integrated circuit receiving the data of the DMA transfer control device.When the read transfer clock signal is inputHas a read pointer for countingBased on the read control circuit for outputting a read request signal for requesting data reading to the handshake circuit according to the value of the read pointer, the buffer memory data transfer request signal, and the value of the read pointer, A transfer request signal for requesting data transfer is output to the integrated circuit that receives the data of the DMA transfer control device.Transfer request signal generation circuit and,Is included.
[0026]
  The DMA transfer control device according to the present invention is a DMA transfer control device that controls direct memory access (DMA) transfer between integrated circuits, and the integrated circuit that receives data of the DMA transfer control device is the DMA transfer control device. Multiple buffer memories that store transfer data and,UpIn parallel with each of the multiple buffer memoriesA plurality of handshake circuits for outputting a buffer memory data transfer request signal for requesting the transfer of data and a data transfer when a write permission signal for permitting data writing is input to the buffer memory A DMA counter that receives the transfer start signal, outputs the write enable signal to the buffer memory, and inputs a read clock signal for reading data; and a count based on the read clock signal;Requests data writing from an integrated circuit that transmits data of the DMA transfer control device.When the write transfer clock signal is inputHas write pointer for countingA write control circuit for outputting a write request signal for requesting writing of data to the buffer memory and the handshake circuit according to a signal output from the write pointer; and the read clock signal. A read control circuit that has a read pointer for counting and outputs a read request signal for requesting reading of the data to the handshake circuit according to a signal output from the read pointer; and the buffer memory data transfer request Based on the signal and the signal output from the write pointer, a transfer request signal for requesting data transfer is output to the integrated circuit that transmits the data of the DMA transfer control device.Transfer request signal generation circuit and,Is included.
[0027]
  The DMA transfer control device according to the present invention is a DMA transfer control device that controls direct memory access (DMA) transfer between integrated circuits, and the integrated circuit that transmits and receives data of the DMA transfer control device Multiple buffer memories that store transfer data and,UpIn parallel with each of the multiple buffer memoriesProvided, when reading data from the other integrated circuit, when a write request signal for requesting writing of data stored in each buffer memory is input, or when writing data from the other integrated circuit When a write permission signal for permitting data writing to the buffer memory is input, a plurality of handshake circuits that output a buffer memory data transfer request signal for requesting the data transfer, and data from the other integrated circuit Is read based on a write clock signal for writing data, and when data is written from the other integrated circuit, the buffer memory receives the transfer start signal for starting data transfer. When a read clock signal for outputting a write enable signal and reading data is input, counting is performed based on the read clock signal. And DMA counter, when reading data from the other integrated circuit, saidRequest to read data from the other integrated circuitWhen the read transfer clock signal is input, the counter counts. When writing data from the other integrated circuit, the read clock is input.Has a read pointer for countingWhen the data is read from the read control circuit that outputs a read request signal for requesting data read to the handshake circuit corresponding to the value of the read pointer and the other integrated circuit, the write clock is When input, it counts and when writing data from the other integrated circuit, theRequest writing data from the other integrated circuitWhen the write transfer clock signal is inputHas write pointer for countingWhen reading data from the other integrated circuit, a write control circuit that outputs a write request signal for requesting writing of the data to the buffer memory and handshake circuit according to the value of the write pointer When writing data from the other integrated circuit based on the buffer memory data transfer request signal and the value of the read pointer, the data of the data is written to the other integrated circuit based on the value of the write pointer. Outputs a transfer request signal requesting transferTransfer request signal generation circuit and,Is included.
[0028]
  A DMA transfer control device according to the present invention is the DMA transfer control device according to any one of claims 1 to 3, whereineachThe buffer memoryProvided in parallel with the buffer memoryThe memory size corresponds to the processing time of the handshake circuit.
[0029]
  Also, a DMA transfer control device according to the present invention is as follows.2Or claims3In the DMA transfer control device described in the above,The DMA counter has a data transfer amount set in advance. When writing data from another integrated circuit, the DMA counter has a number corresponding to the data transfer amount among the plurality of handshake circuits.Start the handshake circuit at the same timeRumoIt is.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
The DMA transfer control device according to the first embodiment describes a read operation for reading data from the first integrated circuit to the second integrated circuit.
FIG. 1 is a circuit configuration diagram of a DMA transfer control apparatus for Read operation according to Embodiment 1 of the present invention.
In FIG. 1, a first integrated circuit 100 includes a logic circuit 101, a DMA counter 121, a write control circuit 107, a read control circuit 108, a read selection circuit 124, a DMARQ generation circuit 115, and eight data buffers. 103a to 103h and eight handshake circuits 106a to 106h.
[0031]
  Hereinafter, each circuit will be described in detail.
  The logic circuit 101 manages 8-bit data, inputs a transfer HOLD signal (Full) 118 for stopping data transfer, and outputs a write signal (WE) 109 for writing data as a write control circuit 107 and a DMA counter. It outputs to 121. The DMA counter 121 has a counter for setting the data transfer amount, inputs the write signal 109, and outputs a transfer completion signal 122 to the logic circuit 101 when the data transfer is completed. The write control circuit 107 has a write pointer. When the write signal 109 is input from the logic circuit 101, the value of the write pointer is added, and the write pointer 109 is added according to the value of the write pointer.Write request signalOne of 110a to 110h is selected and output to one of the data buffers 103a to 103h and the handshake circuits 106a to 106h. When the read control circuit 108 has a read pointer and receives a transfer clock signal (NIORD) 119 for reading data from the second integrated circuit 105, it adds the value of the read pointer and generates a read pointer signal 116 by DMARQ. The signal is output to the circuit 115, and any one of the read signals 120a to 120h is selected according to the value of the read pointer and is output to any one of the handshake circuits 106a to 106h. For example, when the read pointer changes from 0 to 1, a read signal 120a is output, and when the read pointer changes from 1 to 2, a read signal 120b is output. Similarly, the read signal is read according to the change of the read pointer. Signals 120c to 120g are output, and when the read pointer changes from 7 to 0, a read signal 120h is output. The read selection circuit 124 is selected by the write control circuit 107.Write request signalThe 8-bit data input to any of the data buffers 103a to 103h is output to the second integrated circuit 105 through the data line 104 by 110a to 110h. The DMARQ generation circuit 115 is responsive to the read pointer signal 116 output from the read control circuit 108.Buffer transfer request signal114a to 114h is selected and a transfer request signal (DMARQ) 117 for requesting data transfer is transmitted to the second integrated circuit 105, andBuffer transfer request signalIf all of 114a to 114h are input, the transfer HOLD signal 118 is output to the logic circuit 101 in order to stop data writing to the data buffers 103a to 103h. The eight data buffers 103a to 103h are controlled by the eight handshake circuits 106a to 106h, the write control circuit 107, and the read control circuit 108, and are selected by the write control circuit 107.Write request signal110a to 110h are input to the W terminal,Write request signalThe data buffer 103 to which 110 is input receives the data line 102 of 8-bit data from the logic circuit 101, and outputs the input 8-bit data from the Q terminal of the data buffer 103 to the read selection circuit 124. . The eight handshake circuits 106a to 106h are output from the write control circuit 107.Write request signal110a to 110h or any one of read signals 120a to 120h output from the read control circuit 108 is input, and data transfer is requested according to the input signal.Buffer transfer request signal114 a to 114 h are output to the DMARQ generation circuit 115. Specifically, it is connected to the W input terminal of the handshake circuits 106a to 106h.Write request signalIf 110a to 110h are input, the signal is changed to “H” from the F output terminal.Buffer transfer request signal114a to 114h are output. On the other hand, if the read signals 120a to 120h are input to the R input terminals of the handshake circuits 106a to 106h, the signals are changed to "L" from the F output terminal.Buffer transfer request signal114a to 114h are output.
[0032]
  Next, the timing of the Read operation of the DMA transfer control device described above will be described.
  FIG. 2 is a diagram for explaining the timing of the Read operation of the DMA transfer control device according to the first embodiment of the present invention.
  At time t101, when the logic circuit 101 changes the write signal 109 to “H”, the write control circuit 107 inputs the write signal 109 from the logic circuit 101,Write request signal110a is output to the data buffer 103a. At this time, the value of the write pointer of the write control circuit 107 is added. The data buffer 103aWrite request signal110a is input to the W terminal, and the data line 102 is input from the D terminal to write data. Then, the written data is output from the Q terminal of the data buffer 103 a to the data line 123 a and transmitted to the second integrated circuit 105 from the data line 104 through the read selection circuit 124. Also,Write request signal110a is input to the W terminal of the data buffer 103a and also input to the W input terminal of the handshake circuit 106a. At time t102, the handshake circuit 106a is connected to the F output terminal.Buffer transfer request signal114a is changed to “H”. At the same time, the DMARQ generation circuit 115 starts from the handshake circuit 106a.Buffer transfer request signal114a is input and DMARQ 117 is asserted. The DMA counter 121 receives the write signal 109 from the logic circuit 101 and updates the counter value.
[0033]
  Similarly, at time t103, when the logic circuit 101 changes the write signal 109 to “H”, the write control circuit 107 inputs the write signal 109 from the logic circuit 101 and adds one to the value of the write pointer. do it,Write request signal110b is output. The data buffer 103bWrite request signal110b is input to the W terminal and the data line 102 is input to the D terminal to write data. The written data is output from the Q terminal of the data buffer 103 b to the data line 123 b and transmitted from the data line 104 to the second integrated circuit 105 via the read selection circuit 124. Also,Write request signal110b is input to the W terminal of the data buffer 103b and input to the W input terminal of the handshake circuit 106b. At time t104, the handshake circuit 106b is connected to the F output terminal.Buffer transfer request signal114b is changed to “H”.
[0034]
  Here, if NIORD 119 is not transmitted from the second integrated circuit 105 to the read control circuit 108, the handshake circuits 106a to 106h receive the F output terminal at the input of the write signal 109.Buffer transfer request signal114a to 114h are sequentially changed to “H”. At time t105,Buffer transfer request signal114a to 114h are all changed to “H”. At the same time, the DMARQ generation circuit 115Buffer transfer request signalSince all of 114a to 114h are input, the transfer HOLD signal 118 is changed to “H” in order to stop the data transfer. Then, the logic circuit 101 recognizes that the transfer HOLD signal 118 has changed to “H”, changes the write signal 109 to “L”, and stops the data transfer.
[0035]
  Since the read pointer of the read control circuit 108 is “0” in the initial state, the read pointer signal 116 is always generated in the DMARQ generation circuit 115 unless NIORD 119 is received by the read control circuit 108.Buffer transfer request signalA signal for selecting 114a is output. That is, at time t101 to t106, the DMARQ generation circuit 115 always operates.Buffer transfer request signal114 a is selected and DMARQ 117 is transmitted to the second integrated circuit 105.
[0036]
  When NIORD 119 changes to “L” at time t106, read control circuit 108 changes the read pointer from “0” to “1”, andBuffer transfer request signalRead pointer signal 116 for selecting 114b is output to DMARQ generation circuit 115. Then, the DMARQ generation circuit 115 inputs the read pointer signal 116, therebyBuffer transfer request signal114 b is selected and DMARQ 117 is transmitted to the second integrated circuit 105. Also at this timeBuffer transfer request signalSince 114b holds the signal “H”, the DMARQ 117 also holds the signal “H”. The value of the read pointer changes in synchronization with the change of NIORD to “L”, and the read control circuit 108 selects the read signals 120a to 120h according to the value of the read pointer, and the handshake circuit 106a. To ~ 106h.
[0037]
  The read control circuit 108 detects that the read pointer has changed from “0” to “1”, and outputs a read signal 120a at time t107. At time t108, the handshake circuit 106a inputs the read signal 120a from the read control circuit 108 to the R input terminal, and the F output terminalBuffer transfer request signal114a is changed to “L”. The DMARQ generation circuit 115 is supplied from the handshake circuit 106a.Buffer transfer request signal114a is input, and the transfer HOLD signal 118 is changed to "L" in order to resume the data transfer. Then, the logic circuit 101 receives the transfer HOLD signal 118, changes the write signal 109 to “H” at time t110, and restarts the data transfer. Thereafter, sequential data transfer is performed.
[0038]
  When the counter value of the DMA counter 121 becomes “0” at time t111, the DMA counter 121 changes the transfer completion signal 122 to “H”. The logic circuit 101 receives the transfer completion signal 122 from the DMA counter 121 and changes the write signal 109 to “L”. Therefore, since the write control circuit 107 does not output the write signal 109 from the logic circuit 101, the handshake circuits 106a to 106h are connected to the W input terminal.Write request signal110a to 110h cannot be input. That is, each time NIORD 119 changes to “L”, handshake circuits 106a to 106h sequentially input read signals 120a to 120h from the R input terminal, and F output terminalBuffer transfer request signal114a to 114h are sequentially changed to “L”.
[0039]
  At time t112, when the read pointer indicates “0” and NIORD 119 changes to “L”, the DMARQ generation circuit 115 originally has an input of the read pointer signal 116.Buffer transfer request signal114a is selected and DMARQ 117 is output. However, at time t112Buffer transfer request signalSince 114a is “L”, the DMARQ generation circuit 115 negates the DMARQ 117 and notifies the completion of the data transfer. Subsequently, the second integrated circuit 105 recognizes the completion of the data transfer, changes the NIORD 119 to “H”, and completes the data transfer.
[0040]
As described above, according to the DMA transfer control apparatus according to the first embodiment, DMARQ 117 is asserted in synchronization with the counter of DMA counter 121, but negation of DMARQ 117 is performed when NIORD 119 changes to “L”. Therefore, data can be transferred without being influenced by the cycle of the internal clock.
[0041]
Further, since the plurality of buffer memories 103a to 103h and the plurality of handshake circuits 106a to 106h corresponding to the capacity of the buffer memories 103a to 103h are provided in parallel in the integrated circuit, the handshake circuits 106a to 106h The clock frequency difference in the integrated circuit can be absorbed, and continuous transfer of data can be realized.
[0042]
That is, data transfer by the handshake method can be performed at high speed and efficiently without reducing the cycle of the internal clock by the burst transfer method.
[0043]
Embodiment 2. FIG.
The DMA transfer control device according to the second embodiment describes a write operation for writing data from the second integrated circuit to the first integrated circuit.
FIG. 3 is a circuit configuration diagram of a DMA transfer control device for write operation according to the second embodiment of the present invention.
[0044]
In FIG. 3, the first integrated circuit 202 includes a logic circuit 205, a DMA counter 209, a read control circuit 208, a write control circuit 207, a DMARQ generation circuit 212, eight data buffers 203a to 203h, 8 Handshake circuits 206a to 206h.
[0045]
  Hereinafter, each circuit will be described in detail.
  The logic circuit 205 manages 8-bit data, inputs a read request signal (Rdy) 219 for requesting reading of data, and supplies a read signal (RE) 220 for reading data to the read control circuit 208 and the DMA counter 209. Then, a transfer start signal 217 informing the start of data transfer is output to the DMA counter 209 and the write control circuit 207. The DMA counter 209 has a counter for setting the data transfer amount. The DMA counter 209 receives the read signal 220 and the transfer start signal 217, and writes a write permission signal (Flag) 210a according to the set data transfer amount. Any one of -210h is output. For example, if the data transfer amount set in the DMA counter 209 is 8 words, all of the write permission signals 210a to 210h are output, but if the data transfer amount is 1 word, only the write permission signal 210a is output. Is output. The read control circuit 208 has a read pointer. When the read signal 220 is input from the logic circuit 205, the read control circuit 208 outputs any of the read signals 221a to 221h to the handshake circuits 206a to 206h according to the read pointer. 8-bit data is selected from the data lines 222a to 222h from the data buffers 203a to 203h, and the selected 8-bit data is output to the logic circuit 205 through the data line 204 to add a read pointer. When the write control circuit 207 has a write pointer and receives the transfer clock signal (NIOWR) 215 for writing data from the second integrated circuit 200, the write pointer signal is added to the write pointer signal. 213 is output to the DMARQ generation circuit 212, and write signals 216a to 216h are output to any of the data buffers 203a to 203h and the handshake circuits 206a to 206h according to the value of the write pointer. In response to the write pointer signal 213 output from the write control circuit 207, the DMARQ generation circuit 212Buffer transfer request signalOne of 211a to 211h is selected, and a transfer request signal (DMARQ) 214 for requesting data transfer to the second integrated circuit 200 is output. The eight data buffers 203a to 203h are controlled by the eight handshake circuits 206a to 206h, the write control circuit 207, the read control circuit 208, and the DMA counter 209, and are selected by the write control circuit 207. The write signals 216a to 216h are input to the W terminal, and the data buffer 203 to which the selected write signal 216 is input receives 8-bit data from the second integrated circuit 200 through the data line 201, and the read control circuit The data line 222 is output to 208. The eight handshake circuits 206 a to 206 h receive the write permission signal 210 output from the DMA counter 209 according to the read signal 221 selected by the read control circuit 208, and enter the DMARQ generation circuit 212.Buffer transfer request signal211, and any one of the write signals 216a to 216h output from the write control circuit 207 is input, and any one of the data full signals 218a to 218h is output to the read control circuit 208.
[0046]
Next, the timing of the write operation of the DMA transfer control device described above will be described assuming that the data transfer amount set by the DMA counter 209 is n word> 8 words.
[0047]
  FIG. 4 is a diagram for explaining the timing of the write operation of the DMA transfer control device according to the second embodiment of the present invention.
  At time t200, when the logic circuit 205 changes the transfer start signal 217 to “H”, the write control circuit 207 inputs the transfer start signal 217 from the logic circuit 205, resets the write pointer, and writes the write pointer. A write pointer signal 213 indicating “0” is output to the DMARQ generation circuit 212. At time t201, the DMA counter 209 changes the write permission signals 210a to 210h to “H”, and the handshake circuits 206a to 206h receive the write permission signals 210a to 210h from the DMA counter 209. At time t202, the handshake circuits 206a to 206hBuffer transfer request signal211a to 211h are changed to “H”, and the DMARQ generation circuit 212 is changed from the handshake circuits 206a to 206h.Buffer transfer request signalInput 211a to 211h.
[0048]
  The DMARQ generation circuit 212 responds to the input of the write pointer signal 213.Buffer transfer request signalOne of 211a to 211h is selected, and DMARQ 214 is output to the second integrated circuit 200. In this case, since the write pointer indicates “0” at time t202, the DMARQ generation circuit 212Buffer transfer request signal211a is selected and input, and DMARQ 214 is asserted.
[0049]
  The second integrated circuit 200 receives the DMARQ 214 from the DMARQ generation circuit 212, changes the NIOWR 215 to “L” at time t203, and transmits the data line 201 of 8-bit data to the data buffers 203a to 203h. At the same time, since the write pointer of the write control circuit 207 indicates “1”, the write control circuit 207 selects the write signal 216a and outputs it to the data buffer 203a and the handshake circuit 206a. The buffer 203a inputs the data line 201 transmitted from the second integrated circuit 200 and writes data. At time t204, the handshake circuit 206aBuffer transfer request signal211a is changed to “L”, and the Data Full signal 218a is changed to “H”.
[0050]
  Similarly, at time t205, the second integrated circuit 200 changes NIOWR 215 to “L” and transmits the data line 201 of 8-bit data to the data buffers 203a to 203h. At the same time, since the write pointer of the write control circuit 207 indicates “2”, the write control circuit 207 selects the write signal 216b and outputs it to the data buffer 203b and the handshake circuit 206b. The buffer 203b inputs the data line 201 transmitted from the second integrated circuit 200 and writes data. At time t206, the handshake circuit 206bBuffer transfer request signal211b is changed to “L”, and the Data Full signal 218b is changed to “H”.
[0051]
  Subsequently, after the above-described operation, every time the NIOWR 215 of the second integrated circuit 200 changes to “L”, 8-bit data is sequentially written from the second integrated circuit 200 to the data buffers 203c to 203h through the data line 201. At the same time, since the write pointer of the write control circuit 207 is sequentially added, the write control circuit 207 sends the write signals 216c to 216h to the data buffers 203c to 203h according to the value of the write pointer. And output to the handshake circuits 206c to 206h. The handshake circuits 206c to 206h are sequentiallyBuffer transfer request signal211c to 211h are changed to “L”, and Data Full signals 218c to 218h are changed to “H”.
[0052]
  At time t207, when the write pointer indicates “0”, the DMARQ generation circuit 212,Buffer transfer request signal211a is selected and DMARQ 214 is output to the second integrated circuit 200. At this time,Buffer transfer request signalSince 211a is changed to “L”, the DMARQ generation circuit 212 negates the DMARQ 214.
[0053]
The read control circuit 208 calculates the logical sum of the Data Full signals 218 a to 218 h output from the handshake circuits 206 a to 206 h and outputs a read request signal 219 to the logic circuit 205. However, if the read signal 220 is not output from the logic circuit 205 by the time t207, the DMA counter 209 cannot output the write permission signals 210a to 210h. At this time, the second integrated circuit 200 transfers the data. Pause.
[0054]
  When logic circuit 205 changes read signal 220 to “H” at time t208, DMA counter 209 inputs read signal 220 from logic circuit 205, updates the value of the counter, and writes data at time t209. The permission signal 210a is changed to “H”. At time t210, the handshake circuit 206aBuffer transfer request signal211a is changed to “H”. At this time, since the write pointer of the write control circuit 207 indicates “0”, the DMARQ generation circuit 212Buffer transfer request signal211a is selected and input, and DMARQ 214 is asserted.
[0055]
On the other hand, when read signal 220 is output from logic circuit 205 at time t208, read pointer indicates “0” at this time, so read control circuit 208 selects and outputs read signal 221a. The Data Full signal 218a of the handshake circuit 206a is changed to “L”. Further, the read control circuit 208 selects and inputs the data line 222 a from the data buffer 203 a and outputs the data line 204 to the logic circuit 205.
[0056]
  When the counter value of the DMA counter 209 becomes 7 words or less at time t211, the DMA counter 209 does not output the write permission signals 210a to 210h thereafter. That is, the handshake circuits 206a to 206h sequentially input the write signals 216a to 216h after time t211,Buffer transfer request signal211a to 211h are changed to “L”.
[0057]
  At time t212, the second integrated circuit 200 changes the NIOWR 215 to “L”, so that the write pointer of the write control circuit 207 indicates “0”. Since the DMARQ generation circuit 212 is originally a write pointer is “0”.Buffer transfer request signal211a is selected and DMARQ 214 is output to the second integrated circuit 200. At this time,Buffer transfer request signalSince 211a is changed to “L”, the DMARQ 214 negates and notifies the completion of data transfer. Then, at time t213, the second integrated circuit 200 recognizes the completion of the data transfer, changes the NIOWR 215 to “H”, and completes the data transfer.
[0058]
At this time, since the data buffers 203a to 203h have not finished reading data, the read control circuit 208 holds the read request signal 219 in the “H” state. The logic circuit 205 outputs a read signal 220 to read data from the data buffers 203a to 203h.
[0059]
Subsequently, although not shown, when the data reading of the data buffers 203a to 203h is completed, the Data Full signals 218a to 218h of the handshake circuits 206a to 206h are all changed to “L”. Then, the read control circuit 208 changes the read request signal 219 to “L”, and the logic circuit 205 completes the read operation.
[0060]
As described above, according to the DMA transfer control device according to the second embodiment, DMARQ 214 is asserted in synchronization with the counter of DMA counter 209, but negation of DMARQ 214 is performed when NIOWR 215 changes to “L”. Therefore, data can be transferred without being influenced by the cycle of the internal clock.
[0061]
In addition, since a plurality of buffer memories and a plurality of handshake circuits corresponding to the capacity of the buffer memory are provided in parallel in the integrated circuit, the handshake circuit absorbs the difference in clock frequency in the integrated circuit. And continuous transfer of data can be realized.
[0062]
That is, data transfer by the handshake method can be performed at high speed and efficiently without reducing the cycle of the internal clock by the burst transfer method.
[0063]
【The invention's effect】
  As described above, according to the DMA transfer control device of the first aspect of the present invention, a DMA transfer control device that controls direct memory access (DMA) transfer between integrated circuits, An integrated circuit for transmitting data includes a plurality of buffer memories for storing the DMA transfer data, and,UpIn parallel with each of the multiple buffer memoriesA plurality of handshake circuits for outputting a buffer memory data transfer request signal for requesting transfer of the data when a write request signal for requesting writing of data stored in each buffer memory is input; A DMA counter that counts based on a write clock signal for writing, and a write pointer that counts when the write clock signal is input, and the buffer memory according to the value of the write pointer, A write control circuit for outputting the write request signal to the handshake circuit;Requests reading of data from the integrated circuit receiving the data of the DMA transfer control device.When the read transfer clock signal is inputHas a read pointer for countingBased on the read control circuit for outputting a read request signal for requesting data reading to the handshake circuit according to the value of the read pointer, the buffer memory data transfer request signal, and the value of the read pointer, A transfer request signal for requesting data transfer is output to the integrated circuit that receives the data of the DMA transfer control device.Transfer request signal generation circuit and,Therefore, data transfer by the handshake method can be performed at high speed and efficiently without shortening the period of the internal clock by the burst transfer method.
[0064]
  According to a second aspect of the present invention, there is provided a DMA transfer control apparatus that controls direct memory access (DMA) transfer between integrated circuits, and receives data from the DMA transfer control apparatus. An integrated circuit comprising a plurality of buffer memories for storing the DMA transfer data;,UpIn parallel with each of the multiple buffer memoriesA plurality of handshake circuits for outputting a buffer memory data transfer request signal for requesting the transfer of data and a data transfer when a write permission signal for permitting data writing is input to the buffer memory A DMA counter that receives the transfer start signal, outputs the write enable signal to the buffer memory, and inputs a read clock signal for reading data; and a count based on the read clock signal;Requests data writing from an integrated circuit that transmits data of the DMA transfer control device.When the write transfer clock signal is inputHas write pointer for countingA write control circuit for outputting a write request signal for requesting writing of data to the buffer memory and the handshake circuit according to a signal output from the write pointer; and the read clock signal. A read control circuit that has a read pointer for counting and outputs a read request signal for requesting reading of the data to the handshake circuit according to a signal output from the read pointer; and the buffer memory data transfer request Based on the signal and the signal output from the write pointer, a transfer request signal for requesting data transfer is output to the integrated circuit that transmits the data of the DMA transfer control device.Transfer request signal generation circuit and,Therefore, data transfer by the handshake method can be performed at high speed and efficiently without shortening the period of the internal clock by the burst transfer method.
[0065]
  According to a third aspect of the present invention, there is provided a DMA transfer control device for controlling direct memory access (DMA) transfer between integrated circuits, wherein the DMA transfer control device transmits and receives data. An integrated circuit comprising a plurality of buffer memories for storing the DMA transfer data;,UpIn parallel with each of the multiple buffer memoriesProvided, when reading data from the other integrated circuit, when a write request signal for requesting writing of data stored in each buffer memory is input, or when writing data from the other integrated circuit When a write permission signal for permitting data writing to the buffer memory is input, a plurality of handshake circuits that output a buffer memory data transfer request signal for requesting the data transfer, and data from the other integrated circuit Is read based on a write clock signal for writing data, and when data is written from the other integrated circuit, the buffer memory receives the transfer start signal for starting data transfer. When a read clock signal for outputting a write enable signal and reading data is input, counting is performed based on the read clock signal. And DMA counter, when reading data from the other integrated circuit, saidRequest to read data from the other integrated circuitWhen the read transfer clock signal is input, the counter counts. When writing data from the other integrated circuit, the read clock is input.Has a read pointer for countingWhen the data is read from the read control circuit that outputs a read request signal for requesting data read to the handshake circuit corresponding to the value of the read pointer and the other integrated circuit, the write clock is When input, it counts and when writing data from the other integrated circuit, theRequest writing data from the other integrated circuitWhen the write transfer clock signal is inputHas write pointer for countingWhen reading data from the other integrated circuit, a write control circuit that outputs a write request signal for requesting writing of the data to the buffer memory and handshake circuit according to the value of the write pointer When writing data from the other integrated circuit based on the buffer memory data transfer request signal and the value of the read pointer, the data of the data is written to the other integrated circuit based on the value of the write pointer. Outputs a transfer request signal requesting transferTransfer request signal generation circuit and,Therefore, data transfer by the handshake method can be performed at high speed and efficiently without shortening the period of the internal clock by the burst transfer method.
[0066]
  According to a DMA transfer control apparatus of a fourth aspect of the present invention, in the DMA transfer control apparatus of any one of the first to third aspects,eachBuffer memory isProvided in parallel with the buffer memorySince it has a memory size corresponding to the processing time of the handshake circuit, the handshake circuit can absorb the difference in clock frequency of the processing circuit in the integrated circuit and realize continuous transfer of data. Can do.
[0067]
  Further, according to the DMA transfer control device of claim 5 of the present invention,2Or claims3In the DMA transfer control device described in the above,The DMA counter has a data transfer amount set in advance. When writing data from another integrated circuit, the DMA counter has a number corresponding to the data transfer amount among the plurality of handshake circuits.Start the handshake circuit at the same timeRumoThus, a plurality of handshake circuits can be controlled simultaneously.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a DMA transfer control device for Read operation according to Embodiment 1 of the present invention;
FIG. 2 is a diagram for explaining the timing of a Read operation according to Embodiment 1 of the present invention;
FIG. 3 is a circuit configuration diagram of a DMA transfer control device for write operation according to the second embodiment of the present invention;
FIG. 4 is a diagram for explaining the timing of a write operation according to the second embodiment of the present invention.
FIG. 5 is a diagram showing a configuration example of an interface using a conventional DMA transfer control device;
FIG. 6 is a diagram for explaining the timing of a Read operation taking 3Word data transfer as an example;
FIG. 7 is a diagram for explaining the timing of a write operation taking 3word data transfer as an example;
FIG. 8 is a circuit configuration diagram of a DMA interface adopting a burst transfer method.
FIG. 9 is a diagram for explaining the timing of Read operation and Write operation of a burst transfer type DMA interface;
FIG. 10 is a circuit configuration diagram of a DMA interface adopting a handshake method.
FIG. 11 is a diagram for explaining the timing of the Read operation and Write operation of the handshake DMA interface
[Explanation of symbols]
  1 First equipment
  2 Second equipment
  3 External bus
  4 First integrated circuit
  5 Second integrated circuit
  6 Transfer request signal (DMARQ)
  7 Transfer clock signal (NIORD)
  8 Transfer clock signal (NIOWR)
  9 Data line (Data)
  10 First integrated device
  11 Second integrated device
  20 logic circuits
  22 DMA counter
  23 clock
  24 Transfer clock signal (NIORD)
  25 Transfer clock signal (NIOWR)
  26 Data Line (Data)
  27 Transfer request signal (DMARQ)
  28 Transfer start signal
  29 Transfer HOLD signal
  30 First integrated circuit
  31 Second integrated circuit
  40 logic circuits
  41 DMARQ generation circuit 41
  42 DMA counter
  43 clocks
  44 Transfer clock signal (NIORD)
  45 Transfer clock signal (NIOWR)
  46 Transfer start signal
  47 Counter update signal
  48 Transfer request signal (DMARQ)
  49 Clock detection signal
  50 Transfer HOLD signal
  51 Data line (Data)
  100 First integrated circuit
  101 logic circuit
  102, 104, 123 data lines
  103 Data buffer
  105 Second integrated circuit
  106 Handshake circuit
  107 Write control circuit
  108 Read control circuit
  109 Write signal
  110Write request signal
  114, 211  Buffer transfer request signal
  115 DMARQ generation circuit
  116 Read pointer signal
  117 Transfer request signal (DMARQ)
  118 Transfer HOLD signal
  119 Transfer clock (NIORD)
  120 Read signal
  121 DMA counter
  122 Transfer complete signal
  124 Read selection circuit
  200 Second integrated circuit
  201, 204, 222 Data lines
  202 1st integrated circuit
  203 Data buffer
  205 logic circuit
  206 Handshake circuit
  207 Write control circuit
  208 Read control circuit
  209 DMA counter
  210 Write enable signal
  212 DMARQ Generator Circuit
  213 Write pointer signal
  214 Transfer request signal (DMARQ)
  215 Transfer clock (NIOWR)
  216 Write signal
  217 Transfer start signal
  218 Data Full signal
  219 Read request signal
  220, 221 Read signal

Claims (5)

A DMA transfer controller for controlling direct memory access (DMA) transfer between integrated circuits,
An integrated circuit for transmitting data of the DMA transfer control device is:
A plurality of buffer memories for storing the DMA transfer data ;
Provided in parallel with the upper Symbol plurality of buffer memories each and write request signal requesting writing of data stored in the respective buffer memory is inputted, the buffer memory data transfer request signal to request the transfer of the data A plurality of handshake circuits that output
A DMA counter that counts based on a write clock signal for writing data;
A write control circuit having a write pointer for counting when the write clock signal is input, and outputting the write request signal to the buffer memory and handshake circuit corresponding to the value of the write pointer When,
From the integrated circuit to receive data of the DMA transfer controller, when the read transfer clock signal requesting reading of data is input to have a read pointer that counts, the handshake circuit in accordance with the value of said read out pointer A read control circuit for outputting a read request signal for requesting reading of data to
A transfer request signal generating circuit for outputting a transfer request signal for requesting data transfer to an integrated circuit receiving data of the DMA transfer control device based on the value of the buffer memory data transfer request signal and the value of the read pointer ; ,
A DMA transfer control device comprising: A DMA transfer controller for controlling direct memory access (DMA) transfer between integrated circuits,
An integrated circuit that receives the data of the DMA transfer control device comprises:
A plurality of buffer memories for storing the DMA transfer data ;
Provided in parallel with the upper Symbol plurality of buffer memories each, when write enable signal for permitting writing of data in the buffer memory is inputted, a plurality of output buffer memory data transfer request signal to request the transfer of the data Handshake circuit
In response to a transfer start signal for starting data transfer, the write enable signal is output to the buffer memory, and when a read clock signal for reading data is input, a DMA counter that counts based on the read clock signal; ,
From the integrated circuit to transmit the data of the DMA transfer controller, when the write transfer clock signal requesting writing of data is input to have a write pointer that counts, the signal output from the該書write pointer A write control circuit for outputting a write request signal for requesting writing of data to the corresponding buffer memory and handshake circuit ;
Read control having a read pointer for counting when the read clock signal is input, and outputting a read request signal for requesting reading of the data to the handshake circuit according to the signal output from the read pointer Circuit,
Based on the buffer memory data transfer request signal and the signal output from the write pointer, a transfer request for outputting a transfer request signal for requesting data transfer to the integrated circuit for transmitting data of the DMA transfer control device A signal generation circuit;
A DMA transfer control device comprising: A DMA transfer controller for controlling direct memory access (DMA) transfer between integrated circuits,
An integrated circuit for transmitting and receiving data of the DMA transfer control device is:
A plurality of buffer memories for storing the DMA transfer data ;
Provided in parallel with the upper Symbol plurality of buffer memories each, when reading the data from the other of the integrated circuit, when the write request signal requesting writing of data stored in the respective buffer memory is inputted, or When writing data from the other integrated circuit, when a write permission signal for permitting data writing is input to the buffer memory, a plurality of buffer memory data transfer request signals for requesting the data transfer are output. A handshake circuit;
When reading data from the other integrated circuit, it counts based on a write clock signal for writing data, and when writing data from the other integrated circuit, it receives a transfer start signal for starting data transfer. A DMA counter that outputs the write enable signal to the buffer memory and receives a read clock signal for reading data, and performs counting based on the read clock signal;
When reading data from the other integrated circuit, when the read transfer clock signal requesting reading of data from the other of the integrated circuit is inputted performs counting, when writing data from the other integrated circuit, the reading When the clock is input to have a read pointer that counts, in the handshake circuit in accordance with the value of said read out pointer, a read control circuit for outputting a read request signal requesting reading of data,
When reading data from the other integrated circuit performs counting when the write clock is input, when writing data from the other integrated circuit, for requesting writing of data from the other integrated circuits book When write transfer clock signal is input to have a write pointer that counts, in the buffer memory and the handshake circuits corresponding to the value of該書write pointer, outputs a write request signal for requesting writing of the data A write control circuit for
When reading data from the other integrated circuit, it is based on the buffer memory data transfer request signal and the value of the read pointer. When writing data from the other integrated circuit, it is based on the value of the write pointer. A transfer request signal generating circuit for outputting a transfer request signal for requesting data transfer to the other integrated circuit ;
A DMA transfer control device comprising: The DMA transfer control device according to any one of claims 1 to 3,
Each of the buffer memories has a memory size corresponding to the processing time of the handshake circuit provided in parallel with the buffer memory .
A DMA transfer control device. In the DMA transfer control device according to claim 2 or 3 ,
The DMA counter has a data transfer amount set in advance, and when data is written from another integrated circuit, among the plurality of handshake circuits, a number of handshake circuits corresponding to the data transfer amount are simultaneously provided. To start ,
A DMA transfer control device.

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