JP3660097B2 - Logic circuit type verification apparatus and verification method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a sequential circuit type verification method and apparatus using a finite state machine.
[0002]
[Prior art]
With the increase in the scale of logic circuits such as circuits that make up computers in recent years, technologies for shortening circuit design and test periods, that is, logic synthesis technology, simulation technology, formal verification technology, etc., have become increasingly important year by year. It is coming. In these technologies, when a sequential circuit is handled, the sequential circuit is usually mathematically modeled using a finite state machine, and processing such as reduction of the number of states and determination of equivalence is performed on the finite state machine. Is called. In recent years, with the development of a compact technique for expressing transition functions and output functions that are elements of a finite state machine using a binary decision diagram, the above processing can be applied to larger finite state machines. It became.
[0003]
Among the above techniques, the formal verification technique is divided into an equivalence determination technique and a model checking technique. The former is a technique for determining the logical equivalence of two circuits, and the latter is a technique for determining whether a target circuit satisfies a logical property specified by a user.
[0004]
In these formal verification techniques for logic circuits, particularly sequential circuits, in order to construct a finite state machine that models this from a circuit description that describes a given circuit, usually, as shown in FIG. Processing is performed. First, a finite state machine M having an input alphabet as a combination of arbitrary values of all input signals included in given circuit descriptions A and B.₀A, M₀B is made (step 31). Of the inputs to this circuit, the input corresponding to the clock signal is detected automatically or using information by the user. Furthermore, information regarding timing such as what value the clock signal takes when the values of the input signal and output signal other than the clock signal change is obtained from the user (step 32). And based on this, the finite state machine M₀A, M₀From B, a finite state machine (synchronous machine M) having a combination of arbitrary values of input signals other than clock signals as an input alphabet.₁A, M₁B) is configured (step 33). The state transition in the synchronous machine is considered to occur at a given timing by a clock that the synchronous machine itself has. In the sequential circuit equivalence verification technique, two synchronous machines M made in this way from two sequential circuits are used.₁A, M₁By verifying the logical equivalence between B, the equivalence between the original sequential circuits is verified (step 34), and the result is output (step 35).
[0005]
[Problems to be solved by the invention]
However, the equivalence determination technique described above, that is, the technique of constructing each synchronous machine from the circuit descriptions of two sequential circuits whose equivalence is to be determined and determining their logical equivalence, has the following problems. There is a point.
[0006]
In recent years, it has become more important to make a circuit with less power consumption than a normal synchronous circuit, so it is possible to realize a circuit using a gated clock, etc. It has become necessary to realize a combination of transistors without using logic elements such as flip-flops and latches. In such a case, whether or not the state transition of the designed circuit and the change of the value of the input / output signal occur correctly according to the timing of the change of the clock signal and other signals expected by the user is not necessarily guaranteed. .
[0007]
For this reason, if equivalence between circuits is created by creating a synchronous machine from the circuit description, state transitions and input / output signal values may be erroneously entered in the circuit description at timings not intended by the designer. Even if a change occurs, it may not be detected.
[0008]
For example, FIGS. 10A and 10B show circuits that implement a master-slave JK flip-flop and an edge-triggered JK flip-flop using NAND gates, for example. In these two circuits, the values of the other input signals j and k change only while the value of the clock signal clk is 0, and the state transition is at the falling edge of the clock signal, that is, clk = 1 to clk = Assuming that it occurs only at the moment when it becomes zero, it shows a completely equivalent input / output relationship. However, if the value of the input signal may change while the value of the clock signal is 1, these circuits may behave differently.
[0009]
FIG. 11 describes the operation of the JK-flip flop in the VHDL language. This description is based on which JK- of FIG. 10 when formal verification is performed by configuring a synchronous machine. Although it is equivalent to the flip-flop circuit, it is not actually equivalent to the circuit of (a), but is equivalent to only the circuit of (b), for the same reason as described above.
[0010]
The designer uses the edge trigger type JK-flip-flop shown in FIG. 10B in order to realize a certain circuit at the beginning of design, and this is used as the master-slave type JK shown in FIG. -Suppose you change to a flip-flop. In the conventional verification technique, in order to perform verification, the designers only know that the values of the input signals j and k change only while the value of the clock signal is 0, and the state transition occurs at the falling edge of the clock signal. Is specified. Therefore, even if the values of j and k change while the value of the clock signal is 1, the difference before and after the change cannot be detected. Therefore, the designer must verify that the values of j and k do not change while the value of the clock signal is 1, using verification by model checking or the like individually. However, there is a problem that the designer does not always make this confirmation, and the circuit before and after the change is considered to be equivalent without noticing the difference.
[0011]
[Means for Solving the Problems]
  In order to solve the above problems, the invention of claim 1 is given to a circuit description describing the logic circuit and the logic circuit in a formal verification device for formally verifying equivalence of a plurality of logic circuits. A stationary finite state machine generation unit that generates a stationary finite state machine corresponding to the logic circuit from information related to the input signal, and the stationary finite state machine generation unit generated individually from the plurality of circuit descriptions. An equivalence verification unit that verifies logical equivalence of a plurality of stationary finite state machines; and an output unit that outputs a verification result of the equivalence verification unit, wherein the stationary finite state machine generation unit includes the circuit A finite state machine that generates a finite state machine that performs a uniquely defined state transition with respect to the change timing of a predetermined input signal and other input signals among a plurality of input signals of the circuit represented by the description A generation unit, and a conversion unit to a finite state machine that converts the finite state machine generated by the finite state machine generation unit into a stationary finite state machine having no transition to a transient state. And
[0012]
  The invention of claim 5 grasps the invention of claim 1 from the viewpoint of the method, and is a formal verification method for formal verification of equivalence of a plurality of logic circuits, comprising an input / output device. Steady state finite state machine generator, equivalence verifier, finite state machine generator and steady state finite state machine converter provided in the steady state finite state machine generator And using the circuit description describing each logic circuit input from the input / output device and the information about the input signal given to each logic circuit, the finite state machine generation unit, for each logic circuit, A finite state machine that performs a uniquely defined state transition with respect to the change timing of a predetermined input signal and other input signals among a plurality of input signals of the circuit represented by the circuit description. A finite state machine generation process that generates the finite state machine corresponding to each logic circuit generated by the finite state machine generation process by the steady state finite state machine conversion unit. Generated individually by the stationary finite state machine generation unit from a plurality of circuit descriptions by the conversion process to a finite state machine that converts to a stationary finite state machine that does not have a transition to a state, and the equivalence checking unit And equivalence verification processing for verifying logical equivalence of a plurality of stationary finite state machines.
[0013]
  The structure according to claim 1 having such a configuration.Claim 5According to the invention, for the description of the two logic circuits whose equivalence is to be verified, information specifying which one of the input signals does not change at the same time as the other input signal is provided. The steady finite state machine is generated individually by the steady finite state machine generation unit. This information specifies which of the input signals is the clock signal, unlike the prior art in which the user specifies a lot of information such as the clock value when the input / output signal value changes. Only very little information is needed. The steady finite state machine created by the steady finite state machine generator performs a uniquely defined state transition for the timing of the change in the value of any input signal, and transitions to a transient state. It has the feature of not having a transition. Therefore, according to the present invention, the logical equivalence of the two stationary finite state machines generated from the descriptions of the two given logic circuits is formally verified in the equivalence verification unit, so that a plurality of input / output signals can be obtained. It is possible to perform the format verification of the sequential circuit in consideration of the timing of the value change.
[0014]
  Furthermore, according to the invention described in claim 1 or claim 5 having such a configuration, for example, verification between a normal sequential circuit and a circuit in which this is realized by using a gated clock, or a single circuit It is possible to verify equivalence between circuits that include both a transition portion at the rising edge of the clock and a transition portion at the falling edge. In particular, when verifying using a synchronous machine, if the input signal changes in the designed circuit due to an error at a clock timing not intended by the designer, or if a state transition occurs at a clock timing not intended by the designer. It may happen. When such a case is included, this error may be canceled during the construction of the synchronous machine. The present invention solves such a problem by performing equivalence verification without configuring a synchronous machine.
[0015]
  According to a second aspect of the present invention, in the first aspect of the invention, the stationary finite state machine generation unit generates a preliminary finite state machine that generates a preliminary finite state machine based on a circuit description describing the logic circuit. A finite state machine generation unit that includes a machine generation unit and generates a finite state machine that performs a uniquely defined state transition is based on the preliminary finite state machine generated by the preliminary finite state machine generation unit. Thus, a finite state machine that performs a uniquely defined state transition with respect to a change timing of a predetermined input signal and other input signals is generated. The invention of claim 6 grasps the invention of claim 2 from the viewpoint of the method.
[0016]
  According to the inventions of claim 2 and claim 6 described above, a preliminary finite state machine, uniquely, from a circuit description describing the logic circuit and information about an input signal applied to the logic circuit. By generating a finite state machine with different properties such as a finite state machine that performs a defined state transition and a steady finite state machine that does not have a transition to a transient state, the clocks of logic circuits, etc. It is easy to correctly express the relationship between the state transition and the output with respect to the change of the input signal value, including the timing with respect to the change of the clock signal value. Verification can be performed.
[0017]
According to a third aspect of the present invention, the finite state machine generation unit generates a finite state machine that performs a uniquely defined state transition with respect to a timing at which a value of a clock signal and another signal changes simultaneously. Features. According to the third aspect of the present invention, it is possible to generate a finite state machine that takes into account the relationship between the timing of the change in the values of the clock signal and other input / output signals, and more accurate verification of the logic circuit can be performed.
[0018]
According to a fourth aspect of the present invention, the output unit also outputs information found in the stationary finite state machine generation unit. According to the fourth aspect of the present invention, the output unit can output not only the verification result but also the instability of the state discovered at the time of generation of the steady finite state machine, for example. The state machine can be converted efficiently.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
An embodiment described later is realized on a computer, and each function of the embodiment is realized by a predetermined procedure (program) controlling the computer. For example, various types of input units can be adopted depending on the program to be input and the mode of data, and input / output devices such as a keyboard and a mouse, a network connection device, and a data reading device can be used. Each storage unit is for storing data input from the outside, and a desired device such as magnetism, an optical disk device, or a semiconductor memory can be used. Further, the other part is typically constituted by computer software.
[0020]
Each “unit” in this specification is a conceptual one corresponding to each function of the embodiment, and does not necessarily correspond to a specific hardware or software routine on a one-to-one basis. The same hardware element constitutes a different part depending on the case. For example, a computer can be a part when executing a certain instruction and can be a different part when executing another instruction. One part may be realized by only one instruction, or may be realized by a large number of instructions. Therefore, in the present specification, the embodiment will be described below assuming a virtual circuit block (unit) having each function of the embodiment. Further, the steps of each procedure in the present embodiment may be executed in a different order for each execution by changing the execution order and executing a plurality of steps at the same time, as long as it does not contradict its nature.
[0021]
When the present invention is realized as software of a computer, the software is recorded on a recording medium using magnetism or light, and this can be read out by an individual designer and executed by his / her computer. This is one embodiment of the present invention.
[0022]
[A. First Embodiment]
[1. Finite state machine and stationary finite state machine]
[1-1. Definition of finite state machine]
Define a finite state machine as an input for the present invention.
As shown in FIG. 4, the finite state machine M is a set of input symbols composed of a finite number of elements (hereinafter referred to as input alphabet) I, a set of output symbols composed of a finite number of elements (hereinafter referred to as output alphabet) O, finite State set Σ, transition function δ, output function ω, initial state S_init6 sets are designated. This is expressed as a finite state machine M = (I, O, Σ, δ, ω, S_init). Here, the transition function δ is a function from Σ × I to Σ, the output function ω is a function from Σ × I to O, and the initial state S_initIs one element of Σ, namely S_init∈Σ. When the input iεI is given, the transition destination of the state δεΣ by the transition function δ is denoted by δ (s, i), and the output by the output function ω is denoted by ω (s, i). In the following, δ, ω and δ (s, i), ω (s, i) are not distinguished unless particularly confusing.
[0023]
[1-2. Specific examples of finite state machines]
FIG. 5A is an example of a finite state machine, where the input alphabet is I = {0,1}, the output alphabet is O = {0,1}, and the set of states is Σ = {A, B}. A state is represented by enclosing the state name in a circle, such as 200. A set of numbers 202 and 203 attached to an arrow 201 from each state, when an input value 202 is given in the state that is the starting point of the arrow 201, transitions to a state that becomes the end point of the arrow, and an output accompanying this transition This means that the value is 203. In the example of FIG. 5A, when the input 0 is given in the state A, the transition destination state is A, and accordingly, 1 is output. When input 1 is given in state A, the transition destination state is B, and 1 is output accordingly. When the input 0 is given in the state B, the transition destination state is B, and 1 is output accordingly. When the input 1 is given in the state B, the transition destination state is A, and accordingly 0 is output. Reference numeral 204 denotes a state name surrounded by a double circle, which expresses that B is an initial state.
[0024]
The representation of the finite state machine in this specification is not limited to FIG. 5, but as shown in FIG. 12 and the like, the state name and the output value are circled as A / 0, and the input value is 0− The expression described along with the arrow indicating the transition destination is also used.
[0025]
In most sequential circuits, the internal state immediately after the power is turned on is not uniquely determined. For this reason, when the sequential circuit is modeled by a finite state machine, the initial state may not be specified. FIG. 5B shows a finite state machine in such a case, and the initial state is not clearly shown. A finite state machine that does not specify an initial state is hereinafter referred to as M = (I, O, Σ, δ, ω). In the present invention, the finite state machine in which the initial state is not specified and the finite state machine in which the initial state is specified can be handled in almost the same manner in most cases. In other words, unlike a normal finite state machine, the finite state machine targeted by the present invention does not necessarily have an initial state that is an element of Σ, so the internal state immediately after turning on the power is unique. It is also possible to handle sequential circuits that are not fixed.
[0026]
[1-3. Steady state set, stable state, unstable state, transient state, transient transition]
In a finite state machine M = (I, O, Σ, δ, ω), when a certain input iεI continues to be given, a subset S of elements Σ having the number of elements t ≧ 1 S = {s₀, S₁, ..., s_t-1} When an arbitrary state included in ⊆Σ always transits only to a state included in S and can transition to all states included in S, S is a steady state for an input i∈I of the finite state machine M. This is called a state set. In particular, a state included in the steady state set having one element is called a stable state for the input iεI of the finite state machine M. Conversely, a state included in a steady state set having two or more elements is called an unstable state with respect to an input iεI of the finite state machine M.
[0027]
In the finite state machine M = (I, O, Σ, δ, ω), states that are not included in the steady state set for the input i∈I of the finite state machine M are transitive to the input i∈I of the finite state machine M. Call the state. A transition from a transient state is called a transient transition. The relationship between these sets is as shown in FIG.
[0028]
[1-4. State stability]
FIG. 8 is an example of a finite state machine. In this finite state machine, the input alphabet is I = {0, 1}, the output alphabet is O = {0, 1}, and the set of states is Σ = {A, B, C, D, E, F, G , H}, and the initial state is not specified. For example, starting from the state E, if the input 1 continues to be applied, the state finally transitions to the state B via the transient state A, and after that, even if the input 1 continues to be applied, the state B always remains. Stay on. State B is said to be in the “stable state for input 1” in state B. Also, for example, starting from the state A, if the input 0 continues to be given, the state transitions to the state G via the transient state E and the transient state F, and if the input 0 continues to be given thereafter. , State B, state C, and state G in order, these three states continue to transition periodically. With this property, the state set {B, C, G} is said to be in the “steady state set for input 0”.
[0029]
In the finite state machine M of FIG. 9, there is no stable state for the input 0, the steady state sets are {B, C, G} and {D, H}, and the transient states are A and E. And F, and the unstable states are B, C, G, D, and H. For input 1, the stable state is only B, the steady state set is {B} and {C, F, G, H}, the transient states are A, D, and E, and The stable states are C, F, G, and H.
[0030]
[1-5. Steady state finite state machine]
In the following, a steady finite state machine is defined.
It is an object of the conversion unit to the steady finite state machine in the present invention to eliminate the transition from the finite state machine given as input to the transient state and generate a corresponding steady finite state machine.
[0031]
The steady finite state machine newM = (I, O, Σ, newδ, newω) corresponding to the finite state machine M = (I, O, Σ, δ, ω) is the same input alphabet and output as the finite state machine M It has a set of alphabets and the same state. Note that the specified finite state machine M = (I, O, Σ, δ, ω, s in the initial state_init) NewM also has the same initial state.
[0032]
The transition function newδ of the steady finite state machine has the following properties.
(1) The steady state set for the input i∈I of the finite state machine M becomes a steady state set for the same input i even in newM, and the states included in this set are transitions of the finite state machine M by the input i. Transition to the same state as before. This condition also means that the finite state machine M and newM have the same stable state for an arbitrary input i.
[0033]
(2) If the transient state s for the input i∈I of the finite state machine M continues to be given the input i and transitions to a state included in the steady state set S, this state s in newM Transitions to a state included in S in one transition when input i is given.
[0034]
(3) The output function newω has the following properties. The output associated with the transition by input i from the stable state for input iεI of finite state machine M is also equal in newM.
[0035]
(4) If the transitional state s for the input i∈I of the finite state machine M continues to be given the input i and transitions to the stable state, the input i of this state s is given at newM. The output accompanying the transition at this time is equal to the output in the stable state.
In the above definition, there is no particular definition of the output accompanying the transition from the unstable state or the output accompanying the transient transition to the unstable state.
[0036]
A state in which the steady state finite state machine thus defined and the unsteady state finite state machine are transitioned to when the input i is given once in a certain state is compared. The result is as shown in FIG. As is clear from FIG. 7, in the steady finite state machine and the unsteady finite state machine, is there a transition to the transient state for one input i as shown in FIG. There is a difference depending on whether or not. Therefore, the purpose of the conversion unit to the steady finite state machine in the present invention is to obtain a finite state machine that does not have a transition to a transient state (a transition as shown in (C) in the figure).
[0037]
[1-6. Specific example of stationary finite state machine]
The finite state machine newM shown in FIG. 9 is a stationary finite state machine corresponding to the finite state machine M of FIG. 8 and satisfies all the above properties. For example, the steady state set {D, H} for the input 0 of the finite state machine M is a steady state set for the input 0 even in newM. Further, the state D included in the steady state set {D, H} transitions to the state H in both the finite state machine M and newM when the input 0 is given, and the state H is given by the input 0. When it is, the state transitions to the state D in both the finite state machine M and the newM. Also. The transient state A for the input 0 of the finite state machine M is changed to the state G included in the steady state set {B, C, G} via the transient states E and F when the input 0 continues to be given. Is reached and then continues to cyclically transition in {B, C, G}, whereas in newM, the transient state A for input 0 changes the transient state once input 0 is given. Immediately without going through, when the state B included in the steady state set {B, C, G} is reached, and the input 0 continues to be given thereafter, cyclically in {B, C, G} Continue to transition. Further, the stable state B for the input 1 of the finite state machine M is a stable state for the input 1 even in newM, and as long as the input 1 continues to be given in this state B. Both the finite state machine M and newM continue to output stable output values. The transitional states A and E that transition to B at the input 1 both output a stable output value 0 along with this transition.
[0038]
[2. Logic Circuit Form Verification Device of Present Embodiment]
[2-1. Overall configuration]
An outline of an embodiment of a logic circuit type verification apparatus according to the present invention will be described with reference to FIG. The finite state machine conversion device described in FIG. 1 is implemented on a computer. The computer includes a central processing unit (CPU) 1, an input device 2 such as a keyboard and a mouse, an output device 3 such as a CRT display and a printer, and a storage device 4 such as a memory and a hard disk. These devices are connected by a bus 5 and exchange information with each other.
[0039]
The conversion device according to the present embodiment is configured as a program having the following parts executed on such a computer.
[0040]
(1) An input unit 10 for a circuit description to be verified.
[0041]
(2) Auxiliary signal input unit 11 that receives a description indicating which signal is a clock signal among input signals in the circuit.
[0042]
(3) The steady finite state machine generation unit 12 that generates the steady finite state machine newM without transition to the transient state based on the circuit description and the auxiliary information.
[0043]
(4) A preliminary finite state machine M provided in the stationary finite state machine generator 12 and including an arbitrary interpretation according to the timing of the change of the clock signal.₀The generation unit 13 of the first finite state machine that generates
[0044]
(5) The preliminary finite state machine M provided in the steady finite state machine generator 12₀And a second finite state machine generation unit 14 that generates a finite state machine M in which a clock signal is specified based on the auxiliary information and an arbitrary interpretation according to the timing of the change is eliminated.
[0045]
(6) The finite state machine M provided in the steady state finite state machine generation unit 12 and generated by the finite state machine generation unit 14 is converted into a steady state finite state machine newM from which the transition to the transient state is removed. The conversion part 15 for doing.
[0046]
(7) An equivalence verification unit 16 that compares a plurality of the steady finite state machines newM obtained by the conversion unit 15 and verifies their equivalence.
[0047]
(8) A result output unit 17 that outputs the verification result obtained by the equivalence verification unit 16 and the instability of the circuit obtained by the stationary finite state machine generation unit 12.
[0048]
[2-2. Overall action]
FIG. 2 is a diagram for explaining the operation when verifying the equivalence of two circuits in the verification device of FIG. FIG. 3 is a flowchart showing an operation sequence of the verification apparatus according to the present embodiment. In FIG. 2, a circuit description 100A and a circuit description 100B are descriptions of two logic circuits for verifying equivalence, and auxiliary information 200 is an input signal in the circuit described in the circuit description A and the circuit description B. This is a description indicating which signal is a clock signal. That is, these descriptions are input to the apparatus from the circuit description input unit 10 and the auxiliary information input unit 11, and for example, a circuit operation description in a hardware description language such as the VHDL language or a network between logic elements. For example, a circuit description by a list and a circuit description by a transistor net list.
[0049]
In this embodiment, first, the circuit description 100A and the circuit description 100B are individually passed as inputs to the stationary finite state machine generation unit 12 from the circuit description input unit 10 (step 301). In the first finite state machine generation unit 13 of the steady state finite state machine generation unit 12, a preliminary finite state machine M corresponding to these circuit descriptions based on the circuit description 100A and the circuit description 100B.₀A and M₀B is generated (step 302). The auxiliary information input unit 11 passes the auxiliary information 200 paired with the circuit descriptions 100A and 100B to the stationary finite state machine generating unit 12 (step 303). The second generation unit 14 of the steady state finite state machine generation unit 12 specifies the clock signal based on the auxiliary information 200, and specifies the transition destination in consideration of the timing of the change. Finite state machine M₀To generate finite state machines MA and MB from which the arbitrary interpretation is removed (step 304).
[0050]
The conversion unit 15 for the steady finite state machine converts the finite state machines MA and MB obtained as described above into the steady finite state machines newMA and newMB in which the transition to the transient state is eliminated ( 305). The steady finite state machines newMA and newMB obtained by the conversion unit 15 have the same stable state as the finite state machines MA and MB before the conversion, and output the same as the finite state machines MA and MB in the stable state. On the other hand, unlike the finite state machines MA and MB, the transition from an arbitrary transient state has the property of immediately transitioning to a stable state. This eliminates the instantaneous and non-essential behavior of the finite state machines MA, MB.
[0051]
Then, the equivalence checking unit 16 formally verifies equivalence between the steady finite state machines newMA and newMB (step 306), and outputs the result in the output unit 17 (step 307). The output unit 17 outputs information such as the instability of each circuit found in the steady finite state machine generation unit 12.
[0052]
[2-3. Preliminary finite state machine generator 13]
Next, the operation of the preliminary finite state machine generation unit 13 provided in the steady state finite state machine generation unit 12 will be described using an example. For example, when the finite state machine M is made from the circuit that realizes the master-slave type JK-flip-flop shown in FIG. 10A, the preliminary finite state is first obtained using only the information of the circuit description 100 by the following procedure. Machine M₀Followed by a preliminary finite state machine M using auxiliary information 200₀A finite state machine M obtained from
[0053]
Preliminary finite state machine M₀For example, when the circuit description 100 is a netlist description between logic elements as shown in FIG. 10, first, a feedback loop is found from the signal flow of the circuit description 100, and then a status bit is found. However, at this time, the clock signal is treated as one input signal like the other input signals, and is not treated specially. Each state bit found in the overall circuit description can have a value of 0 or 1, and any combination of these values can be represented by a finite state machine M₀Constitutes one state that is an element of the state set. From the relationship between the input signal and the value of the state bit and the output signal and the value of the state bit, the finite state machine M₀Determine the output function and transition function of. Thus, from the circuit of FIG. 10A, for example, the finite state machine M shown in FIG.₀Is made. In the finite state machine of this figure, the initial state is not specified. In FIG. 12, the state name and the output value are circled as A / 0, and the input alphabet [clk, j, i] is represented with an arrow indicating the transition destination as 0−.
[0054]
Further, when a circuit described in the transistor netlist is given to the circuit description 100, for example, using the methods described in (1) to (3) below, a finite number corresponding to this circuit is used. State machine M₀Configure.
[0055]
(1) T.Kam and P.A.Subrahmanyam, “State Machine Abstraction from Circuit Layouts using BDD ′s: Applications in Verification and Synthesis”, in Proc. European Design Automation Conf., 1992, pp. 92-97
(2) J.A. Moonondas, J.M. A. Wehben, J.M. A. Abraham and D.A. G. Saab, “VERTEX: VERification of Transistor-level circuits based on model EXtracation”, in Proc. The European Conf. On Design Automation with the European Event in ASIC Design, 1993, pp. 111-115
(3) M.M. Pandey, A.M. Jain, R.A. E. Bryant, et al. , “Extraction of Finite State Machines from Transistor Netlists by Symbolic Simulation”, in Proc. Of International Conference on Computer Design′95, pp.596-601
[2-4. Finite state machine generator 14 that does not include arbitrary interpretation]
[2-4-1. Problems of synchronous machine created from preliminary finite state machine M0]
After generating the preliminary finite state machine M0 as described above, a known machine such as (d) is followed by creating a synchronous machine.
[0056]
(4) J. Bormann, J. Lohse, M. Payer and G. Venzl, “Model Checking in Industrial Hardware Design”, in 32th ACM / IEEE Design Automation Conference, 1995, pp.298-303
For example, in the technique (4), the finite state machine M created here₀From the user, information such as “when does the change in the input / output signal value occur?” Is obtained from the user, and a finite state machine (synchronous machine) M that does not explicitly include the clock signal.₁Is generated. The information obtained from this user is, for example, that the value of the other input signal changes only while the value of the clock signal is 0, and the value of the other input signal does not change while the value of the clock signal is 1. The output signal value changes at the moment when the value of the clock signal changes from 1 to 0 (at the falling edge of the clock signal).
[0057]
FIG. 13 shows a synchronous machine generated from FIG. 12 using the information that the values of the input signals j and k change only when the value of the clock signal is 0 and a state transition occurs when the clock signal falls. It is an example. However, this method has a problem that it cannot be detected correctly when the designed circuit includes a situation in which the input signal changes at an unintended timing of the designer due to an error. is there. In fact, when this method is used, both of the synchronous machines shown in FIG. 13 are produced from FIGS. 10A and 10B, and the non-equivalence between the two circuits cannot be detected.
[0058]
[2-4-2. Finite state machine M₀Arbitraryness of interpretation in]
Therefore, in the present invention, in order to maintain the relationship between the change timing of the output signal value and the change timing of any input signal value including the clock signal, the finite state machine M₀Therefore, a finite state machine that explicitly includes a clock signal as an input signal without forming a synchronous machine is used as a target for formal verification.
[0059]
However, the finite state machine M configured only from the circuit description 100 by the method described above.₀Is arbitrary depending on whether the change is interpreted as occurring immediately before or immediately after the change of the clock signal when other input signals change at the same time as the clock signal. Due to this arbitrary nature, the two circuit descriptions for which equivalence is verified in the present invention are actually equivalent circuit descriptions, but the finite state machine constructed from them is logically non-equivalent. It can happen.
[0060]
For example, the two finite state machines shown in FIGS. 14A and 14B both have an input alphabet composed of two input signals of the clock signal clk and the other signal a, and an output alphabet composed of a 1-bit output signal. And state A and state D are in the initial state, respectively. These initial states are stable states that continue to output 0 when clk = 1 and a = 0. In these finite state machines, if the value of the input signal a changes from 0 to 1 immediately before the value of clk becomes 0, both finite state machines output as shown in FIGS. 15 (a) and 15 (b). The value of the signal changes from 0 to 1 simultaneously with the fall of clk. When the change in the value of the input signal a is immediately after the value of clk becomes 0, as shown in FIGS. 16A and 16B, the value of the output signal of either finite state machine Also stays at 0. Therefore, if only these situations are considered, the two finite states behave equivalently. However, when the value of a changes from 0 to 1 at the same time that the value of clk changes from 1 to 0, as shown in FIGS. The value changes from 0 to 1, and the latter keeps the value of the output signal at 0.
[0061]
Accordingly, the finite state machine of FIGS. 14 (a) and 14 (b) is arbitrary in interpretation when the values of the clock signal and the other input signal a change at the same time, that is, the former finite state machine When the values of the other input signals a change at the same time, the clock signal is interpreted as changing for a moment, while the latter finite state machine is interpreted as changing the clock signal for a moment earlier. Cause the two to become unequal. However, in an actual circuit, such a situation is not possible, and it is not desirable that there is an arbitrary interpretation.
[0062]
[2-4-3. Generation of finite state machine M that does not include arbitrary interpretation]
In the present invention, the preliminary finite state machine M as described above.₀To solve the problem caused by the arbitraryness of interpretation. For this purpose, in the second finite state machine generator 14, a preliminary finite state machine M₀A new finite state machine M that does not include any interpretation is constructed as follows. Next, the finite state machine M that does not include the arbitrary nature of the interpretation is further converted into a stationary finite state machine newM that does not include a transient transition, and the equivalence is verified.
[0063]
In the second finite state machine generator 14, the finite state machine M₀The finite state machine M is constructed as follows. For example, when the operation of the circuit description 100 is controlled by one clock signal, first, the clock signal clk is specified by the auxiliary information 200 obtained via the auxiliary information input unit 11 and the value immediately before the clock signal is held. State bit c to be introduced. Then, as shown in FIG. 18, depending on whether the value of c is 0 or 1, the finite state machine M₀Each state s included in the two states s₀, S₁These are divided into the states of the finite state machine M. Now, finite state machine M₀, The transition destination of state s when clk = 0 or other input value is i is s ′ (i, 0), and the transition destination of state s when clk = 1 or other input value is i is s ′ (i , 1).
[0064]
At this time, as shown in FIG.₀S ′ when clk = 0 and other input values are i₀(I, 0), clk = 1, when other input value is i, s'₁(I, 0) and s₁S ′ when clk = 0 and other input values are i₀(I, 1), clk = 1 When other input value is i, s ′₁It is determined to be (i, 1).
[0065]
In this way, the transition function δ of the finite state machine M is
[Expression 1]
s'_c= Δ (s_c, I, clk) = (δ₀(S, i, c))_clk
Determined by. Where c is a state bit holding the previous value of the clock signal, i is an input signal other than the clock, and s is a preliminary finite state machine M₀State, δ₀(S_c, I, clk) is a preliminary finite state machine M₀Is a transition function. Similarly, the output function ω of the finite state machine M is
[Expression 2]
o = ω (s_c, I, clk) = ω₀(S, i, c)
Determined by. Where ω₀Is a preliminary finite state machine M₀Is the output function of
[0066]
[2-4-4. Example of finite state machine M that does not include arbitrary interpretation]
An example of a finite state machine made from the finite state machine shown in FIGS. 14A and 14B by using the above method is shown in FIGS. 20A and 20B, respectively. In the example of this figure and the examples of FIGS. 14 and 21, for the sake of convenience of explanation, a finite state machine having an initial state is taken as an example. However, depending on the algorithm used in the equivalence verification unit described later, the initial state May not be necessary. In such a case, a preliminary finite state machine M₀Therefore, when configuring the finite state machine M, the method for determining the initial state need not be specified. On the other hand, if the algorithm used in the equivalence verification unit requires an initial state, a preliminary finite state machine M based on the auxiliary information 200 is used.₀The initial state of_initAnd then in the finite state machine M, s_initS divided into two states_{init 0}, S_{init 1}It is necessary to determine which of these will be the initial state.
[0067]
In the above example, the case where the clock signal cannot be specified by itself as the circuit description given as an input to the stationary finite state machine generation unit has been described. On the other hand, when a circuit description according to the register transfer level of the VHDL language as shown in FIG. 11 is given to the stationary finite state machine generation unit, an attribute such as “'EVENT” or “' LAST_VALUE” is usually used. In many cases, a signal marked with can be interpreted as a clock signal. In such a case, the value of the immediately preceding clock signal can be naturally determined as the status bit. However, the circuit description including a gated clock may not have the above attribute attached to the clock signal. For this reason, in general, in a circuit description for a circuit having one clock signal, it is more appropriate to always specify a clock signal from the outside by auxiliary information and to determine the value immediately before the specified clock signal as a status bit. Finite state machine M₀Can be configured.
[0068]
[2-5. Conversion unit 15 to a stationary finite state machine]
The finite state machine M made as described above is the original finite state machine M.₀Unlike a certain state, when a certain input is given, it may go through several transient states to transition to a stable state. For example, the finite state machine of FIG.₀Then, since the state A remains in the state A when the input of clk = 1 and a = 1 is continuously given, it is called a stable state. At this time, the value 0 is continuously output. Subsequently, when clk = 0 is changed, the state transits to the state C, and then remains in the state C and continues to output 1. Therefore, the state C is also a stable state. In contrast, the finite state machine M₀In the finite state machine M of FIG. 20 (a) constructed from the stable state A that continues to output 0 when clk = 1 and a = 1.₁If clk = 0 in state, state A₀Immediately after transition to state C₀To the stable state C₀Stay on and continue to output 1. State A seen here₀Is called a transient state, and as in this example, the original finite state machine M₀Even if the transition to the transient state is not included in, it may be included in the finite state machine M constructed from now on.
[0069]
In the present invention, in order to remove the transition to the transitional state included in the finite state machine M, the transition unit 15 to the steady state finite state machine is used and the transition to the transitional state is not performed on the finite state machine M. This is converted into a steady state finite state machine newM. As a technique for efficiently performing this conversion, for example, the above (1) and (3) are known. Moreover, although it is not a well-known technique, the conversion method using the iterative square method concerning development of this inventor can also be used.
[0070]
Examples of the steady finite state machine newM obtained by converting the finite state machine M shown in FIGS. 20A and 20B using the above technique in the finite state machine conversion unit 12 are shown in FIGS. 21A and 21B, respectively. Show. For example, in the finite state machine M in FIG. 20A, a stable state A that continues to output 0 with clk = 1 and a = 1.₁, When clk = 0, the transient state A that outputs 0₀After that, stable state C that continues to output 1₀In the stationary finite state machine newM in FIG. 21A, the same stable state A₁In the case of clk = 0, the same stable state C as the transition destination in the case of the finite state machine M without transitioning to any transitional state₀Transition to. Furthermore, as shown in FIGS. 22A, 22B, 23A, 23B and 24A, 24B, the steady finite state machine newM in FIGS. The input / output relationship is equivalent even when the clock signal clk and the other input signal a change at the same time.
[0071]
In this way, the stationary finite state machine generation unit 12 of the present invention is a finite state machine that excludes a preliminary finite state machine generation unit and arbitrary interpretation from the given circuit description and auxiliary information. A stationary finite state machine newM is generated by using a generation unit and a conversion unit to a stationary finite state machine, and this stationary finite state machine newM For situations that cannot be an actual circuit in which the value of the input signal changes, the change in the value of the clock signal always changes later than the change in the value of the other input signal without any arbitrary interpretation. It becomes a finite state machine that can be interpreted uniquely.
[0072]
[2-6. Equivalence verification unit 16]
Next, the operation of the equivalence checking unit 16 in this embodiment shown in FIG. 1 will be described. The equivalence verification unit 16 verifies the logical equivalence between the two steady finite state machines newMA and newMB created from the circuit descriptions 100A and 100B by using the steady finite state machine generation unit 12, and the result. Is output to the output unit 17. As described above, these two stationary finite state machines newMA and newMB indicate the state transition and output relationship with respect to the change of the clock and other input signal values, and the timing with respect to the change of the clock signal value. Therefore, the equivalence verifying unit 16 can verify equivalence without standing in detail in the circuit.
[0073]
For example, the following algorithm can be used as an algorithm for efficiently performing this.
[0074]
(5) O. Coudert, C. Berthet and J. C. Madre, “Verification of Sequential Machines Using Boolean Functional Vectors”, in Formal VLSI Correctness Verification 1989, pp.179-196; USP 5,491,639 T.Filkorn, 1996
In these algorithms, in order to verify the equivalence between the steady finite state machines newMA and newMB, it is necessary to specify respective initial states. On the other hand, if the finite state machine M is converted into the steady finite state machine newM in the stationary finite state machine generation unit 12, the possibility of resetting the finite state machine, such as a conversion method using an iterative square method, If a method in which the alignment possibility between finite state machines is preserved before and after the transformation is adopted, the verification algorithm shown in (6) can be used.
[0075]
(6) USP 5,331,568 C. Pixley, 1994
If this algorithm is used, it is not necessary to specify the initial states of the two finite state machines to be verified. That is, the initial finite state machine M₀When the finite state machine M is created from the above, the initial state cannot be determined only by the information specifying the clock, and the initial state immediately after the hardware is switched on is generally indeterminate. Pixley's algorithm is suitable for verifying equivalence.
[0076]
Pixley's algorithm does not need to specify the initial state of the finite state machine to be verified. Then, the states SA and SB of the two stationary finite state machines newMA and newMB to be compared are defined as being equivalent when always giving the same output sequence to an arbitrary input sequence. At this time, the equivalence of the two stationary finite state machines newMA and newMB is that an arbitrary state {sA, sB} ∈ΣP of the finite state machine MP = newMA × newMB is a set {SA, It is determined by whether or not there is an input sequence that can be transited to SB} εΣP. By using such a technique, in the verification system of the present invention, an error of a circuit designed to change the state at the falling edge of the clock even though the specification is described to change the state at the rising edge of the clock. Can be found.
[0077]
【The invention's effect】
As described above, according to the logic circuit formal verification device of the present invention, the equivalence verification unit performs formal verification on the logical equivalence of two stationary finite state machines generated from the descriptions of two given logic circuits. By doing so, it is possible to perform the format verification of the sequential circuit in consideration of the relationship between the change timing of the input / output signal value and the change timing of the clock signal value.
[0078]
In particular, in the present invention, the clock signal is left as an input signal, as opposed to the method of removing the clock from the input signal of the conventional finite state machine, and the bits constituting the state are also given the value immediately before the clock. Thus, it is possible to detect an error such as a difference in circuit operation due to a change in the input signal other than the clock timing expected by the designer. This is extremely advantageous for verifying the equivalence of a circuit having a low level of abstraction, such as a hardware description based on a transistor netlist or a sequential circuit in which a state is formed by providing a loop to an element.
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing a configuration of an embodiment of a logic circuit verification apparatus according to the present invention.
FIG. 2 is a functional block diagram showing a method of converting two logical descriptions into a finite state machine and comparing them.
FIG. 3 is a flowchart showing the operation of the verification apparatus of FIG. 1;
FIG. 4 is a diagram for explaining the definition of a finite state machine.
FIG. 5 is a diagram showing a specific example of a finite state machine.
FIG. 6 is a diagram showing a relationship between each state taken by a finite state machine.
FIG. 7 compares features of a steady state finite state machine and an unsteady state finite state machine.
FIG. 8 is a diagram showing a specific example of a finite state machine including a transition to a transitional state.
FIG. 9 is a diagram showing a steady finite state machine obtained by converting the finite state machine of FIG. 6;
FIG. 10 is a diagram showing a circuit that realizes a JK-flip-flop.
FIG. 11 is a diagram showing an example of behavioral description of a JK-flip flop in VHDL language.
12 shows a finite state machine made from a circuit that implements the JK flip-flop of FIG. 10 (a). FIG.
FIG. 13 shows a synchronous machine made from the finite state machine of FIG.
FIG. 14 is a diagram comparing state transitions of two finite state machines (a) and (b) in order to explain the arbitrary interpretation of the finite state machine.
15 is a time chart for comparing the input, output, and transition of the two finite state machines (a) and (b) of FIG. 14, and the value of the input signal a is changed from 0 to 1 immediately before the value of clk becomes 0. FIG. Indicates the case of changing.
16 is a time chart for comparing the input, output, and transition of the two finite state machines (a) and (b) in FIG. 14, and the case where the change in the value of the input signal a is immediately after the value of clk becomes zero. Show.
17 is a time chart for comparing the input, output, and transition of the two finite state machines (a) and (b) of FIG. 14, and the value of a is changed from 0 to 1 simultaneously with the change of the value of clk from 1 to 0. The case of changing to is shown.
FIG. 18 illustrates a technique for introducing a bit value that retains the previous clock value into a preliminary finite state machine.
FIG. 19 is a diagram illustrating a technique for determining a transition function of a finite state machine that does not include arbitrary interpretation by the technique of FIG. 18;
FIG. 20 shows a finite state machine (a) (a) that does not include the arbitrary interpretation of the clock value immediately before the two preliminary finite state machines (a) and (b) shown in FIG. The figure which shows b).
FIG. 21 is a diagram showing two stationary finite state machines (a) and (b) converted from the finite state machine of FIG. 20;
22 is a time chart for comparing the input, output, and transition of the two finite state machines (a) and (b) of FIG. 21, and the value of the input signal a is changed from 0 to 1 immediately before the value of clk becomes 0. FIG. Indicates the case of changing.
FIG. 23 is a time chart for comparing the input, output, and transition of the two finite state machines (a) and (b) in FIG. 21, in which the change in the value of the input signal a is immediately after the value of clk becomes zero. Show.
24 is a time chart for comparing the input, output, and transition of the two finite state machines (a) and (b) in FIG. 21, and the value of a is changed from 0 to 1 simultaneously with the change of the value of clk from 1 to 0. The case of changing to is shown.
FIG. 25 is a flowchart showing the operation of a verification apparatus using a conventional synchronous machine.
[Explanation of symbols]
100: Circuit description A, B
200 ... auxiliary information
10 ... Circuit description input section
11 ... Auxiliary information input part
12 ... Stabilized finite state machine generator
13 ... Preliminary finite state machine generator
14 ... Generating part of finite state machine not including arbitraryness
15 ... Converting part to steady finite state machine newM
16. Equivalence verification unit
17 ... Output unit

Claims (6)

In a formal verification device that formally verifies the equivalence of multiple logic circuits,
A stationary finite state machine generating unit that generates a stationary finite state machine corresponding to the logic circuit from a circuit description describing the logic circuit and information about an input signal given to the logic circuit;
An equivalence verification unit for verifying logical equivalence of a plurality of stationary finite state machines generated individually by the stationary finite state machine generation unit from the plurality of circuit descriptions;
An output unit that outputs a verification result of the equivalence verification unit,
The steady state finite state machine generator is
Among the plurality of input signals of the circuit represented by the circuit description, a finite state that generates a finite state machine that performs a uniquely defined state transition with respect to a change timing of a predetermined input signal and other input signals A machine generator,
A conversion unit to a finite state machine that converts the finite state machine generated by the finite state machine generation unit into a stationary finite state machine that does not have a transition to a transient state;
An apparatus for verifying a format of a logic circuit, comprising: The stationary finite state machine generation unit includes a preliminary finite state machine generation unit that generates a preliminary finite state machine based on a circuit description describing the logic circuit, and performs a uniquely defined state transition. The finite state machine generating unit for generating the finite state machine to perform is based on the preliminary finite state machine generated by the preliminary finite state machine generating unit, and the timing of the change of the predetermined input signal and other input signals The logic circuit format verification apparatus according to claim 1, wherein a finite state machine that performs a uniquely defined state transition is generated . The finite state machine generating unit, a clock signal and the timing values of the other signals change simultaneously, according to claim 1 or, characterized in that to generate the finite state machine performs state transitions uniquely defined The format verification apparatus for a logic circuit according to claim 2.   2. The logic circuit format verification apparatus according to claim 1, wherein the output unit also outputs information found in the stationary finite state machine generation unit. In a formal verification method for formal verification of equivalence of multiple logic circuits,
Steady state finite state machine generation unit, equivalence verification unit, finite state machine generation unit and steady state provided in the steady state finite state machine generation unit realized by a computer including an input / output device and a program for controlling the computer Use a finite state machine converter,
Based on a circuit description describing each logic circuit inputted from the input / output device and information on an input signal given to each logic circuit,
The finite state machine generation unit uniquely defines each logic circuit with respect to a change timing of a predetermined input signal and other input signals among a plurality of input signals of the circuit represented by the circuit description. A finite state machine generation process for generating finite state machines that perform state transitions,
The finite state machine corresponding to each logic circuit generated by the finite state machine generation process by the steady finite state machine conversion unit, the steady finite state having no transition to the transient state corresponding to each logic circuit Conversion to a finite state machine that converts to a machine,
Equivalence verification processing for verifying the logical equivalence of a plurality of stationary finite state machines individually generated by the stationary finite state machine generation unit from a plurality of circuit descriptions by the equivalence verification unit. A logic circuit verification method characterized by the above. The steady state finite state machine generator comprises a preliminary finite state machine generator;
By this preliminary finite state machine generation unit, preliminary finite state machine generation processing for generating a preliminary finite state machine based on the circuit description describing the logic circuit;
Based on the preliminary finite state machine generated by the preliminary finite state machine generation unit, the finite state machine generation unit uniquely determines a change timing of a predetermined input signal and other input signals. 6. The format verification method for a logic circuit according to claim 5, further comprising a step of generating a finite state machine that performs the defined state transition .

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