JP3653814B2 - Delay value calculation method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a logical connection verification method in layout design of a semiconductor integrated circuit and a delay value calculation method in timing design.
[0002]
[Prior art]
The synchronous circuit operates the circuit at the operation timing, that is, the rising (falling) timing of the clock signal. An ideal clock distribution is that a clock signal can be obtained simultaneously at any location on a semiconductor substrate (chip). However, in actuality, there is a time delay depending on the routing of the clock signal wiring and connected elements, so the clock signal obtained at a position close to the clock generating element and the clock signal obtained at a distant position are different in arrival time. (Skew) occurs.
[0003]
When the skew increases, synchronization cannot be achieved and normal circuit operation cannot be performed. Therefore, reducing the skew of the clock signal is an important issue.
[0004]
In order to reduce this skew, there is a clock tree design method. A typical example of this is the H-tree method. ("Reduction of Clock delays in VLSI Structure," Proc. IEEE Int. Conf. On Computer Design, 1984).
[0005]
In this system, the wiring paths of two elements (groups) to be connected are wired in an H shape so that the wiring paths are completely symmetric, thereby providing equal delay wiring. For example, an element such as a buffer cell is generally inserted at the H-type branch point. When realizing this, it is often the case that a buffer cell or the like is not inserted on the logic circuit in consideration of the clock structure at the time of logic design, but is inserted at the time of layout design. Accordingly, the logical connection information expressed in the net list does not match the logical connection information after the layout ends.
[0006]
In recent years, it is common to use a layout tool (automatic place and route tool) to perform layout design. However, recently, when the tool corrects the input netlist on the layout side, It has a function to output the reflected corrected netlist. The result of the automatic placement and routing tool output is that the layout is generated based on the modified netlist, but there may be bugs in the tool itself or some manual layout correction after design once, so logical again It is inevitable to perform connection verification.
[0007]
In addition, verifying whether or not it operates at a desired timing with respect to the obtained layout result is the most important for determining whether or not the chip can be manufactured. The process of doing that is called back annotation. It extracts element position information and wiring information (RC network: R is resistance, C is capacitance) from the layout result, calculates element delay and wiring delay, and returns the result to a timing simulator or the like for simulation. That is. In this case, since it is necessary to obtain the element delay and the wiring delay for the entire chip, an enormous amount of time is required unless an efficient method is used. In particular, now that hierarchical design is common, it is difficult to process the entire chip at once.
[0008]
Recently, in order to calculate the delay with high accuracy, a method taking into account the inclination of the input signal of each element and the operation point (driving point) has been adopted, and complicated calculation is often required.
[0009]
In this case, wiring information on the input side of each element is also required. On the other hand, the hierarchical expansion can be expanded only by synthesizing only the net information straddling the hierarchy with the information of the higher hierarchy without being aware of the input / output relationship of the elements. If delay calculation processing and hierarchy expansion processing can be made compatible, efficient delay calculation will be possible.
[0010]
Also, when the delay result is returned to the timing simulator or the like in the clock tree described above, it cannot be simply returned because it is extracted from the layout result different from the original netlist and the delay calculation is performed. This is because information on elements that are not in the original netlist is included. In general, a method of returning a delay value to the timing simulator employs a method of expressing two points of terminals on an element as a pair (from-to) and assigning a delay value therebetween. Therefore, even if an attempt is made to return a delay value with an element not defined on the netlist, the delay value cannot be returned because the element does not exist.
[0011]
[Problems to be solved by the invention]
As described above, when the clock tree is inserted at the time of layout design, the logical information obtained from the net list and the logical information obtained from the layout result are different, and therefore, the normal connection verification between the net list and the layout cannot be performed. Occurs.
[0012]
In addition, when calculating the in-element delay and the wiring delay in consideration of the slope of the input waveform of the element from the layout result, there arises a problem that information required for hierarchical development differs from information required for delay calculation. .
[0013]
Further, when returning the delay result of the clock tree to the timing simulator or the like using the delay result obtained above, an element that is not in the original netlist is included, so that there is a problem that it cannot be simply returned.
[0015]
According to a first aspect of the present invention, one or more element groups (for example, functional blocks and logic cells) that are constituent elements of a semiconductor integrated circuit are arranged and then wired between them according to a logic connection request in a hierarchical manner. A method of calculating an in-element delay and a wiring delay with respect to a layout result of the semiconductor integrated circuit having a designed hierarchical structure, wherein a hierarchy expansion order for determining an order in which the layout hierarchy is expanded in order to calculate a delay A determination step, a block selection step for selecting an element group according to the order determined in the hierarchy expansion order step, and an element group and a net for delay calculation in this hierarchy for the element group selected in the block selection step A first element group / net extraction step for extracting the element, and an intra-element delay and arrangement of the element group / net extracted in the first extraction step. A delay calculating step of calculating a delay consists inner element and a net connected to the net and elements and the element connected to an external terminal for combining the upper layer with respect to the block selecting the element group selected in step A second element group / net extraction step for extracting element groups and nets, and a lower hierarchy obtained by the second element group / net extraction step according to the hierarchy development order obtained in the hierarchy development order determination step A delay value calculating method for a semiconductor integrated circuit, comprising: a layer expansion step for combining the element group and net of the device and the upper layer element and net; and a delay value information combining step for combining all of the delay calculation information It is.
[0017]
[Action]
With the configuration described above, the first invention comprises a net and an element connected to an external terminal of the lower hierarchy and an inner element and a net connected to the element when processing from the lower hierarchy to the upper hierarchy in order. By extracting element groups and nets and synthesizing them with the upper layer, it is possible to accurately determine the inaccurate part in the lower layer delay calculation by the upper layer delay calculation. After being obtained, only accurate delay calculations are selected and synthesized. As a result, not only can hierarchy expansion be performed while performing delay calculations with the minimum necessary data, All the delay calculation results are accurate .
[0020]
【Example】
Hereinafter, a layout verification method and a delay value calculation method according to an embodiment of the present invention will be described with reference to the drawings.
[0021]
(Example 1)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a flowchart for realizing the layout verification method in the first embodiment of the present invention.
[0022]
First, necessary data will be described.
FIG. 4 is a diagram showing a part of a certain circuit. FIG. 4A shows the logic circuit of the original netlist S. The circuit 1 and the buffer 21 are connected, and further connected to the clock terminals of the plurality of flip-flops 22. The data terminal of the flip-flop 22 is connected to the circuit 2.
[0023]
A logic circuit when a clock tree is generated from the netlist S is shown in FIG. With the buffer 21 as a root, the buffers 23 and 24 are inserted into the branches of the tree, and the flip-flop 22 is arranged on the leaf. This is an example of the clock tree method described above. The information extracted from the layout result is considered to be in the state shown in FIG. 4B (as described above, the layout is performed based on this logic circuit, but if that is the case, it is not completely guaranteed). As described above, when the layout tool is used, a corrected netlist can be output, so that a netlist reflecting this clock tree can be obtained. Here, the net list is S ′.
[0024]
As described above, the original netlist S, the corrected netlist S ′, and the layout result diagram created by the layout tool are prepared.
[0025]
Now, the layout verification method in the first embodiment will be described with reference to FIG. First, the difference between the netlists S and S ′ is obtained in the difference extraction step 1 between the netlists SS ′. In the case of FIG. 4, the structure between the buffer 21 and the flip-flop 22 is different. For example, the bold line in FIG.
[0026]
Next, in logical check step 2, logical verification is performed between different parts for each path (between the buffer 21 and the flip-flop 22, between the buffer 21 and the flip-flop 25, etc.). Here, the buffer 21 and the flip-flop 22 will be described as an example. Since the buffer 21 and the flip-flop 22 in FIG. 4A are directly connected by wiring, there is no logical change. In the buffer 21 and the flip-flop 22 in FIG. 4B, only two buffers are inserted and there is no logical change. Therefore, it can be seen that there is no logical change in both figures. This is verified for all paths.
[0027]
As described above, if there is no change in the logic of all the paths, it has been proved that the circuit of FIG. 4 (a) and the circuit of (b) are logically identical. Are equivalent. If there is a discrepancy, the error processing step 4 specifies the location, checks and corrects the netlists S and S ′, and executes again from the netlist SS ′ difference extraction step 1.
[0028]
Finally, using the netlist S ′, the connection verification step 3 by the netlist S ′ is executed, and the logical connection verification of the layout is completed. Step 3 is conventional layout connection verification. Any method may be used.
[0029]
(Example 2)
A second embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a flowchart showing a hierarchical calculation method for delays according to the second embodiment of the present invention.
[0030]
Here, before describing the present invention, the delay calculation step 8 used therein will be described.
[0031]
FIG. 5 is a diagram showing a part of the circuit. In the figure, 30 is an AND element, 31 is a buffer connected to the input side of AND30, 32 is a buffer connected to the output side of AND30, 33 is a net between the buffer 31 and AND30, and 34 is an output side net of AND30.
[0032]
Now, how to calculate the in-element delay of the AND 30 and the wiring delay between the AND 30 and the buffer 32 performed in step 8 will be described.
[0033]
It is known that the delay time varies depending on the slope of the input waveform. For example, the input waveform varies depending on the configuration of the input side net 33 of the AND 30, and the influence thereof has an influence on the in-element delay. Therefore, when calculating the delay, the state of the net on the input side of the AND 30 is represented by an RC network that is modeled by resistance and capacitance, and the slope of the input waveform is calculated from the network. Calculate as a parameter. The wiring delay is a delay due to the influence of wiring from the output side terminal to the input side terminal of a certain element. In FIG. 5, the output side net 34 corresponds to this. This is the same as when calculating the slope of the input waveform, and the RC network is calculated. Based on the result, the wiring delay from each output side terminal to the input side terminal of a certain element is calculated. Is calculated.
[0034]
From the above, it can be seen that when calculating the delay value of an element, accurate calculation cannot be performed unless the input / output side nets of the element are prepared. This delay calculation method is described, for example, in a manual of a commercially available delay calculation tool (reference: published by Excellent Design, “Peacock Reference Manual V2.0”).
[0035]
Next, the delay value calculation method in the second embodiment will be described. FIG. 6A is an example of a circuit. As shown in the figure, there are two hierarchies, and the highest hierarchy is a block A, among which a block B of a hard block (for example, a memory block) and a block C, D of a soft block (for example, a standard cell block) are included. In addition, it is assumed that a plurality of elements 40 (the left side of the element is an input terminal and the right side is an output terminal) and a net (wiring) between the elements exist in the soft block. This hierarchical structure is shown in FIG.
[0036]
First, in the hierarchy development order determination step 5, the hierarchy development order is determined. Expansion is performed from the bottom up. In this figure, after processing blocks C and D, block A is finally expanded. Here, since the block B is a hard block, there is no need to expand it.
[0037]
Next, blocks are selected according to the order (block selection step 6).
First, block C is selected. In the element group / net extraction step 1 for the block C, an element group and a net for delay calculation are extracted. In FIG. 7 (a), the thick line corresponds to it. Based on the element group and the net, the delay calculation step 8 is executed to calculate the delay. The result is written in the file DFC, for example. For example, there is a file expression format in which a delay value is assigned to a pair (from-to) of two element terminals. An example is the SDF format (literature: published by Cadence, "SDF Annotator User Guide").
[0038]
Next, a second element group / net extraction step 9 is executed in order to obtain hierarchical development data. As is clear from the description of the delay calculation step 8 described above, accurate delay calculation cannot be performed unless the input and output of the elements are completely aligned. Therefore, in this step 9, the element group / net (FIG. 7 (a)) used for the delay calculation is not accurately calculated, that is, the net and the element connected to the external terminal 41 and the inner side connected to the element. Extract all elements and nets. The part indicated by the solid line in FIG. Here, the resulting block is referred to as a block C ′. Similarly, for the block D, the first element group / net extraction step 7 and the delay calculation step 8 are executed, the delay calculation is performed (generation of the file DFD), and the element group / net extraction 2 step 9 is executed. Thus, the block D ′ is generated (see FIG. 7B).
[0039]
As described above, the processes of blocks C and D are completed, and blocks in the same hierarchy are no longer present, so the hierarchy development step 10 is executed. The upper layer block is block A. The lower hierarchical blocks are blocks B, C ′, and D ′. In step 10, all element groups and nets are synthesized. FIG. 8 (a) shows the result.
[0040]
Then, the block selection step 6 is executed again to select the block A, the first element group / net extraction step 7 and the delay calculation step 8 are executed (file DFA generation) in the same manner as described above. The group / net extraction 2 step 9 is executed to generate a block A ′ (see FIG. 8A). Note that since block A has no external terminals, block A ′ is empty.
[0041]
As described above, since the development of all the hierarchies has been completed, the delay value information synthesis step 11 is executed in order to finally combine the delay calculation results into one. It is the way of synthesis that must be noted here. FIG. 8B shows at which point the delay calculation result is used for synthesis.
The thick line is the result of delay calculation in the lower layer (DFC and DFD), and the solid line is the result of delay calculation in the upper layer (DFA).
[0042]
The selection criteria for the delay value are as follows.
1) When the net connected to the external terminal is the output side net, the wiring delay of the net on the output side of the element E connected to the net and the intra-element delay of the elements excluding the element E connected thereto are calculated on the lower layer side. Adopt the delayed result.
[0043]
2) When the net connected to the external terminal is the input side net, the wiring delay of the net on the output side of the element E connected to the net and the intra-element delay of the elements excluding the element E connected to the net are calculated on the upper layer side. Adopt delay results.
[0044]
Thus, the entire delay calculation is completed, and the value is returned to the timing simulator or the like for simulation.
[0045]
(Example 3)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a diagram showing a method for calculating a delay value on the clock tree in the third embodiment of the present invention.
[0046]
9A is a logic diagram before clock tree generation, and FIG. 9B is a logic diagram after clock tree generation.
As described in the first embodiment, since the generation of the clock tree is performed at the time of layout design, even if the delay value is simply calculated from the layout diagram, it cannot be returned to the simulator. Therefore, the present invention makes it possible to return it.
[0047]
First, a delay value is calculated using the delay calculation step 12 for the layout design, that is, for the layout result in the state of FIG. In step 12, for example, as shown in the second embodiment, the delay calculation is performed by executing the second of the present invention from the result of the hierarchical layout.
Since the original netlist S has no clock tree, the delay result must be generated in a form in which the added elements are deleted (FIG. 9A).
[0048]
Therefore, in the delay value calculation step 13 in the clock net, the delay is calculated based on the delay value changed by the additional element and the net related thereto. The thick lines in FIGS. 9A and 9B are the same path from the start point to the flip-flop 52. Since the delay value that should be returned originally is the delay time from the start point to the flip-flop 52, in step 13, the sum of the delay values calculated on the path is calculated, and the value is calculated from the start point in FIG. The delay value is 52. In the case of the figure
Delay value of flip-flop 52 from the start point =
(Internal delay of buffer 52) +
(Wiring delay from the output terminal of the buffer 52 to the input terminal of the buffer 53) +
(Intra-element delay of buffer 53) +
(Wiring delay from the output terminal of the buffer 53 to the input terminal of the buffer 54) +
(In-element delay of buffer 54) +
(Wiring delay from the output terminal of the buffer 54 to the input terminal of the flip-flop 52)
It becomes.
[0049]
This calculation is performed for all paths in the clock tree. The obtained result is the delay time on the clock tree.
[0050]
As described above, since the delay calculation is simply the sum of the delay times in the path, it can be calculated very quickly.
[0051]
【The invention's effect】
As described above, according to the first invention , processing is performed with the minimum data necessary for hierarchical development and the minimum data necessary for delay calculation, so that the memory usage is small and accurate and high-speed processing is performed. It becomes possible .
[Brief description of the drawings]
FIG. 1 is a flowchart showing layout verification in the first embodiment of the present invention. FIG. 2 is a flowchart showing a hierarchical delay calculation method in the second embodiment of the present invention. FIG. 4 is a flowchart showing a method for calculating a delay value on a clock tree in the third embodiment. FIG. 4 is a diagram showing an example of a circuit for explaining the first embodiment of the present invention. FIG. 6 is an exploded view for explaining the second embodiment of the present invention. FIG. 7 is an exploded view for explaining the embodiment. FIG. 8 is for explaining the embodiment. FIG. 9 is a diagram showing an example of a circuit for explaining a third embodiment of the present invention.
1 Netlist SS 'Difference Extraction Step 2 Logic Check Step 3 Netlist S' Connection Verification Step 4 Error Processing Step 5 Hierarchy Expansion Order Determination Step 6 Block Selection Step 7 Element Group / Net Extraction 1 Step 8 Delay Calculation Step 9 Element group / net extraction 2 step 10 Hierarchy expansion step 11 Delay value information synthesis step 12 Delay calculation step 13 Delay calculation step in clock net

Claims (1)

In the layout result of the semiconductor integrated circuit having a hierarchical structure in which one or more element groups serving as constituent elements of the semiconductor integrated circuit are arranged and then wired according to a logical connection request to perform hierarchical design. A method for calculating the in-element delay and the wiring delay,
A hierarchy expansion order determination step for determining the order in which the layout hierarchy is expanded for delay calculation;
A block selection step of selecting an element group according to the order determined in the hierarchical expansion order step;
A first element group / net extraction step for extracting an element group and a net for delay calculation in this hierarchy for the element group selected in the block selection step;
A delay calculation step of calculating an intra-element delay and a wiring delay of the element group / net extracted in the first extraction step;
Extracting element groups and nets composed of nets and elements connected to external terminals for synthesizing with the upper hierarchy for the element group selected in the block selection step, and inner elements and nets connected to the elements The element group / net extraction step of
Hierarchical expansion step of synthesizing lower hierarchical element groups and nets obtained by the second element group / net extracting step with higher hierarchical elements and nets in accordance with the hierarchical expansion order obtained in the hierarchical expansion order determining step. When,
A delay value calculation method comprising a delay value information synthesis step for synthesizing all of the delay-calculated information.

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