JP3652591B2 - Data transmission control method and data transmission system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data transmission control technique, and more particularly to a transmission control method for directly transmitting / receiving arbitrary bit pattern data in a transmission function using an asynchronous transmission control device.
[0002]
[Prior art]
In recent years, the performance and price of personal computers have been remarkably increased and rapidly spread to society. Most personal computers are equipped with RS-232-C standard-compliant communication ports as standard, but most of them are dedicated to asynchronous communication. For this reason, these are convenient for producing inexpensive and highly functional data transmission terminals, but the transmission procedure must be asynchronous (asynchronous).
RS-232-C is standardized by the EIA (Electronic Industries Association) as an interface for connecting a data line termination device and a data terminal device. ITU-T recommendation V.24 V.28 and JIS- Also functionally compatible with C-6361.
[0003]
On the other hand, in a computer network, there is a high level data link control procedure (HDLC) as a transmission control method suitable for high speed transmission and having high reliability. The HDLC is a transmission control method suitable for high-speed transmission and having high reliability. However, synchronization control between transmission and reception devices is a frame synchronization method. In data communication using an asynchronous data terminal represented by a personal computer, it is necessary to replace the synchronous control method with the asynchronous method in order to use the features of HDLC. This causes a problem that the zero insertion / zero removal sequence cannot be handled.
[0004]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION In view of the above problems, the present invention is intended to make it possible to use HDLC transmission control procedures in a transmission control system that uses asynchronous data transmission terminals such as personal computers that are widely available at low cost. And
[0005]
And it aims at enabling manufacture of the transmission control system which has high transmission efficiency and high reliability cheaply.
[0006]
[Means for Solving the Problems]
The invention of claim 1 is a data transmission method using a frame format having a frame length of a multiple of 8 bits according to a high level data link control procedure (HDLC) as a transmission format,
When 5 or more consecutive bit patterns occur in the field between the flags in the frame, 8 "0" s are inserted next, thereby extending the frame length in units of 8 bits. It is characterized by being performed.
[0007]
The invention of claim 2 is a data transmission system using a frame format having a frame length of a multiple of 8 bits according to a high level data link control procedure (HDLC) as a transmission format,
When a bit pattern in which five or more “1” s are consecutively generated is generated in the field sandwiched between the flags in the frame, the data transmitting terminal inserts eight “0” s after that to expand the frame length to 8 The data reception terminal deletes the zero 8-bit data and receives it.
[0008]
The invention of claim 3 is characterized in that, in the invention of claim 2, an asynchronous terminal is used as a data transmission terminal or data reception terminal, and arbitrary bit pattern data can be directly transmitted and received.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
(Control by HDLC)
First, the high-level data link control procedure (hereinafter referred to as HDLC) has functions such as a full-duplex communication method, continuous transfer, and simultaneous communication with a plurality of other parties. As a transmission control procedure, it is standardized by ISO. In Japan, a JIS standard conforming to ISO is established.
・ ISO 3309-1984 Information processing systems-Data communication- High level data link control procedures-Frame structure
・ ISO 4335-1984 Data communication-High level data link control procedures-Consolidation of elements of procedures
・ ISO 7809-1984 Information processing systems-Data communication- High level data link control procedures-Consolidation of classes of procedures
・ JIS C 6363-1978 High Level Data Link Control Procedure Frame Configuration ・ JIS C 6364-1978 High Level Data Link Control Procedure Elements ・ JIS C 6365-1978 High Level Data Link Control Procedure Procedure Class [0011]
In HDLC, all information is transmitted in the same frame format, and synchronization control between transmission / reception apparatuses is performed by a frame synchronization method in which flag start / end identification is performed by flag detection.
[0012]
FIG. 1 is an HDLC frame configuration diagram. In the figure, the HDLC frame structure is composed of a bit string called a flag (1) arranged at the beginning and end of a frame, and an information field (2) of 8 × n bit length sandwiched between the flags (1) (hereinafter, , I field) and a 16-bit frame check sequence (3) (hereinafter referred to as FCS).
[0013]
The flag (1) is a fixed bit pattern “01111110” having a length of 8 bits. In HDLC, since frame synchronization between transmitting and receiving apparatuses is performed by flag detection, it is necessary to clearly distinguish the flag (1) from other bit strings. . That is, when the same bit pattern as the flag (1) appears in the configuration of {I field + FCS}, the reception side erroneously detects the start (or end) of the frame.
[0014]
In order to prevent this in HDLC, any bit pattern can be directly transmitted and received using a zero insertion / zero removal sequence. Here, the zero insertion / zero removal sequence means that when five or more “1” s occur continuously in the configuration of {I field + FCS} on the transmission side, This is an operation for restoring the original bit pattern by inserting “0” and removing the inserted “0” on the receiving side. FIG. 2 shows a schematic diagram of the zero insertion / zero removal sequence. FIG. 2 shows an example of transmitting the bit pattern “01111111” in the configuration of {I field + FCS}.
[0015]
(Control by asynchronous mode)
Next, an example of synchronization control using the start-stop synchronization method will be described with reference to FIG. In the start-stop synchronization method, a start bit (6) (referred to as ST) and a stop bit (7) (referred to as SP) are added before and after the data bit string (5). After / 2 (here, T: bit sampling period), a predetermined number of data bits (hereinafter, the number of data bits is k) is sampled from the received signal at T intervals. In the example of FIG. 3, the transmission setting is a start bit (ST) = 1 bit, a stop bit (SP) = 1 bit, a data bit length (k) = 8 bits, and a parity (P) = none, and the bit pattern “01111111”. The example which transmits is shown.
[0016]
That is, in this asynchronous method, the data bit length (k) between the start bit (ST) and the stop bit (SP) must be a constant length, and the transmission / reception frame length must be a multiple of k. However, the above-described HDLC zero insertion / zero removal sequence operation inserts “0” in bit units depending on the content of the transmission bit pattern. For example, the transmission / reception frame length before zero insertion is L, and the transmission / reception frame after zero insertion is When the length is L ′, it is uncertain whether L ′ is a multiple of k even if L is a multiple of k. Therefore, in the start-stop synchronization method, it is not possible to transmit an arbitrary bit pattern using the HDLC frame format.
[0017]
(Control procedure of Embodiment 1)
Therefore, in the first embodiment, the synchronization control method is an asynchronous method, and the data bit length (K) = 8 is set. The reason why K = 8 is that each field length of the HDLC frame is defined as 8 bits or n × 8 bits, so that it is easy to make the transmission / reception frame length (L) a multiple of K. In addition, data processing of each field on the application side becomes easy.
[0018]
As described above, the HDLC zero insertion / zero removal sequence is “next to the fifth“ 1 ”when five or more“ 1 ”s occur continuously in the configuration of {I field + FCS} on the transmission side”. In this case, the transmission control method according to the present embodiment is “5 consecutive occurrences of“ 1 ”in the {I field + FCS} configuration on the transmission side”. In this case, “8 points are continuously inserted after the fifth“ 1 ””, and this operation is a “zero 8-bit insertion / removal sequence”.
[0019]
FIG. 4 is a diagram illustrating a zero 8-bit insertion sequence according to the first embodiment. In FIG. 4, when five “1” s are continuously generated in the I field of the transmission / reception frame (10), eight “0” s are successively inserted after the fifth “1”. In this case, since the frame length (L) of the transmission / reception frame (10) before the insertion of zero 8 bits is 2 × F + I + FCS, L is a multiple of k (8), and the bit pattern in {I field + FCS} Regardless of how many times the zero 8-bit insertion occurs, the frame length (L ′) of the transmission / reception frame (11) becomes L ′ = L + N × 8 (N: the number of zero 8-bit insertions). The length is definitely a multiple of k.
[0020]
As described above, since the frame length (L ′) after insertion of zero 8 bits and each field length in the frame are multiples of k, the flag bit pattern “01111110” is expressed as hexadecimal code “7E” and 8 bits = 1 byte. In other words, the transmission / reception frame after the insertion of zero 8 bits can be regarded as a frame that starts with a “7E” code having a frame length of n bytes and ends with a “7E” code. In the asynchronous data transmission terminal, each field is divided in units of bytes as described above, and the frame format ending with a fixed code makes it easy to identify the start and end of a frame at the time of reception. It is a feature.
[0021]
FIG. 5 shows an example of a transmission control system configuration using the transmission control procedure of the embodiment. In this system configuration example, a personal computer 15 that is an asynchronous data transmission terminal is connected to an NTT dedicated line 18 that is a transmission path via an asynchronous modem 16. The interface between the personal computer 15 and the asynchronous modem 16 is RS-232-C17. Although the hardware listed in the personal computer 15, asynchronous modem 16, and RS-232-C17 are all widely available at low cost, the characteristics of HDLC can be obtained by applying the transmission control procedure of this embodiment. High transmission efficiency and high reliability can be obtained. Further, the transmission control procedure of the present embodiment is not limited to this hardware configuration and can be widely used for asynchronous data transmission systems.
[0022]
【The invention's effect】
As described above, according to the present invention, as in the zero insertion / removal sequence of the HDLC frame format, the flag is clearly distinguished from other fields, and the transmission / reception frame length is maintained at a multiple of 8. Therefore, it is possible to realize data transmission that can use the advantages of HDLC in an asynchronous data transmission terminal.
[0023]
In other words, the HDLC transmission control procedure can be used in a transmission control system using a start-stop synchronization data transmission terminal that is widely available at low cost, and a transmission control system having high transmission efficiency and high reliability is manufactured at low cost. Make it possible.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a transmission frame used in HDLC (High level Data Link Control procedure).
FIG. 2 is a schematic diagram showing an outline of an HDLC “zero insertion / zero removal sequence”;
FIG. 3 is a data extraction processing diagram showing an example of synchronization control by asynchronous transmission.
FIG. 4 is a diagram illustrating a zero 8-bit insertion sequence according to the first embodiment.
FIG. 5 is a configuration diagram showing a transmission control system using the transmission control procedure of the first embodiment.
[Explanation of symbols]
(1) Flag, (2) Information field, (3) Frame check sequence, (4) Data bit, (6) Start bit, (7) Stop bit, (8) Bit sampling period, (10) Zero 8 bit insertion Previous frame, (11) Zero-zero bit inserted frame, 15 PC, 16 asynchronous modem, 17 asynchronous RS-232-C, 18 NTT dedicated line.

Claims (3)

A data transmission method using a frame format having a frame length that is a multiple of 8 bits according to a high-level data link control procedure (HDLC) as a transmission format,
When 5 or more consecutive bit patterns occur in the field between the flags in the frame, 8 "0" s are inserted next, thereby extending the frame length in units of 8 bits. A data transmission control method characterized in that: A data transmission system using a frame format having a frame length that is a multiple of 8 bits according to a high-level data link control procedure (HDLC) as a transmission format,
  When a bit pattern in which five or more “1” s continue in the field between the flags in the frame is generated, the data transmitting terminal inserts eight “0” s next, and expands the frame length by eight. A data transmission system, wherein transmission is performed in bit units, and the data receiving terminal receives the zero 8-bit data after deleting it. 3. The data transmission system according to claim 2, wherein an asynchronous bit system terminal is used as the data transmitting terminal or the data receiving terminal, and arbitrary bit pattern data can be directly transmitted and received.

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